Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a display area, and the display area comprises a first arrangement area and a second arrangement area which are arranged in the column direction; the first arrangement area comprises N rows of light-emitting elements and N rows of pixel circuits, each row of light-emitting elements corresponds to one row of pixel circuits, and the first row of pixel circuits and the second row of pixel circuits are located below the corresponding rows of light-emitting elements respectively; the second arrangement area comprises a target circuit of the display panel, and the second arrangement area is located above the first row of pixel circuits. According to the display panel, the first row of pixel circuits and the second row of pixel circuits are moved to the middle of the display area, so that a wiring area, namely a second arrangement area, is formed above the first row of pixel circuits, the wiring area of the borderless display panel is expanded, and meanwhile, the borderless display panel with high PPI can be realized.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] With the rise of OLED (Organic Light Emitting Diode) and Micro-LED (Micro-Light Emitting Diode), borderless displays have become a focal point of development. In traditional technologies, the first row of pixel circuits in a borderless display panel is located below the first row of light-emitting elements, while the remaining row pixel circuits are located above their respective light-emitting elements. The area above the first row of light-emitting elements serves as a wiring area. This wiring area is used to house circuits related to the display panel.

[0003] However, when there are too many circuits to set up, or the PPI (Pixels Per Inch) is too high, the wiring area of ​​a traditional borderless display panel is insufficient to accommodate these circuits, resulting in a limited wiring area. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device that can expand the wiring area of ​​a borderless display panel to address the aforementioned technical problems.

[0005] In a first aspect, this application provides a display panel, the display panel including a display area, the display area including a first arrangement area and a second arrangement area arranged along a column direction;

[0006] The first arrangement area includes N rows of light-emitting elements and N rows of pixel circuits. Each row of light-emitting elements corresponds to a row of pixel circuits. The first row of pixel circuits and the second row of pixel circuits are located below the corresponding row of light-emitting elements.

[0007] The second arrangement area includes the target circuit of the display panel, and the second arrangement area is located above the first row of pixel circuits.

[0008] In one embodiment, the first row of pixel circuits is located on the side of the first row of light-emitting elements closer to the second row of light-emitting elements, and the second row of pixel circuits is located on the side of the second row of light-emitting elements closer to the third row of light-emitting elements.

[0009] In one embodiment, the third row of pixel circuits to the Nth row of pixel circuits are respectively located on the side of the corresponding row light-emitting element that is close to the previous row light-emitting element.

[0010] In one embodiment, the pixel circuits of the first row to the i-th row are respectively located on the side of the corresponding row light-emitting element that is closer to the next row light-emitting element, and the pixel circuits of the (i+1)-N-th row are respectively located on the side of the corresponding row light-emitting element that is closer to the previous row light-emitting element; wherein, 3≤i≤N-1, and i and N are both integers.

[0011] In one embodiment, the second arrangement area is located between the first row of light-emitting elements and the first row of pixel circuits.

[0012] In one embodiment, the first row of pixel circuits is located on the side of the j-th row of light-emitting elements close to the (j+1)-th row of light-emitting elements, and each two adjacent rows of pixel circuits from the second row to the N-th row are located between each two adjacent rows of light-emitting elements from the (j+1)-th row to the N-th row of light-emitting elements, where 2≤j≤(N-1) / 2, and i and N are both integers.

[0013] In one embodiment, the second arrangement area is located in at least one of the following positions:

[0014] Between the first row of light-emitting elements and the second row of light-emitting elements;

[0015] Between the second row of light-emitting elements and the first row of pixel circuits.

[0016] In one embodiment, the target circuit of the display panel includes multiple types of circuits that do not overlap.

[0017] In one embodiment, the various types of circuits include control circuits, drive circuits, and electrostatic discharge protection circuits.

[0018] Secondly, this application also provides a display device, including the display panel in any of the above embodiments.

[0019] Thirdly, this application also provides a computer device including the display panel in any of the above embodiments.

[0020] The aforementioned display panel, display panel, and computer device, by setting a first and a second arrangement area along the column direction in the display area of ​​the display panel, and placing the first and second row pixel circuits in the first arrangement area below the corresponding row light-emitting elements, realize the movement of the first and second row pixel circuits towards the center of the display area, so that the area above the first row pixel circuits becomes a wiring area, i.e., the second arrangement area, thereby expanding the wiring area of ​​the borderless display panel, and at the same time facilitating the realization of a high PPI borderless display panel. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of a display panel structure in one embodiment;

[0023] Figure 2 This is another structural schematic diagram of the display panel in one embodiment;

[0024] Figure 3 This is another structural schematic diagram of the display panel in one embodiment;

[0025] Figure 4 This is a schematic diagram of the display device in one embodiment;

[0026] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0028] In traditional technology, the first row of pixel circuits in a borderless display panel is located below the first row of light-emitting elements, while the remaining row pixel circuits are located above their respective light-emitting elements. That is, the first and second row pixel circuits are situated between the first and second row of light-emitting elements. The area above the first row of light-emitting elements is used as a wiring area for display panel-related circuitry. However, when there are too many circuits to accommodate, or the PPI is too high, the wiring area of ​​a traditional borderless display panel is insufficient to house all these circuits, resulting in a limited wiring area.

[0029] Therefore, to address the above issues, a display panel is proposed that can expand the wiring area of ​​the borderless display panel and is also conducive to realizing a high PPI borderless display panel.

[0030] In one exemplary embodiment, a display panel is provided, comprising a display area, which includes a first arrangement area and a second arrangement area arranged along a column direction. The first arrangement area includes N rows of light-emitting elements and N rows of pixel circuits, with each row of light-emitting elements corresponding to a row of pixel circuits. The first row of pixel circuits and the second row of pixel circuits are respectively located below the corresponding row of light-emitting elements. The second arrangement area includes the target circuit of the display panel and is located above the first row of pixel circuits.

[0031] The display area refers to the theoretical display area (Active Area) of the display panel, which is the entire area of ​​the display panel, including the effective area for displaying images or videos. The theoretical display area describes the technical specifications of the display panel, such as resolution and screen size. The display panel also includes the actual display area (Visible Area), which is the area that the user can ultimately see and the content is actually displayed. The display panel also has inactive areas, such as some non-light-emitting areas at the edges of the screen, which occupy some space; therefore, the actual display area is smaller than the theoretical display area. Pixel circuits are used to generate images or videos, and light-emitting elements are used to provide a light source for the images or videos to be displayed on the display panel. The target circuit of the display panel refers to the circuitry used to enable the display panel to display images or videos.

[0032] Specifically, the display area includes a first arrangement area and a second arrangement area arranged along the column direction. The first arrangement area includes N rows of light-emitting elements and N rows of pixel circuits, with each row of light-emitting elements corresponding to one row of pixel circuits. The first row of pixel circuits is located below the first row of light-emitting elements, and the second row of pixel circuits is located below the second row of light-emitting elements. The second arrangement area includes the target circuit of the display panel and is located above the first row of pixel circuits. By moving the first row of pixel circuits and the second row of pixel circuits towards the center of the display area, the area above the first row of pixel circuits becomes a wiring area, which serves as the second arrangement area, where the target circuit of the display panel is set.

[0033] For example, in this embodiment, the light-emitting element may be, but is not limited to, an LED (Light Emitting Diode), a Micro LED (Micro Light Emitting Diode), and a Mini LED (Mini Light Emitting Diode). Accordingly, the display panel may be, but is not limited to, an LED display panel, a Micro LED display panel, and a Mini LED display panel.

[0034] Optionally, the first arrangement area may include M columns and N rows of pixel units, each row of pixel units including a row of light-emitting elements and a corresponding row of pixel circuits. Each row of pixel units includes M pixel units, and each pixel unit includes sub-pixels of multiple colors. Each color sub-pixel includes a light-emitting element of that color and a corresponding pixel circuit. Each color sub-pixel is driven by a separate pixel circuit. For example, each pixel unit includes three colors of sub-pixels: red sub-pixels, green sub-pixels, and blue sub-pixels. The red sub-pixel includes a red light-emitting element and a corresponding pixel circuit. The green sub-pixel includes a green light-emitting element and a corresponding pixel circuit. The blue sub-pixel includes a blue light-emitting element and a corresponding pixel circuit.

[0035] Furthermore, the multiple color light-emitting elements of each pixel unit and the pixel circuits corresponding to the multiple color light-emitting elements are arranged sequentially along the column direction.

[0036] Furthermore, for each pixel unit, the straight line containing the left boundary of the leftmost pixel circuit in the pixel unit is the first boundary line, and the straight line containing the right boundary of the rightmost pixel circuit is the second boundary line. The multiple light-emitting elements in the pixel unit are located between the first boundary line and the second boundary line.

[0037] Preferably, the left boundary of the leftmost light-emitting element in each pixel unit is located on the first boundary line, and / or, the right boundary of the rightmost light-emitting element in each pixel unit is located on the second boundary line.

[0038] Preferably, the left boundary of the leftmost light-emitting element in each pixel unit and the right boundary of the rightmost light-emitting element in each pixel unit are both located between the first boundary line and the second boundary line.

[0039] By adjusting the positions of multiple light-emitting elements in each pixel unit to between the left edge of the leftmost pixel circuit and the right edge of the rightmost pixel circuit in each pixel unit, sufficient space can be left on the left and / or right edges of the display area for setting up the gate driver on array (GOA) circuit, thereby achieving a borderless display panel.

[0040] In the aforementioned display panel, by setting a first row area and a second row area arranged along the column direction in the display area of ​​the display panel, and placing the first row pixel circuit and the second row pixel circuit in the first row area below the corresponding row light-emitting elements, the first row pixel circuit and the second row pixel circuit are moved towards the middle of the display area, so that the area above the first row pixel circuit becomes a wiring area, i.e., the second row area, thereby expanding the wiring area of ​​the borderless display panel, and at the same time, it is beneficial to realize a borderless display panel with high PPI.

[0041] In one exemplary embodiment, such as Figure 1 The diagram shown is a schematic representation of a display panel structure. The display panel includes a display area AA, a back panel (the actual display area), and a panel along the column direction (...). Figure 1 The first arrangement area 100 and the second arrangement area 200 are arranged in the Y direction (as shown). The first arrangement area 100 includes N rows of light-emitting elements 101 and N rows of pixel circuits 102. The first row of pixel circuits 102 is located on the side of the first row of light-emitting elements 101 closer to the second row of light-emitting elements 101, and the second row of pixel circuits 102 is located on the side of the second row of light-emitting elements 101 closer to the third row of light-emitting elements 101. That is, in this embodiment, the first row of pixel circuits 102 is only placed between the first row of light-emitting elements 101 and the second row of light-emitting elements 101, and the position of the second row of pixel circuits 102 is adjusted to be below the second row of light-emitting elements 101.

[0042] In one optional embodiment described above, in the first arrangement area 100, the third to Nth row pixel circuits 102 are respectively located on the side of the corresponding row light-emitting element 101 closest to the previous row light-emitting element 101. That is, the second and third row pixel circuits 102 are simultaneously located between the second and third row light-emitting elements 101. The fourth to Nth row pixel circuits 102 are respectively located above the corresponding row light-emitting element 101.

[0043] Furthermore, the first arrangement area 100 may include M columns and N rows of pixel units 103, each row of pixel units 103 including a row of light-emitting elements 101 and a row pixel circuit 102 corresponding to that row of light-emitting elements 101. Each row of pixel units 103 includes M pixel units 103, and each pixel unit 103 includes sub-pixels of multiple colors. Each color sub-pixel 104 includes a light-emitting element 101 of that color and a pixel circuit 102 corresponding to that color light-emitting element 101. Each color sub-pixel is driven by a separate pixel circuit 102. For example, each pixel unit 103 includes three colors of sub-pixels: a red sub-pixel 1041, a green sub-pixel 1042, and a blue sub-pixel 1043. The red sub-pixel 1041 includes a red light-emitting element 101 and a pixel circuit 102 corresponding to the red light-emitting element 101. The green sub-pixel 1042 includes a green light-emitting element 101 and a pixel circuit 102 corresponding to the green light-emitting element 101. The blue sub-pixel includes a blue light-emitting element 101 and a pixel circuit 102 corresponding to the blue light-emitting element 101.

[0044] Furthermore, the multi-color light-emitting elements 101 and the corresponding pixel circuits 102 of each pixel unit 103 are all along the column direction ( Figure 1 (As shown in the Y direction) are arranged sequentially.

[0045] In this embodiment, by adjusting the position of the second row of pixel circuits to below the second row of light-emitting elements, it can be ensured that the second row of pixel circuits will not occupy the space in the row direction, thereby expanding the space above the first row of pixel circuits and expanding the wiring area.

[0046] In one alternative embodiment described above, see [reference] Figure 1 The second row of layout area 200 is located between the first row of light-emitting elements 101 and the first row of pixel circuits 102. Since the position of the second row of pixel circuits 102 has been adjusted to be below the second row of light-emitting elements 101, the second row of pixel circuits 102 will not occupy space in the row direction, thereby expanding the space of the second row of layout area 200 above the first row of pixel circuits 102, realizing the setting of a large number of circuits, and also facilitating the realization of high PPI borderless products.

[0047] In one alternative embodiment described above, see [reference] Figure 1 The second row of circuits, 200, includes various types of circuits, such as control circuits, drive circuits, and electrostatic discharge (ESD) protection circuits. Wires represent control circuits, drive circuits, and other lines other than ESD protection circuits. These different circuit types do not overlap, preventing damage to the target circuits in the display panel and preventing short circuits.

[0048] In one exemplary embodiment, such as Figure 2 The diagram shows another structural schematic of the display panel, which includes a display area AA, a back panel (the actual display area), and a section along the column direction (...). Figure 2 The diagram shows a first arrangement area 100 and a second arrangement area 200 arranged in the Y direction. The first arrangement area 100 includes N rows of light-emitting elements 101 and N rows of pixel circuits 102. The pixel circuits 102 in the first row to the i-th row are located on the side of the corresponding row of light-emitting elements 101 closest to the next row of light-emitting elements 101, and the pixel circuits 102 in the (i+1)-N-th row are located on the side of the corresponding row of light-emitting elements 101 closest to the previous row of light-emitting elements 101. Wherein, 3 ≤ i ≤ N-1, and i and N are both integers. That is, in this embodiment, the pixel circuits 102 in the first row to the i-th row are all located below the corresponding row of light-emitting elements 101, and the pixel circuits 102 in the (i+1)-N-th row are all located above the corresponding row of light-emitting elements 101. The pixel circuits 102 in the i-th row and the pixel circuits 102 in the (i+1)-th row are simultaneously located between the i-th row of light-emitting elements 101 and the (i+1)-th row of light-emitting elements 101. Among them, the i-th row pixel circuit 102 is any row of pixel circuit 102 between the third row pixel circuit 102 and the (N-1)-th row pixel circuit 102.

[0049] In this embodiment, only the first row of pixel circuits is placed between the first row of light-emitting elements and the second row of light-emitting elements. The positions of the second row of pixel circuits to the i-th row of pixel circuits are moved sequentially toward the center of the display area, so that the i-th row of pixel circuits and the (i+1)-th row of pixel circuits are simultaneously located between the i-th row of light-emitting elements and the (i+1)-th row of light-emitting elements. Furthermore, the (i+1)-th row of pixel circuits to the N-th row of pixel circuits are all located above the corresponding row of light-emitting elements. This ensures that the i-th row of pixel circuits does not occupy the space in the row direction, thereby expanding the space above the first row of pixel circuits and expanding the wiring area.

[0050] In one alternative embodiment described above, see [reference] Figure 2The second arrangement area 200 is located between the first row of light-emitting elements 101 and the first row of pixel circuits 102. By moving the positions of the second row of pixel circuits 102 to the i-th row of pixel circuits 102 sequentially toward the center of the display area, the i-th row of pixel circuits 102 and the (i+1)-th row of pixel circuits 102 are simultaneously located between the i-th row of light-emitting elements 101 and the (i+1)-th row of light-emitting elements 101. Furthermore, the (i+1)-th row of pixel circuits 102 to the N-th row of pixel circuits 102 are all located above the corresponding row of light-emitting elements 101. This ensures that the i-th row of pixel circuits does not occupy space in the row direction, thereby expanding the space of the second arrangement area 200 above the first row of pixel circuits 102. This allows for the arrangement of a large number of circuits and also facilitates the realization of borderless products with high PPI.

[0051] In one alternative embodiment described above, see [reference] Figure 2 The second row, AA2, includes various types of circuits, such as control circuits, drive circuits, and electrostatic discharge (ESD) protection circuits. Wires represent control circuits, drive circuits, and other lines other than ESD protection circuits. These different circuit types do not overlap, preventing damage to the target circuits in the display panel and preventing short circuits.

[0052] In an exemplary embodiment, the first row of pixel circuits is located on the side of the j-th row of light-emitting elements close to the (j+1)-th row of light-emitting elements, and each two adjacent rows of pixel circuits from the second row to the N-th row are located between each two adjacent rows of light-emitting elements from the (j+1)-th row to the N-th row of light-emitting elements, where 2≤j≤(N-1) / 2, and i and N are both integers.

[0053] Optionally, the row pixel circuits in the first arrangement area can be squeezed towards the center of the display area, and there is no limit to the number of closely arranged row pixel circuits in the first arrangement area, nor is there any limit to the position of the closely arranged row pixel circuits. Specifically, the first row pixel circuits can be placed only between the j-th row of light-emitting elements and the (j+1)-th row of light-emitting elements. Where 2≤j≤(N-1) / 2, and i and N are both integers. The second to Nth row pixel circuits are moved towards the center of the display area, and each adjacent pair of pixel circuits in the second to Nth rows are simultaneously located between each adjacent pair of light-emitting elements, thus leaving edge space above the first row pixel circuits.

[0054] In this embodiment, by placing only the first row of pixel circuits between the j-th row of light-emitting elements and the (j+1)-th row of light-emitting elements, and squeezing the second row of pixel circuits to the N-th row of pixel circuits toward the center of the display area, edge space (above the first row of pixel circuits) can be left as a second arrangement area, further expanding the area that can be wired.

[0055] In one alternative embodiment described above, the second arrangement area is located in at least one of the following positions: between the first row of light-emitting elements and the second row of light-emitting elements; between the second row of light-emitting elements and the first row of pixel circuits.

[0056] Specifically, the second row of light-emitting elements can be located between the first row of light-emitting elements and the second row of light-emitting elements, or between the second row of light-emitting elements and the first row of pixel circuits. Alternatively, it can be located only between the first row of light-emitting elements and the second row of light-emitting elements, or only between the second row of light-emitting elements and the first row of pixel circuits.

[0057] In this embodiment, by adjusting the position of the first row of pixel circuits to be between the j-th row of light-emitting elements and the (j+1)-th row of light-emitting elements, 2≤j≤(N-1) / 2, the space between each two adjacent rows of light-emitting elements from the first row to the (j-1)-th row of light-emitting elements, as well as the space between the first row of pixel circuits and the (j-1)-th row of light-emitting elements, is reserved as the second arrangement area. This ensures that even when there are too many target circuits on the borderless display panel, there is still enough space to set up the target circuits.

[0058] In one optional embodiment described above, the second arrangement area includes various types of circuits, such as control circuits, drive circuits, and electrostatic discharge (ESD) protection circuits. "Wire" refers to lines other than the ESD protection circuit, such as control circuits and drive circuits. The various types of circuits do not overlap, preventing damage to the target circuits in the display panel and preventing short circuits.

[0059] For example, such as Figure 3 The diagram shown is another structural schematic of the display panel, which includes a display area AA, a back panel (the actual display area), and a section along the column direction (...). Figure 3 The diagram shows a first arrangement area 100 and a second arrangement area 200 arranged in the Y direction. The first arrangement area 100 includes N rows of light-emitting elements 101 and N rows of pixel circuits 102. In the diagram, j is 2. The first row of pixel circuits 102 is located between the second row of light-emitting elements 101 and the third row of light-emitting elements 101. The second row of pixel circuits 102 and the third row of pixel circuits 102 are also located between the third row of light-emitting elements 101 and the fourth row of light-emitting elements 101. The fourth row of pixel circuits 102 and the fifth row of pixel circuits 102 are also located between the fourth row of light-emitting elements 101 and the fifth row of light-emitting elements 101. The sixth row of pixel circuits 102 to the Nth row of pixel circuits 102 are located above the corresponding row of light-emitting elements 101.

[0060] Optionally, each row of light-emitting elements and the corresponding row pixel circuit can be arranged adjacent to each other (see [reference]). Figure 1 and Figure 2It can also be set as a separator (see [link]). Figure 3 ).

[0061] See Figure 3 The second arrangement area 200 includes various types of circuits, such as control circuits, drive circuits, and electrostatic discharge (ESD) protection circuits. "Wire" refers to lines other than the ESD protection circuits, such as control circuits and drive circuits. These various circuit types do not overlap, preventing damage to the target circuits in the display panel and preventing short circuits. The second arrangement area 200 is located between the first row of light-emitting elements 101 and the second row of light-emitting elements 101, and between the second row of light-emitting elements 101 and the first row of pixel circuits 102.

[0062] Based on the same inventive concept, this application also provides a display device. The solution provided by this device is similar to the solution described in the above-described display panel. Therefore, the specific limitations of one or more display device embodiments provided below can be found in the limitations of the display panel above, and will not be repeated here.

[0063] In one exemplary embodiment, a display device is provided, such as Figure 4 As shown, the display device may include device 300 and display panel 400 as described in the above embodiments, with display panel 400 covering device 300. Device 300 may contain various components, such as sensors and processing devices, which are not limited in this embodiment. The display device may be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices with display functions, which are not limited in this embodiment.

[0064] In an exemplary embodiment, the display panel includes a display area, which includes a first arrangement area and a second arrangement area arranged along a column direction; the first arrangement area includes N rows of light-emitting elements and N rows of pixel circuits, each row of light-emitting elements corresponds to a row of pixel circuits, and the first row of pixel circuits and the second row of pixel circuits are respectively located below the corresponding row of light-emitting elements; the second arrangement area includes the target circuit of the display panel, and the second arrangement area is located above the first row of pixel circuits.

[0065] In an exemplary embodiment, the first row of pixel circuits is located on the side of the first row of light-emitting elements closer to the second row of light-emitting elements, and the second row of pixel circuits is located on the side of the second row of light-emitting elements closer to the third row of light-emitting elements.

[0066] In an exemplary embodiment, the third row of pixel circuits to the Nth row of pixel circuits are respectively located on the side of the corresponding row light-emitting element that is close to the previous row light-emitting element.

[0067] In an exemplary embodiment, the pixel circuits of the first row to the i-th row are respectively located on the side of the corresponding row light-emitting element that is close to the next row light-emitting element, and the pixel circuits of the (i+1)-N-th row are respectively located on the side of the corresponding row light-emitting element that is close to the previous row light-emitting element; wherein, 3≤i≤N-1, and i and N are both integers.

[0068] In one exemplary embodiment, the second arrangement area is located between the first row of light-emitting elements and the first row of pixel circuits.

[0069] In an exemplary embodiment, the first row of pixel circuits is located on the side of the j-th row of light-emitting elements close to the (j+1)-th row of light-emitting elements, and each two adjacent rows of pixel circuits from the second row to the N-th row are located between each two adjacent rows of light-emitting elements from the (j+1)-th row to the N-th row of light-emitting elements, where 2≤j≤(N-1) / 2, and i and N are both integers.

[0070] In an exemplary embodiment, the second arrangement area is located in at least one of the following positions: between the first row of light-emitting elements and the second row of light-emitting elements; between the second row of light-emitting elements and the first row of pixel circuits.

[0071] In one exemplary embodiment, the target circuit of the display panel includes multiple types of circuits that do not overlap.

[0072] In one embodiment, the various types of circuits include control circuits, drive circuits, and electrostatic discharge protection circuits.

[0073] In this embodiment, since the display area of ​​the display panel in the display device is provided with a first arrangement area and a second arrangement area arranged along the column direction, and the first row pixel circuit and the second row pixel circuit in the first arrangement area are respectively arranged below the corresponding row light-emitting elements, the first row pixel circuit and the second row pixel circuit are moved towards the middle of the display area, so that the area above the first row pixel circuit becomes a wiring area, i.e., the second arrangement area, thereby expanding the wiring area of ​​the borderless display panel, and at the same time, it is beneficial to realize a borderless display device with high PPI.

[0074] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display panel, and input devices. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display panel, and input devices are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. The display panel is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0075] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0076] In one embodiment, a computer device is provided, including the display panel of any of the above embodiments.

[0077] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0078] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0079] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of protection of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these modifications and improvements all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area, which includes a first row area and a second row area arranged along the column direction; The first arrangement area includes N rows of light-emitting elements and N rows of pixel circuits. Each row of light-emitting elements corresponds to a row of pixel circuits. The first row of pixel circuits and the second row of pixel circuits are located below the corresponding row of light-emitting elements. The second arrangement area includes the target circuit of the display panel, and the second arrangement area is located above the first row of pixel circuits.

2. The display panel according to claim 1, characterized in that, The first row of pixel circuits is located on the side of the first row of light-emitting elements closer to the second row of light-emitting elements, and the second row of pixel circuits is located on the side of the second row of light-emitting elements closer to the third row of light-emitting elements.

3. The display panel according to claim 2, characterized in that, The pixel circuits in the third row to the Nth row are located on the side of the corresponding row light-emitting element closest to the light-emitting element in the previous row.

4. The display panel according to claim 1, characterized in that, The pixel circuits in the first row to the i-th row are located on the side of the corresponding row light-emitting element closest to the light-emitting element in the next row, and the pixel circuits in the (i+1)-N-th row are located on the side of the corresponding row light-emitting element closest to the light-emitting element in the previous row; where 3≤i≤N-1, and i and N are both integers.

5. The display panel according to any one of claims 1 to 4, characterized in that, The second arrangement area is located between the first row of light-emitting elements and the first row of pixel circuits.

6. The display panel according to claim 1, characterized in that, The first row of pixel circuits is located on the side of the j-th row of light-emitting elements that is close to the (j+1)-th row of light-emitting elements. The second row of pixel circuits to the N-th row of pixel circuits are located between each pair of adjacent rows of light-emitting elements from the (j+1)-th row to the N-th row of light-emitting elements, where 2≤j≤(N-1) / 2 and i and N are both integers.

7. The display panel according to claim 6, characterized in that, The second arrangement area is located in at least one of the following positions: Between the first row of light-emitting elements and the second row of light-emitting elements; Between the second row of light-emitting elements and the first row of pixel circuits.

8. The display panel according to claim 1, characterized in that, The target circuit of the display panel includes multiple types of circuits, and these multiple types of circuits do not overlap.

9. The display panel according to claim 8, characterized in that, Various types of circuits include control circuits, drive circuits, and electrostatic discharge protection circuits.

10. A display device, characterized in that, The display device includes the display panel according to any one of claims 1 to 9.

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