Method for fabricating multi-layer stack using different chips based on same base chip and different connection structures

Abstract

The application discloses a method for preparing different chips for multilayer stacking based on same basic chips and different connection structures, which comprises the following steps: using a first mask to perform photoetching on a first basic chip to prepare a first connection structure, so as to obtain a first chip; using a second mask to perform photoetching on a second basic chip to prepare a second connection structure, so as to obtain a second chip; repeating the above steps for multiple times until photoetching on an Nth basic chip to prepare an Nth connection structure is completed, so as to obtain an Nth chip; wherein at least one connection structure in the first to Nth connection structures between the first chip, the second chip,..., and the Nth chip is different. Different connection structures are prepared on the same basic chip, so that different chips required for multilayer stacking are prepared, the same connection pads and the basic chip can be used to prepare different chips meeting the requirements of multilayer stacking, a solution is provided for high-density interlayer connection of distinguishable chips, and high-density interlayer interconnection of multilayer stacking is realized.

Description

Technical Field

[0001] This invention relates to photolithography technology, three-dimensional stacked chip integration methods, and multi-layer stacked chips in the field of semiconductor technology, and in particular to a method for preparing different chips for multi-layer stacking based on the same base chip and different connection structures. Background Technology

[0002] As the critical dimensions of integrated circuits have shrunk dramatically, now approaching the nanometer scale, the challenges posed by quantum tunneling leakage current have become increasingly severe. With the reduction in device size, the integration density of a single chip has not increased proportionally according to Moore's Law. Therefore, three-dimensional integration has become one of the core methods for improving chip integration density.

[0003] To address the challenges of 3D integration, common approaches include using TSV (ultra-deep via) and µBUMP (microsphere) technologies to interconnect multiple layers of chips with tens of thousands to hundreds of thousands of nodes, or achieving high-density planar connections through RDL (rewiring hierarchy) of the interposer, interconnecting multiple chips with thousands to tens of thousands of interconnect lines. While these methods can achieve communication bandwidths in the TB / s range, the still large size of µBUMPs poses a significant challenge for achieving even higher-density interconnects.

[0004] High-bandwidth memory (HBM) is a core chip technology urgently needed for artificial intelligence. Its characteristic is the three-dimensional stacking of multiple chips from the same base chip. Currently, it is mainly solved using the aforementioned traditional high-performance packaging technologies. However, this presents serious challenges for future higher-level stacking and higher-bandwidth connections. The challenge stemming from the inability to proportionally increase integration density as devices shrink makes it difficult to increase the number of devices per chip according to Moore's Law. Separating and stacking memory chips from computing chips, or even stacking multiple memory chips and computing chips from the same base chip, also urgently requires technologies with higher stacking density and less parasitic interconnection.

[0005] In existing technology 1, a wafer-level packaging method for an HBM packaging structure is disclosed (Invention Patent, 2023, Zhang Li, Guo Hongyan et al., CN117712033A). This method uses a wafer-level fan-out process to place solder joints on the sides of the memory chip and logic chip, and replaces the TSV connection of the original packaging structure with a metal pillar channel that runs through all chip modules on the chip side, thus simplifying the process. However, although this prior art simplifies the TSV connection process, it still uses a solder joint structure with relatively large solder joint sizes, which limits the high-density packaging of the chip and results in relatively large parasitic parameters in the packaging structure.

[0006] In prior art 2, a packaging structure and its formation method are disclosed (Invention Patent, 2025, Pan Zhijian, Wang Bu et al., CN120015715A). The packaging structure includes: a substrate; a packaging component bonded to the substrate; a cap disposed above the packaging component and the substrate; and an interface structure sandwiched between the packaging components. The packaging component includes: a first die; a second die laterally spaced from the first die by an underfill; and a molding compound adjacent to the first and second dies. The interface structure includes: an adhesive layer disposed above the underfill and the molding compound; and a thermal interface material (TIM) layer located above the adhesive layer, the first die, and the second die. However, in this prior art, the first and second dies are interconnected using an interposer, and the chip and the interposer are connected using microbumps. Both are relatively large, making it difficult to increase the connection density and reduce the parasitic parameters of the connection structure.

[0007] In prior art 3, a packaging structure and a high-bandwidth memory (HBM) device are disclosed (Utility Model Patent, 2023, Zhuang Xueli, Huang Wenduo, CN220774364U). This packaging structure includes: a first substrate including logic transistors; a first interconnect structure on the first substrate; a first bonding layer on the first interconnect structure; a second bonding layer on and bonded to the first bonding layer; a second interconnect structure above the second bonding layer; a second substrate above the second interconnect structure, the second substrate including a memory device; a protective film on the second substrate; a first through-path extending through a portion of the second interconnect structure and a first portion of the second substrate; and a second through-path extending through the protective film and a second portion of the second substrate to contact the top surface of the first through-path, wherein the first diameter of the first through-path is larger than the second diameter of the second through-path. However, although this prior art reduces the connection size through the second through-path, the size of the first through-path is not reduced, and the connection density and parasitic behavior cannot overcome the limitations of the first through-path size, thus no significant improvement is achieved. Summary of the Invention

[0008] Therefore, embodiments of the present invention provide a method for fabricating different chips for multi-layer stacking based on the same base chip. This method utilizes the same base chip and only changes the connection structure to achieve the fabrication of different chips for multi-layer stacking, thereby solving at least one problem existing in the prior art.

[0009] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0010] A method for fabricating multilayer stacked chips based on the same base chip, wherein the method comprises:

[0011] A first interconnect structure is fabricated on a first base chip using a first mask to obtain a first chip;

[0012] A second connection structure is fabricated on a second base chip using photolithography with a second mask to obtain a second chip.

[0013] Repeat the above steps multiple times until the Nth interconnect structure is fabricated on the Nth base chip using the Nth mask, so as to obtain the Nth chip.

[0014] Among them, in the first chip, the second chip, ..., the Nth chip, at least one of the connection structures between the first to the Nth chips is different;

[0015] The first chip, the second chip, ..., the Nth chip are also provided with connection pads; wherein the connection pads are made using the same mask, and at least a portion of the connection pads are connected to the connection structure.

[0016] In some embodiments, the connection structure is one of the following:

[0017] Connection holes connect the connection pads to the interior of the corresponding chip;

[0018] Ultra-deep holes;

[0019] A combined hole, comprising an ultra-deep hole and a connecting hole communicating with the ultra-deep hole.

[0020] In some embodiments, the connecting holes in the combined holes are located on the front or back of the ultra-deep holes.

[0021] In some embodiments, the thermal deformation coefficient of the connecting holes in the combined holes is greater than that of the ultra-deep holes in the same combined holes.

[0022] In some embodiments, the ultra-deep via is formed only in the semiconductor layer of the corresponding chip, or in the semiconductor layer but not reaching the device layer.

[0023] In some embodiments, the first chip, the second chip, ..., the Nth chip are further provided with an easy bonding layer, which is used to form a tight connection when the first chip, the second chip, ..., the Nth chip are subjected to low-temperature bonding.

[0024] In some embodiments, when the ultra-deep via is used for via connection, the ultra-deep via for via connection further includes an ultra-deep via enable connection structure, which controls whether the ultra-deep via is connected to the inside of the chip via a signal.

[0025] In some embodiments, the connector pad is an etchable material, or the connector pad is a removable sacrificial structure.

[0026] In one or more specific embodiments, the method provided by this invention fabricates different interconnect structures on the same base chip, thereby creating different chips required for multi-layer stacking. Different chips meeting the requirements of multi-layer stacking can be fabricated using the same interconnect pads and base chip, providing a solution for high-density interlayer interconnects that are distinguishable within the same chip, achieving high-density interlayer interconnects in multi-layer stacking. Through this invention, combined with direct bonding of interconnect pads or ultra-deep via etching processes, the problems of excessively large interconnect size, low interconnect density, and excessively large parasitic parameters caused by existing 3D stacking using µBUMP or RDL interconnect structures can be overcome. The size of the interlayer interconnect structure can be reduced to 1µm or even smaller, significantly increasing the storage capacity and bandwidth of currently urgently needed high-bandwidth memory chips. Simultaneously, since this invention uses the same base chip but changes a single photolithography process step to create different chips, the manufacturing cost of different chips can be significantly reduced. Attached Figure Description

[0027] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0028] The structures, proportions, sizes, etc. illustrated in this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0029] Figure 1 This is an example diagram illustrating the method provided by the present invention for achieving multi-layer stacking of different chips based on the same base chip but with different interconnection structures.

[0030] Figure 2 Examples of thinned structures of chips with different multilayer stacking based on the same base chip, obtained through different connection structures, provided by the present invention; wherein... Figure 2 (A) is a schematic diagram showing how to differentiate between different chips based on the same underlying chip without ultra-deep vias using interconnect holes; Figure 2 (B) is a schematic diagram showing how to use interconnect holes to differentiate between different chips based on the same underlying chip with ultra-deep holes; Figure 2 (C) is a schematic diagram illustrating the use of ultra-deep vias to differentiate different chips from the same basic chip with connecting holes; Figure 2The diagram in (D) illustrates how different chips can be distinguished by changing the connecting holes (combined holes) on the front side of the same basic chip with connecting holes and ultra-deep holes. Figure 2 The middle (E) diagram is a schematic diagram of different chips by changing the connecting holes (combined holes) on the back side of the same basic chip with connecting holes and ultra-deep holes; Figure 2 The middle (F) diagram is the second illustration of how to distinguish different chips based on the same basic chip with connecting holes and ultra-deep holes by changing the connecting holes (combined holes) on the back side.

[0031] Figure 3 This is an example of a chip bonding layer structure after thinning of the connection pad and connection structure provided by the present invention; wherein, Figure 3 (A) is a schematic diagram of an easily bonded layer with connection holes below the connecting pad. Figure 3 (B) is a schematic diagram of an easily bonded layer in a chip structure without ultra-deep holes;

[0032] Figure 4 This is a schematic diagram of a three-dimensional stacked chip fabricated using a method for achieving multi-layer stacking with different chips based on the same base chip but with varying interconnect structures, as provided in this invention; wherein, Figure 4 (A) represents a three-dimensional stacked chip with the same basic chip formed by changing the way the connection holes are made; Figure 4 (B) shows a three-dimensional stacked chip with different chip types formed by changing the method of ultra-deep hole formation of the same base chip;

[0033] Figure 5 The diagram shows an example of a three-dimensional stacked chip formed by altering the connection holes to create a different chip with the same basic chip (without ultra-deep holes) as provided by the present invention, and by etching ultra-deep holes after stacking the chips. Detailed Implementation

[0034] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0035] To address the shortcomings of existing technologies, this invention primarily solves the problem of distinguishing identical base chips in high-density interlayer interconnects of 3D stacked chips. By changing the steps of a single-hole photolithography process, N base chips with the same structure can be distinguished, achieving the goal of providing low-cost, distinguishable chip particles (such as HBM (High Bandwidth Memory) chip storage particles, CPU chip cache, or near-field memory chip particles) for high-density interlayer interconnects in 3D stacked chips. By combining this with direct bonding to interconnect pads or ultra-deep via etching processes, the size of the interlayer interconnect structure can be reduced to 1µm or even smaller, thereby increasing inter-chip bandwidth and improving interlayer interconnect density.

[0036] In one specific embodiment, the present invention provides a method for fabricating multilayer stacked chips by fabricating different interconnect structures on the same base chip. The method is based on N base chips with the same structure, and includes:

[0037] A first interconnect structure is fabricated on a first base chip using a first mask to obtain a first chip;

[0038] A second connection structure is fabricated on a second base chip using photolithography with a second mask to obtain a second chip.

[0039] Repeat the above steps multiple times until the Nth interconnect structure is fabricated on the Nth base chip using the Nth mask, so as to obtain the Nth chip.

[0040] Among the first chip, the second chip, ..., the Nth chip, at least one of the connection structures between the chips is different.

[0041] The first chip, the second chip, ..., the Nth chip are also provided with connection pads; wherein the connection pads are made using the same mask, and at least a portion of the connection pads are connected to the connection structure.

[0042] It should be understood that the above-mentioned connection structure can be a single connecting hole, a single ultra-deep hole, or a combination of a connecting hole and an ultra-deep hole. The connecting hole may also be a combination of multiple connecting holes (including but not limited to the hole structure of conventional chips) to connect the connecting pad to the interior of the corresponding chip (a common method in small-size process nodes), or even a combination of multiple internal interconnects and multiple connecting holes to connect the connecting pad to the interior of the corresponding chip. During fabrication, only the connecting holes connected to the connecting pads need to be fabricated. If it is convenient for process implementation, other connecting holes in the combination can be selected to implement the invention, or one layer can be selected to connect the internal interconnects of two connecting hole layers in the combination to implement the invention (i.e., controlling the on / off state of the combination connecting hole by fabricating the interconnects), and this is not limited.

[0043] For the fabrication of combined vias formed by connecting vias and ultra-deep vias, either the connecting vias or the ultra-deep vias can be fabricated. If ultra-deep vias are fabricated, the connecting vias of the base chip must be identical; if connecting vias are fabricated, the ultra-deep vias of the base chip must be identical. Similarly, connection vias may be formed by multiple connection vias forming combined connection vias, especially for connecting vias on the front side of the chip. These combined connecting vias may also be formed by multiple connecting vias (including but not limited to those using conventional chip hole structures), or even by multiple internal interconnects and multiple connecting vias forming combined connecting vias. During fabrication, only the connecting vias connected to the connection pads need to be fabricated (example of connecting vias on the connection pad surface). If it is convenient for process implementation, other connecting vias in the combined connecting vias can be selected to implement this invention, or the internal interconnects connecting two connecting via layers in the combined connecting vias can be selected to implement this invention (i.e., controlling the on / off state of the combined connecting vias by fabricating connection lines). This is not limited.

[0044] Specifically, such as Figure 1 As shown, a method for implementing multi-layer stacking of different chips based on the same base chip 10 by changing the interconnection structure includes N base chips 10 with the same structure, and:

[0045] The first connection structures 3111 and 3112 are fabricated by photolithography on the first base chip using the first mask to obtain the first chip 101.

[0046] By replacing the second mask, the second connection structures 3121 and 3122 are fabricated by photolithography on the second base chip to obtain the second chip 102.

[0047] Repeat the above steps multiple times until the Nth basic chip is successfully photolithographically fabricated to create the Nth interconnect structure 31N1 and 31N2, thus obtaining the Nth chip 10N.

[0048] The first chip 101, the second chip 102, ..., the Nth chip 10N, at least one of the connection structures between the first to the Nth chips is different.

[0049] It should be understood that, in Figure 1 In the figures, reference numerals 3111 and 3112 both represent the first connecting structure. Different reference numerals are used to distinguish the first connecting structures when they are in different positions. Reference numerals 3121 and 3122 both represent the second connecting structure. Different reference numerals are used to distinguish the second connecting structure when they are in different positions. Similarly, reference numerals 31N1 and 31N2 both represent the Nth connecting structure. Different reference numerals are used to distinguish the Nth connecting structure when they are in different positions.

[0050] The number and layout of the connection structures described are merely illustrative examples illustrating the differences between the connection structures of various chips, and are not actually limited, as long as the design meets the chip stacking requirements. It should be noted that in typical thick semiconductor chip stacking, N chips are stacked sequentially from back to front from chip 1 to N, in which case connection structures in the same position are connected together, while those in different positions are not. However, for thin chips, due to the difficulty of clamping, a substrate is needed as a carrier to facilitate clamping, which may result in front-back, front-front, or back-back stacking. This is mainly to speed up stacking efficiency and ensure manufacturability. Therefore, the position of the connection structures needs to be considered in advance during fabrication to address different rotation, mirroring, and other placement issues.

[0051] In some embodiments, the connection structure is one of the following:

[0052] Connection holes connect the connection pads to the interior of the corresponding chip;

[0053] Ultra-deep holes;

[0054] A combined hole, comprising an ultra-deep hole and a connecting hole communicating with the ultra-deep hole.

[0055] The connecting holes in the combined holes are located on the front or back of the ultra-deep holes.

[0056] Specifically, the aforementioned connection structure involves a connection pad connecting to a via, or an ultra-deep via, or a combination of vias inside the chip. The combination of vias includes an ultra-deep via and a connecting hole connected to it. The connecting hole in the combination of vias can be located on either the front or back side of the ultra-deep via.

[0057] The thermal deformation coefficient of the connecting holes in the combined vias is greater than that of the ultra-deep vias in the same combined vias. The aforementioned ultra-deep vias are only formed in the semiconductor layer of the corresponding chip, or are formed in the semiconductor layer but do not reach the device layer.

[0058] It should be understood that, regarding the specific connection structure to be selected, since connecting holes, ultra-deep vias, or combined vias coexist, are actually short-circuited together on the same chip, the choice of which structure to use for differentiating different chips from the same basic chip in this invention can be made based on actual needs. Specifically, for example... Figure 2 As shown, Figure 2 (A) is a chip without ultra-deep holes. This chip structure can be stacked and then etched with ultra-deep holes. It is distinguished by the connection hole 321 that is connected to the inside of the chip. The connection pad 3011 is connected to the inside of the chip through the connection hole 321, while the connection pad 3012 has no connection hole and is not connected to the inside. Figure 2 Image (B) shows an example of a base chip with ultra-deep vias, although both are distinguished by the connection holes 321 that connect to the inside of the chip. Figure 2 The (B) chip structure is mainly used for direct bonding connections, and no further etching of ultra-deep holes is required after stacking. Figure 2 In the middle (C), an ultra-deep hole 331 is used to distinguish different chips from the same basic chip. If there is an ultra-deep hole 331, it can form a connection with other chips to transmit signals to this chip or transmit signals from this chip to other chips. If there is no ultra-deep hole 331, it is impossible to transmit signals to this chip or transmit signals from this chip to other chips through the ultra-deep hole of this chip. Figure 2 Examples (D), (E), and (F) illustrate structures that differentiate the same base chip 10 into different chips by changing the connecting via 341 on the front side of the ultra-deep via 331 and the connecting via 351 on the back side of the ultra-deep via 331 in the combined via. The connecting vias 341 and 351 connected by the ultra-deep via 331 have several drawbacks. Since the ultra-deep via 331 is typically large, retaining large vias in the device layer and metal interconnect layer affects device fabrication and / or the interconnect layout and wiring between devices. Therefore, the ultra-deep via can be fabricated only in the semiconductor layer, or in the semiconductor layer without reaching the device layer. Furthermore, for direct bonding processes in chip stacking, the thermal deformation coefficient of the ultra-deep via needs to be comparable to that of the chip's semiconductor material to reduce the mismatch between the ultra-deep via's deformation under high and low temperature environments and the large deformation caused by its large size, which could lead to stress-induced device failure. However, since bonding requires materials with a high thermal deformation coefficient, reliability and bonding feasibility are contradictory. Solving this problem requires that the thermal deformation coefficient of the connecting vias in the combined via be greater than that of the ultra-deep vias in the same combined via. Figure 2 In the middle (D), the chips are distinguished by changing the connecting hole 341 on the front side; Figure 2 In the case of direct bonding and stacking of traditional chips, since the chips have already been made with ultra-deep holes, they can be distinguished by making deformation holes (connecting holes) on the back side. On the one hand, this can distinguish between chips, and on the other hand, it can solve the need for the connecting holes required for direct bonding to deform at a lower temperature for solid-to-solid bonding. Figure 2 In the case of thinner semiconductor chips (E), to reduce the impact of the external environment on the chip, an isolation layer 96 can be further fabricated on the back side to isolate the influence of the external environment, such as... Figure 2 As shown in (F); of course, in practice, an isolation layer can also be fabricated on the front side for environmental protection. In addition, in the fabrication of specific connection structures, besides etching the connection structures from the front side, ultra-deep vias, ultra-deep vias in combination vias, and / or connecting vias can also be fabricated from the back side of the thinned chip.

[0059] It should be understood that, in Figure 2 In the attached drawings, reference numerals 341 and 351 both indicate connecting holes in the combined holes. The two connecting holes are located at different positions relative to the ultra-deep holes, and different reference numerals are used to distinguish them.

[0060] The first chip, the second chip, ..., the Nth chip are also provided with connection pads; wherein the connection pads are made using the same mask, and at least a portion of the connection pads are connected to the connection structure.

[0061] In some embodiments, the first chip, the second chip, ..., the Nth chip are further provided with an easy-bonding layer. The easy-bonding layer is used to form a tight connection when the first chip, the second chip, ..., the Nth chip are subjected to low-temperature bonding.

[0062] Specifically, as mentioned above, the first chip, second chip, ..., Nth chip also includes the fabrication of connection pads. Inter-chip connections, especially wafer-level bonding, can have errors on the order of micrometers (µm), resulting in significant alignment deviations. Connection pads larger than the vias can be fabricated to mitigate the effects of alignment deviations. It should be noted that the connection pads on the first chip, second chip, ..., Nth chip are fabricated using the same mask, and at least a portion of each connection pad is connected to the connection structure. That is, this invention uses different connection structures to distinguish between the first chip, second chip, ..., Nth chip, without needing to differentiate the fabrication of the connection pads; the connection pads for each chip are identical. Furthermore, since the purpose of the connection pads is to address alignment deviation issues, if the size of ultra-deep vias, combined vias, or connecting vias is large enough to overcome the effects of alignment deviations, the connection pads can also be fabricated inside the chip as connecting lines, forming connections between the vias and ultra-deep or combined vias. In this case, the bonding connection can be directly completed by the ultra-deep or combined vias.

[0063] Furthermore, to enhance the bonding strength of the chips, the first chip, the second chip, ..., the Nth chip, also include an easy-bonding layer. A specific example is shown below. Figure 3 As shown, Figure 3 Figure (A) illustrates a structure with connection holes beneath the connection pads. This structure can be stacked to form a three-dimensional integrated circuit using a direct bonding method. Vertical electrical connections can be formed between the connection pads and connection holes through one or more bonding methods, such as connection pad-to-connection pad, connection pad-to-connection hole, and connection hole-to-connection hole. To achieve a good connection effect, easy-bonding layers 511 and 541 can be fabricated on the connection pads 3011 and 3012, easy-bonding layer 521 can be fabricated on the connection hole 331, and easy-bonding layers 531 and 551 can be fabricated in the non-connection areas. During bonding, the easy-bonding layers are activated (e.g., by plasma activation, sulfuric acid activation, etc.), and then bonded after appropriate heating (e.g., 200℃~300℃) and pressure to form a rigid connection and a better connection effect. Figure 3(B) shows a chip structure without ultra-deep holes. This chip can be etched to create ultra-deep holes after three-dimensional stacking and bonding to form vertical connections. Figure 3 The structure shown in Figure (B) involves fabricating a non-connection area easy-bond layer 531 on the front side and a non-connection area easy-bond layer 551 on the back side. After bonding via one or more methods (front-to-back, front-to-front, back-to-back), ultra-deep vias are etched to form the connection. Although the easy-bond layers 531 are fabricated on the connection pads 3011 and 3012, further etching after bonding will not affect the connection formed between the chips via the connection pads. The easy-bond layers on the front and back sides can be fabricated together after chip thinning, or the front easy-bond layer can be fabricated first, followed by the back easy-bond layer after chip thinning, depending on the actual process requirements.

[0064] It should be understood that, in Figure 3 In the figures, reference numerals 3011 and 3012 both represent connecting pads, and different reference numerals are used to distinguish the different positions of the connecting pads; reference numerals 511, 521, and 541 all represent easily bonded layers in the connecting areas, and different reference numerals are used to distinguish the different positions of the easily bonded layers in each connecting area; reference numerals 531 and 551 both represent easily bonded layers in the non-connecting areas, and different reference numerals are used to distinguish the different positions of the easily bonded layers in each non-connecting area.

[0065] In some embodiments, when the ultra-deep via is used for via connection, the ultra-deep via for via connection further includes an ultra-deep via enable connection structure, which controls whether the ultra-deep via is connected to the inside of the chip via a signal.

[0066] Specifically, Figure 4 This invention provides an example of a three-dimensional stacked chip fabricated using a method that modifies the interconnection structure based on the same base chip to achieve multi-layer stacking with different chips. Figure 4In section (A), differentiated chips based on the same base chip are formed by changing the way the connection pads connect to the internal connection holes of the chip. For example, the connection pads connecting chip 401 to ultra-deep via 3314 are not connected to the internal connection holes of the chip; the connection pads connecting chip 402 to ultra-deep via 3326 are not connected to the internal connection holes of the chip; the connection pads connecting chip 403 to ultra-deep vias 3335 and 3336 are not connected to the internal connection holes of the chip. Thus, if an external signal is sent from each connection pad of chip 401, chips 401, 402, and 403 connected to ultra-deep via 3311 can all transmit signals; chips 402 and 403 connected to ultra-deep via 3314 can transmit signals, while chip 401 is not connected; for chips connected to ultra-deep via 3315, chips 401 and 402 can transmit signals, while chip 403 cannot; for chips connected to ultra-deep via 3316, chip 401 can transmit signals, while chips 402 and 403 cannot. Thus, although chips 401, 402, and 403 are based on the same chip, they can still be distinguished by using different connection holes when stacked.

[0067] Figure 4 Image (B) illustrates differentiated chips formed using different ultra-deep vias (or connecting vias that connect to the ultra-deep via on the front and / or back sides), sharing the same basic chip. Figure 4 Unlike (A), the connection pads of each chip and the connection holes that connect the connection pads to the inside of the chip are all the same. For example, if the ultra-deep vias connecting chip 401 to connection pads 3013 and 3016 are not fabricated, the ultra-deep vias connecting chip 402 to connection pads 3026, etc., are not fabricated, and the ultra-deep vias connecting chip 403 to connection pads 3036, etc., are not fabricated. Thus, assuming that external signals are sent from the connection pads of chip 401, chips 401, 402, and 403 connected to ultra-deep via 3311 can all transmit signals; for chips connected to ultra-deep via 3315, chips 401 and 402 can transmit signals, but chip 403 cannot; connection pad 3016 has no ultra-deep vias connecting to chip 402, so only chip 401 can transmit signals through connection pad 3016, while chips 402 and 403 cannot. Thus, although chips 401, 402, and 403 are based on the same chip, they can still be distinguished by stacking them up using different ultra-deep holes.

[0068] It needs to be explained that, for Figure 4In the (B) structure, such as the chip connected to the ultra-deep via 3314, it is desired that chips 402 and 403 can transmit signals, but not chip 401. That is, it is desired that the ultra-deep via 3314 is a via connection structure, and it is not desired that it forms a signal transmission connection with the internal structure of the chip. Since the connection pads of each chip and the connection holes connecting the connection pads to the internal structure of the chip are the same in this method, under normal circumstances, the ultra-deep via 3314 can form a signal transmission connection with the internal structure of chip 401. To solve this problem, when the ultra-deep via is used for via connection, the ultra-deep via for via connection also includes an ultra-deep via enabling connection structure. This ultra-deep via enabling connection structure enables whether the ultra-deep via is connected to the internal structure of the chip through signal control. For example... Figure 4 In section (B), the connector pad 3013 is fabricated as an enable connection structure and enables connection with the connector pad 3314. The enable signal from the connector pad 3013 controls whether the ultra-deep via 3314 is connected to the inside of the chip 401. That is, although 3314 is connected to the inside of the chip, the signal from the connector pad 3013 logically disconnects the ultra-deep via 3314 from the inside of the chip 401. Since the connector pad 3013 does not have an ultra-deep via connected to it to further transmit the signal to chips 402 and 403, the enable signal does not affect the connection of ultra-deep vias 3324 and 3334 to the inside of chips 402 and 403, thus solving the problem of the ultra-deep via 3314 forming a via.

[0069] It should be understood that, in Figure 4 In the attached figures, reference numerals 3311, 3314, 3315, 3316, 3324, 3325, 3326, 3334, 3335, and 3336 all represent ultra-deep vias. Different reference numerals are used to distinguish the ultra-deep vias based on their location. Reference numerals 401, 402, and 403 all represent chips. Different reference numerals are used to distinguish the chips based on their location. Reference numerals 3013, 3016, 3026, and 3036 all represent connector pads. Different reference numerals are used to distinguish the connector pads based on their location.

[0070] In some embodiments, the connector pad is an etchable material, or the connector pad is a removable sacrificial structure.

[0071] Specifically, Figure 5 This example illustrates a method of forming vertical connections through ultra-deep hole etching after stacking three-dimensional chips. Figure 5As shown, the connector pads used here are etchable or removable sacrificial structures. Examples include connector pads 3031, 3012, 3022, and 3032. If etchable, ultra-deep via (UTV) etching creates holes with good verticality. For instance, connector pad 3012 forms a hole in the center. After UTV etching, sidewall deposits are cleaned, and UTV connection material (such as copper or tungsten) is deposited. This material connects to the connector pads of each chip through the UTV. By changing the way the connector pads connect to the internal holes of the chip, differentiated chips with the same basic chip are created. Figure 5 As shown, external connection signals are introduced into the stacked 3D chips through external connection pad 373 and transmitted into the stacked 3D chips through ultra-deep via 3331. Since connection pads 3011 and 3021 are not connected to the internal vias of the chips, external connection pad 373 only transmits signals to chip 403. However, connection pads 3012, 3022, and 3032, which are connected to external connection pad 374, are all connected to the internal vias of the chips. Therefore, external connection pad 374 can transmit signals to chips 401, 402, and 403. Furthermore, taking a 3D stacked integrated circuit as an example, to reduce metal etching contamination of the chip, non-conductive sacrificial materials can be used to fabricate sacrificial connection pads. These sacrificial connection pads are then removed during ultra-deep via etching using isotropic or near-isotropic methods, and further material is grown to fill the gaps, forming a better electrical connection with the ultra-deep via. Specifically, the connecting pads 3011, 3021, 3031, 3012, 3022, and 3032 are completely removed during the etching of ultra-deep vias 3331 and 3332. Connecting material is then used to fill the vias during the formation of the electrical connections between them, achieving the effect of connecting the ultra-deep vias to the chip's interior. Furthermore, to obtain good isolation and reduce environmental impact (such as moisture and sodium ion contamination), insulating material 92 and environmentally friendly isolation materials 93 and 95 (understandably, there are two types of isolation materials, labeled 93 and 95 in the attached diagram) can be deposited during the fabrication process to protect the stacked chip.

[0072] It should be understood that, in Figure 5 In the attached figures, reference numerals 3011, 3021, 3031, 3012, 3022, and 3032 all represent connecting pads. Different reference numerals are used to distinguish the connecting pads depending on their location. Reference numerals 373 and 374 both represent external connecting pads. Different reference numerals are used to distinguish the external connecting pads depending on their location. Reference numerals 3331 and 3332 both represent ultra-deep holes. Different reference numerals are used to distinguish the ultra-deep holes depending on their location.

[0073] In one or more specific embodiments, the method provided by this invention fabricates different interconnect structures on the same base chip, thereby creating different chips required for multi-layer stacking. Different chips meeting the requirements of multi-layer stacking can be fabricated using the same interconnect pads and base chip, providing a solution for high-density interlayer interconnects that are distinguishable within the same chip, achieving high-density interlayer interconnects in multi-layer stacking. Through this invention, combined with direct bonding of interconnect pads or ultra-deep via etching processes, the problems of excessively large interconnect size, low interconnect density, and excessively large parasitic parameters caused by existing 3D stacking using µBUMP or RDL interconnect structures can be overcome. The size of the interlayer interconnect structure can be reduced to 1µm or even smaller, significantly increasing the storage capacity and bandwidth of currently urgently needed high-bandwidth memory chips. Simultaneously, since this invention uses the same base chip but changes a single photolithography process step to create different chips, the manufacturing cost of different chips can be significantly reduced.

[0074] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solution of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating multilayer stacked different chips based on the same base chip, characterized in that, Based on N basic chips with the same structure, the method includes: A first interconnect structure is fabricated on a first base chip using a first mask to obtain a first chip; A second connection structure is fabricated on a second base chip using photolithography with a second mask to obtain a second chip. Repeat the above steps multiple times until the Nth interconnect structure is fabricated on the Nth base chip using the Nth mask, so as to obtain the Nth chip. Among them, in the first chip, the second chip, ..., the Nth chip, at least one of the connection structures between the first to the Nth chips is different; The first chip, the second chip, ..., the Nth chip are also provided with connection pads; wherein the connection pads are made using the same mask, and at least a portion of the connection pads are connected to the connection structure. The connection structure includes a combination hole, and the connection structure is used to distinguish chips for the same basic chip. The combined via includes an ultra-deep via and a connecting via communicating with the ultra-deep via. The connecting via is located on the front or back of the ultra-deep via. The thermal deformation coefficient of the ultra-deep via is comparable to that of the chip semiconductor material. The thermal deformation coefficient of the connecting via is greater than that of the ultra-deep via in the same combined via.

2. The method for fabricating multilayer stacked different chips based on the same base chip according to claim 1, characterized in that, Ultra-deep vias are either only formed in the semiconductor layer of the corresponding chip, or formed in the semiconductor layer but not reaching the device layer.

3. The method for fabricating multilayer stacked different chips based on the same base chip according to claim 1, characterized in that, The first chip, the second chip, ..., the Nth chip are further provided with an easy bonding layer, which is used to form a tight connection when the first chip, the second chip, ..., the Nth chip are bonded at low temperature.

4. The method for fabricating multilayer stacked different chips based on the same base chip according to claim 3, characterized in that, When the ultra-deep via is used for via connection, the ultra-deep via for via connection also includes an ultra-deep via enable connection structure, which controls whether the ultra-deep via is connected to the inside of the chip via a signal.

5. The method for fabricating multilayer stacked different chips based on the same base chip according to claim 1, characterized in that, The connector pad is made of an etchable material, or the connector pad is a removable sacrificial structure.

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