Pixel driving circuit, driving method thereof and display device

Abstract

The invention discloses a pixel driving circuit, a driving method thereof and a display device. The pixel driving circuit comprises a driving control sub-circuit, a reset sub-circuit, a driving sub-circuit and a light-emitting control sub-circuit, the light-emitting control sub-circuit is configured to provide a signal of a first power line (VDD) to a second node (N2) and provide a signal of a third node (N3) to a fifth node (N5) under the control of signals of a first light-emitting signal line (EM1) and a second light-emitting signal line (EM2); the display device includes a first control unit electrically connected to a first light emitting signal line (EM1) and a second light emitting signal line (EM2), respectively, configured to provide signals to the first light emitting signal line (EM1) and the second light emitting signal line (EM2), a period of time in which the first control unit provides the active level signal to the first light emitting signal line (EM1) and a period of time in which the active level signal is provided to the second light emitting signal line (EM2) do not partially overlap.

Description

Pixel driving circuit and driving method thereof, and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, in particular to a pixel driving circuit and driving method thereof, and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of protection of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit arranged in a display device, comprising: a driving control sub-circuit, a reset sub-circuit, a driving sub-circuit, and a light-emitting control sub-circuit.

[0006] The reset sub-circuit is electrically connected with at least one reset signal line, a first initial signal line, a second initial signal line, a reference signal line, a second node, a fourth node, and a fifth node, respectively, and is configured to provide the second node with a signal of the reference signal line, the fourth node with a signal of the first initial signal line, and the fifth node with a signal of the second initial signal line under the control of a signal of the at least one reset signal line.

[0007] The driving control sub-circuit is electrically connected with at least two scan signal lines, a data signal line, a first power supply line, a first node, a second node, a third node, and a fourth node, respectively, and is configured to provide the second node with a signal of the data signal line and the first node with a signal of the third node or the fourth node under the control of signals of the at least two scan signal lines and the first power supply line.

[0008] The driving sub-circuit is electrically connected with the first node, the second node, and the third node, respectively, and is configured to provide the third node with a driving signal under the control of signals of the first node and the second node.

[0009] The light emitting control sub-circuit is electrically connected with the first light emitting signal line, the second light emitting signal line, the first power supply line, the second node, the third node and the fifth node respectively, and is configured to provide a signal of the first power supply line to the second node and a signal of the third node to the fifth node under control of signals of the first light emitting signal line and the second light emitting signal line.

[0010] The display device comprises a first control unit electrically connected with the first light emitting signal line and the second light emitting signal line respectively and configured to provide signals to the first light emitting signal line and the second light emitting signal line, and a time period during which the first control unit provides an effective level signal to the first light emitting signal line and a time period during which the first control unit provides an effective level signal to the second light emitting signal line are partially non-overlapping.

[0011] In an exemplary embodiment, the driving sub-circuit comprises a third transistor, and the light emitting control sub-circuit comprises a fifth transistor and a sixth transistor.

[0012] The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node.

[0013] The control electrode of the fifth transistor is electrically connected with the first light emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node.

[0014] The control electrode of the sixth transistor is electrically connected with the second light emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fifth node.

[0015] In an exemplary embodiment, the display device comprises a plurality of row pixel driving circuits, and a second light emitting signal line connected with an i-th row pixel driving circuit and a first light emitting signal line connected with an i+1-th row pixel driving circuit are the same signal line.

[0016] In an exemplary embodiment, the start time of a time period during which the first control unit provides an effective level signal to the first light emitting signal line is earlier than the start time of a time period during which the first control unit provides an effective level signal to the second light emitting signal line, and the end time of the time period during which the first control unit provides an effective level signal to the first light emitting signal line is earlier than the end time of the time period during which the first control unit provides an effective level signal to the second light emitting signal line.

[0017] In an exemplary embodiment, the at least one reset signal line comprises a first reset signal line, and the reset sub-circuit comprises a first transistor, a seventh transistor and a ninth transistor.

[0018] The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the first initial signal line, and the second electrode of the first transistor is electrically connected with the fourth node;

[0019] The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the second initial signal line, and the second electrode of the seventh transistor is electrically connected with the fifth node;

[0020] The control electrode of the ninth transistor is electrically connected with the first reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node;

[0021] The display device further includes a second control unit electrically connected with the first reset signal line and configured to provide a signal to the first reset signal line;

[0022] The time period in which the second control unit provides the valid level signal to the first reset signal line at least partially overlaps at least one of the time period in which the first control unit provides the invalid level signal to the first light-emitting signal line and the time period in which the first control unit provides the invalid level signal to the second light-emitting signal line.

[0023] In an exemplary embodiment, the at least one reset signal line includes a first reset signal line and a second reset signal line.

[0024] The reset sub-circuit is configured to provide, under control of a signal of the first reset signal line, a signal of the first initial signal line to the fourth node, provide, under control of a signal of the second reset signal line, a signal of the second initial signal line to the fifth node, and provide a signal of the reference signal line to the second node.

[0025] The display device further includes a second control unit electrically connected with the first reset signal line and the second reset signal line respectively and configured to provide a signal to the first reset signal line and the second reset signal line.

[0026] The time period in which the second control unit provides the valid level signal to the first reset signal line does not overlap the time period in which the second control unit provides the valid level signal to the second reset signal line, and the end time of the time period in which the second control unit provides the valid level signal to the second reset signal line is earlier than the start time of the time period in which the second control unit provides the valid level signal to the first reset signal line.

[0027] At least one of a time period during which the second control unit provides the active level signal to the first reset signal line and a time period during which the second control unit provides the active level signal to the second reset signal line at least partially overlaps with at least one of a time period during which the first control unit provides the inactive level signal to the first light-emitting signal line and a time period during which the first control unit provides the inactive level signal to the second light-emitting signal line.

[0028] In an exemplary implementation, the reset sub-circuit includes a first transistor, a seventh transistor, and a ninth transistor.

[0029] The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the fourth node.

[0030] The control electrode of the seventh transistor is electrically connected to the second reset signal line, the first electrode of the seventh transistor is electrically connected to the second initial signal line, and the second electrode of the seventh transistor is electrically connected to the fifth node.

[0031] The control electrode of the ninth transistor is electrically connected to the second reset signal line, the first electrode of the ninth transistor is electrically connected to the reference signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0032] In an exemplary implementation, the at least two scan signal lines include a first scan signal line and a third scan signal line.

[0033] The drive control sub-circuit is configured to, under the control of the signal of the first scan signal line, provide the signal of the data signal line to the second node, provide the signal of the third node to the fourth node, and under the control of the signal of the third scan signal line, provide the signal of the fourth node to the first node.

[0034] The display device further includes a third control unit and a fourth control unit. The third control unit is electrically connected to the first scan signal line and is configured to provide a signal to the first scan signal line. The fourth control unit is electrically connected to the third scan signal line and is configured to provide a signal to the third scan signal line.

[0035] The time period during which the third control unit provides the active level signal to the first scan signal line at least partially overlaps with the time period during which the fourth control unit provides the active level signal to the third scan signal line.

[0036] At least one of a time period in which the third control unit provides the active level signal to the first scan signal line and a time period in which the fourth control unit provides the active level signal to the third scan signal line at least partially overlaps with at least one of a time period in which the first control unit provides the inactive level signal to the first light-emitting signal line and a time period in which the first control unit provides the inactive level signal to the second light-emitting signal line.

[0037] In an exemplary embodiment, the drive control sub-circuit includes a capacitor, a second transistor, a fourth transistor, and an eighth transistor, the capacitor includes a first plate and a second plate;

[0038] The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the third node;

[0039] The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node;

[0040] The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fourth node;

[0041] The first plate of the capacitor is electrically connected with the first power supply line, and the second plate of the capacitor is electrically connected with the first node.

[0042] In an exemplary embodiment, the at least two scan signal lines include a first scan signal line, a second scan signal line, and a third scan signal line;

[0043] The drive control sub-circuit is configured to provide, under control of a signal of the first scan signal line, a signal of the data signal line to the second node, provide, under control of a signal of the second scan signal line, a signal of the third node to the fourth node, and provide, under control of a signal of the third scan signal line, a signal of the fourth node to the first node;

[0044] The display device further includes a third control unit, a fourth control unit, and a fifth control unit, the third control unit is electrically connected with the first scan signal line and is configured to provide a signal to the first scan signal line, the fourth control unit is electrically connected with the third scan signal line and is configured to provide a signal to the third scan signal line, and the fifth control unit is electrically connected with the second scan signal line and is configured to provide a signal to the second scan signal line;

[0045] The time period in which the fifth control unit provides the active level signal to the second scan signal line includes a first time period and a second time period, and the end time of the first time period is earlier than the start time of the second time period.

[0046] The third control unit provides the effective level signal to the first scan signal line in a time period at least partially overlapping with the second time period and not overlapping with the first time period;

[0047] At least one of the first time period and the second time period at least partially overlaps with a time period in which the fourth control unit provides the effective level signal to the third scan signal line;

[0048] The time period in which the fourth control unit provides the effective level signal to the third scan signal line at least partially overlaps with at least one of a time period in which the first control unit provides the ineffective level signal to the first light-emitting signal line and a time period in which the first control unit provides the ineffective level signal to the second light-emitting signal line.

[0049] In an exemplary embodiment, the drive control sub-circuit includes a capacitor, a second transistor, a fourth transistor, and an eighth transistor, the capacitor includes a first plate and a second plate;

[0050] The control electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the fourth node, and the second electrode of the second transistor is electrically connected to the third node;

[0051] The control electrode of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second node;

[0052] The control electrode of the eighth transistor is electrically connected to the third scan signal line, the first electrode of the eighth transistor is electrically connected to the first node, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0053] In a second aspect, the present disclosure also provides a display device, including: a plurality of sub-pixels, at least one sub-pixel including the above-mentioned pixel drive circuit.

[0054] In an exemplary embodiment, further including: a plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines, at least one of the first light-emitting signal lines and the second light-emitting signal lines extending at least partially along the first direction;

[0055] The first light-emitting signal line connected to the pixel drive circuit of the jth row of sub-pixels and the second light-emitting signal line connected to the pixel drive circuit of the j-1th row of sub-pixels are the same signal line, 1≤j≤N, N being the total number of rows of sub-pixels.

[0056] In an exemplary embodiment, further including: a plurality of first reset signal lines, the first reset signal lines extending at least partially along the first direction;

[0057] The first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels includes two lines, the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels and the second first reset signal line connected to the pixel driving circuit of the j-1th row of sub-pixels are the same signal line, and the second first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels and the first first reset signal line connected to the pixel driving circuit of the j+1th row of sub-pixels are the same signal line.

[0058] In an example embodiment, further comprising: a plurality of first scan signal lines, a plurality of third scan signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, and a plurality of reference signal lines;

[0059] At least one of the first scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, and the reference signal line extends at least partially along a first direction;

[0060] The first light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels, the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels, the first scan signal line connected to the pixel driving circuit of the jth row of sub-pixels, the second light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels, and the second first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels are arranged in a second direction in sequence, and the first direction intersects the second direction;

[0061] The reference signal line connected to the pixel driving circuit of the jth row of sub-pixels has an orthographic projection on the substrate that at least partially overlaps the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels, the second initial signal line connected to the pixel driving circuit of the jth row of sub-pixels has an orthographic projection on the substrate that at least partially overlaps the first light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels, the third scan signal line connected to the pixel driving circuit of the jth row of sub-pixels has an orthographic projection on the substrate that is located between the orthographic projection on the substrate of the first scan signal line connected to the pixel driving circuit of the jth row of sub-pixels and the orthographic projection on the substrate of the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels, and the orthographic projection on the substrate of the second initial signal line connected to the pixel driving circuit of the jth row of sub-pixels is located on a side of the orthographic projection on the substrate of the second first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels that is away from the orthographic projection on the substrate of the second light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels.

[0062] In an example embodiment, the at least one pixel driving circuit includes: a first transistor to a ninth transistor, and at least one transistor includes: an active pattern;

[0063] The active patterns of the first transistor, the second transistor, the third transistor, the fourth transistor, the sixth transistor and the seventh transistor in the same sub-pixel are in one body structure, and the active patterns of the fifth transistor and the ninth transistor in the same sub-pixel are in one body structure;

[0064] The active pattern of the fifth transistor in the pixel driving circuit of the jth row of sub-pixels is arranged along the first direction with the active pattern of the sixth transistor in the pixel driving circuit of the (j-1)th row of sub-pixels, and the active pattern of the ninth transistor in the pixel driving circuit of the jth row of sub-pixels, the active pattern of the first transistor in the pixel driving circuit of the jth row of sub-pixels and the active pattern of the seventh transistor in the pixel driving circuit of the (j-1)th row of sub-pixels are arranged along the first direction.

[0065] In the example embodiment, the at least one transistor further comprises: a first pole and a second pole, the active pattern comprises a first region and a second region, the second pole of the fifth transistor and the second pole of the ninth transistor are in one body structure and extend along the second direction;

[0066] The first region of the active pattern of the third transistor and the second region of the active pattern of the fourth transistor are in one region, and the second region of the active pattern of the fifth transistor and the second region of the active pattern of the ninth transistor are in one region,

[0067] The second pole of the fifth transistor is connected with the first region of the active pattern of the third transistor and the second region of the active pattern of the fifth transistor respectively;

[0068] The orthogonal projection of the second pole of the fifth transistor in the pixel driving circuit of the jth column of sub-pixels on the base at least partially overlaps with the orthogonal projection of at least one of the reference signal line connected with the pixel driving circuit of the jth row of sub-pixels, the second initial signal line connected with the (j-1)th row of sub-pixels, the third scanning signal line connected with the pixel driving circuit of the jth row of sub-pixels and the first scanning signal line connected with the pixel driving circuit of the jth row of sub-pixels on the base.

[0069] In the example embodiment, further comprising: a plurality of initial connection lines, a plurality of first power supply lines and a plurality of data signal lines, at least one of the first power supply line, the data signal line and the initial connection line at least partially extends along the second direction, and the first direction intersects with the second direction;

[0070] The at least one initial connection line is electrically connected with the at least one first initial signal line.

[0071] In an example embodiment, further comprising: a substrate and a driving structure layer disposed on the substrate, the driving structure layer is provided with a pixel driving circuit, the pixel driving circuit comprises: at least one N-type transistor, at least one P-type transistor and a capacitor, the capacitor comprises a first plate and a second plate, the transistor comprises: an active pattern, a control electrode, a first electrode and a second electrode, the third scan signal line comprises a first sub-signal line and a second sub-signal line;

[0072] The driving structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are sequentially stacked on the substrate;

[0073] The first semiconductor layer at least comprises: an active pattern of at least one P-type transistor;

[0074] The first conductive layer at least comprises: a first scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first reset signal line, and a first plate of the capacitor of at least one pixel driving circuit and a control electrode of at least one P-type transistor;

[0075] The second conductive layer at least comprises: a first sub-signal line of the third scan signal line, a second initial signal line and a second plate of the capacitor in the pixel driving circuit of at least one sub-pixel;

[0076] The second semiconductor layer at least comprises: an active pattern of at least one N-type transistor;

[0077] The third conductive layer at least comprises: a second sub-signal line of the third scan signal line, a first initial signal line, a reference signal line;

[0078] The fourth conductive layer at least comprises: an initial connection line at the first electrode and the second electrode of at least one transistor of at least one pixel driving circuit.

[0079] In a third aspect, the present disclosure further provides a driving method of a pixel driving circuit, configured to drive the pixel driving circuit, the method comprising:

[0080] The reset sub-circuit provides a signal of the reference signal line to the second node, a signal of the first initial signal line to the fourth node, and a signal of the second initial signal line to the fifth node under the control of the signal of the at least one reset signal line;

[0081] The driving control sub-circuit provides a signal of the data signal line to the second node, and a signal of the third node or the fourth node to the first node under the control of the signals of the at least two scan signal lines and the first power supply line;

[0082] The driving sub-circuit provides a driving signal to the third node under the control of the signals of the first node and the second node;

[0083] The light emitting control sub-circuit provides a signal of the first power supply line to the second node and a signal of the third node to the fifth node under the control of signals of the first light emitting signal line and the second light emitting signal line.

[0084] Other aspects can become apparent from the following detailed description when read in conjunction with the drawings.

[0085] SUMMARY

[0086] The accompanying drawings are included to provide a further understanding of the present technology, and constitute a part of this specification. The drawings illustrate embodiments of the present technology and, together with the specification, serve to explain the principles of the present technology. The present technology should not be construed as being limited to the embodiments set forth in the figures, which are presented as specific examples.

[0087] FIG. 1 is a structural schematic diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0088] FIG. 2 is a timing diagram of signals of the first light emitting signal line and the second light emitting signal line;

[0089] FIG. 3 is an equivalent circuit diagram of a driving sub-circuit and a light emitting control sub-circuit;

[0090] FIG. 4 is an equivalent circuit diagram of a reset sub-circuit;

[0091] FIG. 5 is another equivalent circuit diagram of the reset sub-circuit;

[0092] FIG. 6 is an equivalent circuit diagram of a driving control sub-circuit;

[0093] FIG. 7 is another equivalent circuit diagram of the driving control sub-circuit;

[0094] FIG. 8 is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

[0095] FIG. 9 is another equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0096] FIG. 10 is a third equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0097] FIG. 11 is a fourth equivalent circuit diagram of the pixel driving circuit according to an embodiment of the present disclosure;

[0098] FIG. 12 is a timing diagram of the pixel driving circuit according to FIG. 8;

[0099] FIG. 13 is a timing diagram of the pixel driving circuit according to FIG. 9;

[0100] FIG. 14 is a timing diagram of the pixel driving circuit according to FIG. 10;

[0101] FIG. 15 is a timing diagram of the pixel driving circuit according to FIG. 11;

[0102] FIG. 16 is a structural schematic diagram of a display device according to an embodiment of the present disclosure;

[0103] FIG. 17 is a schematic diagram of part of the film layers in FIG. 16;

[0104] FIG. 18 is a schematic diagram of part of the film layers in FIG. 16;

[0105] FIG. 19 is a schematic diagram of FIG. 16 after forming a light-blocking layer pattern;

[0106] FIG. 20 is a schematic diagram of a first semiconductor layer pattern in FIG. 16;

[0107] FIG. 21 is a schematic diagram of FIG. 16 after forming the first semiconductor layer pattern;

[0108] FIG. 22 is a schematic diagram of a first conductive layer pattern in FIG. 16;

[0109] FIG. 23 is a schematic diagram of FIG. 16 after forming the first conductive layer pattern;

[0110] FIG. 24 is a schematic diagram of a second conductive layer pattern in FIG. 16;

[0111] FIG. 25 is a schematic diagram of FIG. 16 after forming the second conductive layer pattern;

[0112] FIG. 26 is a schematic diagram of a second semiconductor layer pattern in FIG. 16;

[0113] FIG. 27 is a schematic diagram of FIG. 16 after forming the second semiconductor layer pattern;

[0114] FIG. 28 is a schematic diagram of a third conductive layer pattern in FIG. 16;

[0115] FIG. 29 is a schematic diagram of FIG. 16 after forming the third conductive layer pattern;

[0116] FIG. 30 is a schematic diagram of FIG. 16 after forming a sixth insulating layer pattern;

[0117] FIG. 31 is a schematic diagram of a fourth conductive layer pattern in FIG. 16;

[0118] FIG. 32 is a schematic diagram of FIG. 16 after forming the fourth conductive layer pattern;

[0119] FIG. 33 is a schematic diagram of FIG. 16 after forming a first planarization layer pattern;

[0120] FIG. 34 is a schematic diagram of a fifth conductive layer pattern in FIG. 16;

[0121] FIG. 35 is a schematic diagram of FIG. 16 after forming the fifth conductive layer pattern.

[0122] DETAILED DESCRIPTION

[0123] For the purpose of making the objects, technical solutions and advantages of the present disclosure clearer, below, the embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments can be implemented in multiple different forms. It will be easily understood by those skilled in the art that the modes and details can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the content described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other in so far as there is no contradiction in combination unless otherwise mentioned. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed description of some known functions and known components will be omitted in the present disclosure. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed

[0124] In the drawings, the size, the thickness, or the region of each constituent element shown in some cases is exaggerated for clarity in some cases. Thus, one embodiment of the present disclosure is not necessarily limited to such a scale. The shapes and the sizes of the components shown in the drawings and the relative arrangement thereof are not necessarily limited to those shown in the drawings. The drawings provided only ideal examples, and the shape of the embodiments of the present disclosure is not limited to the shape shown in the drawings and the numerical value and the like.

[0125] In this specification, ordinal numbers such as "first", "second", and "third" are used to avoid confusion among the constituent elements, and are not intended to limit the number in the aspect of the quantity.

[0126] In this specification, in order to facilitate the description of the present specification and simplify the description, words indicating the orientation or the positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of the constituent elements with reference to the drawings, and are not intended to indicate or imply that the device or the element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0127] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be interpreted in a broad sense. For example, it can be fixed connection, or detachable connection, or integrally connected; can be mechanical connection, or electrical connection; can be directly connected, or indirectly connected through an intermediate component, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0128] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0129] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor having opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Thus, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other.

[0130] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0131] In this specification, "parallel" means a state where an angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" means a state where an angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0132] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0133] In the present disclosure, "about" means not strictly limited to the limit, allowing values within the range of process and measurement error.

[0134] A pixel driving circuit and a light emitting device are provided in a display product, the pixel driving circuit drives the light emitting device to emit light, and thus display is realized. When the level of at least one signal in the pixel driving circuit changes, charge is discharged, and thus the signal of a part of nodes in the pixel driving circuit is unstable, which affects the reliability of the pixel driving circuit and reduces the display effect of the display substrate.

[0135] To this end, the present disclosure provides a pixel driving circuit.

[0136] FIG. 1 is a structural schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG. 1, the pixel driving circuit provided by the embodiment of the present disclosure, which is arranged in a display device, can include a driving control sub-circuit, a reset sub-circuit, a driving sub-circuit, and a light-emitting control sub-circuit.

[0137] As shown in FIG. 1, the reset sub-circuit is electrically connected with at least one reset signal line, a first initial signal line INIT1, a second initial signal line INIT2, a reference signal line REF, a second node N2, a fourth node N4, and a fifth node N5, respectively, and is configured to provide, under the control of a signal of the at least one reset signal line, a signal of the reference signal line REF to the second node N2, a signal of the first initial signal line INIT1 to the fourth node N4, and a signal of the second initial signal line INIT2 to the fifth node N5; the driving control sub-circuit is electrically connected with at least two scan signal lines, a data signal line Data, a first power supply line VDD, a first node N1, the second node N2, a third node N3, and the fourth node N4, respectively, and is configured to provide, under the control of signals of the at least two scan signal lines and the first power supply line VDD, a signal of the data signal line Data to the second node N2, and a signal of the third node N3 or the fourth node N4 to the first node N1; the driving sub-circuit is electrically connected with the first node N1, the second node N2, and the third node N3, respectively, and is configured to provide, under the control of signals of the first node N1 and the second node N2, a driving signal to the third node N3; and the light-emitting control sub-circuit is electrically connected with a first light-emitting signal line EM1, a second light-emitting signal line EM2, the first power supply line VDD, the second node N2, the third node N3, and the fifth node N5, respectively, and is configured to provide, under the control of signals of the first light-emitting signal line EM1 and the second light-emitting signal line EM2, a signal of the first power supply line VDD to the second node N2, and a signal of the third node N3 to the fifth node N5.

[0138] FIG. 2 is a timing diagram of signals of the first light-emitting signal line and the second light-emitting signal line. As shown in FIG. 2, the display device includes a first control unit electrically connected with the first light-emitting signal line EM1 and the second light-emitting signal line EM2, respectively, and configured to provide signals to the first light-emitting signal line EM1 and the second light-emitting signal line EM2, and the first control unit provides an active level signal to the first light-emitting signal line EM1 in a time period that is partially non-overlapping with a time period in which the first control unit provides the active level signal to the second light-emitting signal line EM2.

[0139] In an exemplary embodiment, the display device includes a plurality of rows of pixel driving circuits, and a second light-emitting signal line connected with an i-th row of pixel driving circuits is the same signal line as a first light-emitting signal line connected with an i+1-th row of pixel driving circuits.

[0140] In an exemplary embodiment, as shown in FIG. 1, the at least one reset signal line can include a first reset signal line Resetl, or can include a first reset signal line Resetl and a second reset signal line Reset2.

[0141] In an exemplary embodiment, as shown in FIG. 1, the at least one scan signal line can include a first scan signal line Gate 1 and a third scan signal line Gate 3, or can include a first scan signal line Gate 1, a second scan signal line Gate 2 and a third scan signal line Gate 3.

[0142] As shown in FIG. 1, the light emitting element EL is electrically connected to the fourth node N4 and the second power supply line VSS, respectively.

[0143] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT 1 is constant, and is a direct current signal, and the voltage value of the signal of the first initial signal line INIT 1 can be -3V. The direct current signal can be a signal whose size and direction do not change over time.

[0144] In an exemplary embodiment, the voltage value of the signal of the second initial signal line INIT2 is constant, and is a direct current signal, and the voltage value of the signal of the second initial signal line INIT2 can be 0V.

[0145] In an exemplary embodiment, the voltage value of the signal of the reference signal line REF is constant, and is a direct current signal, and the voltage value of the signal of the reference signal line REF can be 5V.

[0146] In an exemplary embodiment, the light emitting element EL can be electrically connected to the fifth node N5 and the second power supply line VSS, respectively.

[0147] In an exemplary embodiment, the first power supply line VDD continuously provides a high level signal, and the second power supply line VSS continuously provides a low level signal.

[0148] In an exemplary embodiment, the light emitting element EL can be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer and a second electrode (cathode) stacked. Exemplarily, the anode of the organic electroluminescent diode is electrically connected to the fourth node N4, and the cathode of the organic electroluminescent diode is electrically connected to the second power supply line VSS.

[0149] In exemplary embodiments, the organic light-emitting layer can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked. In exemplary embodiments, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0150] The present disclosure can disperse the charge discharge that occurs when the signal level changes, can ensure the stability of the node signal in the pixel driving circuit, improve the reliability of the pixel driving circuit, and ensure the display effect of the display substrate, by the first control unit providing the time period of the active level signal to the first light-emitting signal line and the time period of the active level signal to the second light-emitting signal line partially not overlapping.

[0151] In exemplary embodiments, FIG. 3 is an equivalent circuit diagram of a driving sub-circuit and a light-emitting control sub-circuit, as shown in FIG. 3, the driving sub-circuit includes a third transistor T3, and the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6. The control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fifth transistor T5 is electrically connected with the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5.

[0152] In the example embodiment, the third transistor T3 can be referred to as a driving transistor. The third transistor T3 can determine the size of a driving current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between the control electrode and the first electrode.

[0153] In the example embodiment, the fifth transistor T5 can be referred to as a first light emitting transistor, and the sixth transistor T6 can be referred to as a second light emitting transistor. When the signal of the first light emitting signal line EM1 and the signal of the second light emitting signal line EM2 are both active level signals, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device EL to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0154] An example structure of the driving sub-circuit is shown in FIG. 3. It is easily understood by those skilled in the art that the implementation of the driving sub-circuit is not limited to this.

[0155] An example structure of the light emitting control sub-circuit is also shown in FIG. 3. It is easily understood by those skilled in the art that the implementation of the light emitting control sub-circuit is not limited to this.

[0156] In the example embodiment, as shown in FIG. 2, in the example embodiment, the start time of the time period during which the first control unit provides the active level signal to the first light emitting signal line EM1 is earlier than the start time of the time period during which the first control unit provides the active level signal to the second light emitting signal line EM2, and the end time of the time period during which the first control unit provides the active level signal to the first light emitting signal line EM1 is earlier than the end time of the time period during which the first control unit provides the active level signal to the second light emitting signal line EM2.

[0157] In the example embodiment, FIG. 4 is an equivalent circuit diagram of the reset sub-circuit. FIG. 4 is described by taking at least one reset signal line including a first reset signal line Reset1 as an example. As shown in FIG. 4, when the at least one reset signal line includes the first reset signal line Reset1, the reset sub-circuit can include a first transistor T1, a seventh transistor T7, and a ninth transistor T9. As shown in FIG. 4, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the seventh transistor T7 is electrically connected with the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5; the control electrode of the ninth transistor T9 is electrically connected with the first reset signal line Reset1, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2.

[0158] In an example embodiment, when the at least one reset signal line includes the first reset signal line Reset1, the display device further includes a second control unit electrically connected to the first reset signal line Reset1 and configured to provide a signal to the first reset signal line Reset1; and a time period during which the second control unit provides a valid level signal to the first reset signal line Reset1 at least partially overlaps with at least one of a time period during which the first control unit provides an invalid level signal to the first emission signal line EM1 and a time period during which the first control unit provides an invalid level signal to the second emission signal line EM2.

[0159] In an example embodiment, when the at least one reset signal line includes the first reset signal line Reset1 and the second reset signal line Reset2, the reset sub-circuit is configured to provide a signal of the first initial signal line INIT1 to the fourth node N4 under control of a signal of the first reset signal line Reset1, provide a signal of the second initial signal line INIT2 to the fifth node N5 under control of a signal of the second reset signal line Reset2, and provide a signal of the reference signal line REF to the second node N2.

[0160] In an example embodiment, FIG. 5 is another equivalent circuit diagram of the reset sub-circuit. FIG. 5 is described by way of example in which the at least one reset signal line includes the first reset signal line Reset1 and the second reset signal line Reset2. When the at least one reset signal line includes the first reset signal line Reset1 and the second reset signal line Reset2, the reset sub-circuit can include a first transistor T1, a seventh transistor T7, and a ninth transistor T9. The control electrode of the first transistor T1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the fourth node N4. The control electrode of the seventh transistor T7 is electrically connected to the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fifth node N5. The control electrode of the ninth transistor T9 is electrically connected to the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected to the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected to the second node N2.

[0161] In the example embodiment, when the at least one reset signal line includes a first reset signal line Reset1 and a second reset signal line Reset2, the display device further includes a second control unit electrically connected to the first reset signal line Reset1 and the second reset signal line Reset2, and configured to provide signals to the first reset signal line Reset1 and the second reset signal line Reset2. The time period during which the second control unit provides an active level signal to the first reset signal line Reset1 does not overlap with the time period during which the second control unit provides an active level signal to the second reset signal line Reset2, and the end time of the time period during which the second control unit provides an active level signal to the second reset signal line Reset2 is earlier than the start time of the time period during which the second control unit provides an active level signal to the first reset signal line Reset1. At least one of the time period during which the second control unit provides an active level signal to the first reset signal line Reset1 and the time period during which the second control unit provides an active level signal to the second reset signal line Reset2 at least partially overlaps with at least one of the time period during which the first control unit provides an inactive level signal to the first emission signal line EM1 and the time period during which the first control unit provides an inactive level signal to the second emission signal line EM2.

[0162] FIGS. 4 and 5 also show two example structures of the reset sub-circuit. It is easy for those skilled in the art to understand that the implementation of the reset sub-circuit is not limited thereto.

[0163] In the example embodiment, when the at least two scan signal lines include a first scan signal line Gate1 and a third scan signal line Gate3, the drive control sub-circuit is configured to provide, under the control of the signal of the first scan signal line Gate1, the signal of the data signal line Data to the second node N2, the signal of the third node N3 to the fourth node N4, and under the control of the signal of the third scan signal line Gate3, the signal of the fourth node N4 to the first node N1.

[0164] In an example embodiment, FIG. 6 is an equivalent circuit diagram of the driving control sub-circuit, which is described by taking an example of at least two scan signal lines including the first scan signal line Gate1 and the third scan signal line Gate3. When the at least two scan signal lines include the first scan signal line Gate1 and the third scan signal line Gate3, the driving control sub-circuit can include the capacitor C, the second transistor T2, the fourth transistor T4, and the eighth transistor T8, and the capacitor C includes the first plate and the second plate. The control electrode of the second transistor T2 is electrically connected to the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected to the fourth node N4, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The control electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The control electrode of the eighth transistor T8 is electrically connected to the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the fourth node N4. The first plate of the capacitor C is electrically connected to the first power supply line VDD, and the second plate of the capacitor C is electrically connected to the first node N1.

[0165] In an example embodiment, when the at least two scan signal lines include the first scan signal line Gate1 and the third scan signal line Gate3, the display device further includes a third control unit and a fourth control unit. The third control unit is electrically connected to the first scan signal line Gate1 and is configured to provide a signal to the first scan signal line Gate1. The fourth control unit is electrically connected to the third scan signal line Gate3 and is configured to provide a signal to the third scan signal line Gate3. The time period in which the third control unit provides an active level signal to the first scan signal line Gate1 at least partially overlaps with the time period in which the fourth control unit provides an active level signal to the third scan signal line Gate3. At least one of the time period in which the third control unit provides an active level signal to the first scan signal line Gate1 and the time period in which the fourth control unit provides an active level signal to the third scan signal line Gate3 at least partially overlaps with at least one of the time period in which the first control unit provides an inactive level signal to the first light-emitting signal line EM1 and the time period in which the first control unit provides an inactive level signal to the second light-emitting signal line EM2.

[0166] In the example embodiment, when the at least two scan signal lines include a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3, the driving control sub-circuit is configured to provide a signal of the data signal line Data to the second node N2 under control of a signal of the first scan signal line Gate1, provide a signal of the third node N3 to the fourth node N4 under control of a signal of the second scan signal line Gate2, and provide a signal of the fourth node N4 to the first node N1 under control of a signal of the third scan signal line Gate3.

[0167] In the example embodiment, FIG. 7 is another equivalent circuit diagram of the driving control sub-circuit. FIG. 7 is described by taking an example that the at least two scan signal lines include a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3. When the at least two scan signal lines include the first scan signal line Gate1, the second scan signal line Gate2, and the third scan signal line Gate3, the driving control sub-circuit can include a capacitor C, a second transistor T2, a fourth transistor T4, and an eighth transistor T8, and the capacitor C includes a first plate and a second plate. The control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the third node N3. The control electrode of the fourth transistor T4 is electrically connected with the second scan signal line Gate2, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2. The control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4. The first plate of the capacitor C is electrically connected with the first power supply line VDD, and the second plate of the capacitor C is electrically connected with the first node N1.

[0168] In the example embodiment, when the at least two scan signal lines include a first scan signal line Gate1, a second scan signal line Gate2, and a third scan signal line Gate3, the display device further includes a third control unit, a fourth control unit, and a fifth control unit, the third control unit is electrically connected with the first scan signal line Gate1 and is configured to provide a signal to the first scan signal line Gate1, the fourth control unit is electrically connected with the third scan signal line Gate3 and is configured to provide a signal to the third scan signal line Gate3, and the fifth control unit is electrically connected with the second scan signal line Gate2 and is configured to provide a signal to the second scan signal line Gate2. A time period in which the fifth control unit provides an effective level signal to the second scan signal line Gate2 includes a first time period and a second time period, and an end time of the first time period is earlier than a start time of the second time period. A time period in which the third control unit provides an effective level signal to the first scan signal line Gate1 at least partially overlaps with the second time period and does not overlap with the first time period. At least one of the first time period and the second time period at least partially overlaps with a time period in which the fourth control unit provides an effective level signal to the third scan signal line Gate3. The time period in which the fourth control unit provides an effective level signal to the third scan signal line Gate3 at least partially overlaps with at least one of a time period in which the first control unit provides an ineffective level signal to the first emission signal line EM1 and a time period in which the first control unit provides an ineffective level signal to the second emission signal line EM2.

[0169] In the example embodiment, the transistor type of the eighth transistor T8 is different from the transistor type of at least one of the second transistor T2 and the fourth transistor T4. For example, the eighth transistor T8 can be an N-type transistor, and the second transistor T2 and the fourth transistor T4 can be P-type transistors, and the present disclosure does not make any limitation in this regard.

[0170] Two example structures of the drive control sub-circuit are shown in FIGS. 6 and 7. It is easy for those skilled in the art to understand that the implementation of the drive control sub-circuit is not limited thereto.

[0171] FIG. 8 is an equivalent circuit diagram one of a pixel driving circuit provided by the embodiment of the present disclosure. FIG. 8 is described by taking at least one reset signal line including a first reset signal line Reset1, and at least one scan signal line including a first scan signal line Gate1 and a third scan signal line Gate3 as an example. As shown in FIG. 8, the driving sub-circuit includes a third transistor T3, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7 and a ninth transistor T9, and the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4 and an eighth transistor T8. Wherein, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with a first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with a fourth node N4; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with a third node N3; the control electrode of the third transistor T3 is electrically connected with a first node N1, the first electrode of the third transistor T3 is electrically connected with a second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with a data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with a first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with a first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with a second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with a fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected with a second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected with the first reset signal line Reset1, the first electrode of the ninth transistor T9 is electrically connected with a reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the first plate of the capacitor C is electrically connected with the first power supply line VDD, and the second plate of the capacitor C is electrically connected with the first node N1.

[0172] FIG. 9 is a second equivalent circuit diagram of the pixel driving circuit provided by the embodiment of the present disclosure. FIG. 9 is described by taking at least one reset signal line including a first reset signal line Reset1 and a second reset signal line Reset2, and at least one scan signal line including a first scan signal line Gate1 and a third scan signal line Gate3 as an example. As shown in FIG. 9, the driving sub-circuit includes a third transistor T3, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7 and a ninth transistor T9, and the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the first scan signal line Gate1, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected with the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the first plate of the capacitor C is electrically connected with the first power supply line VDD, and the second plate of the capacitor C is electrically connected with the first node N1.

[0173] FIG. 10 is an equivalent circuit diagram three of the pixel driving circuit provided by the embodiment of the present disclosure. FIG. 10 is described by taking at least one reset signal line including a first reset signal line Reset1, at least one scan signal line including a first scan signal line Gate1, a second scan signal line Gate2 and a third scan signal line Gate3 as an example. As shown in FIG. 10, the driving sub-circuit includes a third transistor T3, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7 and a ninth transistor T9, the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the first reset signal line Reset1, the first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected with the first reset signal line Reset1, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the first plate of the capacitor C is electrically connected with the first power supply line VDD, and the second plate of the capacitor C is electrically connected with the first node N1.

[0174] Fig. 11 is a fourth equivalent circuit diagram of the pixel driving circuit provided by the embodiment of the present disclosure. Fig. 11 is described by taking at least one reset signal line including a first reset signal line Reset1 and a second reset signal line Reset2, and at least one scan signal line including a first scan signal line Gate1, a second scan signal line Gate2 and a third scan signal line Gate3 as an example. As shown in Fig. 11, the driving sub-circuit includes a third transistor T3, the light-emitting control sub-circuit includes a fifth transistor T5 and a sixth transistor T6, the reset sub-circuit includes a first transistor T1, a seventh transistor T7 and a ninth transistor T9, and the driving control sub-circuit includes a capacitor C, a second transistor T2, a fourth transistor T4 and an eighth transistor T8. Among them, the control electrode of the first transistor T1 is electrically connected with the first reset signal line Reset1, the first electrode of the first transistor T1 is electrically connected with the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected with the fourth node N4; the control electrode of the second transistor T2 is electrically connected with the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected with the fourth node N4, and the second electrode of the second transistor T2 is electrically connected with the third node N3; the control electrode of the third transistor T3 is electrically connected with the first node N1, the first electrode of the third transistor T3 is electrically connected with the second node N2, and the second electrode of the third transistor T3 is electrically connected with the third node N3; the control electrode of the fourth transistor T4 is electrically connected with the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected with the data signal line Data, and the second electrode of the fourth transistor T4 is electrically connected with the second node N2; the control electrode of the fifth transistor T5 is electrically connected with the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is electrically connected with the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected with the second node N2; the control electrode of the sixth transistor T6 is electrically connected with the second light-emitting signal line EM2, the first electrode of the sixth transistor T6 is electrically connected with the third node N3, and the second electrode of the sixth transistor T6 is electrically connected with the fifth node N5; the control electrode of the seventh transistor T7 is electrically connected with the second reset signal line Reset2, the first electrode of the seventh transistor T7 is electrically connected with the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected with the fifth node N5; the control electrode of the eighth transistor T8 is electrically connected with the third scan signal line Gate3, the first electrode of the eighth transistor T8 is electrically connected with the first node N1, and the second electrode of the eighth transistor T8 is electrically connected with the fourth node N4; the control electrode of the ninth transistor T9 is electrically connected with the second reset signal line Reset2, the first electrode of the ninth transistor T9 is electrically connected with the reference signal line REF, and the second electrode of the ninth transistor T9 is electrically connected with the second node N2; the first plate of the capacitor C is electrically connected with the first power supply line VDD, and the second plate of the capacitor C is electrically connected with the first node N1.

[0175] According to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor. When the transistor is a P-type transistor, the on voltage is a low-level voltage (for example, 0 V, -5 V, -10 V, or other suitable voltages), and the off voltage is a high-level voltage (for example, 5 V, 10 V, or other suitable voltages). When the transistor is an N-type transistor, the on voltage is a high-level voltage (for example, 5 V, 10 V, or other suitable voltages), and the off voltage is a low-level voltage (for example, 0 V, -5 V, -10 V, or other suitable voltages).

[0176] In an example embodiment, the pixel driving circuit provided by the present disclosure includes a ninth transistor, which can reset the first electrode of the third transistor, improve the variable refresh rate of the display device, and avoid image sticking of the display device.

[0177] In an example embodiment, the fifth transistor T5 and the sixth transistor T6 in the pixel driving circuit provided by the present disclosure are controlled by different light-emitting signal lines, which can more flexibly adjust the signal of the second node N2.

[0178] In an example embodiment, the signal of the first reset signal line connected to the pixel driving circuit can be the same as the signal of the first scan signal line connected to the pixel driving circuit of at least the previous row of the pixel driving circuit, and the present disclosure does not make any limitation thereto.

[0179] In an example embodiment, the signal of the second reset signal line connected to the pixel driving circuit can be the same as the signal of the first scan signal line connected to the pixel driving circuit of at least the previous two rows of the pixel driving circuit, and the present disclosure does not make any limitation thereto.

[0180] In an example embodiment, the first transistor T1 to the ninth transistor T9 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementation manners, the first transistor T1 to the ninth transistor T9 can include P-type transistors and N-type transistors. For example, the eighth transistor T8 can be an N-type transistor, and the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 can be P-type transistors.

[0181] In an example embodiment, the first transistor T1 to the ninth transistor T9 can adopt a low temperature poly-silicon thin film transistor, or can adopt an oxide thin film transistor, or can adopt a low temperature poly-silicon thin film transistor and an oxide thin film transistor. The active layer of the low temperature poly-silicon thin film transistor adopts low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor adopts oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature polycrystalline oxide (LTPO) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0182] In an example embodiment, some of the first transistor T1 to the ninth transistor T9 can be oxide transistors, and some of the first transistor T1 to the ninth transistor T9 can be low temperature poly-silicon transistors. The oxide transistors can reduce leakage current, improve the performance of the pixel driving circuit, and reduce the power consumption of the pixel driving circuit.

[0183] FIG. 12 is a timing diagram of the pixel driving circuit provided in FIG. 8. FIG. 8 is described by taking the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 as P-type transistors and the eighth transistor T8 as an N-type transistor as an example. As shown in FIG. 12, the working process of the pixel driving circuit provided in FIG. 8 can include:

[0184] The first stage S11 is called the initialization stage, the signal of the first reset signal line Reset1 is a low-level signal, and the signals of the first scan signal line Gate1, the third scan signal line Gate3, the first emission signal line EM1 and the second emission signal line EM2 are high-level signals. The first transistor T1, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0185] The first transistor T1 and the eighth transistor T8 are turned on, the signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, the first node N1 and the fourth node N4 are initialized (reset), the pre-stored voltage in the first node N1 and the fourth node N4 is emptied, and the initialization is completed. The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fifth node N5, the anode of the light emitting element EL is initialized (reset), the pre-stored voltage in the anode of the light emitting element EL is emptied, and the initialization is completed. The ninth transistor T9 is turned on, the signal of the reference signal line REF is written to the second node N2, the second node N2 is initialized (reset), the pre-stored voltage in the second node N2 is emptied, and the initialization is completed.

[0186] In the second stage S12, referred to as a threshold compensation and data writing stage, the signal of the first scan signal line Gate1 is a low level signal, and the signals of the first reset signal line Reset1, the third scan signal line Gate3, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals. The data signal line Data outputs a data voltage. The second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0187] The second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4 and the turned-on eighth transistor T8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3.

[0188] In the third stage S13, the signals of the third scan signal line Gate3 and the first light emitting signal line EM1 are low level signals, and the signals of the first scan signal line Gate1, the first reset signal line Reset1 and the second light emitting signal line EM2 are high level signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0189] The fifth transistor T5 is turned on, and the signal of the first power supply line VDD is written to the second node N2.

[0190] In the fourth stage S14, referred to as the light emitting stage, the signals of the first light emitting signal line EM1, the second light emitting signal line EM2 and the third scan signal line Gate3 are low level signals, and the signals of the first reset signal line Reset1 and the first scan signal line Gate1 are high level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0191] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD is provided to the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on sixth transistor T6, so as to drive the light emitting element EL to emit light.

[0192] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0193] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0194] FIG. 13 is a timing diagram of the pixel driving circuit provided in FIG. 9. FIG. 9 is described by taking the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 as P-type transistors and the eighth transistor T8 as an N-type transistor as an example. As shown in FIG. 13, the working process of the pixel driving circuit provided in FIG. 9 can include:

[0195] In the first stage S21, referred to as the first initialization stage, the signal of the second reset signal line Reset2 is a low level signal, and the signals of the first reset signal line Reset1, the first scan signal line Gate1, the third scan signal line Gate3, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high level signals. The seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off.

[0196] The seventh transistor T7 is turned on, and the signal of the second initial signal line INIT2 is written to the fifth node N5, the anode of the light emitting element EL is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The ninth transistor T9 is turned on, and the signal of the reference signal line REF is written to the second node N2, the second node N2 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0197] The second stage S22 is called the second initialization stage, the signal of the first reset signal line Reset1 is a low-level signal, and the signals of the second reset signal line Reset2, the first scan signal line Gate1, the third scan signal line Gate3, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals. The first transistor T1 and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0198] The first transistor T1 and the eighth transistor T8 are turned on, and the signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, the first node N1 and the fourth node N4 are initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0199] The third stage S23 is called the threshold compensation and data writing stage, the signal of the first scan signal line Gate1 is a low-level signal, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third scan signal line Gate3, the first light emitting signal line EM1 and the second light emitting signal line EM2 are high-level signals. The data signal line Data outputs a data voltage. The second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0200] The second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, and the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4 and the turned-on eighth transistor T8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3.

[0201] In the fourth stage S24, the signals of the third scan signal line Gate3 and the first emission signal line EM1 are low level signals, and the signals of the first scan signal line Gate1, the first reset signal line Reset1, the second reset signal line Reset2 and the second emission signal line EM2 are high level signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0202] The fifth transistor T5 is turned on, and the signal of the first power supply line VDD is written into the second node N2.

[0203] In the fifth stage S25, called the emission stage, the signals of the first emission signal line EM1, the second emission signal line EM2 and the third scan signal line Gate3 are low level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2 and the first scan signal line Gate1 are high level signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0204] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage outputted by the first power supply line VDD provides a driving voltage for the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on sixth transistor T6, thereby driving the light emitting element EL to emit light.

[0205] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: 2 = K * [(Vdd - Vd + |Vth|) - Vth] 2 = K * (Vdd - Vd) 2

[0206] wherein I is the driving current flowing through the third transistor T3, that is, the driving current of the light emitting element EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage outputted by the data signal line Data, and Vdd is the power supply voltage outputted by the first power supply line VDD.

[0207] FIG. 14 is a timing chart of the operation of the pixel driving circuit provided in FIG. 10. FIG. 10 is described by way of example in which the first to seventh transistors T1 to T7 and the ninth transistor T9 are P-type transistors and the eighth transistor T8 is an N-type transistor. As shown in FIG. 14, the operation of the pixel driving circuit provided in FIG. 10 can include:

[0208] The first stage S31 is called an initialization stage. The signals of the first reset signal line Reset1 and the second scan signal line Gate2 are low-level signals, and the signals of the first scan signal line Gate1, the third scan signal line Gate3, the first emission signal line EM1, and the second emission signal line EM2 are high-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0209] The first transistor T1 and the eighth transistor T8 are turned on, and the signal of the first initialization signal line INIT1 is written to the first node N1 through the fourth node N4 to initialize (reset) the first node N1 and the fourth node N4 and clear the pre-stored voltage in the interior thereof, thereby completing initialization. The first transistor T1 and the second transistor T2 are turned on, and the signal of the first initialization signal line INIT1 is written to the third node N3 through the fourth node N4 to initialize (reset) the third node N3 and the fourth node N4 and clear the pre-stored voltage in the interior thereof, thereby completing initialization. The seventh transistor T7 is turned on, and the signal of the second initialization signal line INIT2 is written to the fifth node N5 to initialize (reset) the anode of the light emitting element EL and clear the pre-stored voltage in the interior thereof, thereby completing initialization. The ninth transistor T9 is turned on, and the signal of the reference signal line REF is written to the second node N2 to initialize (reset) the second node N2 and clear the pre-stored voltage in the interior thereof, thereby completing initialization.

[0210] The second stage S32 is called an initialization stage. The signals of the first reset signal line Reset1, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the first emission signal line EM1, and the second emission signal line EM2 are high-level signals. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned off.

[0211] In the third stage S33, called threshold compensation and data writing stage, the signals of the first and second scan signal lines Gate1 and Gate2 are low level signals, and the signals of the first reset signal line Reset1, the third scan signal line Gate3, the first and second light emitting signal lines EM1 and EM2 are high level signals. The data signal line Data outputs a data voltage. The second, fourth and eighth transistors T2, T4 and T8 are turned on, and the first, fifth, sixth, seventh and ninth transistors T1, T5, T6, T7 and T9 are turned off.

[0212] The data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4 and the turned-on eighth transistor T8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged into the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data, and Vth is the threshold voltage of the third transistor T3.

[0213] In the fourth stage S34, the signals of the third scan signal line Gate3 and the first light emitting signal line EM1 are low level signals, and the signals of the first, second, first reset signal line Reset1 and second light emitting signal lines Gate1, Gate2, Reset1 and EM2 are high level signals. The fifth transistor T5 is turned on, and the first, second, fourth, sixth, seventh, eighth and ninth transistors T1, T2, T4, T6, T7, T8 and T9 are turned off.

[0214] The signal of the first power supply line VDD is written to the second node N2 through the turned-on fifth transistor T5.

[0215] In the fifth stage S35, called light emitting stage, the signals of the first, second and third light emitting signal lines EM1, EM2 and Gate3 are low level signals, and the signals of the first reset signal line Reset1, the first and second scan signal lines Gate1 and Gate2 are high level signals. The fifth and sixth transistors T5 and T6 are turned on, and the first, second, fourth, seventh, eighth and ninth transistors T1, T2, T4, T7, T8 and T9 are turned off.

[0216] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power supply voltage output by the first power supply line VDD is supplied to the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on sixth transistor T6 to drive the light emitting element EL to emit light.

[0217] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*(Vdd-Vd) 2

[0218] wherein I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL, K is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line Data, and Vdd is the power supply voltage output by the first power supply line VDD.

[0219] FIG. 15 is a timing diagram of the pixel driving circuit provided in FIG. 11. FIG. 11 is described by taking the first transistor T1 to the seventh transistor T7 and the ninth transistor T9 as P-type transistors and the eighth transistor T8 as an N-type transistor as an example. As shown in FIG. 15, the working process of the pixel driving circuit provided in FIG. 11 can include:

[0220] The first stage S41 is referred to as the first initialization stage, the signals of the second reset signal line Reset2 and the second scan signal line Gate2 are low-level signals, and the signals of the first reset signal line Reset1, the first scan signal line Gate1, the third scan signal line Gate3, the first light emitting signal line EM1, and the second light emitting signal line EM2 are high-level signals. The second transistor T2, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, and the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off.

[0221] The seventh transistor T7 is turned on, the signal of the second initial signal line INIT2 is written to the fifth node N5, the anode of the light emitting element EL is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The ninth transistor T9 is turned on, the signal of the reference signal line REF is written to the second node N2, the second node N2 is initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed. The second transistor T2 and the eighth transistor T8 are turned on, so that the third node N3, the fourth node N4 and the first node N1 are communicated, and the signal of the second node N2 charges the first node N1, so that the voltage value of the signal of the first node N1 is Vref+Vth. At this time, the third transistor T3 is in a weak bias state, which is beneficial to the hysteresis recovery of the third transistor, and the threshold voltage drift caused by the bias state of the third transistor in the last display frame can be recovered.

[0222] The second stage S42 is called the second initialization stage, the signal of the first reset signal line Reset1 is a low-level signal, and the signals of the second reset signal line Reset2, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals. The first transistor T1 and the eighth transistor T8 are turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0223] The first transistor T1 and the eighth transistor T8 are turned on, and the signal of the first initial signal line INIT1 is written to the first node N1 through the fourth node N4, so that the first node N1 and the fourth node N4 are initialized (reset), the internal pre-stored voltage is emptied, and the initialization is completed.

[0224] The third stage S43 is called the threshold compensation and data writing stage, the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are low-level signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the third scan signal line Gate3, the first light-emitting signal line EM1 and the second light-emitting signal line EM2 are high-level signals. The data signal line Data outputs the data voltage. The second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the ninth transistor T9 are turned off.

[0225] The second transistor T2, the fourth transistor T4 and the eighth transistor T8 are turned on, the data voltage output by the data signal line Data is provided to the first node N1 through the turned-on fourth transistor T4, the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fourth node N4 and the turned-on eighth transistor T8, and the difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor T3 is charged to the capacitor C until the voltage of the first node N1 is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor T3.

[0226] In the fourth stage S44, the signals of the third scan signal line Gate3 and the first light-emitting signal line EM1 are low signals, and the signals of the first scan signal line Gate1, the second scan signal line Gate2, the first reset signal line Reset1, the second reset signal line Reset2 and the second light-emitting signal line EM2 are high signals. The fifth transistor T5 is turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0227] The fifth transistor T5 is turned on, and the signal of the first power supply line VDD is written to the second node N2.

[0228] In the fifth stage S45, referred to as a light-emitting stage, the signals of the first light-emitting signal line EM1, the second light-emitting signal line EM2 and the third scan signal line Gate3 are low signals, and the signals of the first reset signal line Reset1, the second reset signal line Reset2, the first scan signal line Gate1 and the second scan signal line Gate2 are high signals. The fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 are turned off.

[0229] The fifth transistor T5 and the sixth transistor T6 are turned on, and the power voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the light-emitting element EL through the turned-on fifth transistor T5, the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0230] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between the control electrode and the first electrode. Since the voltage of the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth]2 = K * (Vdd - Vd) 2

[0231] wherein I is a driving current flowing through the third transistor T3, that is, a driving current of the light emitting device EL, K is a constant, Vgs is a voltage difference between the control electrode and the first electrode of the third transistor T3, Vth is a threshold voltage of the third transistor T3, Vd is a data voltage output by the data signal line Data, and Vdd is a power voltage output by the first power supply line VDD.

[0232] In the pixel driving circuit provided in the example embodiments, the second transistor T4 is driven by the first scan signal line Gate1 and the fourth transistor T4 is driven by the second scan signal line Gate2, so that the second transistor T2 and the fourth transistor T4 are driven separately, the weak bias reset of the driving transistor is realized, and the bias state of the driving transistor is improved.

[0233] The display device provided in the example embodiments of the present disclosure further includes a substrate and a plurality of sub-pixels disposed on the substrate, wherein at least one sub-pixel includes a pixel driving circuit.

[0234] FIG. 16 is a structural schematic diagram of a display device provided in the example embodiments of the present disclosure, FIG. 17 is a schematic diagram of part of the film layers in FIG. 16, and FIG. 18 is another schematic diagram of part of the film layers in FIG. 16. As shown in FIGS. 16 to 18, the display device provided in the example embodiments of the present disclosure further includes a plurality of first light emitting signal lines EM1 and a plurality of second light emitting signal lines EM2, and at least one of the first light emitting signal lines EM1 and the second light emitting signal lines EM2 extends at least partially along the first direction D1. FIGS. 16 to 18 are described by taking the pixel driving circuit provided in FIG. 8 as an example.

[0235] The first light emitting signal line EM1(j) connected to the pixel driving circuit of the jth row of sub-pixels and the second light emitting signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels are the same signal line, 1≤j≤N, and N is the total number of rows of sub-pixels.

[0236] In an exemplary embodiment, as shown in FIGS. 16-18, the display device further comprises a plurality of first reset signal lines Reset1, the first reset signal lines Reset1 extending at least partially along the first direction D1. The first reset signal lines to which the pixel driving circuit of the jth row of sub-pixels is connected include two, the first first reset signal line Reset1(j) to which the pixel driving circuit of the jth row of sub-pixels is connected and the second first reset signal line Reset1(j-1) to which the pixel driving circuit of the (j-1)th row of sub-pixels is connected are the same signal line, and the second first reset signal line Reset1(j) to which the pixel driving circuit of the jth row of sub-pixels is connected and the first first reset signal line Reset1(j+1) to which the pixel driving circuit of the (j+1)th row of sub-pixels is connected are the same signal line.

[0237] In an exemplary embodiment, as shown in FIGS. 16-18, the display device further comprises a plurality of first scan signal lines Gate1, a plurality of third scan signal lines Gate3, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, and a plurality of reference signal lines REF. At least one of the first scan signal lines Gate1, the third scan signal lines Gate3, the first initial signal lines INIT1, the second initial signal lines INIT2, and the reference signal lines REF extends at least partially along the first direction D1.

[0238] In an exemplary embodiment, as shown in FIGS. 16-18, the first emission signal line EM1(j) to which the pixel driving circuit of the jth row of sub-pixels is connected, the first first reset signal line Reset1(j) to which the pixel driving circuit of the jth row of sub-pixels is connected, the first scan signal line Gate1(j) to which the pixel driving circuit of the jth row of sub-pixels is connected, the second emission signal line EM2(j) to which the pixel driving circuit of the jth row of sub-pixels is connected, and the second first reset signal line Reset1(j) to which the pixel driving circuit of the jth row of sub-pixels is connected are arranged in the second direction D2 in sequence, and the first direction D1 and the second direction D2 intersect.

[0239] In the exemplary embodiments, as shown in FIGS. 16-18, the orthogonal projection of the reference signal line REF(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate at least partially overlaps the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels, the orthogonal projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate at least partially overlaps the orthogonal projection of the first emission signal line EM1(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate, the orthogonal projection of the third scan signal line Gate3(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate is between the orthogonal projection of the first scan signal line Gate1(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate and the orthogonal projection of the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate, and the orthogonal projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate is on one side of the orthogonal projection of the second reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels away from the orthogonal projection of the second emission signal line EM2(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate.

[0240] In the exemplary embodiments, as shown in FIG. 16, the at least one pixel driving circuit includes the first transistor T1 to the ninth transistor T9, and the at least one transistor includes an active pattern.

[0241] The active pattern T11 of the first transistor, the active pattern T21 of the second transistor, the active pattern T31 of the third transistor, the active pattern T41 of the fourth transistor, the active pattern T61 of the sixth transistor, and the active pattern T71 of the seventh transistor located in the same sub-pixel are in one structure, and the active pattern T51 of the fifth transistor and the active pattern T91 of the ninth transistor located in the same sub-pixel are in one structure.

[0242] The active pattern T51(j) of the fifth transistor in the pixel driving circuit of the jth row of sub-pixels is arranged along the first direction D1 with the active pattern T61(j-1) of the sixth transistor in the pixel driving circuit of the j-1th row of sub-pixels, and the active pattern T91(j) of the ninth transistor in the pixel driving circuit of the jth row of sub-pixels, the active pattern T11(j) of the first transistor in the pixel driving circuit of the jth row of sub-pixels, and the active pattern T71(j-1) of the seventh transistor in the pixel driving circuit of the j-1th row of sub-pixels are arranged along the first direction D1.

[0243] In an exemplary embodiment, as shown in FIGS. 16-19, the at least one transistor further comprises: a first electrode and a second electrode, the active pattern comprises a first region and a second region, the second electrode T54 of the fifth transistor and the second electrode T94 of the ninth transistor are in a unitary structure and extend along the second direction D2.

[0244] In an exemplary embodiment, the first region of the active pattern of the third transistor and the second region of the active pattern of the fourth transistor are the same region, the second region of the active pattern of the fifth transistor and the second region of the active pattern of the ninth transistor are the same region. The second electrode of the fifth transistor is connected to the first region of the active pattern of the third transistor and the second region of the active pattern of the fifth transistor, respectively.

[0245] In an exemplary embodiment, the orthogonal projection of the second electrode T54(j) of the fifth transistor in the pixel driving circuit of the jth column of sub-pixels on the substrate at least partially overlaps with the orthogonal projection of at least one of the reference signal line REF(j) connected to the pixel driving circuit of the jth row of sub-pixels, the second initial signal line INIT2(j-1) connected to the (j-1)th row of sub-pixels, the third scan signal line Gate3(j) connected to the pixel driving circuit of the jth row of sub-pixels, and the first scan signal line Gate1(j) connected to the pixel driving circuit of the jth row of sub-pixels on the substrate.

[0246] In an exemplary embodiment, as shown in FIG. 16, the display device can further comprise: a plurality of initial connection lines INL, a plurality of first power supply lines VDD, and a plurality of data signal lines Data, at least one of the first power supply lines VDD, the data signal lines Data, and the initial connection lines INL at least partially extends along the second direction D2. Among them, at least one initial connection line INL is electrically connected to at least one first initial signal line INIT1.

[0247] In an exemplary embodiment, the display device further comprises: a substrate and a driving structure layer provided on the substrate, the driving structure layer is provided with a pixel driving circuit, the pixel driving circuit comprises: at least one N-type transistor, at least one P-type transistor, and a capacitor, the capacitor comprises: a first electrode plate and a second electrode plate, the transistor comprises: an active pattern, a control electrode, a first electrode, and a second electrode, the third scan signal line comprises a first sub-signal line and a second sub-signal line.

[0248] The driving structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer, which are sequentially stacked on the substrate.

[0249] The first semiconductor layer at least comprises: an active pattern of at least one P-type transistor.

[0250] The first conductive layer at least includes a first scan signal line, a first light-emitting signal line, a second light-emitting signal line, a first reset signal line, and a first plate of a capacitor in the at least one pixel driving circuit and a control electrode of the at least one P-type transistor.

[0251] The second conductive layer at least includes a first sub-signal line of a third scan signal line, a second initial signal line, and a second plate of a capacitor in a pixel driving circuit of the at least one sub-pixel.

[0252] The second semiconductor layer at least includes an active pattern of the at least one N-type transistor.

[0253] The third conductive layer at least includes a second sub-signal line of a third scan signal line, a first initial signal line, and a reference signal line.

[0254] The fourth conductive layer at least includes an initial connection line and a first electrode and a second electrode of the at least one transistor in the at least one pixel driving circuit.

[0255] In the exemplary embodiments, the substrate can be a rigid substrate or a flexible substrate, wherein the rigid substrate can be, but is not limited to, one or more of glass, conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers.

[0256] In the exemplary embodiments, the display device can further include a light-emitting structure layer.

[0257] In the exemplary embodiments, the light-emitting structure layer includes, in sequence, an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer, which are stacked on the substrate. The anode layer includes an anode of the at least one light-emitting device, the organic structure layer includes an organic light-emitting layer, and the cathode layer includes a cathode of the at least one light-emitting device.

[0258] The preparation process of the display substrate is exemplarily illustrated below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0259] FIGS. 19 to 35 are illustrated by taking two columns of pixel driving circuits provided in FIG. 16 as an example. The preparation process of the display substrate provided in the present disclosure can include:

[0260] (1) forming a light shielding layer pattern, in the exemplary embodiments, forming a light shielding layer pattern includes: depositing a light shielding thin film on a substrate, patterning the light shielding thin film by a patterning process, forming a light shielding layer pattern, as shown in FIG. 19, which is a schematic diagram after forming a light shielding layer pattern in FIG. 16.

[0261] In the exemplary embodiments, as shown in FIG. 19, the light shielding layer pattern can include: an array arrangement, and light shielding portions SDL arranged at intervals with each other, and the light shielding layer pattern can further include: a first light shielding connecting portion SL1 and a second light shielding connecting portion SL2.

[0262] In the exemplary embodiments, the shape of the light shielding portion SHL can be square.

[0263] In the exemplary embodiments, the first light shielding connecting portion SL1 connects adjacent light shielding portions SDL in the same column. In the exemplary embodiments, the shape of the first light shielding connecting portion SL1 can be a strip structure extending along the second direction D2.

[0264] In an exemplary embodiment, the second light shielding connection portion SL2 connects the adjacent light shielding portions SDL located in the same row. In an exemplary embodiment, the second light shielding connection portion SL2 can have a shape of a strip structure extending in the first direction D1.

[0265] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern can include sequentially depositing a first insulating thin film and a first semiconductor thin film on the substrate, patterning the first semiconductor thin film by a patterning process, and forming a first insulating layer covering the substrate and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIGS. 20 and 21, where FIG. 20 is a schematic view of the first semiconductor layer pattern in FIG. 16, and FIG. 21 is a schematic view of FIG. 16 after forming the first semiconductor layer pattern.

[0266] In an exemplary embodiment, as shown in FIGS. 20 and 21, the first semiconductor layer pattern can include at least an active pattern T11 of a first transistor, an active pattern T21 of a second transistor, an active pattern T31 of a third transistor, an active pattern T41 of a fourth transistor, an active pattern T51 of a fifth transistor, an active pattern T61 of a sixth transistor, an active pattern T71 of a seventh transistor, and an active pattern T91 of a ninth transistor of at least one sub-pixel. The active pattern T11(j) of the first transistor in FIG. 21 refers to the active pattern of the first transistor of the pixel driving circuit of the jth row of sub-pixels, the active pattern T21(j) of the second transistor refers to the active pattern of the second transistor of the pixel driving circuit of the jth row of sub-pixels, the active pattern T31(j) of the third transistor refers to the active pattern of the third transistor of the pixel driving circuit of the jth row of sub-pixels, the active pattern T41(j) of the fourth transistor refers to the active pattern of the fourth transistor of the pixel driving circuit of the jth row of sub-pixels, the active pattern T51(j) of the fifth transistor refers to the active pattern of the fifth transistor of the pixel driving circuit of the jth row of sub-pixels, the active pattern T61(j) of the sixth transistor refers to the active pattern of the sixth transistor of the pixel driving circuit of the jth row of sub-pixels, the active pattern T71(j) of the seventh transistor refers to the active pattern of the seventh transistor of the pixel driving circuit of the jth row of sub-pixels, and the active pattern T91(j) of the ninth transistor refers to the active pattern of the ninth transistor of the pixel driving circuit of the jth row of sub-pixels.

[0267] In an exemplary embodiment, the active patterns T11, T21, T31, T41, T51, T61, T71, and T91 of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor of the adjacent sub-pixels located in the same row are symmetrically disposed with respect to a virtual straight line extending in the second direction D2.

[0268] In the example embodiment, the active pattern T11 of the first transistor, the active pattern T21 of the second transistor, the active pattern T31 of the third transistor, the active pattern T41 of the fourth transistor, the active pattern T61 of the sixth transistor, and the active pattern T71 of the seventh transistor located in the same sub-pixel are in one body structure. The active pattern T51 of the fifth transistor and the active pattern T91 of the ninth transistor located in the same sub-pixel are in one body structure. The one body structure of the active pattern T11 of the first transistor, the active pattern T21 of the second transistor, the active pattern T31 of the third transistor, the active pattern T41 of the fourth transistor, the active pattern T61 of the sixth transistor, and the active pattern T71 of the seventh transistor located in the same sub-pixel and the one body structure of the active pattern T51 of the fifth transistor and the active pattern T91 of the ninth transistor located in the same sub-pixel are arranged separately.

[0269] In the example embodiment, for the pixel driving circuit of the jth row of sub-pixels, in the first direction D1, the active pattern T41(j) of the fourth transistor can be located on the same side of the active pattern T31(j) of the third transistor, the active pattern T61(j) of the sixth transistor can be located on the same side of the active pattern T31(j) of the third transistor, and the active pattern T61(j) of the sixth transistor and the active pattern T41(j) of the fourth transistor can be located on different sides of the active pattern T31(j) of the third transistor in the same sub-pixel. In the second direction D2, the active pattern T11(j) of the first transistor, the active pattern T21(j) of the second transistor, the active pattern T41(j) of the fourth transistor, the active pattern T51(j) of the fifth transistor, and the active pattern T91(j) of the ninth transistor located in the third transistor of the pixel driving circuit of the jth row of sub-pixels are close to the side of the pixel driving circuit of the j-1th row of sub-pixels, and the active pattern T71(j) of the seventh transistor can be located on the side of the pixel driving circuit of the jth row of sub-pixels close to the pixel driving circuit of the j+1th row of sub-pixels.

[0270] In the example embodiment, the active pattern T51(j) of the fifth transistor and the active pattern T91(j) of the ninth transistor in the pixel driving circuit of the jth row of sub-pixels are located on the side of the active pattern T41(j) of the fourth transistor in the pixel driving circuit of the jth row of sub-pixels close to the pixel driving circuit of the j-1th row of sub-pixels, and the active pattern T51(j) of the fifth transistor in the pixel driving circuit of the jth row of sub-pixels is located on the side of the active pattern T91(j) of the ninth transistor away from the active pattern T31(j) of the third transistor.

[0271] In the exemplary embodiment, the active pattern T51(j) of the fifth transistor in the pixel driving circuit of the jth row of sub-pixels is arranged along the first direction D1 with the active pattern T61(j-1) of the sixth transistor in the pixel driving circuit of the j-1th row of sub-pixels. The active pattern T91(j) of the ninth transistor in the pixel driving circuit of the jth row of sub-pixels, the active pattern T11(j) of the first transistor in the pixel driving circuit of the jth row of sub-pixels, and the active pattern T71(j-1) of the seventh transistor in the pixel driving circuit of the j-1th row of sub-pixels are arranged along the first direction D1.

[0272] In the exemplary embodiment, for at least one sub-pixel, the shape of the active pattern T31 of the third transistor can be an upside-down “Ω” shape. The shape of the active pattern T11 of the first transistor, the active pattern T41 of the fourth transistor, the active layer T51 of the fifth transistor, the active pattern T61 of the sixth transistor, the active layer T71 of the seventh transistor, and the active layer T91 of the ninth transistor can be an “I” shape. The shape of the active pattern T21 of the second transistor can be a “┐” shape.

[0273] In the exemplary embodiment, the active pattern of each transistor can include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiment, for the pixel driving circuit of at least one sub-pixel, the second region T11_2 of the active pattern T11 of the first transistor can simultaneously serve as the first region T21-1 of the active pattern T21 of the second transistor, the first region T31_1 of the active pattern T31 of the third transistor can simultaneously serve as the second region T41_2 of the active pattern T41 of the fourth transistor, the second region T31_2 of the active pattern T31 of the third transistor can simultaneously serve as the second region T21-2 of the active pattern T21 of the second transistor and the first region T61_1 of the active pattern T61 of the sixth transistor, the second region T61_2 of the active pattern T61 of the sixth transistor can serve as the second region T71_2 of the active pattern T71 of the seventh transistor, the second region T51_2 of the active pattern T51 of the fifth transistor can serve as the second region T91_2 of the active pattern T91 of the ninth transistor, and the first region T11-1 of the active pattern T11 of the first transistor, the first region T41_1 of the active pattern T41 of the fourth transistor, the first region T51_1 of the active pattern T51 of the fifth transistor, the first region T71_1 of the active pattern T71 of the seventh transistor, and the first region T91-1 of the active pattern T91 of the ninth transistor can be separately provided.

[0274] In the exemplary embodiment, the first region T71_1 of the active pattern T71 of the seventh transistor of at least two adjacent sub-pixels in the same row is the same region.

[0275] In the exemplary embodiments, the normal projection of the active pattern of the third transistor T31 in the pixel driving circuit of the at least one sub-pixel on the substrate at least partially overlaps with the normal projection of the light shielding portion on the substrate.

[0276] (3) Forming the first conductive layer pattern, in the exemplary embodiments, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the second insulating thin film and the first conductive thin film by a patterning process to form a second insulating layer pattern and a first conductive layer pattern on the second insulating layer, as shown in FIG. 22 and FIG. 23, wherein FIG. 22 is a schematic diagram of the first conductive layer pattern in FIG. 16, and FIG. 23 is a schematic diagram of FIG. 16 after the first conductive layer pattern is formed. In the exemplary embodiments, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0277] In the exemplary embodiments, as shown in FIG. 22 and FIG. 23, the first conductive layer pattern can include: a first scanning signal line Gate1, a first light emitting signal line EM1, a second light emitting signal line EM2, a first reset signal line Reset1, and a first plate C1 of a capacitor of the at least one pixel driving circuit, a control electrode T11 of the first transistor, a control electrode T22 of the second transistor, a control electrode T32 of the third transistor, a control electrode T42 of the fourth transistor, a control electrode T52 of the fifth transistor, a control electrode T62 of the sixth transistor, a control electrode T72 of the seventh transistor, and a control electrode T92 of the ninth transistor. Gate1(j) in FIG. 22 refers to the first scanning signal line connected to the pixel driving circuit of the jth row of sub-pixels, EM1(j) refers to the first light emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels, EM2(j) refers to the second light emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels, and Reset1(j) refers to the first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels.

[0278] In the exemplary embodiments, the first light emitting signal line EM1(j) connected to the pixel driving circuit of the jth row of sub-pixels and the second light emitting signal line EM2(j-1) connected to the pixel driving circuit of the j-1th row of sub-pixels are the same signal line.

[0279] In the example embodiment, the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels includes two lines. The first line of the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels is the same signal line as the second line of the first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels, and the second line of the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels is the same signal line as the first line of the first reset signal line Reset1(j+1) connected to the pixel driving circuit of the (j+1)th row of sub-pixels.

[0280] In the example embodiment, the first emission signal line EM1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second emission signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels), the first line of the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second line of the first reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels), the first scan signal line Gate1(j) connected to the pixel driving circuit of the jth row of sub-pixels, the second emission signal line EM2(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the first emission signal line EM1(j+1) connected to the pixel driving circuit of the (j+1)th row of sub-pixels), and the second line of the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the first line of the first reset signal line Reset1(j+1) connected to the pixel driving circuit of the (j+1)th row of sub-pixels) are arranged in the second direction D2 in sequence.

[0281] In the example embodiment, the first plate C1 of the capacitor of the pixel driving circuit of the adjacent sub-pixel, the control electrode T11 of the first transistor, the control electrode T22 of the second transistor, the control electrode T32 of the third transistor, the control electrode T42 of the fourth transistor, the control electrode T52 of the fifth transistor, the control electrode T62 of the sixth transistor, the control electrode T72 of the seventh transistor, and the control electrode T92 of the ninth transistor are symmetrically arranged with respect to the virtual straight line extending in the second direction D2.

[0282] In the example embodiment, for the pixel driving circuit of the jth row of sub-pixels, the shape of the first plate C1(j) can be a rectangular shape, the corner of the rectangular shape can be chamfered, and the orthographic projection of the first plate C1(j) on the substrate at least partially overlaps with the orthographic projection of the active pattern of the third transistor on the substrate. In the example embodiment, the first plate C1(j) can simultaneously serve as one plate of the capacitor and the gate electrode T32(j) of the third transistor.

[0283] In an example embodiment, a normal projection of the first plate of the capacitor on the substrate at least partially overlaps with a normal projection of the light-shielding portion on the substrate.

[0284] In an example embodiment, the first scan signal line Gate1 can have a linear shape in which a main body portion extends along the first direction D1. The first scan signal line Gate1 connected to the pixel drive circuit of the jth row of subpixels can be located on a side of the pixel drive circuit of the jth row of subpixels that is closer to the first plate C1(j) of the capacitor in the pixel drive circuit of the jth row of subpixels (also the gate electrode T32(j) of the third transistor). An area of the first scan signal line Gate1 connected to the pixel drive circuit of the jth row of subpixels that overlaps with the active pattern of the second transistor in the pixel drive circuit of the jth row of subpixels can serve as the gate electrode T22(j) of the second transistor, and an area of the first scan signal line Gate1 connected to the pixel drive circuit of the jth row of subpixels that overlaps with the active pattern of the fourth transistor in the pixel drive circuit of the jth row of subpixels can serve as the gate electrode T42(j) of the fourth transistor.

[0285] In an example embodiment, the first emission signal line EM1 can have a linear shape in which a main body portion extends along the first direction D1. The first emission signal line EM1 connected to the pixel drive circuit of the jth row of subpixels (also the second emission signal line EM2 connected to the pixel drive circuit of the (j-1)th row of subpixels) can be located on a side of the first scan signal line Gate1 connected to the pixel drive circuit of the jth row of subpixels that is farther from the first plate C1(j) of the capacitor in the pixel drive circuit of the jth row of subpixels (also the gate electrode T32(j) of the third transistor). An area of the first emission signal line EM1 connected to the pixel drive circuit of the jth row of subpixels (also the second emission signal line EM2 connected to the pixel drive circuit of the (j-1)th row of subpixels) that overlaps with the active pattern of the fifth transistor in the pixel drive circuit of the jth row of subpixels can serve as the gate electrode T52(j) of the fifth transistor in the pixel drive circuit of the jth row of subpixels, and an area of the first emission signal line EM1 connected to the pixel drive circuit of the jth row of subpixels (also the second emission signal line EM2 connected to the pixel drive circuit of the (j-1)th row of subpixels) that overlaps with the active pattern of the sixth transistor in the pixel drive circuit of the (j-1)th row of subpixels can serve as the gate electrode T62(j-1) of the sixth transistor in the pixel drive circuit of the (j-1)th row of subpixels.

[0286] In the example embodiment, the shape of the second light emission signal line EM2 can be a line shape in which a main body portion extends along the first direction D1. The second light emission signal line EM2(j) connected to the pixel driving circuit of the jth row of subpixels (also the first light emission signal line EM1(j) connected to the pixel driving circuit of the (j+1)th row of subpixels) can be located on a side of the first plate C1(j) of the capacitor in the pixel driving circuit of the jth row of subpixels (also the gate electrode T32(j) of the third transistor) away from the first scan signal line Gate1(j) connected to the pixel driving circuit of the jth row of subpixels. An area in which the second light emission signal line EM2(j) connected to the pixel driving circuit of the jth row of subpixels (also the first light emission signal line EM1(j) connected to the pixel driving circuit of the (j+1)th row of subpixels) overlaps with the active pattern of the fifth transistor of the pixel driving circuit of the (j+1)th row of subpixels serves as the gate electrode T52(j+1) of the fifth transistor in the pixel driving circuit of the (j+1)th row of subpixels, and an area in which the second light emission signal line EM2(j) connected to the pixel driving circuit of the jth row of subpixels (also the first light emission signal line EM1(j) connected to the pixel driving circuit of the (j+1)th row of subpixels) overlaps with the active pattern of the sixth transistor of the pixel driving circuit of the jth row of subpixels serves as the gate electrode T62(j) of the sixth transistor in the pixel driving circuit of the jth row of subpixels.

[0287] In the example embodiment, the shape of the first reset signal line Reset1 can be a line shape in which a main body portion extends along the first direction D1.

[0288] In the exemplary embodiment, the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels) is located between the first emission signal line EM1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second emission signal line EM2(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels) and the first scan signal line Gate1(j) connected to the pixel driving circuit of the jth row of sub-pixels, the region where the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels) overlaps with the active pattern of the first transistor of the pixel driving circuit of the jth row of sub-pixels serves as the gate electrode T12(j) of the first transistor in the pixel driving circuit of the jth row of sub-pixels, the region where the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels) overlaps with the active pattern of the ninth transistor of the pixel driving circuit of the jth row of sub-pixels serves as the gate electrode T92(j) of the ninth transistor in the pixel driving circuit of the jth row of sub-pixels, and the region where the first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the second reset signal line Reset1(j-1) connected to the pixel driving circuit of the (j-1)th row of sub-pixels) overlaps with the active pattern of the seventh transistor of the pixel driving circuit of the (j-1)th row of sub-pixels serves as the gate electrode T72(j-1) of the seventh transistor in the pixel driving circuit of the (j-1)th row of sub-pixels.

[0289] In the exemplary embodiment, the second first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the jth row of sub-pixels) is located on the side away from the first plate C1(j) (also the gate electrode T32(j) of the third transistor) of the capacitor in the pixel driving circuit of the jth row of sub-pixels of the second emission signal line EM2(j) (also the first emission signal line EM1(j+1) connected to the pixel driving circuit of the j+1th row of sub-pixels). The region where the second first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the jth row of sub-pixels) overlaps with the active pattern of the first transistor of the pixel driving circuit of the j+1th row of sub-pixels serves as the gate electrode T12(j+1) of the first transistor in the pixel driving circuit of the j+1th row of sub-pixels, the region where the second first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the jth row of sub-pixels) overlaps with the active pattern of the ninth transistor of the pixel driving circuit of the j+1th row of sub-pixels serves as the gate electrode T92(j+1) of the ninth transistor in the pixel driving circuit of the j+1th row of sub-pixels, and the region where the second first reset signal line Reset1(j) connected to the pixel driving circuit of the jth row of sub-pixels (also the first first reset signal line Reset1(j+1) connected to the pixel driving circuit of the jth row of sub-pixels) overlaps with the active pattern of the seventh transistor of the pixel driving circuit of the jth row of sub-pixels serves as the gate electrode T72(j) of the seventh transistor in the pixel driving circuit of the jth row of sub-pixels.

[0290] In the exemplary embodiment, the first scan signal line Gate1, the first reset signal line Reset1, the first emission signal line EM1 and the second emission signal line EM2 can be of equal width design or of non-equal width design, can be straight lines or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0291] In the example embodiment, after the first conductive layer pattern is formed, the first semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield. The first semiconductor layer in the region shielded by the first conductive layer forms the channel region of the first to seventh transistors and the ninth transistor, and the first semiconductor layer in the region not shielded by the first conductive layer is conductorized, that is, the first and second regions of the first to seventh transistors and the ninth transistor are conductorized. The second region T11_2 of the active pattern T11 of the first transistor after conductorization (also the first region T21-1 of the active pattern T21 of the second transistor) is multiplexed as the second electrode T14 of the first transistor (also the first electrode T13 of the second transistor), the first region T31_1 of the active pattern T31 of the third transistor (also the second region T41_2 of the active pattern T41 of the fourth transistor) is multiplexed as the first electrode T33 of the third transistor (also the second electrode T44 of the fourth transistor), and the second region T31_2 of the active pattern T31 of the third transistor (also the second region T21-2 of the active pattern T21 of the second transistor and the first region T61_1 of the active pattern T61 of the sixth transistor) is multiplexed as the second electrode T34 of the third transistor (also the second electrode T24 of the second transistor and the first electrode T63 of the sixth transistor).

[0292] In the example embodiment, the gate electrode of the first transistor is disposed across the active pattern of the first transistor, the gate electrode of the second transistor is disposed across the active pattern of the second transistor, the gate electrode of the third transistor is disposed across the active pattern of the third transistor, the gate electrode of the fourth transistor is disposed across the active pattern of the fourth transistor, the gate electrode of the fifth transistor is disposed across the active pattern of the fifth transistor, the gate electrode of the sixth transistor is disposed across the active pattern of the sixth transistor, the gate electrode of the seventh transistor is disposed across the active pattern of the seventh transistor, and the gate electrode of the ninth transistor is disposed across the active pattern of the ninth transistor, that is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active pattern.

[0293] (4) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the third insulating thin film and the second conductive thin film by a patterning process to form a third insulating layer pattern and a second conductive layer pattern on the second insulating layer, as shown in FIG. 24 and FIG. 25. FIG. 24 is a schematic diagram of the second conductive layer pattern in FIG. 16, and FIG. 25 is a schematic diagram of FIG. 16 after the second conductive layer pattern is formed. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0294] In an exemplary embodiment, as shown in FIG. 24 and FIG. 25, the second conductive layer pattern can include: a first sub-signal line Gate3A of the third scan signal line, a second initial signal line INIT2, and a second plate C2 of the capacitor and a first control pole T82A of the eighth transistor in the pixel driving circuit of at least one sub-pixel. Gate3A(j) refers to the first sub-signal line of the third scan signal line connected to the pixel driving circuit of the jth row of sub-pixels, and INIT2(j) refers to the second initial signal line connected to the pixel driving circuit of the jth row of sub-pixels. C2(j) refers to the second plate of the capacitor in the pixel driving circuit of the jth row of sub-pixels, and T82A(j) refers to the first control pole of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels.

[0295] In an exemplary embodiment, the second plate C2 of the capacitor and the first control pole T82A of the eighth transistor of the pixel driving circuit of the adjacent sub-pixels in the same row are symmetrically arranged with respect to the virtual straight line extending along the second direction D2.

[0296] In an exemplary embodiment, the second plate C2 of the capacitor of the pixel driving circuit of the adjacent sub-pixels in the same row is electrically connected.

[0297] In an exemplary embodiment, the main contour of the second plate C2 of the capacitor can be rectangular, and the corners of the rectangular shape can be chamfered. The orthographic projection of the second plate of the capacitor on the substrate at least partially overlaps the orthographic projection of the first plate on the substrate. The second plate can serve as the other plate of the capacitor, and the first plate and the second plate constitute the capacitor of the pixel driving circuit. The second plate of the capacitor is provided with an opening V0, which can be rectangular in shape and can be located in the middle of the second plate of the capacitor, forming a ring structure. The opening V0 exposes the third insulating layer covering the first plate, and the orthographic projection of the first plate on the substrate contains the orthographic projection of the opening on the substrate. In an exemplary embodiment, the opening exposes the first plate, so that the first pole of the eighth transistor formed subsequently is connected to the first plate.

[0298] In the example embodiment, the first sub-signal line Gate3A of the third scan signal line can be in a linear shape with a main body extending along the first direction D1. The orthographic projection of the first sub-signal line Gate3A(j) of the third scan signal line connected to the pixel driving circuit of the jth row of sub-pixels on the base substrate is located between the orthographic projection of the first scan signal line connected to the pixel driving circuit of the jth row of sub-pixels on the base substrate and the orthographic projection of the first first reset signal line (also the second first reset signal line connected to the pixel driving circuit of the j-1th row of sub-pixels) on the base substrate. The area where the first sub-signal line Gate3A(j) of the third scan signal line connected to the pixel driving circuit of the jth row of sub-pixels overlaps with the active pattern of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels formed subsequently serves as the first control electrode of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels.

[0299] In the example embodiment, the second initial signal line INIT2 can be in a linear shape with a main body extending along the first direction D1. The orthographic projection of the second initial signal line INIT2(j) connected to the pixel driving circuit of the jth row of sub-pixels on the base substrate is located on the side away from the orthographic projection of the second emission signal line (also the first emission signal line connected to the pixel driving circuit of the j+1th row of sub-pixels) on the base substrate of the second first reset signal line (also the first second reset signal line connected to the pixel driving circuit of the j+1th row of sub-pixels) connected to the pixel driving circuit of the jth row of sub-pixels on the base substrate.

[0300] In the example embodiment, the second initial signal line and the first sub-signal line of the third scan signal line can be in an equal-width design or a non-equal-width design, and can be a straight line or a broken line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0301] (5) Forming a second semiconductor layer pattern. In the example embodiment, forming the second semiconductor layer pattern can include: on the base substrate on which the aforementioned pattern is formed, sequentially depositing a fourth insulating thin film and a second semiconductor thin film on the base substrate, patterning the fourth insulating thin film and the second semiconductor thin film by a patterning process, forming a fourth insulating layer pattern and a second semiconductor layer pattern on the third insulating layer, as shown in FIG. 26 and FIG. 27, FIG. 26 is a schematic diagram of the second semiconductor layer pattern in FIG. 16, and FIG. 27 is a schematic diagram after the second semiconductor layer pattern is formed in FIG. 16.

[0302] In an exemplary embodiment, as shown in FIGS. 26 and 27, the second semiconductor layer can include an active pattern T81 of the eighth transistor of the pixel driving circuit of at least one of the sub-pixels. T81(j) refers to the active pattern of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels.

[0303] In an exemplary embodiment, as shown in FIGS. 26 and 27, the active pattern T81 of the eighth transistor includes a first active portion A1 and a second active portion A2, the first active portion A1 is in a linear shape extending along the second direction D2, the second active portion A2 is in a linear shape extending along the first direction D1, and the first active portion A1 and the second active portion A2 are arranged at right angles.

[0304] In an exemplary embodiment, the first active portion in the active pattern T81(j) of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels has a normal projection on the substrate that at least partially overlaps with a normal projection on the substrate of the first sub-signal line of the third scan signal line connected to the pixel driving circuit of the jth row of sub-pixels, and the second active portion in the active pattern T81(j) of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels has a normal projection on the substrate that at least partially overlaps with a normal projection on the substrate of the first scan signal line connected to the pixel driving circuit of the jth row of sub-pixels.

[0305] In an exemplary embodiment, the active pattern T11 of the eighth transistor is disposed across the first control electrode of the eighth transistor.

[0306] (6) Forming a third conductive layer pattern, in an exemplary embodiment, forming the second semiconductor layer pattern can include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating thin film and a third conductive thin film, patterning the fifth insulating thin film and the third conductive thin film through a patterning process, forming a fifth insulating layer pattern and a third conductive layer pattern on the fifth insulating layer, as shown in FIGS. 28 and 29, FIG. 28 is a schematic diagram of the third conductive layer pattern in FIG. 16, and FIG. 29 is a schematic diagram after the third conductive layer pattern in FIG. 16 is formed. In an exemplary embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0307] In an exemplary embodiment, as shown in FIGS. 28 and 29, the third conductive layer pattern can include a second sub-signal line Gate3B of the third scan signal line, a first initial signal line INIT1, a reference signal line REF, and a first control electrode T82B of the eighth transistor in the pixel driving circuit of at least one sub-pixel. Gate3B(j) refers to the second sub-signal line of the third scan signal line to which the pixel driving circuit of the jth row of sub-pixels is connected, INIT1(j) refers to the first initial signal line to which the pixel driving circuit of the jth row of sub-pixels is connected, REF(j) refers to the reference signal line to which the pixel driving circuit of the jth row of sub-pixels is connected, and T82B(j) refers to the second control electrode of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels.

[0308] In an exemplary embodiment, the second control electrodes T82B of the eighth transistors of the pixel driving circuits of the adjacent sub-pixels in the same row are symmetrically disposed with respect to a virtual straight line extending in the second direction D2

[0309] In an exemplary embodiment, the second sub-signal line Gate3B of the third scan signal line can have a linear shape in which a main body portion extends in the first direction D1. The normal projection of the second sub-signal line Gate3B(j) of the third scan signal line to which the pixel driving circuit of the jth row of sub-pixels is connected on the base at least partially overlaps the normal projection of the first sub-signal line of the third scan signal line to which the pixel driving circuit of the jth row of sub-pixels is connected. The area in which the second sub-signal line Gate3B(j) of the third scan signal line to which the pixel driving circuit of the jth row of sub-pixels is connected overlaps the active pattern of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels serves as the second control electrode of the eighth transistor in the pixel driving circuit of the jth row of sub-pixels.

[0310] In an exemplary embodiment, the first initial signal line INIT1 can have a linear shape in which a main body portion extends in the first direction D1. The normal projection of the second initial signal line INIT2(j) to which the pixel driving circuit of the jth row of sub-pixels is connected on the base at least partially overlaps the normal projection of the first emission signal line to which the pixel driving circuit of the jth row of sub-pixels is connected (which is also the second emission signal line to which the pixel driving circuit of the jth-1 row of sub-pixels is connected).

[0311] In an exemplary embodiment, the reference signal line REF can have a linear shape in which a main body portion extends in the first direction D1. The normal projection of the reference signal line REF(j) to which the pixel driving circuit of the jth row of sub-pixels is connected on the base at least partially overlaps the normal projection of the first reset signal line to which the pixel driving circuit of the jth row of sub-pixels is connected (which is also the second reset signal line to which the pixel driving circuit of the jth-1 row of sub-pixels is connected).

[0312] In the example embodiment, the first initial signal line, the reference signal line, and the second sub-signal line of the third scan signal line can be designed with equal width or non-equal width, can be a straight line or a broken line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0313] (7) Forming a sixth insulating layer pattern, comprising: depositing a sixth insulating thin film on the substrate on which the aforementioned pattern is formed, and patterning the sixth insulating thin film by a patterning process to form a sixth insulating layer pattern covering the aforementioned pattern, the sixth insulating layer being provided with a plurality of via hole patterns, as shown in FIG. 30, which is a schematic diagram after the formation of the sixth insulating layer pattern in FIG. 16.

[0314] In the example embodiment, as shown in FIG. 30, the plurality of via holes of the sixth insulating layer at least include a first via hole V1 to a sixteenth via hole V16 of the pixel driving circuit of at least one sub-pixel.

[0315] In the example embodiment, the first via hole V1 is located within the range of the first active pattern of the first transistor on the substrate, and the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 are etched to expose the surface of the first active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the first transistor formed subsequently with the first active layer of the first transistor through the via hole.

[0316] In the example embodiment, the first via hole V1 is located within the range of the first active pattern of the first transistor on the substrate, and the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 are etched to expose the surface of the first active layer of the first transistor, and the first via hole V1 is configured to connect the first electrode of the first transistor formed subsequently with the first active layer of the first transistor through the via hole.

[0317] In an example embodiment, the second via V2 is located within the footprint of the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the second via V2 are etched away, exposing the surface of the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor), and the second via V2 is configured to allow the second electrode of the first transistor (also the first electrode of the second transistor and the second electrode of the eighth transistor) to be connected to the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through the via.

[0318] In an example embodiment, the third via V3 is located within the footprint of the first region of the active pattern of the third transistor (also the second region of the active pattern of the fourth transistor) on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the third via V3 are etched away, exposing the surface of the first region of the active pattern of the third transistor (also the second region of the active pattern of the fourth transistor), and the third via V3 is configured to allow the second electrode of the fifth transistor (also the second electrode of the ninth transistor) to be connected to the first region of the active pattern of the third transistor (also the second region of the active pattern of the fourth transistor) through the via.

[0319] In an example embodiment, the fourth via V4 is located within the footprint of the first region of the active pattern of the fourth transistor on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the fourth via V4 are etched away, exposing the surface of the first region of the active pattern of the fourth transistor, and the fourth via V4 is configured to allow the first electrode of the fourth transistor to be connected to the first region of the active pattern of the fourth transistor through the via.

[0320] In an example embodiment, the fifth via V5 is located within the footprint of the first region of the active pattern of the fifth transistor on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the fifth via V5 are etched away, exposing the surface of the first region of the active pattern of the fifth transistor, and the fifth via V5 is configured to allow the first electrode of the fifth transistor to be connected to the first region of the active pattern of the fifth transistor through the via.

[0321] In an exemplary embodiment, the sixth via V6 is located within the range of the second region of the active pattern of the fifth transistor (also the second region of the active pattern of the ninth transistor) on the substrate in the orthographic projection on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the sixth via V6 are etched away, exposing the surface of the second region of the active pattern of the fifth transistor (also the second region of the active pattern of the ninth transistor), and the sixth via V6 is configured to enable the second electrode of the fifth transistor (also the second electrode of the ninth transistor) formed subsequently to connect with the second region of the active pattern of the fifth transistor (also the second region of the active pattern of the ninth transistor) through the via.

[0322] In an exemplary embodiment, the seventh via V7 is located within the range of the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the seventh transistor) on the substrate in the orthographic projection on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the seventh via V7 are etched away, exposing the surface of the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the seventh transistor), and the seventh via V7 is configured to enable the second electrode of the sixth transistor (also the second electrode of the seventh transistor) formed subsequently to connect with the second region of the active pattern of the sixth transistor (also the second region of the active pattern of the seventh transistor) through the via.

[0323] In an exemplary embodiment, the eighth via V8 is located within the range of the first region of the active pattern of the seventh transistor on the substrate in the orthographic projection on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the eighth via V8 are etched away, exposing the surface of the first region of the active pattern of the seventh transistor, and the eighth via V8 is configured to enable the first electrode of the seventh transistor formed subsequently to connect with the first region of the active pattern of the seventh transistor through the via.

[0324] In an exemplary embodiment, the ninth via V9 is located within the range of the first region of the active pattern of the ninth transistor on the substrate in the orthographic projection on the substrate, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the ninth via V9 are etched away, exposing the surface of the first region of the active pattern of the ninth transistor, and the ninth via V9 is configured to enable the first electrode of the ninth transistor formed subsequently to connect with the first region of the active pattern of the ninth transistor through the via.

[0325] In the example embodiment, the tenth via V10 is configured such that a first electrode of an eighth transistor to be formed later is connected to the first electrode plate of the capacitor through the via.

[0326] In the example embodiment, the eleventh via V11 is configured such that a first electrode of a fifth transistor to be formed later is connected to the second electrode plate of the capacitor through the via.

[0327] In the example embodiment, the twelfth via V12 is configured such that a first electrode of a seventh transistor to be formed later is connected to the second initial signal line through the via.

[0328] In the example embodiment, the thirteenth via V13 is configured such that a first electrode of the eighth transistor to be formed later is connected to the first region of the active pattern of the eighth transistor through the via.

[0329] In the example embodiment, the fourteenth via V14 is configured such that a second electrode of the first transistor to be formed later (also a first electrode of the second transistor and a second electrode of the eighth transistor) is connected to the second region of the active pattern of the eighth transistor through the via.

[0330] In the example embodiment, the fifteenth via V15 is configured such that a first electrode of the first transistor to be formed later is connected to the first initial signal line through the via.

[0331] In an exemplary embodiment, the normal projection of the sixteenth via V16 on the substrate is within the range of the normal projection of the reference signal line on the substrate, exposing the surface of the reference signal line, and the sixteenth via V16 is configured to connect the first electrode of the ninth transistor formed subsequently therewith to the reference signal line.

[0332] In an exemplary embodiment, the at least one pixel driving circuit shares the same eighth via with one of the adjacent pixel driving circuits in the same row.

[0333] (8) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth conductive thin film by a patterning process, thereby forming the fourth conductive layer pattern, as shown in FIGS. 31 and 32. FIG. 31 is a schematic view of the fourth conductive layer pattern in FIG. 16, and FIG. 32 is a schematic view of FIG. 16 after the fourth conductive layer pattern is formed.

[0334] In an exemplary embodiment, as shown in FIGS. 31 and 32, the fourth conductive layer pattern can include: an initial connection line INL connected to the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, the first electrode T43 of the fourth transistor, the first electrode T53 of the fifth transistor, the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, the first electrode T83 and the second electrode T84 of the eighth transistor, and the first electrode T93 and the second electrode T94 of the ninth transistor of the at least one pixel driving circuit.

[0335] In an exemplary embodiment, the first electrode T13 of the first transistor is separately provided and has a shape of a block extending at least partially along the second direction D2. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through the first via, and is electrically connected to the first initial signal line through the fifteenth via.

[0336] In an exemplary embodiment, the second electrode T14 of the first transistor, the first electrode T23 of the second transistor, and the second electrode T84 of the eighth transistor are in an integrated structure and have a shape of a line extending along the first direction D1. The second electrode T14 of the first transistor (also the first electrode T23 of the second transistor and the second electrode T84 of the eighth transistor) is connected to the second region of the active pattern of the first transistor (also the first region of the active pattern of the second transistor) through the second via, and is connected to the second region of the active pattern of the eighth transistor through the fourteenth via.

[0337] In the example embodiment, the first electrode T43 of the fourth transistor is separately provided and has a shape of a line extending in the second direction D2. The first electrode T43 of the fourth transistor is connected to the first region of the active layer of the fourth transistor through the fourth via V4.

[0338] In the example embodiment, the first electrode T53 of the fifth transistor is separately provided and has a shape of a broken line extending at least partially in the first direction D1. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through the fifth via V5 and connected to the second plate of the capacitor through the eleventh via V11.

[0339] In the example embodiment, the second electrode T54 of the fifth transistor and the second electrode T94 of the ninth transistor are in an integral structure and have a shape of a line extending in the second direction D2. The second electrode T54 of the fifth transistor (also the second electrode T94 of the ninth transistor) is connected to the first region of the active pattern of the third transistor (also the second region of the active pattern of the fourth transistor) through the third via V3 and connected to the second region of the active pattern of the fifth transistor (also the second region of the active pattern of the ninth transistor) through the sixth via V6.

[0340] In the example embodiment, the integral structure of the second electrode T54(j) of the fifth transistor and the second electrode T94(j) of the ninth transistor in the pixel driving circuit of the j-th column of sub-pixels at least partially overlaps the orthogonal projection of at least one of the reference signal line connected to the pixel driving circuit of the j-th row of sub-pixels, the second initial signal line connected to the (j-1)-th row of sub-pixels, the third scan signal line connected to the pixel driving circuit of the j-th row of sub-pixels, and the first scan signal line connected to the pixel driving circuit of the j-th row of sub-pixels on the substrate.

[0341] In the example embodiment, the second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) has a shape of a line extending in the second direction D2. The second electrode T64 of the sixth transistor (also the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the sixth transistor (also the second region of the active layer of the sixth transistor) through the seventh via V7.

[0342] In the example embodiment, the initial connection line INL can have a shape of a line with a main body portion extending in the second direction D2. The initial connection line INL can be located between at least two adjacent sub-pixels. The initial connection line INL is in an integral structure with the first electrode T73 of the seventh transistor of the pixel driving circuit of at least one sub-pixel. The first electrode T73 of the seventh transistor extends at least partially in the first direction D1, is connected to the first region of the active pattern of the seventh transistor through the eighth via V8, and is connected to the second initial signal line through the twelfth via V12.

[0343] In the exemplary embodiment, the first electrode T83 of the eighth transistor is separately provided and shaped as a broken line extending at least partially along the second direction D2, the first electrode T83 of the eighth transistor is connected to the first plate of the capacitor through the tenth via, and is electrically connected to the first region of the active pattern of the eighth transistor through the thirteenth via.

[0344] In the exemplary embodiment, the first electrode T93 of the ninth transistor is separately provided and shaped as a broken line extending at least partially along the first direction D1, the first electrode T93 of the ninth transistor is connected to the first region of the active pattern of the ninth transistor through the ninth via, and is electrically connected to the reference signal line through the sixteenth via.

[0345] (9) Forming a first planar layer pattern. In the exemplary embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a seventh insulating thin film, patterning the seventh insulating thin film through a patterning process to form a seventh insulating layer, coating a first planar thin film on the seventh insulating layer, and patterning the first planar thin film through a patterning process to form a first planar layer pattern covering the aforementioned pattern, the first planar layer being provided with a plurality of via patterns, as shown in FIG. 33, which is a schematic diagram after the first planar layer pattern is formed in FIG. 16.

[0346] In the exemplary embodiment, as shown in FIG. 33, the plurality of via patterns on the first planar layer include a seventeenth via V17 to a nineteenth via V19.

[0347] In the exemplary embodiment, as shown in FIG. 33, the seventeenth via V17 has a footprint on the substrate within the footprint of the first electrode of the fourth transistor on the substrate, the seventh insulating layer in the seventeenth via V17 is etched away to expose the surface of the first electrode of the fourth transistor, and the seventeenth via V17 is configured to allow a data signal line to be formed subsequently to be connected to the first electrode of the fourth transistor through the via.

[0348] In the exemplary embodiment, as shown in FIG. 33, the eighteenth via V18 has a footprint on the substrate within the footprint of the first electrode of the fifth transistor on the substrate, the seventh insulating layer in the eighteenth via V18 is etched away to expose the surface of the first electrode of the fifth transistor, and the eighteenth via V18 is configured to allow a first power supply line to be formed subsequently to be connected to the first electrode of the fifth transistor through the via.

[0349] In an exemplary embodiment, as shown in FIG. 33, the normal projection of the nineteenth via V19 on the substrate is located within the range of the normal projection of the second electrode of the sixth transistor (also the second electrode of the seventh transistor) on the substrate, the seventh insulating layer within the nineteenth via V19 is etched away to expose the surface of the second electrode of the sixth transistor (also the second electrode of the seventh transistor), and the nineteenth via V19 is configured to enable the anode connecting electrode formed subsequently to connect with the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the via.

[0350] (10) Forming the fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer pattern can include: depositing a fifth conductive thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth conductive thin film through a patterning process to form the fifth conductive layer pattern, as shown in FIG. 34 and FIG. 35, wherein FIG. 34 is a schematic diagram of the fifth conductive layer pattern in FIG. 16, and FIG. 35 is a schematic diagram of FIG. 16 after the fifth conductive layer pattern is formed.

[0351] In an exemplary embodiment, as shown in FIG. 34 and FIG. 35, the fifth conductive layer pattern can at least include: a data signal line Data, a first power supply line VDD, and an anode connecting electrode AL.

[0352] In an exemplary embodiment, the pixel driving circuit is connected with the first signal line VDD connected with one of the adjacent pixel driving circuits in the same row, and a plurality of annular regions R are arranged between the two first signal lines VDD connected adjacently, and at least one anode connecting electrode AL is located in at least one annular region.

[0353] In an exemplary embodiment, the data signal line Data has a linear shape with a main body part extending at least partially along the second direction D2, and is electrically connected with the first electrode of the fourth transistor through the seventeenth via.

[0354] In an exemplary embodiment, the data signal line VDD has a linear shape with a main body part extending at least partially along the second direction D2, and is electrically connected with the first electrode of the fifth transistor through the eighteenth via.

[0355] In an exemplary embodiment, the anode connecting electrode AL has a strip shape extending at least partially along the second direction D2, and is electrically connected with the second electrode of the sixth transistor (also the second electrode of the seventh transistor) through the nineteenth via.

[0356] (11) forming a light emitting structure layer. In an exemplary embodiment, forming the light emitting structure layer comprises: coating a second planar thin film on the substrate with the aforementioned pattern formed thereon, patterning the second planar thin film to form a second planar layer pattern, depositing an anode thin film on the substrate with the aforementioned pattern formed thereon, patterning the anode thin film by a patterning process to form an anode layer pattern, depositing a pixel definition thin film on the substrate with the aforementioned pattern formed thereon, patterning the pixel definition thin film by a patterning process to form a pixel definition layer pattern exposing the anode layer pattern, coating an organic light emitting material on the substrate with the pixel definition layer pattern formed thereon, patterning the organic light emitting material by a patterning process to form an organic structure layer pattern, depositing a cathode thin film on the substrate with the organic material layer pattern formed thereon, patterning the cathode thin film by a patterning process to form a cathode layer.

[0357] In an exemplary embodiment, the organic structure layer can comprise: an organic light emitting layer of the light emitting element.

[0358] In an exemplary embodiment, the cathode layer can comprise: a cathode of the plurality of light emitting elements.

[0359] In an exemplary embodiment, the first semiconductor layer can be an amorphous silicon layer or a polysilicon layer.

[0360] In an exemplary embodiment, the second semiconductor layer can be a metal oxide layer. The metal oxide layer can comprise an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium and tin, an oxide containing indium and zinc, an oxide containing silicon, indium and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer can be a single layer, or can be a double layer, or can be a multi-layer.

[0361] In an exemplary embodiment, at least one of the first conductive layer to the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or an alloy material having conductivity, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. For example, the first conductive layer can be made of molybdenum.

[0362] In an exemplary embodiment, the anode layer can be made of a transparent conductive material, such as any one or more of indium gallium zinc oxide (a-IGZO), zinc oxide nitride (ZnON) and indium zinc tin oxide (IZTO).

[0363] In the example embodiment, the cathode layer can adopt a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material with conductivity, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. Exemplarily, the fourth conductive layer can be a three-layer stacked structure formed by titanium, aluminum, and titanium.

[0364] In the example embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer can adopt any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer.

[0365] In the example embodiment, the first planar layer and the second planar layer can adopt an organic material.

[0366] The display substrate provided by the example embodiment of the present disclosure can be applied to any resolution display product.

[0367] The example embodiment of the present disclosure further provides a driving method of the pixel driving circuit, and the pixel driving circuit is provided with a driving method, which can include the following steps:

[0368] The reset sub-circuit provides a signal of a reference signal line to the second node, a signal of a first initial signal line to the fourth node, and a signal of a second initial signal line to the fifth node under the control of a signal of at least one reset signal line.

[0369] The driving control sub-circuit provides a signal of a data signal line to the second node and a signal of the third node or the fourth node to the first node under the control of signals of at least two scan signal lines and a first power supply line.

[0370] The driving sub-circuit provides a driving signal to the third node under the control of signals of the first node and the second node.

[0371] The light-emitting control sub-circuit provides a signal of the first power supply line to the second node and a signal of the third node to the fifth node under the control of signals of a first light-emitting signal line and a second light-emitting signal line.

[0372] The pixel driving circuit is the pixel driving circuit provided by any one of the foregoing example embodiments, and has similar principles and effects, which will not be described herein again.

[0373] The example embodiment of the present disclosure further provides a display device, which includes a display substrate.

[0374] The display substrate is the display substrate provided by any one of the foregoing embodiments, and has similar principles and effects of implementation, which will not be described here again.

[0375] In an example embodiment, the display device can be electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component having a display function.

[0376] The drawings in the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0377] For the sake of clarity, the thickness and size of a layer or microstructure are exaggerated in the drawings used to describe embodiments of the present disclosure. It can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly" on or under the other element, or there can be an intermediate element.

[0378] Although the embodiments disclosed in the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A pixel driving circuit, disposed in a display device, comprising: The drive control sub-circuit, the reset sub-circuit, the drive sub-circuit and the light-emitting control sub-circuit; The reset sub-circuit is electrically connected with at least one reset signal line, a first initial signal line, a second initial signal line, a reference signal line, a second node, a fourth node and a fifth node respectively, and is configured to provide a signal of the reference signal line to the second node, a signal of the first initial signal line to the fourth node and a signal of the second initial signal line to the fifth node under control of a signal of the at least one reset signal line; The drive control sub-circuit is electrically connected with at least two scan signal lines, a data signal line, a first power supply line, a first node, a second node, a third node and a fourth node respectively, and is configured to provide a signal of the data signal line to the second node and a signal of the third node or the fourth node to the first node under control of signals of the at least two scan signal lines and the first power supply line; The drive sub-circuit is electrically connected with the first node, the second node and the third node respectively, and is configured to provide a drive signal to the third node under control of signals of the first node and the second node; The light-emitting control sub-circuit is electrically connected with a first light-emitting signal line, a second light-emitting signal line, a first power supply line, the second node, the third node and a fifth node respectively, and is configured to provide a signal of the first power supply line to the second node and a signal of the third node to the fifth node under control of signals of the first light-emitting signal line and the second light-emitting signal line; The display device comprises a first control unit electrically connected with the first light-emitting signal line and the second light-emitting signal line respectively and configured to provide signals to the first light-emitting signal line and the second light-emitting signal line, and a time period during which the first control unit provides an effective level signal to the first light-emitting signal line and a time period during which the first control unit provides an effective level signal to the second light-emitting signal line partially do not overlap.

2. The pixel driving circuit according to claim 1, wherein The drive sub-circuit comprises a third transistor, and the light-emitting control sub-circuit comprises a fifth transistor and a sixth transistor; The control electrode of the third transistor is electrically connected with the first node, the first electrode of the third transistor is electrically connected with the second node, and the second electrode of the third transistor is electrically connected with the third node; The control electrode of the fifth transistor is electrically connected with the first light-emitting signal line, the first electrode of the fifth transistor is electrically connected with the first power supply line, and the second electrode of the fifth transistor is electrically connected with the second node; The control electrode of the sixth transistor is electrically connected with the second light-emitting signal line, the first electrode of the sixth transistor is electrically connected with the third node, and the second electrode of the sixth transistor is electrically connected with the fifth node.

3. The pixel driving circuit of claim 2, wherein, The display device comprises a plurality of row pixel drive circuits, and a second light-emitting signal line connected with an i-th row pixel drive circuit and a first light-emitting signal line connected with an i+1-th row pixel drive circuit are the same signal line.

4. The pixel driving circuit of claim 1, wherein, The first control unit provides the first light-emitting signal line with an active level signal earlier than the second light-emitting signal line.

5. The pixel driving circuit of claim 1, wherein, The at least one reset signal line includes a first reset signal line, and the reset sub-circuit includes a first transistor, a seventh transistor and a ninth transistor. The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the first initial signal line, and the second electrode of the first transistor is electrically connected with the fourth node. The control electrode of the seventh transistor is electrically connected with the first reset signal line, the first electrode of the seventh transistor is electrically connected with the second initial signal line, and the second electrode of the seventh transistor is electrically connected with the fifth node. The control electrode of the ninth transistor is electrically connected with the first reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node. The display device further includes a second control unit electrically connected with the first reset signal line and configured to provide a signal to the first reset signal line. The time period in which the second control unit provides the first reset signal line with an active level signal at least partially overlaps at least one of the time period in which the first control unit provides the first light-emitting signal line with an inactive level signal and the time period in which the first control unit provides the second light-emitting signal line with an inactive level signal.

6. The pixel driving circuit of claim 1, wherein, The at least one reset signal line includes a first reset signal line and a second reset signal line. The reset sub-circuit is configured to provide the fourth node with a signal of the first initial signal line under the control of a signal of the first reset signal line, provide the fifth node with a signal of the second initial signal line under the control of a signal of the second reset signal line, and provide the second node with a signal of the reference signal line. The display device further includes a second control unit electrically connected with the first reset signal line and the second reset signal line respectively and configured to provide a signal to the first reset signal line and the second reset signal line. The time period in which the second control unit provides the first reset signal line with an active level signal does not overlap with the time period in which the second control unit provides the second reset signal line with an active level signal, and the end time of the time period in which the second control unit provides the second reset signal line with an active level signal is earlier than the start time of the time period in which the second control unit provides the first reset signal line with an active level signal. At least one of the time period in which the second control unit provides the first reset signal line with an active level signal and the time period in which the second control unit provides the second reset signal line with an active level signal at least partially overlaps at least one of the time period in which the first control unit provides the first light-emitting signal line with an inactive level signal and the time period in which the first control unit provides the second light-emitting signal line with an inactive level signal.

7. The pixel driving circuit of claim 6, wherein, The reset sub-circuit includes a first transistor, a seventh transistor and a ninth transistor. The control electrode of the first transistor is electrically connected with the first reset signal line, the first electrode of the first transistor is electrically connected with the first initial signal line, and the second electrode of the first transistor is electrically connected with the fourth node; The control electrode of the seventh transistor is electrically connected with the second reset signal line, the first electrode of the seventh transistor is electrically connected with the second initial signal line, and the second electrode of the seventh transistor is electrically connected with the fifth node; The control electrode of the ninth transistor is electrically connected with the second reset signal line, the first electrode of the ninth transistor is electrically connected with the reference signal line, and the second electrode of the ninth transistor is electrically connected with the second node.

8. The pixel driving circuit of claim 1, wherein, The at least two scan signal lines include a first scan signal line and a third scan signal line; The driving control sub-circuit is configured to provide a signal of the data signal line to the second node, provide a signal of the third node to the fourth node under control of a signal of the first scan signal line, and provide a signal of the fourth node to the first node under control of a signal of the third scan signal line. The display device further includes a third control unit and a fourth control unit, the third control unit is electrically connected with the first scan signal line and is configured to provide a signal to the first scan signal line, and the fourth control unit is electrically connected with the third scan signal line and is configured to provide a signal to the third scan signal line. The time period in which the third control unit provides an active level signal to the first scan signal line at least partially overlaps with the time period in which the fourth control unit provides an active level signal to the third scan signal line. At least one of the time period in which the third control unit provides an active level signal to the first scan signal line and the time period in which the fourth control unit provides an active level signal to the third scan signal line at least partially overlaps with at least one of the time period in which the first control unit provides an inactive level signal to the first light-emitting signal line and the time period in which the first control unit provides an inactive level signal to the second light-emitting signal line.

9. The pixel driving circuit of claim 8, wherein, The driving control sub-circuit includes a capacitor, a second transistor, a fourth transistor and an eighth transistor, the capacitor includes a first electrode plate and a second electrode plate; The control electrode of the second transistor is electrically connected with the first scan signal line, the first electrode of the second transistor is electrically connected with the fourth node, and the second electrode of the second transistor is electrically connected with the third node; The control electrode of the fourth transistor is electrically connected with the first scan signal line, the first electrode of the fourth transistor is electrically connected with the data signal line, and the second electrode of the fourth transistor is electrically connected with the second node; The control electrode of the eighth transistor is electrically connected with the third scan signal line, the first electrode of the eighth transistor is electrically connected with the first node, and the second electrode of the eighth transistor is electrically connected with the fourth node; The first electrode plate of the capacitor is electrically connected with the first power supply line, and the second electrode plate of the capacitor is electrically connected with the first node.

10. The pixel driving circuit of claim 1, wherein, The at least two scan signal lines include a first scan signal line, a second scan signal line and a third scan signal line; The driving control sub-circuit is configured to provide a signal of the data signal line to the second node under control of a signal of the first scan signal line, provide a signal of the third node to the fourth node under control of a signal of the second scan signal line, and provide a signal of the fourth node to the first node under control of a signal of the third scan signal line. The display device further comprises a third control unit, a fourth control unit and a fifth control unit, the third control unit is electrically connected with the first scan signal line and is configured to provide a signal to the first scan signal line, the fourth control unit is electrically connected with the third scan signal line and is configured to provide a signal to the third scan signal line, and the fifth control unit is electrically connected with the second scan signal line and is configured to provide a signal to the second scan signal line; The time period in which the fifth control unit provides the valid level signal to the second scan signal line comprises a first time period and a second time period, and the end time of the first time period is earlier than the start time of the second time period; The time period in which the third control unit provides the valid level signal to the first scan signal line at least partially overlaps with the second time period and does not overlap with the first time period; At least one of the first time period and the second time period at least partially overlaps with the time period in which the fourth control unit provides the valid level signal to the third scan signal line; The time period in which the fourth control unit provides the valid level signal to the third scan signal line at least partially overlaps with at least one of the time period in which the first control unit provides the invalid level signal to the first light-emitting signal line and the time period in which the first control unit provides the invalid level signal to the second light-emitting signal line.

11. The pixel driving circuit of claim 10, wherein, The drive control sub-circuit comprises a capacitor, a second transistor, a fourth transistor and an eighth transistor, the capacitor comprises a first pole plate and a second pole plate; The control pole of the second transistor is electrically connected with the second scan signal line, the first pole of the second transistor is electrically connected with the fourth node, and the second pole of the second transistor is electrically connected with the third node; The control pole of the fourth transistor is electrically connected with the first scan signal line, the first pole of the fourth transistor is electrically connected with the data signal line, and the second pole of the fourth transistor is electrically connected with the second node; The control pole of the eighth transistor is electrically connected with the third scan signal line, the first pole of the eighth transistor is electrically connected with the first node, and the second pole of the eighth transistor is electrically connected with the fourth node. A plurality of sub-pixels, at least one sub-pixel comprises the pixel drive circuit as claimed in any one of claims 1 to 11.

12. A display device comprising: A plurality of first light-emitting signal lines and a plurality of second light-emitting signal lines, at least one of the first light-emitting signal lines and the second light-emitting signal lines at least partially extends along the first direction; 13. The display device of claim 12, further comprising: The first light-emitting signal line connected with the pixel drive circuit of the jth row of sub-pixels and the second light-emitting signal line connected with the pixel drive circuit of the j-1th row of sub-pixels are the same signal line, 1≤j≤N, and N is the total number of rows of sub-pixels. A plurality of first reset signal lines, the first reset signal lines at least partially extend along the first direction; 14. The display device of claim 13, further comprising: The first reset signal lines connected with the pixel drive circuit of the jth row of sub-pixels comprise two first reset signal lines, the first first reset signal line connected with the pixel drive circuit of the jth row of sub-pixels and the second first reset signal line connected with the pixel drive circuit of the j-1th row of sub-pixels are the same signal line, and the second first reset signal line connected with the pixel drive circuit of the jth row of sub-pixels and the first first reset signal line connected with the pixel drive circuit of the j+1th row of sub-pixels are the same signal line. ​ 15. The display device of claim 14, further comprising: The plurality of first scan signal lines, the plurality of third scan signal lines, the plurality of first initial signal lines, the plurality of second initial signal lines and the plurality of reference signal lines; At least one of the first scan signal line, the third scan signal line, the first initial signal line, the second initial signal line and the reference signal line extends at least partially along the first direction; The first light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels, the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels, the first scan signal line connected to the pixel driving circuit of the jth row of sub-pixels, the second light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels and the second first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels are arranged in the second direction in sequence, and the first direction intersects the second direction; The normal projection of the reference signal line connected to the pixel driving circuit of the jth row of sub-pixels on the substrate at least partially overlaps the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels, the normal projection of the second initial signal line connected to the pixel driving circuit of the jth row of sub-pixels at least partially overlaps the normal projection of the first light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels on the substrate, the normal projection of the third scan signal line connected to the pixel driving circuit of the jth row of sub-pixels is located between the normal projection of the first scan signal line connected to the pixel driving circuit of the jth row of sub-pixels and the normal projection of the first first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels on the substrate, and the normal projection of the second initial signal line connected to the pixel driving circuit of the jth row of sub-pixels is located on the side of the normal projection of the second first reset signal line connected to the pixel driving circuit of the jth row of sub-pixels away from the normal projection of the second light-emitting signal line connected to the pixel driving circuit of the jth row of sub-pixels on the substrate.

16. The display device of claim 15, wherein, The at least one pixel driving circuit comprises a first transistor to a ninth transistor, and at least one transistor comprises an active pattern; The active patterns of the first transistor, the active pattern of the second transistor, the active pattern of the third transistor, the active pattern of the fourth transistor, the active pattern of the sixth transistor and the active pattern of the seventh transistor in the same sub-pixel are in an integrated structure, and the active pattern of the fifth transistor and the active pattern of the ninth transistor in the same sub-pixel are in an integrated structure; The active pattern of the fifth transistor in the pixel driving circuit of the jth row of sub-pixels and the active pattern of the sixth transistor in the pixel driving circuit of the j-1th row of sub-pixels are arranged along the first direction, the active pattern of the ninth transistor in the pixel driving circuit of the jth row of sub-pixels, the active pattern of the first transistor in the pixel driving circuit of the jth row of sub-pixels and the active pattern of the seventh transistor in the pixel driving circuit of the j-1th row of sub-pixels are arranged along the first direction. The at least one transistor further comprises a first pole and a second pole, the active pattern comprises a first region and a second region, the second pole of the fifth transistor and the second pole of the ninth transistor are in an integrated structure and extend along the second direction; 17. The display device of claim 16, wherein, The at least one transistor further comprises a first pole and a second pole, the active pattern comprises a first region and a second region, the second pole of the fifth transistor and the second pole of the ninth transistor are in an integrated structure and extend along the second direction; The first region of the active pattern of the third transistor and the second region of the active pattern of the fourth transistor are the same region, and the second region of the active pattern of the fifth transistor and the second region of the active pattern of the ninth transistor are the same region, The second electrode of the fifth transistor is connected with the first region of the active pattern of the third transistor and the second region of the active pattern of the fifth transistor respectively; The second electrode of the fifth transistor in the pixel driving circuit of the jth column of sub-pixels at least partially overlaps in orthographic projection on the substrate with at least one of the reference signal line connected with the pixel driving circuit of the jth row of sub-pixels, the second initial signal line connected with the j-1th row of sub-pixels, the third scan signal line connected with the pixel driving circuit of the jth row of sub-pixels, and the first scan signal line connected with the pixel driving circuit of the jth row of sub-pixels.

18. The display device of claim 15, further comprising: The plurality of initial connection lines, the plurality of first power supply lines, and the plurality of data signal lines, at least one of the first power supply lines, the data signal lines, and the initial connection lines at least partially extends along the second direction, the first direction intersects with the second direction; At least one initial connection line is electrically connected with at least one first initial signal line.

19. The display device of claim 18, further comprising: The substrate and the driving structure layer arranged on the substrate, the driving structure layer is provided with a pixel driving circuit, the pixel driving circuit comprises: at least one N-type transistor, at least one P-type transistor and a capacitor, the capacitor comprises a first electrode plate and a second electrode plate, the transistor comprises: an active pattern, a control electrode, a first electrode and a second electrode, the third scan signal line comprises a first sub-signal line and a second sub-signal line; The driving structure layer comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer which are sequentially stacked on the substrate; The first semiconductor layer at least comprises: the active pattern of the at least one P-type transistor; The first conductive layer at least comprises: the first scan signal line, the first light-emitting signal line, the second light-emitting signal line, the first reset signal line, and the first electrode plate of the capacitor of the at least one pixel driving circuit and the control electrode of the at least one P-type transistor; The second conductive layer at least comprises: the first sub-signal line of the third scan signal line, the second initial signal line, and the second electrode plate of the capacitor in the pixel driving circuit of the at least one sub-pixel; The second semiconductor layer at least comprises: the active pattern of the at least one N-type transistor; The third conductive layer at least comprises: the second sub-signal line of the third scan signal line, the first initial signal line, and the reference signal line; The fourth conductive layer at least comprises: the first electrode and the second electrode of the at least one transistor of the at least one pixel driving circuit.

20. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 11, the method comprising: The reset sub-circuit provides the signal of the reference signal line to the second node, the signal of the first initial signal line to the fourth node, and the signal of the second initial signal line to the fifth node under the control of the signal of the at least one reset signal line; The driving control sub-circuit provides a signal of a data signal line to the second node and a signal of the third node or the fourth node to the first node under control of signals of at least two scan signal lines and the first power supply line; The driving sub-circuit provides a driving signal to the third node under control of signals of the first node and the second node; The light emitting control sub-circuit provides a signal of the first power supply line to the second node and a signal of the third node to the fifth node under control of signals of the first light emitting signal line and the second light emitting signal line.

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