Chip, equipment and task execution method

Abstract

The invention provides a chip, equipment and a task execution method, and relates to the technical field of chips. The chip comprises at least one operation array, wherein the operation array comprises a pseudo operand generation unit and a calculation unit; the pseudo operand generating unit is used for generating a pseudo operand; the calculation unit is used for executing a second calculation task based on the pseudo operand after the first calculation task based on the effective operand is completed; wherein the power consumption of the operation array for executing the second calculation task is smaller than that of the operation array for executing the first calculation task; and the computing unit is also used for stopping executing the second computing task when the second computing task is executed for a set time length. The chip effectively suppresses the voltage overshoot of the chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip, device, and task execution method. Background Technology

[0002] In modern chip design, computing performance is a core function. To improve computing power, massively parallel computing arrays are commonly used within chips.

[0003] However, the highly synchronized power consumption behavior of massively parallel computing arrays can cause voltage overshoot, where the total power consumption of the chip drops sharply due to multiple computing arrays completing operations simultaneously within a very short period, resulting in a rapid and significant surge in chip voltage. This has become a key bottleneck restricting chip performance and reliability.

[0004] Therefore, further research is needed on how to effectively suppress chip voltage overshoot. Summary of the Invention

[0005] This application provides a chip, a device, and a task execution method. The technical solution provided by this application is as follows.

[0006] According to one aspect of the embodiments of this application, a chip is provided, the chip including at least one arithmetic array, the arithmetic array including: a pseudo-operand generation unit and a calculation unit; The pseudo-operand generation unit is used to generate pseudo-operands; The computing unit is configured to perform a second computing task based on the pseudo-operands after completing a first computing task based on the valid operands; wherein the power consumption of the computing array in performing the second computing task is less than the power consumption in performing the first computing task. The computing unit is further configured to stop executing the second computing task when the execution of the second computing task reaches a set time.

[0007] According to one aspect of the embodiments of this application, an electronic device is provided, the electronic device including the above-described chip.

[0008] According to one aspect of the embodiments of this application, a task execution method applied to a chip is provided, the chip including at least one arithmetic array, the arithmetic array including: a pseudo-operand generation unit and a calculation unit; The method includes: The pseudo-operand generation unit generates pseudo-operands; After completing a first computation task based on valid operands, the computing unit executes a second computation task based on the pseudo operands; wherein the power consumption of the computing array in executing the second computation task is less than the power consumption in executing the first computation task. The computing unit stops executing the second computing task when the set time has elapsed.

[0009] The technical solutions provided in this application embodiment may have the following beneficial effects: By generating pseudo-operands through a pseudo-operand generation unit, the computing unit can continue to execute a second computing task based on the pseudo-operands after completing the first computing task based on the valid operands. Furthermore, the power consumption of executing the second computing task is less than that of the first computing task. Thus, the chip can maintain a certain power consumption after the valid computation is completed, and allow the power consumption to gradually decrease under control, avoiding the problem of a large voltage surge caused by a sudden drop in power consumption. Simultaneously, by controlling the execution time of the second computing task, unnecessary resource waste can be avoided. Therefore, the technical solution proposed in this application effectively suppresses chip voltage overshoot without sacrificing chip computing performance. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a chip provided in one possible implementation of this application; Figure 2 This is a schematic diagram of a pseudo-operand generation unit provided in one possible implementation of this application; Figure 3 This is a schematic diagram showing the power consumption change curves of no power consumption control and power consumption control provided in one possible implementation of this application; Figure 4 This is a schematic diagram of the computation array provided in one possible implementation of this application; Figure 5 This is a flowchart of a task execution method applied to a chip provided in one possible implementation of this application; Figure 6 This is a simplified structural block diagram of an electronic device provided in one possible implementation of this application. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0013] The chips and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of chips and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0014] The technical solutions of this application embodiment can be applied to various chips. Examples include: Central Processing Unit (CPU), Graphics Processing Unit (GPU), Artificial Intelligence Accelerator (AIA), Tensor Processing Unit (TPU), Neural Processing Unit (NPU), Digital Signal Processor (DSP), Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), Network Processing Unit (NPU), Cryptographic Processor, Image Signal Processor (ISP), Audio Digital Signal Processor (ADSP), Baseband Processor (BP), Internet of Things Terminal Chip, Autonomous Driving Control Chip, High-End Router Chip, Switch Chip, Server Accelerator Card Chip, and Computing in Memory (MIC) chip. Chip (CIM), Processing in Memory Chip (PIM), Reconfigurable Computing Chip, Heterogeneous Computing Chip, Network on Chip (NoC), Many Core Processor, Vector Processor, Vision Processing Unit.VPU, radar signal processing chip, satellite navigation baseband chip, blockchain computing chip, scientific computing acceleration chip, or other chips, etc. Typically, the chip in the embodiments of this application can be a GPU, or a chip with the same or similar functions as a GPU.

[0015] Before introducing the chip proposed in this application, the relevant technologies will be briefly described below.

[0016] Computational array: In this embodiment, a computational array refers to a hardware module within a chip designed to enhance parallel processing capabilities, consisting of multiple identical computing units integrated in a specific structure. The basic unit of a computational array is a computing unit, which can be an arithmetic logic unit performing basic arithmetic operations (such as addition and multiplication), a multiply-accumulate unit performing multiply-accumulate operations, or a dedicated processing engine for a specific computation (such as matrix multiplication and convolution). These computing units do not exist in isolation but are replicated (i.e., "instantiated") on a large scale and organized through interconnection structures to form a set capable of simultaneously executing a large number of identical or similar operations. A computational array may contain tens, hundreds, or even thousands of computing units. Computational arrays typically accept unified instruction control but operate on different data or process highly homogeneous subtasks within the same large task. This high degree of synchronization between control and data is the foundation for achieving high-performance computing, but it is also the root cause of its highly synchronized power consumption behavior. In summary, the "computation array" of the computing task in the embodiments of this application covers the cluster of computing units designed to achieve parallel computing in various types of chips. It is the core of computing power of modern chips and also the area where power consumption and voltage issues are most concentrated.

[0017] Voltage Overshoot: In modern chip design, computing performance is a core function. Current parallel computing chips instantiate multiple computational arrays (MAAs) to increase computing power, employing massively parallel computing arrays (MLAs). However, the highly synchronized power consumption behavior of MLAs can cause voltage overshoot. Specifically, a large number of MLAs typically execute computational tasks in parallel with very short start and end times. When the MLAs finish computation within a short period, it means that a large number of transistors stop switching almost synchronously. This causes a sharp drop in the chip's total current demand over several clock cycles, meaning the chip's power consumption drops drastically from very high to very low. Ultimately, this results in a rapid and significant surge in the voltage actually received by the chip, far exceeding its rated operating voltage. This voltage overshoot phenomenon can lead to chip malfunctions, and frequent large voltage surges are more likely to damage transistors, affecting the chip's lifespan.

[0018] Among the relevant technologies, there are the following two solutions: 1. By staggering the completion times of the computation array through software scheduling, power consumption can be gradually reduced rather than drastically decreased, thus avoiding significant voltage overshoot in the chip. However, this approach has the following problems.

[0019] On the one hand, software scheduling relies on accurate prediction of the execution time of computational tasks. However, in modern complex computing architectures, the execution time of computational tasks is highly dependent on dynamic factors such as the specific pattern of input data, cache hits, and memory access latency. These factors are extremely difficult to predict accurately at compile time or before task distribution. Therefore, static or semi-static scheduling strategies inevitably deviate from the actual execution situation, resulting in a significant discrepancy between the actual and expected power consumption reduction. This makes the effect of suppressing voltage overshoot uncontrollable, unreliable, and lacking universality.

[0020] On the other hand, achieving effective scheduling requires deep involvement of the software layer (such as the operating system, drivers, or compiler) in the power management of the underlying chip hardware. Therefore, the software must be able to accurately sense, track, and control the microstates of a large number of computing arrays. This not only increases the design complexity and verification cost of the software but also introduces additional runtime overhead to the system, making the co-design of the entire hardware and software system more complex.

[0021] Finally, this technology achieves a gradual reduction in power consumption by scheduling the computing arrays to idle or delay them. Specifically, some computing arrays that have completed computations must be forced to idle and cannot be immediately put into new computing tasks, or the start of new tasks is postponed. This approach reduces the chip's computing throughput and resource utilization.

[0022] 2. Overvoltage is not suppressed in the chip; that is, overcharge voltage is allowed to act directly on the transistor, and overvoltage is accepted as long as timing and functional problems do not occur. However, this approach introduces the following problems.

[0023] On the one hand, overshoot voltage means that the transistors of a chip are momentarily subjected to voltages far exceeding their rated operating voltages. This repeated overshoot voltage accelerates the aging effect of transistors, specifically manifested as: hot carrier injection, leading to transistor threshold voltage drift and slow performance degradation; and dielectric breakdown over time, significantly increasing the risk of permanent gate oxide breakdown, which in severe cases directly causes transistor failure. Therefore, accepting voltage overshoot is tantamount to sacrificing the long-term lifespan and stability of the chip in exchange for temporary design convenience.

[0024] On the other hand, in the back-end stage of chip design, strict acceptance is required to ensure that the design meets all performance and reliability standards. The phenomenon of voltage overshoot means that designers must consider this situation in their chip models. Specifically, this includes: (1) Conservative design: In order to withstand voltage overshoot, it is necessary to use voltage conditions different from those of ordinary chips for static timing analysis, which directly leads to the compression of timing margin. In order to meet timing requirements, designers may use larger and more power-consuming transistors when designing chips, thereby sacrificing performance or increasing power consumption and area; (2) Complex modeling and verification: Accurately predicting the magnitude of voltage overshoot is itself an extremely complex electromagnetic simulation problem, which increases the computational load and time cost of verification. At the same time, a large number of decoupling capacitors need to be added to the layout to reduce voltage, which occupies chip area and increases chip manufacturing cost.

[0025] Finally, as chip computing power continues to expand, the number and density of parallel computing units (i.e., computing arrays) will increase, leading to more dramatic drops in power consumption and a more severe voltage overshoot problem. What is tolerable under current chip manufacturing processes will become unbearable under future, more advanced processes with lower supply voltages and more fragile transistors.

[0026] To address the aforementioned problems, this application provides a solution for suppressing voltage overshoot in chips. Please refer to... Figure 1 , Figure 1 This is a schematic diagram of a chip provided in one possible implementation of this application.

[0027] like Figure 1 As shown, the chip 100 includes at least one arithmetic array 110, which includes a pseudo-operand generation unit 111 and a calculation unit 112. Optionally, each arithmetic array 110 includes a pseudo-operand generation unit 111 and a calculation unit 112.

[0028] In some embodiments, the pseudo-operand generation unit 111 is used to generate pseudo-operands.

[0029] For example, a pseudo-operand is a data element with the same bit width as the valid operand. The difference between pseudo-operands and valid operands lies in their function. Pseudo-operands do not participate in meaningful mathematical calculations to produce valid results. Their purpose is to control the internal circuitry of the computing unit when it has no actual task, thereby regulating the power consumption of the computing unit. Specifically, if the computing unit directly enters an idle state after completing a valid calculation, it will cause a sharp drop in power consumption, leading to a voltage surge in the chip. By inputting multiple pseudo-operands into the computing unit, its internal circuitry can be kept in a non-zero state, thus transforming the sharp drop in power consumption into a gradual decrease. In some embodiments, the pseudo-operand itself is data, and its structure is embodied in a predefined bit pattern. The aforementioned bit patterns are either fixedly stored in hardware or generated in real time, and include, but are not limited to, the following types: all-zero / all-one patterns, such as 0000... or 1111...; alternating patterns, such as 1010...10 or 0101...01; walking patterns, such as a single '1' bit shifted left or right sequentially within a continuous period, for example (0001, 0010, 0100, 1000). Walking patterns can generate regular, localized circuit activity; pseudo-random patterns, generated by a hardware pseudo-random sequence generator, simulate the randomness of real data and can generate pseudo-operands similar to valid operands. It is worth noting that the above pseudo-operands are merely illustrative examples, and this embodiment does not limit them.

[0030] In some embodiments, the pseudo-operand generation unit is a hardware module that generates and outputs pseudo-operands of the aforementioned specific bit pattern according to preset requirements. Under the management of control logic, the pseudo-operand generation unit switches between "valid operand input" and "pseudo-operand input" through circuits such as multiplexers. Exemplarily, the pseudo-operand generation unit can be a combination of any one or more of the following hardware structures: a fixed-value register, consisting of a set of flip-flops, whose initial value after power-on is determined by hardware circuitry, such as a fixed high or low level connection via metal layer wiring, or set by a one-time programmable unit; a configurable register file, a small memory or set of registers written by the system via a configuration bus. System software / firmware can write different pseudo-operand bit patterns into these registers, and the hardware control logic selects which pseudo-operand to output based on the strategy; a circular buffer, a First-In-First-Out (FIFO) or circular buffer, which internally stores several preset pseudo-operand values; and a counter, a binary counter. Its output value is itself a continuously changing sequence, which can be used as a pseudo-operand and provides regular bit flips. It is worth noting that the above-described pseudo-operand generation unit is merely an illustrative example, and this embodiment does not limit it.

[0031] In some embodiments, the computing unit 112 is configured to perform a second computing task based on pseudo-operands after completing a first computing task based on valid operands. The power consumption of the computing array performing the second computing task is less than the power consumption of performing the first computing task.

[0032] The calculation unit 112 is also used to stop executing the second calculation task when the execution of the second calculation task reaches a set time.

[0033] In some embodiments, the computing unit is the core processing element in the arithmetic array; it is a fully hardware-based digital logic circuit used to perform arithmetic and logical operations. In this application, the computing unit is a general term referring to any module capable of receiving operands and performing computational functions. Its specific implementation forms include, but are not limited to: 1. Arithmetic Logic Unit (ALU): A multifunctional circuit capable of performing a set of basic arithmetic and logical operations, such as addition, subtraction, bit manipulation, etc.

[0034] 2. Multiplier: A hardware circuit specifically designed to perform multiplication operations. Its implementation structure varies, including but not limited to: array multipliers: composed of a partial product generator and an array of adders; Wallace tree multipliers: using a Wallace tree structure to compress partial products; and Booth-coded multipliers: employing the Booth algorithm to reduce the number of partial products.

[0035] 3. Multiply-Accumulate Unit (MAC): A composite unit integrating a multiplier and an adder, used to perform the (A×B) + C operation.

[0036] 4. Vector processing unit: A parallel computing unit capable of performing the same operation on multiple operands simultaneously.

[0037] 5. Custom computing accelerators: Dedicated hardware circuits optimized for specific functions (such as convolution and Fourier transform).

[0038] It is worth noting that the above-described calculation unit is merely an illustrative example and is not intended to limit the scope of this embodiment.

[0039] In some embodiments, the first computation task refers to the computation performed by the computing unit based on valid operands. Valid operands refer to operands from the upstream data stream that carry valid information required for processing in practical applications, such as artificial intelligence inference, scientific computing, and graphics rendering. Exemplarily, the computation types included in the first computation task cover all operations supported by the computing unit, such as: multiplication, calculating the product of two valid operands; addition / accumulation, calculating the sum or cumulative sum of two or more valid operands; multiply-accumulate, performing multiplication followed immediately by addition; and fusion operations, such as complex operations composed of basic operations like dot product and matrix multiplication.

[0040] In some embodiments, the second computation task refers to a computation task performed by the computing unit based on pseudo-operands after completing the first computation task. The introduction of the second computation task is not for obtaining meaningful computation results; its core function is power management. Exemplarily, the type of computation performed by the second computation task may be the same in form as the first computation task, but since the input is a pseudo-operand, its essence is "computation without practical meaning," such as: pseudo-multiplication operation, multiplying one pseudo-operand by another pseudo-operand (or a fixed value); pseudo-addition operation, performing addition on pseudo-operands; pseudo-multiplication-accumulation operation, formally performing multiplication-accumulation, but the input is always a pseudo-operand; no-operation, in some computing units, the input pseudo-operand may simply pass through the data path without triggering the activation of all circuits, its effect is equivalent to a specific no-operation.

[0041] In some embodiments, the power consumption of the arithmetic array performing the second computational task is less than that performing the first computational task. For example, when performing the first computational task, the sequence of valid operands is determined by the upper-layer application, and the results of operations between its data and consecutive operands are uncontrollable and can be very high, such as when processing two very different matrices. For example, the first computational task may cause a large number of logic gates within the computational unit to flip simultaneously, resulting in significant power consumption for the arithmetic array. When performing the second computational task, the bit pattern of the pseudo-operands is pre-defined, and one of its core design goals is to reduce the difference between the current operand and one or more previous operands. For example, a sequence of all zeros, fixed values, or slowly changing values ​​can be used as pseudo-operands. Operations between pseudo-operands directly reduce the number of logic gates affected within the computational unit, decreasing the total amount of capacitors requiring charging and discharging, thereby reducing power consumption. For example, the first computational task may activate all or most of the data paths of the computational unit. For example, when a multiplier within a computational unit processes random valid operands, all stages such as partial product generation, compression, and final addition are in a highly active state, resulting in high power consumption for the first computational task. The second computation task can avoid activating the entire data path by using specific pseudo-operands. For example, by using all zeros as pseudo-operands to input to the multiplier in the computation unit, the output of most AND gates (used to generate partial products) will remain 0, and only a very small number of nodes in the subsequent addition tree will be flipped. The activity of the entire circuit is restricted to a very low level, thus the power consumption of the second computation task is low.

[0042] In some embodiments, after completing a first computational task based on valid operands, the computing unit does not execute a second computational task based on pseudo-operands indefinitely, but actively stops the second computational task after a set duration. For example, voltage overshoot is a phenomenon that occurs at the beginning of a sharp drop in power consumption. When the computing unit switches from executing the first computational task to the second computational task, the power consumption begins to decrease from a peak. This decrease is usually not an instantaneous action, but a decay process lasting several clock cycles. During this period, the current change in the circuit is still relatively large, but much smaller than the impact of a direct shutdown. After a specific set duration, the power consumption of the computing unit has been buffered by the second computational task, smoothly transitioning from a high level to a sufficiently low level. For example, the greater the drop in power consumption per unit time, the higher the voltage surge will be, assuming other conditions remain unchanged; conversely, if the drop in power consumption per unit time is smaller and slower, the voltage surge will be smaller, assuming other conditions remain unchanged. Based on the above, even if the second computational task is completely stopped, allowing the computing unit to enter an idle state, the magnitude and speed of its power consumption drop have been greatly reduced, and the resulting current change is insufficient to cause an excessively large voltage surge. Continuing to execute the second computational task at this point would be an unnecessary waste of resources.

[0043] For example, the aforementioned set duration is a predefined parameter, the specific value of which is determined by system design requirements and can be implemented through various hardware methods. Specifically, it includes: a fixed number of clock cycles: a hardware counter starts counting when the second computing task is started. When the count value reaches a preset fixed value, such as 8, 16, or 32 clock cycles, the counter generates a signal as a control signal to stop execution. This preset value can be stored in a configuration register or fixed by hardware circuitry; a configurable number of clock cycles: to adapt to different voltage domains or operating frequencies, the duration can be configurable. The system can write a value representing the duration into a dedicated register via the configuration bus, and the hardware counter uses this value as a counting target; an adaptive duration based on monitoring feedback: in some embodiments, the set duration can be adaptive. The hardware can integrate simple detection circuitry or a current sensor. When chip noise is detected to have subsided, for example, no voltage overshoot is detected for several consecutive cycles, a stop signal is generated in advance. Conversely, if a voltage overshoot is detected, the execution time of the second computing task can be appropriately extended.

[0044] It is worth noting that the first and second computational tasks described above are merely illustrative examples, and this embodiment does not limit them.

[0045] The technical solution provided in this application generates pseudo-operands through a pseudo-operand generation unit. After completing the first calculation task based on the valid operands, the computing unit can continue to execute the second calculation task based on the pseudo-operands, and the power consumption of executing the second calculation task is less than that of the first calculation task. Thus, the chip can maintain a certain power consumption after the valid calculation is completed, and allow the power consumption to gradually decrease under control, avoiding the problem of a large voltage surge caused by a sharp drop in power consumption. Simultaneously, by controlling the execution time of the computing unit for the second calculation task, unnecessary resource waste can be avoided. Therefore, without sacrificing the chip's computing performance, chip voltage overshoot is effectively suppressed.

[0046] In some embodiments, the second computation task is a multiplication computation task.

[0047] For example, computing units typically integrate multiple computational functions, and the power consumption of different functions varies. Specifically, logical operations (such as AND, OR, NOT, XOR): have simple implementation circuits, are usually bit-parallel operations, have no long path dependencies, and have the lowest power consumption; shift operations: implemented through multiplexers, power consumption mainly comes from the switching of the multiplexer, and its power consumption is higher than logical operations but usually lower than arithmetic operations; addition operations: addition operations have higher power consumption than logical operations, but its critical path length is linearly related to the bit width, and its power consumption level is moderate; multiplication operations: the multiplier is the largest and most complex module in the computing unit. An n-bit multiplication operation requires generating n partial products, which are compressed and accumulated through a multi-stage adder network, where n is a positive integer. This process involves a large number of logic gates (such as AND gates and full adders) and deep combinational logic, and a single operation causes most of the internal nodes to flip. Therefore, its peak power consumption is significantly higher than all other operations, and it is the main source of power consumption within the computing unit.

[0048] For example, the embodiments of this application aim to suppress voltage overshoot in the chip. Multiplication tasks in computing tasks are the main cause of this phenomenon, so directly managing their power consumption behavior can achieve significant results. By executing a multiplication task (i.e., a second computing task) after completing the first computing task, the computing unit can maintain a power consumption level higher than the idle state for a set period, avoiding a sharp drop in power consumption due to the cessation of the first computing task. Furthermore, even if the first computing task is a mixed operation, such as some computing units performing addition operations and some performing multiplication operations, by setting the second computing task as a multiplication task, unified management of the overall power consumption behavior of the computing array can be achieved. Specifically, in this mixed computing scenario, the power consumption levels of the first computing tasks executed by different computing units in the aforementioned computing array vary. If they directly enter an idle state after completion, the total power consumption of the chip will exhibit a complex drop pattern, which may still cause localized sharp changes in current, further leading to voltage overshoot. By controlling all computing units in the computing array to uniformly perform multiplication calculations with higher power consumption as a secondary computing task, all computing units in the computing array can be placed under a controllable and consistent power management framework.

[0049] In some embodiments, the pseudo-operands include a first pseudo-operand and a second pseudo-operand, which are used for multiplication calculation tasks.

[0050] For example, when the second computation task is a multiplication task, the pseudo-operands used specifically include two inputs: a first pseudo-operand and a second pseudo-operand for multiplication. The first pseudo-operand and the second pseudo-operand are two different pseudo-operands that are jointly input into the computation unit to execute the second computation task, thereby controlling the power consumption of the computation unit in executing the second computation task.

[0051] In some embodiments, the first pseudo-operand is set to a fixed value. This fixed value refers to a value pre-set at the hardware level and remaining unchanged during the execution of the second computational task, such as all zeros, all ones, or any other fixed constant. Exemplarily, by fixing the first pseudo-operand, the activity of the circuitry directly related to it within the computational unit can be stabilized immediately. This avoids unpredictable and potentially superimposed circuit flipping caused by simultaneous changes in the first and second pseudo-operands, establishing a stable and predictable power consumption mechanism for the entire second computational task. Furthermore, setting the first pseudo-operand to a fixed value simplifies the control logic and hardware. Using a fixed value means that the first pseudo-operand can be directly provided by a set of hardware connected to high / low level flip-flops, or read from a read-only register, without complex generation logic, thereby reducing the hardware overhead and complexity of the pseudo-operand generation unit.

[0052] In some embodiments, the second pseudo-operand is configured as a variable value, meaning that it can change according to a predetermined sequence within the execution cycle of a second computational task. Exemplarily, the variability of the second pseudo-operand, as the primary variable for power consumption regulation, is the core of power consumption control. By generating a numerical sequence that changes according to a predetermined pattern through hardware circuitry and inputting it as the second pseudo-operand into the computing unit, the activity level of the internal circuitry of the computing unit during the second computational task can be controlled, i.e., the power consumption level of the computing unit can be controlled. Specifically, by designing the variation pattern of the second pseudo-operand, the power consumption of the computing unit during the execution of the second computational task can exhibit a controlled and clear trend, rather than unpredictable and chaotic fluctuations.

[0053] By employing a combination of fixed and variable operands, the aim is to stabilize the activity of the corresponding circuitry within the computational unit using a fixed first pseudo-operand, thereby reducing the complexity of power management and pseudo-operand generation units. Simultaneously, a variable second pseudo-operand is used as a single control variable to manage the power consumption reduction process of the computational unit. It is worth noting that the aforementioned first and second pseudo-operands are merely illustrative examples, and this embodiment does not limit their application.

[0054] In some embodiments, the mantissa portion of the first pseudo-operand is all 1s and the exponent portion is all 0s.

[0055] For example, the first pseudo-operand used for the second computation task adopts a floating-point format. A floating-point format typically consists of three fields: a sign bit, an exponent bit, and a mantissa bit. Specifically, the sign bit indicates whether the value is positive or negative; the exponent bit indicates the magnitude of the value, and its value determines the position of the decimal point, directly affecting the exponent of the calculation result; the mantissa bit indicates the significant digits or precision of the value, determining the precision of the calculation. In floating-point multiplication, the exponents of the two pseudo-operands are added, and the mantissas are multiplied. The processing of these two fields by the operational logic is relatively independent. An anomaly in the exponent part will cause the result to become infinity (INF) or not-a-number (NaN), while the value and number of bits of the mantissa part directly determine the number and form of partial products that the computation unit needs to generate and process during computation. These partial products refer to the intermediate product terms generated during binary multiplication. More non-zero bits and larger values ​​in the mantissa result in a denser and more complex partial product array, which in turn makes the summation of partial products more frequent and the circuit switching more violent, thereby increasing the power consumption of the computing unit.

[0056] In one aspect of this application's embodiments, all bits of the mantissa portion of the first pseudo-operand are 1. In binary multiplication, the partial product is generated based on the following principle: each bit of the multiplicand (mantissa of the first pseudo-operand) is ANDed with each bit of the multiplier (mantissa of the second pseudo-operand) to generate the corresponding partial product row. For example, when all bits of the mantissa portion of the first pseudo-operand are 1, its binary representation is all bits are 1, which brings the following key features: Assuming a 4-digit mantissa format is used, the mantissa of the first pseudo-operand is fixed at 1111.

[0057] Case 1: The second pseudo-operand has a mantissa of 1010.

[0058] Bit 0(1) → 1111&0 = 0000 Bit 1 (0) → 1111 & 1 = 1111 (left shift by 1 bit) Bit 2(1) → 1111 & 0 = 0000 (left shift by 2 bits) Bit 3(0) → 1111 & 1 = 1111 (left shift 3 bits) The partial product array generated under the above case 1 is: 0000, 1111, 0000, 1111.

[0059] Case 2: The mantissa of the second pseudo-operand becomes 1110.

[0060] Bit 0(1) → 1111&0 = 0000 Bit 1 (0) → 1111 & 1 = 1111 (left shift by 1 bit) Bit 2(0) → 1111 & 1 = 1111 (left shift by 2 bits) Bit 3(0) → 1111 & 1 = 1111 (left shift 3 bits) The partial product array generated under case 2 above is: 0000, 1111, 1111, 1111.

[0061] When the mantissa of the second pseudo-operand changes from 1010 to 1110, only the second bit changes from 1 to 0, and the corresponding partial product changes from 0000 to 1111. This means: 1. Only a single partial product row changes, while the rest of the partial products remain unchanged; 2. This partial product row changes from all 0s to all 1s, with each bit flipped; 3. The number and position of the flipped bits are entirely determined by the change in the second pseudo-operand. This design ensures that every bit change in the second pseudo-operand produces a definite and maximum change in circuit activity in the partial product array, thus making the power consumption change linearly related to the change in the second pseudo-operand. When the second pseudo-operand changes in a specific sequence, the power consumption of the computational unit will exhibit a corresponding and predictable trend, providing a necessary foundation for precise power consumption control.

[0062] In one aspect of this application's embodiments, all bits of the exponent portion of the first pseudo-operand are 0. In floating-point format, an exponent of all 0s represents a value of zero or a very small denormalized number. When a first pseudo-operand with all bits of its exponent portion being 0 is multiplied by a second pseudo-operand with a normal exponent value, the exponent portion of the result will not overflow. For example, specifically assuming an 8-bit exponent format is used, the exponent of the first pseudo-operand is 00000000, and the exponent of the second pseudo-operand is 10000000. When multiplying them, the exponent of the result is calculated using exponent addition: 00000000 + 10000000 = 10000000. This result remains within the normal exponent range and will not cause exponent overflow, thereby avoiding the generation of abnormal results such as INF or NaN.

[0063] It is worth noting that the above-described method for setting the first pseudo-operand is merely an illustrative example, and this embodiment does not limit it.

[0064] By setting all bits of the mantissa portion of the first pseudo-operand to 1, the power consumption change caused by the change of the second pseudo-operand can be better reflected. By setting all bits of the exponent portion of the first pseudo-operand to 0, the calculation result of the second calculation task can be avoided as INF or NaN due to the exponent, which would affect subsequent calculation tasks.

[0065] In some embodiments, the value of at least one bit in the mantissa portion of the second pseudo-operand is flipped over per unit time.

[0066] For example, the power consumption of the arithmetic array is primarily affected by the flipping activity of individual bits of the operands of the two input computation units between computational tasks.

[0067] In some embodiments, the flip rate refers to the frequency at which a signal node in a digital circuit undergoes a logical change between two consecutive computational tasks. For example, for a computational unit, the operand flip rate refers to the number and proportion of bits that change in the binary representation of the operand value input in the current computational task compared to the operand value input in the previous computational task. Specifically, for each computational task, the computational unit accepts two operands, whose values ​​directly determine the initial state and activity process of the internal circuitry of the computational unit. Changes in operand values ​​are manifested as the flipping of individual bits. For example, suppose the computational unit calculated 3 multiplied by 5 in the previous computational task (binary: 0011 × 0101), and in the current computational task calculates 6 multiplied by 2 (binary: 0110 × 0010). For operand A: it changes from 0011 to 0110. The first and third bits are flipped. For operand B: it changes from 0101 to 0010. The first, second, and third bits are flipped. In this scenario, multiple bits of the two operands are flipped within consecutive computational tasks. If the current computational task is still 3 multiplied by 5, i.e., binary: 0011×0101, then the flip rate is zero. It is worth noting that the above description of the flip rate and the specific values ​​involved are merely illustrative examples, and this embodiment does not limit it.

[0068] In some embodiments, after receiving operands A and B, the computing unit begins logical calculations. The operands pass through multiple levels of logic gates and eventually stabilize at the result. During operand propagation and stabilization, if the output of any logic gate needs to change from 0 to 1 or from 1 to 0 (i.e., a flip occurs), the load capacitor connected to the output of that gate must be charged and discharged. This charging and discharging process draws current from the power supply, consuming energy and generating power consumption. The larger the circuit scale and the more complex the data path of the computing unit, the more nodes need to be flipped in a single calculation, resulting in higher power consumption. When a computational task ends, the logic gates within the computing unit enter an idle waiting period until a new operand is input. During this idle waiting period, as long as no new operand is loaded, the state of each node within the computing unit remains stable. Since there is no change in logic state, there is no need to charge and discharge the load capacitor. Therefore, the dynamic current drawn from the power supply drops sharply to near zero; this transition from a highly dynamic state to a near-idle state manifests as a sharp drop in power consumption.

[0069] For example, based on the above principles, the impact of the flip-flop rate on the power consumption of the computing unit is as follows: 1. High operand flip rate leads to high power consumption: A high operand flip rate means that the new operand differs significantly in binary bits from the operand of the previous computation task. To calculate the correct result, the internal logic circuitry must perform a large amount of recalculation, resulting in a massive number of logic gate nodes undergoing state flips along the entire data path from partial product generation to final summation. The large number of nodes requiring charging and discharging, and the large total capacitance, result in high power consumption within the computation task.

[0070] 2. Low toggle rate leads to low power consumption: When the operand toggle rate is low, it means that the new operand is very similar to, or even identical to, the operand of the previous computational task. For bit positions that have not changed, the inputs of the internal logic paths they control remain unchanged, so most logic gates on these paths do not need to toggle, and their corresponding capacitors do not need to be charged or discharged. Only those local circuits directly affected by the toggled bit positions need to be updated. Therefore, the total number of nodes that need to be charged and discharged within the computational task is significantly reduced, and the total power consumption is reduced accordingly.

[0071] Based on the above, the power consumption of the arithmetic array is mainly affected by the toggle rate of each bit of the two operands. A lower toggle rate means fewer toggles in the combinational logic values ​​affected by the bits, resulting in less charging and discharging of the corresponding capacitors and lower power consumption. Conversely, a higher toggle rate means more toggles in some operand bits, leading to more toggles in the combinational logic values ​​of the computational units and thus higher power consumption. Furthermore, the toggle rate is a key variable determining chip power consumption. It is worth noting that the above description of the toggle rate and the specific values ​​involved are merely illustrative examples. Those skilled in the art will understand that the embodiments of this application only use the bit toggle rate of the operands as an exemplary means of controlling the power consumption of the arithmetic array. Any other physical quantity or circuit state variable that can equivalently characterize and / or control the power consumption of the arithmetic array falls within the protection scope of this application.

[0072] In one aspect of this application's embodiments, the first pseudo-operand is fixed with all 1s in the mantissa and all 0s in the exponent. Based on this, by flipping at least one bit in the mantissa portion of the second pseudo-operand every unit of time, active control of the computing unit's power consumption can be established. Specifically, the number of bits flipped in the mantissa portion of the second pseudo-operand directly determines the number of partially product rows that change in the partially product array of the computing unit. The more bits flipped, the more partially product rows are affected, the stronger the circuit activity of the computing unit, and the higher the power consumption level.

[0073] In one aspect of the embodiments of this application, the toggle rate of the mantissa portion of the second pseudo-operand is fixed at a unit time (e.g., a single clock cycle), then the toggle rate depends on the number of bits toggled per unit time. This toggle mode ensures the regularity and predictability of power consumption variations.

[0074] For example, linear control of the computing unit's power consumption can be achieved by adjusting the number of toggled bits in the mantissa portion of the second pseudo-operand. When a high power consumption level needs to be maintained, multiple bits in the mantissa portion of the second pseudo-operand are toggled simultaneously. Each toggled bit triggers a complete change in the corresponding partial product row from all 0s to all 1s (or from all 1s to all 0s), thereby generating strong circuit activity within the computing unit. Conversely, when a smooth reduction in power consumption is required, the number of toggled bits in the mantissa portion of the second pseudo-operand can be gradually reduced. Each reduction in toggled bits reduces the state change of a partial product row, correspondingly reducing the internal circuit activity of the computing unit and achieving a gradual decrease in power consumption.

[0075] By controlling the number of flipped bits in the mantissa portion of the second pseudo-operand, the power consumption level of the computing unit can be precisely adjusted, achieving a transition from high to low. On the other hand, due to the characteristic that the mantissa of the first pseudo-operand is all 1s, the contribution of each flipped bit in the mantissa portion of the second pseudo-operand to power consumption is relatively independent and additive, resulting in a good linear relationship between power consumption change and the number of flipped pseudo-bits. Finally, this design only requires implementing the corresponding bit-flipping logic in the pseudo-operand generation unit, resulting in low hardware overhead and simple and reliable control logic.

[0076] In some embodiments, the second computation task includes N subtasks executed sequentially, where N is an integer greater than 1. When the computation unit executes the i-th subtask, the number of bits whose mantissa portion of the second pseudo-operand is flipped is greater than the number of bits whose mantissa portion of the second pseudo-operand is flipped when the (i+1)-th subtask is executed, where i is a positive integer less than N.

[0077] In some embodiments, the second computational task includes N subtasks executed sequentially, where N is an integer greater than 1. The power consumption of the computation array executing the i-th subtask is greater than the power consumption of executing the (i+1)-th subtask, where i is a positive integer less than N.

[0078] In one aspect of this embodiment, the first pseudo-operand and the second pseudo-operand generated by the pseudo-operand generation unit are sent to the computing unit to execute the second computing task. Throughout the execution of the second computing task, the first pseudo-operand remains fixed (all 1s in the mantissa, all 0s in the exponent), while the mantissa portion of the second pseudo-operand changes according to a preset pattern. Specifically, as the subtasks progress sequentially, the number of bits in the mantissa portion of the second pseudo-operand that are flipped in each subsequent subtask is reduced. Due to the setting of the first pseudo-operand's mantissa being all 1s, each flipped bit in the mantissa of the second pseudo-operand triggers a state flip (from all 0s to all 1s or from all 1s to 0) of a complete partial product row in the computing unit's partial product array. Therefore, the reduction in the number of flipped bits directly leads to a reduction in the number of rows in the partial product array that undergo state flips, thereby weakening the circuit activity of the combinational logic within the computing unit. This gradual weakening of circuit activity manifests macroscopically as a gradual reduction in the power consumption of the arithmetic array.

[0079] For example, taking a computing unit supporting the FP16 floating-point format as an example, this computing unit includes a floating-point multiplication unit for performing a second computation task based on a first pseudo-operand and a second pseudo-operand. Assuming the second computation task is configured to include three sequentially executed subtasks (i.e., N=3), each subtask lasting 10 clock cycles, the specific implementation is as follows: First subtask (i=1): In this stage, the mantissa portion of the second pseudo-operand is configured to have 8 bits flipped every unit of time. This setting ensures that when the second pseudo-operand is multiplied by the first pseudo-operand (whose mantissa is all 1s), a large number of rows in the resulting partial product array are in an active state, thus maintaining high activity within the computational unit's internal circuitry. Therefore, the arithmetic array consumes a relatively high amount of power during this subtask, effectively absorbing the power peak that follows the completion of the first computational task.

[0080] Second subtask (i=2): In this stage, the mantissa portion of the second pseudo-operand is configured to have 5 bits flipped per unit time. The reduced number of flipped bits compared to the first subtask directly leads to a corresponding decrease in the number of rows in the partial product array where state flips occur, thus reducing the activity of the internal circuitry of the computation unit. Macroscopically, this manifests as a first significant step-like decrease in power consumption when the arithmetic array executes the second subtask compared to the first subtask.

[0081] The third subtask (i=3): In this stage, the mantissa portion of the second pseudo-operand is configured to have 2 bits flipped every unit of time. At this point, only a few partial product rows are affected and undergo state flips, and most combinational logic nodes within the computation unit have stabilized, significantly reducing circuit activity. Therefore, the power consumption level of the arithmetic array is greatly reduced in this stage, approaching its idle power consumption level.

[0082] Through the above-described progressively decreasing sequence from 8 to 5, and then to 2 flipped bits, the total power consumption of the computing array during the execution of the second computation task is achieved in a phased and controlled process, starting from the high bit after the effective computation has just ended, going through two intermediate transition levels, and finally smoothly decreasing to the low bit.

[0083] It is worth noting that the above description and specific values ​​(such as the specific values ​​and sequences of the number of subtasks and the number of toggled bits) of the progressively decreasing power consumption of the computing array are merely illustrative examples, and this embodiment does not limit them. Any technical solution that controls the pseudo-operand characteristics input to the computing unit to achieve progressively decreasing or smoothly decaying power consumption of the computing unit during idle periods falls within the protection scope of this application.

[0084] By controlling the number of mantissa flip bits of the second pseudo-operand to decrease sequentially in different subtask stages, a stepwise reduction in the power consumption of the computing array is achieved. In each subtask stage, by configuring a specific number of flip bits, the internal circuitry of the computing unit maintains a corresponding activity level, thereby maintaining different power consumption levels.

[0085] Specifically, as the subtasks are executed sequentially, the number of mantissa flip bits in the second pseudo-operand gradually decreases. Correspondingly, the number of rows in the partial product array within the computation unit that experience state flips decreases step by step, and the intensity of circuit activity gradually weakens. Ultimately, the power consumption smoothly transitions from a relatively high level immediately after the effective computation task ends, through multiple power consumption levels, to a lower level close to the idle state. This phased power management method effectively avoids sudden and significant drops in power consumption, providing a reliable guarantee for suppressing voltage surges.

[0086] For example, the computation array achieves the aforementioned gradual reduction in power consumption by receiving specific pseudo-operands. Therefore, the pseudo-operand generation unit needs to be capable of generating the corresponding sequence. The specific implementation of this unit is described in detail below.

[0087] For example, such as Figure 2 As shown, Figure 2 This is a schematic diagram of a pseudo-operand generation unit provided in one possible implementation of this application. The pseudo-operand generation unit 200 includes a counter 210, a series generator 220, and a pseudo-operand generator 230. The pseudo-operand generator includes an XOR gate array 240.

[0088] In one aspect of this embodiment, a counter is used to receive the operand validity status sent by the computing unit to start timing and to measure the number of clock cycles, so as to achieve precise control over the duration of a specific operation. Exemplarily, a counter refers to any hardware module capable of counting clock cycles and outputting corresponding status values. Specific implementations include, but are not limited to: a synchronous binary counter: composed of multiple cascaded flip-flops, with the output of each flip-flop connected to the input of the next stage flip-flop, and a carry signal generated through combinational logic. Triggered by the edge of the clock signal, the counter output value performs binary increment counting, with the least significant bit toggling once per clock cycle, and the toggling frequency of the higher bits decreasing by half at each stage; a circular counter: composed of a group of flip-flops connected end-to-end to form a circular shift register. Through a preset initial state, a single "1" bit is cyclically shifted under clock triggering, with each state lasting one clock cycle, generating a periodic timing control signal; and a loadable counter: based on a basic counter, a parallel loading port is added. When the count reaches a preset value, an overflow signal is generated, and the count value can be reinitialized through the loading port, achieving flexible control over the start and end points of the counting cycle. It is worth noting that the specific implementation of the counter described above is merely an illustrative example. Any hardware circuit capable of counting clock cycles and outputting corresponding state values ​​falls within the protection scope of this application.

[0089] In one aspect of this embodiment, a series generator is used to generate control parameters corresponding to different power consumption levels, so as to control the bit flipping of the mantissa portion of different numbers of second pseudo-operands in different time periods. Exemplarily, a series generator refers to any module capable of outputting corresponding control parameters based on the power consumption level of the current operational array. Specific implementations include, but are not limited to: a lookup table: implemented by read-only memory or registers, storing control parameters (such as bitmasks) corresponding to different series. The corresponding control parameters are directly output using the current series as an address index; a programmable register set: containing multiple configurable registers, each storing the control parameters corresponding to one series. The value of the corresponding register is selected as the output by a multiplexer based on the current series; a state machine combinational logic: identifying the current series through a finite state machine and generating the corresponding control parameters in real time in conjunction with combinational logic circuits. For example, the required bitmask is generated by a shift register or a specific encoding circuit; a microcode controller: controlled by a microinstruction sequence, each microinstruction containing the control parameters for the corresponding series. The corresponding microinstructions are executed sequentially or by jumps using a program counter. It is worth noting that the specific implementation of the above-mentioned series generator is only an illustrative example, and any hardware circuit that can output corresponding control parameters according to a preset series is within the protection scope of this application.

[0090] In this embodiment, the stage generator achieves precise control over the power consumption reduction process by pre-setting intermediate stages for power reduction. Its core mechanism involves outputting one or more bit masks corresponding to intermediate stages to control the mantissa portion of the second pseudo-operand to undergo different numbers of bit flips at different intermediate stages. The bit mask is a binary number with the same width as the second pseudo-operand. The encoding rules and working mechanism of the bit mask are as follows: positions that need to trigger bit flips are set to 1, and positions that do not need to be flipped are set to 0. When the stage generator outputs a bit mask, the mask is XORed with the mantissa of the second pseudo-operand. In this operation, bits with a mask value of 1 will have their corresponding mantissa bits flipped (0 becomes 1, 1 becomes 0), while bits with a mask value of 0 will retain their mantissa bits unchanged. By controlling the number of 1s in the bit mask, the number of flipped bits can be precisely controlled, thereby achieving a step-wise adjustment of the circuit's power consumption. For example, when the preset intermediate stage is one, there is one intermediate stage, and the power consumption change path is: high → intermediate stage → low. In this mode, the series generator stores the corresponding bitmask: controlling the flipping of relatively high bits. For example, for a 10-bit mantissa, the mask 10'b0000111111 (low 6 bits are 1) is used, so that the low 6 bits of the mantissa are flipped. In this configuration, power consumption drops directly from a high level through an intermediate step to a low level, forming a clear two-stage decrease. For example, when the preset intermediate level is three, there are three intermediate steps, and the power consumption change path is: high → intermediate level one → intermediate level two → intermediate level three → low. The series generator stores the corresponding three bitmasks: first-level bitmask: 10'b0011111111 (controls the flipping of the low 8 bits), second-level bitmask: 10'b0000011111 (controls the flipping of the low 5 bits), and third-level bitmask: 10'b0000000011 (controls the flipping of the low 2 bits). In this configuration, power consumption drops directly from a high level through three intermediate steps to a low level, forming a clear four-stage decrease. In this configuration, by using the three bitmasks that progressively reduce the number of flipped bits, power consumption is reduced in three steps from high to low, with each intermediate step corresponding to a different power consumption level.

[0091] The preset number of intermediate stages directly affects the suppression effect of voltage surge. For example, if the computing unit enters an idle state immediately after completing effective calculations, it is equivalent to a preset intermediate stage of zero. This extreme case causes power consumption to drop sharply from its peak to its minimum in a very short time, resulting in a huge current change rate and thus triggering voltage overshoot in the chip. In this embodiment, by introducing a preset number of intermediate stages, precise control of the power consumption reduction process is achieved: when a large number of intermediate stages (e.g., 4-5 stages) are preset, the power consumption exhibits a smooth, stepped decrease. The power consumption drop at each intermediate stage is small, and the current change is gradual, effectively suppressing voltage surge; when a small number of intermediate stages (e.g., 1-2 stages) are preset, the power consumption decreases at a faster rate. Although it cannot completely eliminate voltage surge, it is still a significant improvement compared to existing technologies.

[0092] In one aspect of this embodiment, the size of the preset intermediate levels is related to the data format of the pseudo-operands. Specifically, the mantissa bit width of the data format determines the upper limit of the configurable intermediate levels. Taking FP32 and FP16 formats as examples: for FP16 format pseudo-operands, the mantissa bit width is 10, so theoretically a maximum of 10 intermediate levels can be set; while for FP32 format pseudo-operands, the mantissa bit width is larger, thus enabling the support of more intermediate levels.

[0093] In one aspect of this embodiment, the preset number of intermediate stages is related to the power consumption level of the computing unit when it finishes the first computing task. When the power consumption level is high when the first computing task ends, more intermediate stages can be preset to avoid excessive power consumption drops between adjacent intermediate stages; for scenarios with relatively low power consumption peaks, the number of intermediate stages can be appropriately reduced to reduce the time of the second computing task while ensuring the suppression effect.

[0094] In this embodiment, a counter is used to control the duration of each intermediate step, achieving timing management of the power reduction process through precise clock cycle measurement. For example, the counter achieves precise timing control by measuring the number of clock cycles. At the start of each intermediate step, the counter increments / decrements from an initial value. When the count reaches a preset threshold for that intermediate step, a switching signal is generated, triggering the stage generator to send the bitmask corresponding to the next intermediate step. For example, assuming a preset intermediate stage number of three and a preset duration of 10 clock cycles for each intermediate step, the entire power reduction process requires 30 clock cycles. Specifically, extending the duration of each intermediate step, i.e., extending the hold time on each step (e.g., from 10 cycles to 15 cycles), increases the dwell time of power consumption on each step, resulting in smoother current changes and further suppressing voltage spikes. Shortening the duration of each intermediate step, i.e., reducing the hold time on each step (e.g., from 10 cycles to 5 cycles), accelerates the power reduction speed, making it suitable for computing arrays with high requirements for task switching speed.

[0095] It is worth noting that the specific implementation of the above-described series generator and counter is merely an illustrative example. Any hardware solution that achieves power reduction by configuring power reduction levels and / or controlling the duration of each level is within the scope of protection of this application.

[0096] In one aspect of this embodiment, a pseudo-operand generator is used to perform bit-flipping operations on the input pseudo-operand within a preset time based on the bitmask sent by the series generator, in order to generate a new second pseudo-operand. Exemplarily, the pseudo-operand generator refers to any module capable of flipping one or more bits of the input pseudo-operand based on a bitmask. Exemplarily, the core principle of the pseudo-operand generator is to utilize the characteristics of the XOR operation: when one input is 1, the output is the opposite of the other input; when the input is 0, the output remains unchanged. Based on this characteristic, specific implementations include, but are not limited to: an XOR gate array, composed of multiple independent XOR gates in parallel, the size of which matches the bit width of the pseudo-operand. One input of each XOR gate is connected to the corresponding bit of the input pseudo-operand, and the other input is connected to the corresponding control bit of the bitmask. When the bitmask output by the series generator is loaded onto the array, a bitwise XOR operation is performed: if the mask control bit is logic '1', the corresponding bit in the output second pseudo-operand is flipped relative to the input (0 becomes 1, 1 becomes 0); if the control bit is logic '0', the corresponding bit output is the same as the input pseudo-operand. This XOR gate array implementation has a regular structure, high parallelism, and can achieve fast and accurate bit-level control; Multiplexer array: composed of a set of 2-to-1 multiplexers. The two data input terminals of each selector are connected to the original bit of the input pseudo-operand and its inverted signal, respectively, and the selection terminal is connected to the corresponding control bit of the bitmask. When the control bit is '1', the inverted signal is output, realizing bit flipping; when the control bit is '0', the original signal is output, keeping the bit unchanged; Lookup table structure: implemented through programmable memory or combinational logic. The input pseudo-operand and the bitmask are used together as the input address. All possible output values ​​corresponding to the input combinations are pre-stored in the memory, and the flipped second pseudo-operand is directly output by looking up the table. It is worth noting that the specific implementation of the above pseudo-operand generator is only an illustrative example. Any hardware circuit that can perform bit-condition flipping on the input operand based on the bit mask is within the protection scope of this application.

[0097] In one aspect of this embodiment, the final output of the pseudo-operand generator is a complete pseudo-operand, which consists of two parts: a first pseudo-operand and a newly generated second pseudo-operand. For example, since the first pseudo-operand is a fixed value that remains unchanged during power consumption control, it can be stored internally in the pseudo-operand generator or in a register directly connected to it. The second pseudo-operand, as described above, is generated in real-time by the pseudo-operand generator based on the input pseudo-operand and the bitmask provided by the series generator, using circuits such as an XOR gate array. The bit-flipping pattern of its mantissa is precisely controlled by the bitmask, thereby simulating different operand characteristics to guide a step-like change in power consumption. In the output stage, the pseudo-operand generator combines the internally held fixed first pseudo-operand with the newly generated second pseudo-operand in the current clock cycle to form a complete output word (i.e., a pseudo-operand), which is then sent to the subsequent processing unit.

[0098] In this embodiment, the pseudo-operand generator performs continuous bit-flipping operations on the input pseudo-operand based on the bitmask sent by the series generator to generate a second pseudo-operand for performing the second computational task. This process continues within each intermediate step, with one bit-flipping operation performed every clock cycle until a counter indicates the end of the duration of that intermediate step.

[0099] For example, the workflow of a pseudo-operand generator is as follows: 1. When the computation unit begins executing the second computation task, it sends an operand validity status to the timer in the pseudo-operand generation unit. The counter receives the information and starts timing. Simultaneously, the pseudo-operand generator receives the second valid operand from the last valid operand at the end of the first computation task, uses it as the initial input pseudo-operand, and sets all its exponent parts to zero.

[0100] 2. The series generator outputs the corresponding bitmask based on the current intermediate step value. Bits that need to be flipped are set to 1, and bits that do not need to be flipped are set to 0.

[0101] 3. In each clock cycle: The pseudo-operand generator receives the current input pseudo-operand and bit mask; according to the data sequence of the bit mask, the XOR gate array inside the pseudo-operand generator flips a specific bit in the mantissa of the current input pseudo-operand to generate a new second pseudo-operand; the new second pseudo-operand and the fixed-value first pseudo-operand are output to the external unit as a new pseudo-operand, and the new second pseudo-operand is used as the input pseudo-operand for the next clock cycle.

[0102] 4. The counter measures the duration of the current intermediate step. When the duration reaches the preset value, the series generator is triggered, instructing it to send the bitmask corresponding to the next intermediate step.

[0103] 5. Repeat steps 3-4 until all intermediate steps have been completed.

[0104] For example, taking a computing unit that supports FP16 floating-point format as an example, the second computing task is executed based on the first pseudo-operand and the second pseudo-operand, and three intermediate steps are configured, each of which lasts for 10 clock cycles: First pseudo-operand configuration: all 1s in the mantissa and all 0s in the exponent.

[0105] The second pseudo-operand configuration: The initial value is the second valid operand from the last valid operand at the end of the first computation task, with its exponent set to zero. The mantissa flip configuration is as follows: Intermediate level: lasts for 10 clock cycles, with a bitmask of 10'b0011111111, and controls the lowest 8 bits of the mantissa portion of the input pseudo-operand to flip once per clock cycle.

[0106] Intermediate Level 2: Lasts for 10 clock cycles, with a bitmask of 10'b0000011111, controlling the lowest 5 bits of the mantissa portion of the input pseudo-operand to flip once per clock cycle.

[0107] The middle three levels: last for 10 clock cycles, with a bitmask of 10'b0000000011, and the lowest 2 bits of the mantissa portion of the control input pseudo-operand are toggled once per clock cycle.

[0108] With the above configuration, the power consumption of the computing unit starts from the highest level after the effective computation ends, goes through three distinct power consumption steps (corresponding to 8-bit, 5-bit and 2-bit toggles respectively), and smoothly transitions to a power consumption level close to the idle state within 30 clock cycles, effectively suppressing the chip voltage overshoot phenomenon.

[0109] It is worth noting that the specific workflow, bitmask sequence, and specific values ​​of the above-mentioned pseudo-operand generator are merely illustrative examples. Any hardware unit that can generate pseudo-operands that cause the power consumption of the computing unit to decrease in a step or smoothly by controlling the operand bit flipping mode is within the protection scope of this application.

[0110] In some embodiments, the second computation task includes N subtasks executed sequentially, where N is an integer greater than 1. The computation unit, after completing the first computation task based on valid operands, executes the i-th subtask based on pseudo-operands, where i is initially set to 1. If the execution of the i-th subtask reaches the set clock cycle corresponding to the i-th subtask, the (i+1)-th subtask is executed based on pseudo-operands. If the execution of the N-th subtask reaches the set clock cycle corresponding to the N-th subtask, the execution of the N-th subtask is stopped.

[0111] In this embodiment, the above implementation process is based on the collaborative work of the computation unit and the pseudo-operand generation unit. Exemplarily, the implementation process includes, but is not limited to: 1. Initialization and Task Startup: After the computation unit completes the first computation task based on valid operands, the pseudo-operand generation unit begins operation. At this time, index i is initialized to 1, indicating the start of the first subtask in the second computation task.

[0112] 2. Subtask Execution and Power Consumption Control: For the i-th subtask, the series generator outputs the corresponding i-th level bitmask based on the index i of the current subtask. This bitmask defines the number of bits that need to be continuously flipped in the mantissa of the second pseudo-operand during the current subtask. The total number N of subtasks is equal to the preset value of the intermediate step. The pseudo-operand generator receives this bitmask and starts working in a loop with the second valid operand (whose exponent has been set to zero) at the end of the first computation task as its initial input. In each clock cycle, it flips the specified bits of the current second pseudo-operand according to the bitmask, generates a new second pseudo-operand, and outputs it. The computation unit repeatedly executes the second computation task based on the fixed first pseudo-operand and the continuously changing second pseudo-operand. Since the number of flipped bits of the second pseudo-operand is fixed, the computation unit maintains a stable power consumption level during this subtask.

[0113] 3. Subtask Switching: The counter is responsible for timing the i-th subtask. The set clock period for each subtask is preset and is an integer multiple of the clock period. When the counter measures that the duration of the current subtask has reached its set value, it sends a switching signal to the series generator. This switching signal triggers the index i to increment (i = i + 1). After receiving the switching signal, the series generator sends the (i+1)-th level bitmask to the pseudo-operand generator. Based on the new bitmask, the pseudo-operand generator continues to generate new second pseudo-operands, and the calculation unit then begins to execute the (i+1)-th subtask.

[0114] 4. Process End: Repeat steps 2 and 3 until i = N, i.e., the last subtask is executed. When the duration of the Nth subtask also reaches its set clock cycle, the counter triggers a termination signal, stopping the execution of the Nth subtask. At this time, the pseudo-operand generation unit stops working, the computing unit enters an idle state, but its power consumption level has smoothly decreased to the minimum point through N steps.

[0115] It is worth noting that the subtask execution process, level switching conditions, and specific parameter configurations (such as level N, duration of each subtask, etc.) of the above-mentioned second computing task are merely illustrative examples. Any hardware control scheme that divides the idle period of the computing unit into multiple consecutive stages and controls the power consumption level of each stage based on pseudo-operands to achieve a gradual and / or smooth reduction in power consumption is within the scope of protection of this application.

[0116] For example, such as Figure 3 As shown, Figure 3 This diagram illustrates a comparison of power consumption changes with and without power consumption control, as provided in one possible implementation of this application. The solid line represents the power consumption change curve without power consumption control. In this scenario, after the computing unit completes the first computing task, the power consumption drops sharply from its peak to the lowest idle power consumption level within a very short time. This drastic current change easily triggers voltage surges. The dashed line represents the power consumption change curve with power consumption control, i.e., the power consumption control effect achieved by the embodiment of this application. In this scenario, by executing the second computing task after the first computing task ends, and dividing the second computing task into multiple (N=3 in the example) consecutive sub-tasks, the power consumption starts from the peak and gradually decreases through three intermediate steps: the first, second, and third intermediate power consumption levels, ultimately reducing the power consumption to the lowest idle power consumption level. Each sub-task maintains a stable power consumption level within its set clock cycle. This stepped power consumption decay method reduces the rate of current change, thereby effectively suppressing voltage surges.

[0117] By setting specific timeframes for each subtask of the second computing task, it is ensured that the computing unit can remain on each intermediate step for a sufficiently long time, effectively stabilizing the power consumption level of the computing unit in the corresponding subtask. This avoids a sharp drop in power consumption caused by premature switching of intermediate steps, which would weaken the power control effect. At the same time, precise time control also ensures that the total duration of the entire power reduction process is controllable, effectively suppressing voltage spikes while avoiding unnecessary resource waste.

[0118] In some embodiments, the arithmetic array further includes an operand reading unit and an operand selection unit.

[0119] The operand reading unit is used to send a first signal to the pseudo-operand generation unit and the operand selection unit. The first signal is used to indicate whether a pseudo-operand is generated.

[0120] The pseudo-operand generation unit is used to generate a pseudo-operand and send it to the operand selection unit when the first signal indicates that a pseudo-operand should be generated.

[0121] The operand reading unit is also used to send the valid operand to the operand selection unit when a valid operand is read.

[0122] The operand selection unit is used to send the valid operand or pseudo operand to the calculation unit according to the first signal.

[0123] For example, such as Figure 4 As shown, Figure 4 This is a schematic diagram of an arithmetic array provided in one possible implementation of this application. The arithmetic array 400 includes an operand reading unit 410, a pseudo-operand generation unit 420, an operand selection unit 430, and a calculation unit 440.

[0124] In some embodiments, the operand reading unit is used to read valid operands from an upstream data source, such as a cache, memory, or data bus, and generate corresponding signals to indicate the current computational task status of the computation array. Exemplarily, the operand reading unit refers to any hardware module capable of reading operand data and generating corresponding status identifiers. Specific implementations include, but are not limited to: a data loading controller: comprising an instruction cache interface, opcode decoding logic, and an address generator. This unit determines whether a valid computational task exists by decoding the current instruction and generates a first signal accordingly, while simultaneously controlling the data cache or memory interface to read valid operands; and a state machine-based data controller: managing the data reading process through a state machine. The states of the aforementioned state machine include "idle," "reading," and "data valid," and their outputs directly or indirectly serve as the first signal, controlling the read and write operations of the data bus. The Direct Memory Access (DMA) controller, in a DMA architecture, includes request arbitration logic to determine whether the processor within the chip has initiated a valid computation task request, generating the first signal accordingly, and controlling the DMA transfer of valid operands. The pipeline task monitoring unit, in a pipelined processor architecture, monitors the task flags at each stage of the pipeline, using combinational logic to determine whether a first computation task awaits execution, and generating the corresponding first signal. It is worth noting that the specific implementation of the operand reading unit described above is merely an illustrative example; any hardware circuit capable of reading valid operands and generating corresponding status signals falls within the scope of this application.

[0125] In this embodiment, the operand reading unit performs its function by identifying the type of input operands. Specifically, the operand reading unit determines the current operating state of the computation array by detecting the type flag carried in the input operands. When the read operand is marked as a valid operand (e.g., a valid operand is marked as "1"), it indicates that the computation unit has a first computation task to be executed or is being executed. When the read operand is a pseudo-operand (e.g., a pseudo-operand is marked as "0") or no valid operand is read, it indicates that the computation unit is in an idle state. Based on the operand type identification result, the operand reading unit generates a corresponding first signal. When a valid operand is identified, the first signal is set to indicate that no pseudo-operand is generated. When a pseudo-operand is identified or no valid operand is identified, the first signal is set to indicate that a pseudo-operand is generated (as in the operand valid state in the above embodiment). The first signal generated by the operand reading unit has two independent output paths: one is sent to the pseudo-operand generation unit to control its start / stop state, and the other is sent to the operand selection unit to control its data selection, i.e., selecting whether to output a pseudo-operand or a valid operand. The aforementioned operand type-based identification mechanism ensures that the computing units in the arithmetic array can accurately distinguish between the first and second computing tasks, achieving accurate switching between different computing tasks. This guarantees the normal execution of the first computing task while maintaining necessary circuit activity during idle periods by executing the second computing task, thereby suppressing voltage spikes. It is worth noting that the aforementioned operand type identification mechanism, the logic for generating the first signal, and the specific workflow are merely illustrative examples. Any hardware implementation scheme controlling the switching between the first and second computing tasks by the computing units in the arithmetic array falls within the protection scope of this application.

[0126] In some embodiments, the operand selection unit is used to select whether to send a valid operand or a pseudo-operand to the computing unit according to the first signal. Exemplarily, the operand selection unit refers to any hardware module capable of selecting and outputting one from multiple data sources according to a control signal. Specific implementations include, but are not limited to: a multiplexer, consisting of a set of parallel 2-to-1 multiplexers. The data input of each selector is connected to the corresponding bits of the valid operand and the pseudo-operand, respectively, and the selection terminals are jointly controlled by the first signal. When the first signal indicates that no pseudo-operand is generated, the valid operand is selected for output; otherwise, the pseudo-operand is selected for output; a buffer-based logic unit, using multiple buffers to control the output of the valid operand and the pseudo-operand respectively. The first signal, after decoding, generates two mutually exclusive enable signals, ensuring that only one set of buffers is in working state at any given time, thereby realizing the selection of the data path; and a clock gate, which, in scenarios where clock domains intersect, controls the timing of different data paths by gated clocks. The first signal selects and synchronizes the valid operand or pseudo-operand to the operating clock domain of the computing unit. A crossbar switch, in computing units supporting multiple operand inputs, employs a small crossbar switch structure to establish a data connection between the operand reading unit or pseudo-operand generation unit and the computing unit input port based on the first signal. It is worth noting that the specific implementation of the operand selection unit described above is merely an illustrative example; any hardware circuit capable of selecting between valid and pseudo-operands based on the first signal falls within the protection scope of this application.

[0127] In this embodiment of the application, the operand selection unit receives a first signal from the operand reading unit, which indicates the current working mode of the pseudo-operand generation unit, i.e. whether to generate pseudo-operands or not.

[0128] For example, when the first signal indicates that no dummy operand is generated, the operand selection unit sends the valid operand to the calculation unit. Conversely, when the first signal indicates that a dummy operand is generated, the operand selection unit transmits the dummy operand to the calculation unit.

[0129] In this embodiment, the arithmetic array achieves instant switching between two working modes: performing effective computation and performing power management, through the collaborative working mechanism of four units: an operand reading unit, an operand selection unit, a pseudo-operand generation unit, and a computation unit. Specifically, the operand reading unit, acting as the scheduling center of the arithmetic array, determines that the computation unit has a first computation task to be executed or is currently executing when it reads data marked as valid operands from upstream data sources such as the instruction pipeline, task queue, or data interface, and sends a first signal to other units. This first signal is simultaneously sent to the pseudo-operand generation unit and the operand selection unit. In this embodiment, when the first signal indicates that no pseudo-operands should be generated, the operand reading unit sends the read valid operands to the operand selection unit; the pseudo-operand generation unit, upon receiving the first signal indicating no pseudo-operand generation, enters a stop-run state, i.e., stops generating pseudo-operands; the operand selection unit delivers the valid operands to the computation unit; and the computation unit executes the first computation task based on the input valid operands, completing normal arithmetic or logical operations.

[0130] In one aspect of this embodiment, when the first computation task is completed and the operand reading unit no longer reads new valid operands, it updates the first signal to indicate the generation of pseudo-operands and sends the second valid operand from the last valid operand at the end of the first computation task to the pseudo-operand generation unit; the operand reading unit stops sending valid operands to the operand selection unit; the pseudo-operand generation unit receives the first signal indicating the generation of pseudo-operands and switches to the running state. Its internal counter, series generator, and pseudo-operand generator begin to work collaboratively to generate corresponding pseudo-operands and send them to the operand selection unit; the operand selection unit sends the pseudo-operands to the computation unit; the computation unit executes the second computation task based on the fixed first pseudo-operand and the continuously changing second pseudo-operand. It is worth noting that the above-mentioned collaborative mechanism, signal interaction logic, and workflow of the four units are merely illustrative examples. Any hardware architecture that uses operand reading, pseudo-operand generation, and data selection to achieve switching of the computation unit's working mode falls within the protection scope of this application.

[0131] By introducing an operand reading unit and an operand selection unit, and coordinating with a pseudo-operand generation unit and a calculation unit, when the first signal indicates that no pseudo-operand is generated, the operand selection unit sends the valid operand to the calculation unit to execute the first calculation task. Conversely, when the first signal indicates that a pseudo-operand is generated, the pseudo-operand generation unit generates the pseudo-operand, and the operand selection unit sends the pseudo-operand to the calculation unit, which then begins executing the second calculation task. This mechanism enables rapid switching between valid and pseudo-operands, ensuring that the arithmetic array maintains a certain power consumption level during the intervals between valid calculations, thereby effectively suppressing voltage spikes and ensuring the immediacy of the arithmetic array's valid calculations.

[0132] In some embodiments, the pseudo-operand generation unit is further configured to stop generating pseudo-operands in response to a third computation task based on valid operands during the execution of a second computation task by the computation unit.

[0133] The computing unit is also used to stop executing the second computing task and start executing the third computing task.

[0134] In this embodiment, the third computational task refers to a new computational task based on valid operands that arrives while the computational unit is executing a second computational task based on pseudo-operands. Similar to the first computational task, the arrival of the third computational task will also cause the operand reading unit to set the first signal to indicate that a first computational task is pending execution. Essentially, both the first and third computational tasks are valid computational tasks that need to be processed by the computational unit; the only difference is the timing of their arrival: the first computational task arrives during the initial idle period of the computation array, while the third computational task arrives during the power management process (during the execution of the second computational task).

[0135] For example, the valid pseudo-operand generation unit continuously receives a first signal sent by the operand reading unit. When the operand reading unit reads a new valid operand, i.e., a valid operand for the third computational task, during the execution of the second computational task, and switches the first signal to indicate the presence of a first computational task, it sends the valid operand to the operand selection unit. After receiving the first signal, the pseudo-operand generation unit stops generating pseudo-operands. Specifically, this includes: the counter stops counting and resets its current count value to the initial state; the stage generator stops working and resets its output to the bitmask corresponding to the first power level, i.e., the intermediate stage; the pseudo-operand generator stops working and resets its internal state to the initial state. Simultaneously, the operand selection unit receives the first signal and switches the data it sends to the computation unit from pseudo-operands to valid operands, thereby sending the valid operand for executing the third computational task to the computation unit. After receiving the valid operand from the operand selection unit, the computation unit immediately stops executing the second computational task and begins executing the third computational task based on the valid operand.

[0136] By establishing a rapid task response mechanism, it is ensured that effective computing tasks always have the highest priority. When a new effective computing task, i.e., the third computing task, arrives during the power management process (i.e., during the second computing task), the generation of pseudo-operands and the execution of the second computing task can be immediately stopped, and the execution of the third computing task can be quickly switched to. This mechanism ensures that while suppressing chip voltage overshoot, the computing performance of the arithmetic array is not affected by the power management process.

[0137] In some embodiments, when the chip includes multiple computing arrays, the computing tasks performed by the different computing arrays are independent of each other.

[0138] In this embodiment, the computing array acts as an independent hardware module executing computational tasks, and its internal computing units typically perform the same or similar operations. This structural characteristic makes the power consumption behavior within the same computing array synchronous, thus suitable for sharing a single pseudo-operand generation unit for unified power management. Different computing arrays may have significant differences, including: task type differences: different computing arrays may be responsible for different computational tasks such as matrix multiplication and convolution operations; power consumption differences: each computing array has different power consumption levels and variation patterns due to different computational complexity; and working time differences: the task start time, duration, and end time of each computing array may be different. Based on these differences, this embodiment adopts a design where the computational tasks executed by different computing arrays are independent, that is, each computing array is configured with an independent pseudo-operand generation unit and power management mechanism. It is worth noting that the specific implementation of the above-mentioned independent management of multiple computing arrays is only an illustrative example, and any hardware architecture that can provide independent power management capabilities for different computing arrays falls within the protection scope of this application.

[0139] By configuring independent power management mechanisms for multiple computing arrays within the chip, fine-grained system-level power control is achieved. Each computing array can independently configure the most suitable power reduction parameters based on factors such as the characteristics of its computational task and power consumption level, including the number of intermediate stages, the duration of each intermediate step, and the number of toggling bits. This design ensures that each computing array can effectively suppress voltage overshoot at the end of an effective computational task, while also preventing systemic voltage superposition that could result from simultaneous power state switching by multiple computing arrays. In summary, this approach improves the overall power integrity of the chip while ensuring the computational performance of each computing array.

[0140] The chip proposed in this application generates pseudo-operands through a pseudo-operand generation unit. After completing the first computation task based on the valid operands, the computing unit can continue to execute a second computation task based on the pseudo-operands, and the power consumption of executing the second computation task is less than that of the first computation task. Thus, the chip can maintain a certain power consumption after the valid computation is completed, and allow the power consumption to gradually decrease under control, avoiding the problem of a large voltage surge caused by a sharp drop in power consumption. At the same time, by controlling the execution time of the second computation task, unnecessary resource waste can be avoided. Therefore, without sacrificing chip computing performance, the chip proposed in this application effectively suppresses chip voltage overshoot.

[0141] The technical solutions provided in the embodiments of this application will be described and explained below using method embodiments. For content not described in the method embodiments, please refer to the above embodiments, which will not be repeated here.

[0142] For example, such as Figure 5 As shown, Figure 5 This is a flowchart of a task execution method applied to a chip provided in one possible implementation of this application, which may include at least one of the following steps.

[0143] In some embodiments, the chip includes at least one arithmetic array, which includes a pseudo-operand generation unit and a computation unit. For a detailed description of the chip, please refer to the embodiments described above.

[0144] Step 510: The pseudo-operand generation unit generates pseudo-operands.

[0145] In some embodiments, the pseudo-operands include a first pseudo-operand and a second pseudo-operand, which are used for multiplication calculation tasks.

[0146] In this embodiment, the first pseudo-operand is set to a fixed value. This fixed value refers to a value pre-set at the hardware level and remaining unchanged during the execution of the second computational task, such as all zeros, all ones, or any other fixed constant. For example, by fixing the first pseudo-operand, the activity of the circuits directly related to it within the computational unit can be stabilized immediately. This avoids unpredictable and potentially superimposed circuit flipping caused by simultaneous changes in the first and second pseudo-operands, establishing a stable and predictable power consumption mechanism for the entire second computational task. Furthermore, setting the first pseudo-operand to a fixed value simplifies the control logic and hardware. Using a fixed value means that the first pseudo-operand can be directly provided by a set of hardware connected to high / low level flip-flops, or read from a read-only register, without complex generation logic, thereby reducing the hardware overhead and complexity of the pseudo-operand generation unit.

[0147] In this embodiment, the second pseudo-operand is configured as a variable value, meaning that it can change according to a predetermined sequence within the execution cycle of a second computational task. Exemplarily, the variability of the second pseudo-operand, as the primary variable for power consumption regulation, is the core of power consumption control. By generating a numerical sequence that changes according to a predetermined pattern through hardware circuitry and inputting it as the second pseudo-operand into the computational unit, the activity level of the internal circuitry of the computational unit during the second computational task can be controlled, i.e., the power consumption level of the computational unit can be controlled. Specifically, by designing the change pattern of the second pseudo-operand, the power consumption of the computational unit during the execution of the second computational task can exhibit a controlled and clear trend, rather than unpredictable and chaotic fluctuations.

[0148] In some embodiments, the pseudo-operand generation unit includes a counter, a series generator, and a pseudo-operand generator.

[0149] In this embodiment, the stage generator achieves precise control over the power consumption reduction process by pre-setting intermediate stages for power reduction. Its core mechanism involves outputting one or more bit masks corresponding to intermediate stages to control the mantissa portion of the second pseudo-operand to undergo different numbers of bit flips at different intermediate stages. The bit mask is a binary number with the same width as the second pseudo-operand. The encoding rules and working mechanism of the bit mask are as follows: positions that need to trigger bit flips are set to 1, and positions that do not need to be flipped are set to 0. When the stage generator outputs a bit mask, the mask is XORed with the mantissa of the second pseudo-operand. In this operation, bits with a mask value of 1 will have their corresponding mantissa bits flipped (0 becomes 1, 1 becomes 0), while bits with a mask value of 0 will retain their mantissa bits unchanged. By controlling the number of 1s in the bit mask, the number of flipped bits can be precisely controlled, thereby achieving a step-wise adjustment of the circuit's power consumption. For example, when the preset intermediate stage is one, there is one intermediate stage, and the power consumption change path is: high → intermediate stage → low. In this mode, the stage generator stores the corresponding bit mask: controlling the flipping of relatively high bits, such as using the mask 10'b0000111111 (low 6 bits are 1) for a 10-bit mantissa, so that the low 6 bits of the mantissa are flipped. In this configuration, power consumption drops directly from a high level through an intermediate step to a low level, forming a clear two-stage decrease. For example, when the preset intermediate stage is three, there are three intermediate steps, and the power consumption change path is: high → intermediate stage one → intermediate stage two → intermediate stage three → low. The series generator stores three corresponding bitmasks: first-level bitmask: 10'b0011111111 (controls the flipping of the lower 8 bits), second-level bitmask: 10'b0000011111 (controls the flipping of the lower 5 bits), and third-level bitmask: 10'b0000000011 (controls the flipping of the lower 2 bits). In this configuration, power consumption decreases from a high level through three intermediate steps before reaching a low level, forming a clear four-stage decrease. In this configuration, by using the three bitmasks that progressively reduce the number of flipped bits, a three-step decrease in power consumption from high to low is achieved, with each intermediate step corresponding to a different power consumption level.

[0150] In this embodiment, a counter is used to control the duration of each intermediate step, achieving timing management of the power reduction process through precise clock cycle measurement. For example, the counter achieves precise timing control by measuring the number of clock cycles. At the start of each intermediate step, the counter increments / decrements from an initial value. When the count reaches a preset threshold for that intermediate step, a switching signal is generated, triggering the stage generator to send the bitmask corresponding to the next intermediate step. For example, assuming a preset intermediate stage number of three and a preset duration of 10 clock cycles for each intermediate step, the entire power reduction process requires 30 clock cycles. Specifically, extending the duration of each intermediate step, i.e., extending the hold time on each step (e.g., from 10 cycles to 15 cycles), increases the dwell time of power consumption on each step, resulting in smoother current changes and further suppressing voltage spikes. Shortening the duration of each intermediate step, i.e., reducing the hold time on each step (e.g., from 10 cycles to 5 cycles), accelerates the power reduction speed, making it suitable for computing arrays with high requirements for task switching speed.

[0151] It is worth noting that the specific implementation of the above-described series generator and counter is merely an illustrative example. Any hardware solution that achieves power reduction by configuring power reduction levels and / or controlling the duration of each level is within the scope of protection of this application.

[0152] In this embodiment, the pseudo-operand generator performs continuous bit-flipping operations on the input pseudo-operand based on the bitmask sent by the series generator to generate a second pseudo-operand for performing the second computational task. This process continues within each intermediate step, with one bit-flipping operation performed every clock cycle until a counter indicates the end of the duration of that intermediate step.

[0153] For example, the workflow of a pseudo-operand generator is as follows: 1. When the computation unit begins executing the second computation task, it sends an operand validity status to the timer in the pseudo-operand generation unit. The counter receives the information and starts timing. Simultaneously, the pseudo-operand generator receives the second valid operand from the last valid operand at the end of the first computation task, uses it as the initial input pseudo-operand, and sets all its exponent parts to zero.

[0154] 2. The series generator outputs the corresponding bitmask based on the current intermediate step value. Bits that need to be flipped are set to 1, and bits that do not need to be flipped are set to 0.

[0155] 3. In each clock cycle: The pseudo-operand generator receives the current input pseudo-operand and bit mask; according to the data sequence of the bit mask, the XOR gate array inside the pseudo-operand generator flips a specific bit in the mantissa of the current input pseudo-operand to generate a new second pseudo-operand; the new second pseudo-operand and the fixed-value first pseudo-operand are output to the external unit as a new pseudo-operand, and the new second pseudo-operand is used as the input pseudo-operand for the next clock cycle.

[0156] 4. The counter measures the duration of the current intermediate step. When the duration reaches the preset value, the series generator is triggered, instructing it to send the bitmask corresponding to the next intermediate step.

[0157] 5. Repeat steps 3-4 until all intermediate steps have been completed.

[0158] For example, taking a computing unit that supports FP16 floating-point format as an example, the second computing task is executed based on the first pseudo-operand and the second pseudo-operand, and three intermediate steps are configured, each of which lasts for 10 clock cycles: First pseudo-operand configuration: all 1s in the mantissa and all 0s in the exponent.

[0159] The second pseudo-operand configuration: The initial value is the second valid operand from the last valid operand at the end of the first computation task, with its exponent set to zero. The mantissa flip configuration is as follows: Intermediate level: lasts for 10 clock cycles, with a bitmask of 10'b0011111111, and controls the lowest 8 bits of the mantissa portion of the input pseudo-operand to flip once per clock cycle.

[0160] Intermediate Level 2: Lasts for 10 clock cycles, with a bitmask of 10'b0000011111, controlling the lowest 5 bits of the mantissa portion of the input pseudo-operand to flip once per clock cycle.

[0161] The middle three levels: last for 10 clock cycles, with a bitmask of 10'b0000000011, and the lowest 2 bits of the mantissa portion of the control input pseudo-operand are toggled once per clock cycle.

[0162] With the above configuration, the power consumption of the computing unit starts from the highest level after the effective computation ends, goes through three distinct power consumption steps (corresponding to 8-bit, 5-bit and 2-bit toggles respectively), and smoothly transitions to a power consumption level close to the idle state within 30 clock cycles, effectively suppressing the chip voltage overshoot phenomenon.

[0163] It is worth noting that the specific workflow, bitmask sequence, and specific values ​​of the above-mentioned pseudo-operand generator are merely illustrative examples. Any hardware unit that can generate pseudo-operands that cause the power consumption of the computing unit to decrease in a step or smoothly by controlling the operand bit flipping mode is within the protection scope of this application.

[0164] Step 520: After completing the first computation task based on valid operands, the computing unit executes the second computation task based on pseudo-operands. The power consumption of the computing array executing the second computation task is less than the power consumption of executing the first computation task.

[0165] In some embodiments, the power consumption of the arithmetic array performing the second computational task is less than that performing the first computational task. For example, when performing the first computational task, the sequence of valid operands is determined by the upper-layer application, and the results of operations between its data and consecutive operands are uncontrollable and can be very high, such as when processing two very different matrices. For example, the first computational task may cause a large number of logic gates within the computational unit to flip simultaneously, resulting in significant power consumption for the arithmetic array. When performing the second computational task, the bit pattern of the pseudo-operands is pre-defined, and one of its core design goals is to reduce the difference between the current operand and one or more previous operands. For example, a sequence of all zeros, fixed values, or slowly changing values ​​can be used as pseudo-operands. Operations between pseudo-operands directly reduce the number of logic gates affected within the computational unit, decreasing the total amount of capacitors requiring charging and discharging, thereby reducing power consumption. For example, the first computational task may activate all or most of the data paths of the computational unit. For example, when a multiplier within a computational unit processes random valid operands, all stages such as partial product generation, compression, and final addition are in a highly active state, resulting in high power consumption for the first computational task. The second computation task avoids activating the entire data path by using pseudo-operands. For example, by using all zeros as pseudo-operands to input to the multipliers in the computation unit, the outputs of most AND gates (used to generate partial products) will remain 0, and only a very small number of nodes in the subsequent addition tree will be flipped. The activity of the entire circuit is restricted to a very low level, resulting in lower power consumption for the second computation task.

[0166] In some embodiments, the second computation task is a multiplication computation task.

[0167] For example, computing units typically integrate multiple computational functions, and the power consumption of different functions varies. Specifically, logical operations (such as AND, OR, NOT, XOR): have simple implementation circuits, are usually bit-parallel operations, have no long path dependencies, and have the lowest power consumption; shift operations: implemented through multiplexers, power consumption mainly comes from the switching of the multiplexer, and its power consumption is higher than logical operations but usually lower than arithmetic operations; addition operations: addition operations have higher power consumption than logical operations, but its critical path length is linearly related to the bit width, and its power consumption level is moderate; multiplication operations: the multiplier is the largest and most complex module in the computing unit. An n-bit multiplication operation requires generating n partial products, which are compressed and accumulated through a multi-stage adder network, where n is a positive integer. This process involves a large number of logic gates (such as AND gates and full adders) and deep combinational logic, and a single operation causes most of the internal nodes to flip. Therefore, its peak power consumption is significantly higher than all other operations, and it is the main source of power consumption within the computing unit.

[0168] For example, the embodiments of this application aim to suppress voltage overshoot in the chip. Multiplication tasks in computing tasks are the main cause of this phenomenon, so directly managing their power consumption behavior can achieve significant results. By executing a multiplication task (i.e., a second computing task) after completing the first computing task, the computing unit can maintain a power consumption level higher than the idle state for a set period, avoiding a sharp drop in power consumption due to the cessation of the first computing task. Furthermore, even if the first computing task is a mixed operation, such as some computing units performing addition operations and some performing multiplication operations, by setting the second computing task as a multiplication task, unified management of the overall power consumption behavior of the computing array can be achieved. Specifically, in this mixed computing scenario, the power consumption levels of the first computing tasks executed by different computing units in the aforementioned computing array vary. If they directly enter an idle state after completion, the total power consumption of the chip will exhibit a complex drop pattern, which may still cause localized sharp changes in current, further leading to voltage overshoot. By controlling all computing units in the computing array to uniformly perform multiplication calculations with higher power consumption as a secondary computing task, all computing units in the computing array can be placed under a controllable and consistent power management framework.

[0169] In some embodiments, the second computation task includes N subtasks executed sequentially, where N is an integer greater than 1. After completing the first computation task based on valid operands, the computation unit executes the i-th subtask based on pseudo-operands, where i is initially set to 1. If the execution of the i-th subtask reaches the set clock cycle corresponding to the i-th subtask, the (i+1)-th subtask is executed based on pseudo-operands. If the execution of the N-th subtask reaches the set clock cycle corresponding to the N-th subtask, the execution of the N-th subtask is stopped.

[0170] In some embodiments, the power consumption of the arithmetic array executing the i-th subtask is greater than the power consumption of executing the (i+1)-th subtask, where i is a positive integer less than N.

[0171] In this embodiment, the above implementation process is based on the collaborative work of the computing unit and the pseudo-operand generation unit. Specifically, exemplarily, it includes: 1. Initialization and Task Startup: After the computation unit completes the first computation task based on valid operands, the pseudo-operand generation unit begins operation. At this time, index i is initialized to 1, indicating the start of the first subtask in the second computation task.

[0172] 2. Subtask Execution and Power Consumption Control: For the i-th subtask, the series generator outputs the corresponding i-th level bitmask based on the index i of the current subtask. This bitmask defines the number of bits that need to be continuously flipped in the mantissa of the second pseudo-operand during the current subtask. The total number N of subtasks is equal to the preset value of the intermediate step. The pseudo-operand generator receives this bitmask and starts working in a loop with the second valid operand (whose exponent has been set to zero) at the end of the first computation task as its initial input. In each clock cycle, it flips the specified bits of the current second pseudo-operand according to the bitmask, generates a new second pseudo-operand, and outputs it. The computation unit repeatedly executes the second computation task based on the fixed first pseudo-operand and the continuously changing second pseudo-operand. Since the number of flipped bits of the second pseudo-operand is fixed, the computation unit maintains a stable power consumption level during this subtask.

[0173] 3. Subtask Switching: The counter is responsible for timing the i-th subtask. The set clock period for each subtask is preset and is an integer multiple of the clock period. When the counter measures that the duration of the current subtask has reached its set value, it sends a switching signal to the series generator. This switching signal triggers the index i to increment (i = i + 1). After receiving the switching signal, the series generator sends the (i+1)-th level bitmask to the pseudo-operand generator. Based on the new bitmask, the pseudo-operand generator continues to generate new second pseudo-operands, and the calculation unit then begins to execute the (i+1)-th subtask.

[0174] 4. Process End: Repeat steps 2 and 3 until i = N, i.e., the last subtask is executed. When the duration of the Nth subtask also reaches its set clock cycle, the counter triggers a termination signal, stopping the execution of the Nth subtask. At this time, the pseudo-operand generation unit stops working, the computing unit enters an idle state, but its power consumption level has smoothly decreased to the minimum point through N steps.

[0175] It is worth noting that the subtask execution process, level switching conditions, and specific parameter configurations (such as level N, duration of each subtask, etc.) of the above-mentioned second computing task are merely illustrative examples. Any hardware control scheme that divides the idle period of the computing unit into multiple consecutive stages and controls the power consumption level of each stage based on pseudo-operands to achieve a gradual and / or smooth reduction in power consumption is within the scope of protection of this application.

[0176] Step 530: When the second computing task has been executed for a set time, the computing unit stops executing the second computing task.

[0177] In some embodiments, after completing a first computational task based on valid operands, the computing unit does not execute a second computational task based on pseudo-operands indefinitely, but actively stops the second computational task after a set duration. For example, voltage overshoot is a phenomenon that occurs at the beginning of a sharp drop in power consumption. When the computing unit switches from executing the first computational task to the second computational task, the power consumption begins to decrease from a peak. This decrease is usually not an instantaneous action, but a decay process lasting several clock cycles. During this period, the current change in the circuit is still relatively large, but much smaller than the impact of a direct shutdown. After a specific set duration, the power consumption of the computing unit has been buffered by the second computational task, smoothly transitioning from a high level to a sufficiently low level. For example, the greater the drop in power consumption per unit time, the higher the voltage surge will be, assuming other conditions remain unchanged; conversely, if the drop in power consumption per unit time is smaller and slower, the voltage surge will be smaller, assuming other conditions remain unchanged. Based on the above, even if the second computational task is completely stopped, allowing the computing unit to enter an idle state, the magnitude and speed of its power consumption drop have been greatly reduced, and the resulting current change is insufficient to cause an excessively large voltage surge. Continuing to execute the second computational task at this point would be an unnecessary waste of resources.

[0178] For example, the aforementioned set duration is a predefined parameter, the specific value of which is determined by system design requirements and can be implemented through various hardware methods. Specifically, it includes: a fixed number of clock cycles: a hardware counter starts counting when the second computing task is started. When the count value reaches a preset fixed value, such as 8, 16, or 32 clock cycles, the counter generates a signal as a control signal to stop execution. This preset value can be stored in a configuration register or fixed by hardware circuitry; a configurable number of clock cycles: to adapt to different voltage domains or operating frequencies, the duration can be configurable. The system can write a value representing the duration into a dedicated register via the configuration bus, and the hardware counter uses this value as a counting target; an adaptive duration based on monitoring feedback: in some embodiments, the set duration can be adaptive. The hardware can integrate simple detection circuitry or a current sensor. When chip noise is detected to have subsided, for example, no voltage overshoot is detected for several consecutive cycles, a stop signal is generated in advance. Conversely, if a voltage overshoot is detected, the execution time of the second computing task can be appropriately extended.

[0179] In some embodiments, the arithmetic array further includes an operand reading unit and an operand selection unit.

[0180] The operand reading unit sends a first signal to the pseudo-operand generation unit and the operand selection unit. The first signal is used to indicate whether a pseudo-operand is generated.

[0181] When the first signal indicates that a pseudo-operand should be generated, the pseudo-operand generation unit generates a pseudo-operand and sends the pseudo-operand to the operand selection unit.

[0182] When the operand reading unit reads a valid operand, it sends the valid operand to the operand selection unit.

[0183] In this embodiment, the arithmetic array achieves instant switching between two working modes: performing effective computation and performing power management, through the collaborative working mechanism of four units: operand reading unit, operand selection unit, pseudo-operand generation unit, and computation unit.

[0184] For example, the operand reading unit acts as the scheduling center of the computation array. When it reads data marked as valid operands from upstream data sources such as the instruction pipeline, task queue, or data interface, it determines that the computation unit has a first computation task to be executed or is currently executing, and sends a first signal to other units. The aforementioned first signal is simultaneously sent to the pseudo-operand generation unit and the operand selection unit.

[0185] For example, when the first signal indicates that no pseudo-operands are generated, the operand reading unit sends the read valid operands to the operand selection unit; the pseudo-operand generation unit receives the first signal indicating that no pseudo-operands are generated and enters a stop-run state, that is, stops generating pseudo-operands; the operand selection unit sends the valid operands to the calculation unit; the calculation unit performs the first calculation task based on the input valid operands and completes normal arithmetic or logical operations.

[0186] For example, when the first computation task is completed and the operand reading unit no longer reads new valid operands, it updates the first signal to indicate the generation of pseudo-operands and sends the second valid operand from the last valid operand at the end of the first computation task to the pseudo-operand generation unit; the operand reading unit stops sending valid operands to the operand selection unit; the pseudo-operand generation unit receives the first signal indicating the generation of pseudo-operands and switches to the running state. Its internal counter, series generator, and pseudo-operand generator begin to work together to generate corresponding pseudo-operands and send the pseudo-operands to the operand selection unit; the operand selection unit sends the pseudo-operands to the computation unit; the computation unit executes the second computation task based on the fixed first pseudo-operand and the continuously changing second pseudo-operand in the pseudo-operands.

[0187] It is worth noting that the coordination mechanism, signal interaction logic, and workflow of the above four units are merely illustrative examples. Any hardware architecture that achieves the switching of working modes of computing units through operand reading, pseudo-operand generation, and data selection is within the protection scope of this application.

[0188] For other details not described in detail in the method embodiments, please refer to the descriptions in the embodiments above, which will not be repeated here.

[0189] In summary, the task execution method for chips proposed in this application generates pseudo-operands through a pseudo-operand generation unit. After completing the first computation task based on the valid operands, the computing unit can continue to execute the second computation task based on the pseudo-operands, and the power consumption of executing the second computation task is less than that of the first computation task. Thus, the chip can maintain a certain power consumption after the valid computation is completed, and allow the power consumption to gradually decrease under control, avoiding the problem of a large voltage surge caused by a sharp drop in power consumption. Simultaneously, by controlling the execution time of the computing unit for the second computation task, unnecessary resource waste can be avoided. Therefore, the task execution method for chips proposed in this application effectively suppresses chip voltage overshoot without sacrificing chip computing performance.

[0190] In some embodiments, an electronic device is also provided, which includes the aforementioned chip.

[0191] For example, such as Figure 6 As shown, Figure 6 This is a simplified structural block diagram of an electronic device provided in one possible implementation of this application. The electronic device 600 includes a processor 610 and a memory 620.

[0192] Processor 610 may include one or more processing cores, such as a quad-core processor or an octa-core processor. Processor 610 may be implemented using at least one hardware form selected from DSP, FPGA, and PLA (Programmable Logic Array). Processor 610 may also include a main processor and a coprocessor. The main processor, also known as the CPU, is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 610 may integrate a GPU, which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 610 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0193] The memory 620 may include one or more computer-readable storage media, which may be non-transitory. The memory 620 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 620 are used to store a computer program configured to be executed by one or more processors to implement the task execution method applied to the chip described above.

[0194] Those skilled in the art will understand that Figure 6 The structure shown does not constitute a limitation on the electronic device 600, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0195] In some embodiments, the electronic device 600 may be a server, a server cluster, an artificial intelligence computing cluster, a cloud computing cluster, etc., and this application does not limit it.

[0196] It should be understood that "multiple" as mentioned herein refers to two or more. Furthermore, the step numbers described herein are merely illustrative of one possible order of execution. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this practice.

[0197] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip, characterized by The chip comprises at least one operation array, and the operation array comprises a pseudo operand generation unit and a calculation unit; The pseudo operand generation unit is configured to generate a pseudo operand; The calculation unit is configured to perform a second calculation task based on the pseudo operand after completing a first calculation task based on a valid operand; wherein power consumption of the operation array in performing the second calculation task is less than power consumption in performing the first calculation task; The calculation unit is further configured to stop performing the second calculation task if performing the second calculation task reaches a set time length.

2. The chip according to claim 1, characterized in that, The second calculation task comprises N subtasks performed in sequence, and N is an integer greater than 1; Power consumption of the operation array in performing an ith subtask is greater than power consumption of the operation array in performing an (i+1)th subtask, i is a positive integer less than N.

3. The chip of claim 2, wherein, The calculation unit is configured to: perform an ith subtask based on the pseudo operand after completing the first calculation task based on the valid operand, i is initially 1; perform an (i+1)th subtask based on the pseudo operand if performing the ith subtask reaches a set clock cycle corresponding to the ith subtask; stop performing the Nth subtask if performing the Nth subtask reaches a set clock cycle corresponding to the Nth subtask.

4. The chip of claim 1, wherein The second calculation task is a multiplication calculation task.

5. The chip of claim 4, wherein, The pseudo operand comprises a first pseudo operand and a second pseudo operand, and the first pseudo operand and the second pseudo operand are used for the multiplication calculation task; The first pseudo operand is a fixed value, and the second pseudo operand is a variable value.

6. The chip of claim 5, wherein, At least one bit in a mantissa part of the second pseudo operand flips in unit time.

7. The chip of claim 6, wherein The second calculation task comprises N subtasks performed in sequence, and N is an integer greater than 1; When the calculation unit performs an ith subtask, a number of bit positions in the mantissa part of the second pseudo operand that flip is greater than a number of bit positions in the mantissa part of the second pseudo operand that flip when the calculation unit performs an (i+1)th subtask, i is a positive integer less than N.

8. The chip of claim 5, wherein, The mantissa part of the first pseudo operand is all 1, and the exponent part of the first pseudo operand is all 0.

9. The chip of claim 1, wherein, The operation array further comprises an operand reading unit and an operand selection unit; The operand reading unit is configured to send a first signal to the pseudo operand generation unit and the operand selection unit, and the first signal is used to indicate whether to generate the pseudo operand; The pseudo operand generation unit is configured to generate the pseudo operand and send the pseudo operand to the operand selection unit if the first signal indicates to generate the pseudo operand; The operand reading unit is further configured to send the valid operand to the operand selection unit if the valid operand is read; The operand selection unit is configured to send the valid operand or the pseudo operand to the calculation unit according to the first signal.

10. The chip of claim 1, wherein The pseudo operand generation unit is further configured to, in a process in which the calculation unit executes the second calculation task, stop generating the pseudo operand in response to a third calculation task based on the effective operand; The calculation unit is further configured to stop executing the second calculation task and start executing the third calculation task.

11. The chip according to any one of claims 1 to 10, characterized in that In a case where the chip comprises a plurality of the operation arrays, the calculation tasks executed by different operation arrays are independent of each other.

12. An electronic device, comprising: The electronic device comprises the chip according to any one of claims 1 to 11.

13. A task execution method applied to a chip, characterized by, The chip comprises at least one operation array, and the operation array comprises a pseudo operand generation unit and a calculation unit. The method comprises: The pseudo operand generation unit generates a pseudo operand; The calculation unit executes a second calculation task based on the pseudo operand after completing a first calculation task based on an effective operand; wherein the power consumption of the operation array in executing the second calculation task is less than the power consumption in executing the first calculation task; The calculation unit stops executing the second calculation task in a case where the execution of the second calculation task reaches a set time length.

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