CPU frequency equalization self-adaptive control method and device

Abstract

The invention discloses a CPU frequency balance self-adaptive control method and device. The method comprises the steps that the numerical values of load voltage of a CPU are set into a continuous high-voltage area, a reference area and a low-voltage area from large to small; acquiring the load voltage of the CPU core in real time; judging the interval of the load voltage; when the load voltage lasts for more than a first preset duration and is in a high-voltage region, dynamically adjusting the basic frequency of a CPU clock according to the cache occupancy, so that the basic frequency is dynamically increased until the load voltage drops to a reference region; and when the load voltage is in the low-voltage region for more than a second preset duration, dynamically adjusting the basic frequency according to the cache occupancy, so that the basic frequency is dynamically reduced until the load voltage rises to the reference region. Compared with the prior art, when the load voltage continuously deviates from the reference interval, the clock basic frequency is dynamically adjusted according to the cache occupancy, so that the load voltage is stabilized in the reference area for a long time, the response is rapid, and the load voltage is prevented from instantaneously dropping.

Description

Technical Field

[0001] This invention relates to the field of computers, and more particularly to a method and apparatus for CPU frequency equalization adaptive control. Background Technology

[0002] With the increasing computing demands and the diversification of application scenarios, the demand for multi-core and many-core system-on-chips (SoCs) has risen significantly. Especially in fields such as artificial intelligence (AI), the Internet of Things (IoT), edge computing, and high-performance computing (HPC), the processing power of multiple cores can better meet the needs of parallel processing and real-time data analysis. However, the resulting power consumption and heat issues have become increasingly prominent, and the rational management of CPU power consumption presents a significant technical challenge.

[0003] Current common SoC power management is based on the PCSA power control system architecture standard. It defines the power management mechanism between the operating system and hardware through ACPI, and uses OSPM to guide SCP in adjusting supply voltage, controlling power consumption, and managing clock speeds based on the current workload and usage scenario. Operating system-based SoC power management frameworks are system-level, coarse-grained, and strongly correlated with system business scenarios. However, power consumption changes at the SoC level are actually microscopic and transient, a complex manifestation of the combined effects of multiple factors. Simply performing system-level power control is clearly insufficient to meet the granular control requirements of complex, large-scale SoCs.

[0004] The ARM architecture, with its high energy efficiency, flexibility, scalability, and mature ecosystem, shows promising prospects in the rapid development of cloud computing and the Internet of Things. The ARM V9 architecture introduces the AMU (Activity Monitoring Unit) feature for system power management and monitoring, and the MPMM (Activity Monitoring Unit) feature to support microarchitecture-level power management mechanisms. MPMM achieves monitoring through auxiliary AMU counters. External power controllers can use these metrics to predict SoC power consumption, limiting the number of cores capable of executing high-activity workloads or switching to different DVFS (Dynamic Voltage Scaling) operating points. However, these features are currently software- and system-level oriented, and suffer from slow response times, making it difficult to handle transient voltage drops.

[0005] Therefore, there is an urgent need for a CPU frequency equalization adaptive control method and device that can solve the above problems. Summary of the Invention

[0006] The purpose of this invention is to provide a CPU frequency equalization adaptive control method and device, which dynamically adjusts the clock base frequency according to the cache occupancy rate when the load voltage continuously deviates from the reference range, so that the load voltage remains stable in the reference range for a long time, with fast response and can prevent the load voltage from dropping instantaneously.

[0007] To achieve the above objectives, the present invention provides a CPU frequency balancing adaptive control method, comprising: setting the CPU load voltage values ​​from large to small as a continuous high voltage region, a reference region, and a low voltage region; real-time acquisition of the CPU core load voltage; determining the range of the CPU core load voltage; when the load voltage remains in the high voltage region for a first preset duration, dynamically adjusting the CPU clock base frequency according to the cache occupancy rate, so that the CPU clock base frequency dynamically increases until the load voltage drops to the reference region; when the load voltage remains in the low voltage region for a second preset duration, dynamically adjusting the CPU clock base frequency according to the cache occupancy rate, so that the CPU clock base frequency dynamically decreases until the load voltage rises to the reference region.

[0008] Preferably, the load voltage variation trend is monitored. The reference region is divided into an upper half and a lower half by a reference voltage. The load voltage in the upper half is greater than that in the lower half. When the load voltage is in the lower half of the reference region and continues to decrease for a third preset time period, the fast and weak gap clock is paused. This invention adjusts the load voltage from both the base frequency and clock management aspects, effectively controlling the load voltage to remain stable over a long period.

[0009] Preferably, by monitoring the trend of the load voltage change, and when the load voltage is in a low voltage region and continues to decrease for a fourth preset time period, the fast and weak-gap clock is paused, and the base frequency of the CPU clock is reduced to a preset value. This invention regulates the load voltage from both the base frequency and clock management aspects, effectively controlling the load voltage to remain stable over a long period.

[0010] Preferably, when the load voltage is below the low voltage region, recording is interrupted and an accident is reported.

[0011] Preferably, controlling the dynamic increase or decrease of the CPU clock's base frequency specifically includes: querying the current cache occupancy, determining the current frequency band based on the cache occupancy, obtaining the base frequency corresponding to the frequency band based on the mapping relationship between the frequency band and the base frequency, so as to adjust the CPU clock's base frequency.

[0012] Specifically, the cache occupancy rate includes one or more of the following: cache entry occupancy rate, cache entry read access occupancy rate, cache entry write access occupancy rate, integer execution entry occupancy rate, and vector execution entry occupancy rate.

[0013] Preferably, the base frequency is adjusted according to phase-locked loop (PLL) technology, and the PLL is monitored in real time to see if it is successfully locked. If the locking fails, the base frequency output is turned off, and the PLL is re-locked.

[0014] Preferably, controlling the dynamic increase or decrease of the base frequency of the CPU clock specifically includes: dynamically adjusting the base frequency of the CPU clock based on the mapping relationship between cache occupancy and base frequency, wherein the higher the cache occupancy, the higher the base frequency, and the mapping relationship between cache occupancy and base frequency is a step-like relationship or a linear relationship.

[0015] Preferably, the CPU load voltage values ​​are set from largest to smallest as the highest voltage point, the high limit warning voltage point, the reference voltage point, the low limit warning voltage point, and the minimum voltage point. The interval between the highest voltage point and the high limit warning voltage point is the high voltage region, the interval between the low limit warning voltage point and the high limit warning voltage point is the reference region, and the interval between the low limit warning voltage point and the minimum voltage point is the low voltage region. The reference voltage point divides the reference region into an upper half interval and a lower half interval.

[0016] The present invention also provides a CPU frequency equalization adaptive control device, characterized in that it includes a memory, a processor and one or more operation commands, wherein the operation commands are stored in the memory and can be executed by the processor to perform the CPU frequency equalization adaptive control method as described above.

[0017] Compared with the prior art, the present invention dynamically adjusts the clock base frequency according to the cache occupancy rate when the load voltage continuously deviates from the reference range, so that the load voltage remains stable in the reference range for a long time, with a fast response and prevents the load voltage from dropping instantaneously. Attached Figure Description

[0018] Figure 1 This is a flowchart of the CPU frequency equalization adaptive control method of the present invention.

[0019] Figure 2 This is a structural block diagram of the CPU frequency equalization adaptive control device of the present invention.

[0020] Figure 3 This is a schematic diagram illustrating the change of load voltage over time according to the present invention. Detailed Implementation

[0021] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0022] refer to Figure 1 The present invention discloses a CPU frequency equalization adaptive control method, including steps S1 to S4b.

[0023] Before step S1, the value of the CPU load voltage U1 is set from large to small as a continuous high voltage region C1, a reference region C2, and a low voltage region C3.

[0024] Specifically, the CPU load voltage U1 is set from largest to smallest as the highest voltage point V1, the high-limit warning voltage point V2, the reference voltage point V3, the low-limit warning voltage point V4, and the minimum voltage point V5, forming a high-voltage region C1, a reference region C2 (including an upper half C21 and a lower half C22), and a low-voltage region C3, respectively. The area between the highest voltage point V1 and the high-limit warning voltage point V2 is the high-voltage region C1; the area between the low-limit warning voltage point V2 and the high-limit warning voltage point V4 is the reference region C2; and the area between the low-limit warning voltage point V2 and the minimum voltage point V5 is the low-voltage region C3. The reference voltage point V3 divides the reference region C2 into an upper half C21 and a lower half C22.

[0025] S1 collects the CPU core's load voltage U1 in real time.

[0026] S2 determines the range of the CPU core's load voltage U1.

[0027] S3a, when the load voltage U1 remains in the high voltage region C1 for more than a first preset time t1, step S4a, dynamically adjust the base frequency of the CPU clock according to the cache occupancy rate, so that the base frequency of the CPU clock dynamically increases until the load voltage U1 drops to the reference region C2.

[0028] The cache occupancy rate includes one or more of the following: cache entry occupancy rate, cache entry read access occupancy rate, cache entry write access occupancy rate, integer execution entry occupancy rate, and vector execution entry occupancy rate. The cache occupancy rate is calculated using the PMU (Power Management Unit). The PMU records cache and power consumption-related events to calculate the cache occupancy rate. When the cache occupancy rate includes multiple of these factors, the weighted sum of each factor is first calculated. This weighted sum is then used as the total cache occupancy rate to adjust the CPU clock's base frequency; a higher cache occupancy rate results in a lower base frequency.

[0029] S3b, when the load voltage U1 remains in the low voltage region C3 for more than a second preset time t2, step S4b is executed.

[0030] S4b dynamically adjusts the base frequency of the CPU clock based on the cache occupancy rate, causing the base frequency of the CPU clock to decrease dynamically until the load voltage U1 rises to the reference region C2. Specifically, the base frequency is dynamically adjusted within a certain base frequency range.

[0031] In this embodiment, the cache occupancy rate and the frequency range have a stepped or linear relationship. Specifically, in this embodiment, steps S4a and S4b are as follows: query the current cache occupancy rate, determine the current frequency range based on the cache occupancy rate, and obtain the base frequency corresponding to the frequency range based on the mapping relationship between the frequency range and the base frequency, so as to adjust the base frequency of the CPU clock.

[0032] Specifically, when dynamically adjusting the base frequency of the CPU clock based on the cache occupancy rate, the base frequency is adjusted using phase-locked loop (PLL) technology; it also continuously monitors in real time whether the PLL is successfully locked. If the locking fails, the base frequency output is turned off, and the PLL is re-locked.

[0033] Preferably, the CPU frequency equalization adaptive control method also includes steps S3c and S4c. In step S2, the changing trend of the load voltage U1 is also monitored.

[0034] Step S3c: When the load voltage U1 is in the lower half of the reference region C2, C22 and continues to decrease for a third preset time t3, step S4c is executed: control the fast and weak gap clock to pause until the load voltage U1 rises to the upper half of the reference region C2, C21.

[0035] Preferably, the CPU frequency equalization adaptive control method also includes S3d and S4d. In step S2, the changing trend of the load voltage U1 is also monitored.

[0036] Step S3d: When the load voltage U1 is in the low voltage region C3 and continues to decrease for a fourth preset duration t4, steps S4c and S4d are executed. S4c controls the fast and weak-gap clock to pause until the load voltage U1 rises to the upper half of the reference region C2, C21. The fourth preset duration t4 is less than the third preset duration t3. S4d controls the CPU clock's base frequency to decrease to a preset value until the load voltage U1 rises to the reference region C2. This preset value is a lower limit close to the base frequency range or the lower limit of the base frequency. In this embodiment, the preset value is to dynamically reduce the base frequency to 70% based on the current base frequency.

[0037] Better alternatives include S3e and S4e for CPU frequency equalization adaptive control methods.

[0038] Step S3e: When the load voltage U1 is lower than the low voltage region C3, step S4e is executed. In S4e, recording is interrupted and an incident is reported.

[0039] refer to Figure 2The present invention also discloses a CPU frequency equalization adaptive control device, including a memory 11, a processor 12 and one or more operation commands 13, wherein the operation commands 13 are stored in the memory 11 and can be executed by the processor 12 to perform the CPU frequency equalization adaptive control method as described above.

[0040] refer to Figure 3 The figure shows the variation curve of the load voltage U1 of this invention. The vertical axis in the figure, from top to bottom, represents the highest voltage point V1, the high-limit warning voltage point V2, the reference voltage point V3, the low-limit warning voltage point V4, and the minimum voltage point V5, forming a high-voltage region C1, a reference region C2 (including an upper half C21 and a lower half C22), and a low-voltage region C3, respectively. The area between the highest voltage point V1 and the high-limit warning voltage point V2 is the high-voltage region C1; the area between the low-limit warning voltage point V2 and the high-limit warning voltage point V4 is the reference region C2; and the area between the low-limit warning voltage point V4 and the minimum voltage point V5 is the low-voltage region C3. The reference voltage point V3 divides the reference region C2 into an upper half C21 and a lower half C22.

[0041] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the scope of the present invention are still within the scope of the present invention.

Claims

1. A CPU frequency equalization adaptive control method, characterized by: The method comprises the following steps: arranging the values of the load voltage of the CPU from large to small into a continuous high-voltage region, a reference region, and a low-voltage region; collecting the load voltage of the CPU core in real time; judging the interval of the load voltage of the CPU core; when the load voltage is in the high-voltage region for more than a first preset time length, dynamically adjusting the base frequency of the CPU clock according to the cache occupancy ratio, so that the base frequency of the CPU clock is dynamically increased until the load voltage drops to the reference region; when the load voltage is in the low-voltage region for more than a second preset time length, dynamically adjusting the base frequency of the CPU clock according to the cache occupancy ratio, so that the base frequency of the CPU clock is dynamically decreased until the load voltage rises to the reference region.

2. The CPU frequency equalization adaptive control method according to claim 1, characterized by: monitoring the change trend of the load voltage, the reference region is divided into an upper half interval and a lower half interval by a reference voltage, the load voltage in the upper half interval is greater than the load voltage in the lower half interval, when the load voltage is in the lower half interval of the reference region and continues to decrease for a third preset time length, the fast and weak gap clock is controlled to be paused.

3. The CPU frequency equalization adaptive control method of claim 1, wherein: monitoring the change trend of the load voltage, when the load voltage is in the low-voltage region and continues to decrease for a fourth preset time length, the fast and weak gap clock is controlled to be paused, and the base frequency of the CPU clock is controlled to be reduced to a preset value.

4. The CPU frequency equalization adaptive control method of claim 1, wherein: when the load voltage is lower than the low-voltage region, interrupting the recording and reporting of the accident.

5. The CPU frequency equalization adaptive control method of claim 1, wherein: dynamically increasing or decreasing the base frequency of the CPU clock specifically comprises: inquiring the current cache occupancy ratio, determining the current frequency step region according to the cache occupancy ratio, obtaining the base frequency corresponding to the frequency step region according to the mapping relationship between the frequency step region and the base frequency, and adjusting the base frequency of the CPU clock.

6. The CPU frequency equalization adaptive control method of claim 5, wherein: The cache occupancy ratio includes one or more of the cache entry occupancy ratio, the cache entry read access occupancy ratio, the cache entry write access occupancy ratio, the integer execution entry occupancy ratio, and the vector execution entry occupancy ratio.

7. The CPU frequency equalization adaptive control method of claim 1, wherein: The base frequency is adjusted according to the phase-locked loop technology, and whether the phase-locked loop is successfully locked is continuously monitored in real time, if the locking fails, the base frequency output is turned off, and the phase-locked loop locking is re-performed.

8. The CPU frequency equalization adaptive control method of claim 1, wherein: dynamically increasing or decreasing the base frequency of the CPU clock specifically comprises: dynamically adjusting the base frequency of the CPU clock according to the mapping relationship between the cache occupancy ratio and the base frequency, the higher the cache occupancy ratio is, the higher the base frequency is, and the mapping relationship between the cache occupancy ratio and the base frequency is a step relationship or a linear relationship.

9. The CPU frequency equalization adaptive control method of claim 1, wherein: arranging the values of the load voltage of the CPU from large to small into a continuous high-voltage region, a reference region, and a low-voltage region, the interval between the highest voltage point and the high-limit early warning voltage point is the high-voltage region, the interval between the low-limit early warning voltage point and the high-limit early warning voltage point is the reference region, and the interval between the low-limit early warning voltage point and the minimum voltage point is the low-voltage region, and the reference voltage point divides the reference region into an upper half interval and a lower half interval.

10. A CPU frequency equalization adaptive control device, characterized by comprising: A computer program product comprising a memory, a processor and one or more operation commands stored in the memory and executable by the processor for performing the CPU frequency balancing adaptive control method according to any one of claims 1-9.

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