Cache memory, cache reset method and computer system
By using the command processing module and invalidation module in the high-speed cache memory to perform invalidation processing by matching cache lines with function identifiers, the problems of high flexibility and high resource consumption in the prior art are solved, and efficient and flexible FLR request response is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-24
- Publication Date
- 2026-03-06
AI Technical Summary
In existing technologies, the flexibility of handling invalidation in response to FLR requests is low, and the resource overhead is large, making it difficult to meet performance requirements.
A high-speed cache memory is provided, including a command processing module, a drain module, and an invalidation module. By generating drain requests and invalidation requests, and using function identifiers to match cache lines for invalidation processing, the cache memory avoids the use of TCAM and achieves batch invalidation processing of target cache lines.
It improves the flexibility of handling invalidation in response to FLR requests, reduces resource overhead and latency, improves processing efficiency, and ensures that cache lines for other functions are not affected.
Smart Images
Figure CN121614418A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of storage technology, and in particular to a cache memory, a cache reset method, and a computer system. Background Technology
[0002] FLR (Function Level Reset) is a reset mechanism defined in the PCIe specification for a single PCIe function. It allows the operating system or device driver to perform a software-triggered reset of a specific PCIe function without affecting other functions of the same device. When the cache receives an FLR request, it needs to invalidate the cache lines.
[0003] In related technologies, there is a lack of flexibility in responding to FLR requests for invalidation handling. Summary of the Invention
[0004] Based on this, a cache memory, cache reset method, and computer system are provided to improve the flexibility of responding to FLR requests for invalidation handling.
[0005] In a first aspect, this application provides a cache memory. The cache memory includes:
[0006] The command processing module generates a drain request upon receiving a function layer reset request for the target function; and sends the drain request as the last off-chip access request corresponding to the target function to the off-chip host. The drain module instructs the command processing module to generate an invalidation request containing the function identifier of the target function upon receiving drain response data corresponding to the drain request. The invalidation module receives the invalidation request sent by the command processing module, responds to the invalidation request, determines the target cache line corresponding to the target function from each cache line according to the function identifier and the tag value of each cache line in the cache memory, and invalidates the target cache line.
[0007] In one embodiment, the invalid module is specifically used to: for each cache line, match the function identifier with the tag value of the cache line; if the tag value of the cache line includes the function identifier, then determine that the tag value of the cache line matches the function identifier successfully; and take the successfully matched cache line as the target cache line.
[0008] In one embodiment, the invalidation request further includes a cache group number to be scanned; the invalidation module is specifically used to: determine the first cache line in the cache group indicated by the cache group number to be scanned; match the function identifier with the tag value of each first cache line; and take the first cache line that matches successfully as the target cache line.
[0009] In one embodiment, the command processing module is specifically configured to: receive an initial request; determine whether the initial request is a functional layer reset request; and if the initial request is determined to be a functional layer reset request, determine whether the functional layer reset request is valid.
[0010] If the functional layer reset request is determined to be valid, a drain request is generated.
[0011] In one embodiment, the command processing module is specifically configured to: determine whether the function identifier of the target function included in the function layer reset request is recorded in the reset record table; if not, determine that the function layer reset request is valid and record the function identifier of the target function in the reset record table; if yes, determine that the function layer reset request is invalid.
[0012] In one embodiment, before receiving the drain response data corresponding to the drain request, the drain module is further configured to: maintain a miss request queue corresponding to each cache line in the cache memory; the miss request queue includes multiple miss access requests that have missed the cache line; determine whether to respond to each miss access request in the miss request queue based on the storage status of the cache line and the function to which each access request belongs; wherein, the storage status of the cache line is used to indicate whether the cache line has been invalidated.
[0013] In one embodiment, the emptying module is specifically configured to: when the storage state of the cache line is that the cache line has been invalidated, for each missed access request, determine whether the function identifier included in the missed access request is recorded in the reset record table; if the function identifier included in the missed access request is not recorded in the reset record table, then when the cache line data is returned from the off-chip host, respond to the missed access request based on the cache line data; if the function identifier included in the missed access request is recorded in the reset record table, then do not respond to the missed access request.
[0014] In one embodiment, the emptying module is further configured to: invalidate the corresponding cache line if the missed request is an invalid request.
[0015] In one embodiment, the command processing module is further configured to: after generating the drain request, if other access requests containing the function identifier of the target function are received, then intercept the other access requests.
[0016] In one embodiment, the invalidation module is further configured to send a completion signal to the command processing module after invalidating the target cache line; the command processing module is further configured to return a reset response signal to the upper layer upon receiving the completion signal; wherein the reset response signal is used to indicate that the invalidation process has ended.
[0017] Secondly, this application also provides a cache reset method. The method is applied to a cache memory as described in any of the first aspects; the method includes:
[0018] Upon receiving a function layer reset request for the target function, a drain request is generated;
[0019] The drain request is sent to the external host as the last external access request corresponding to the target function.
[0020] Upon receiving the drain response data corresponding to the drain request, the target cache line corresponding to the target function is determined from each cache line based on the function identifier of the target function and the tag value of each cache line in the cache memory, and the target cache line is invalidated.
[0021] Thirdly, this application also provides a computer system, the computer system including a central processing unit and a cache memory as described in any of the first aspects;
[0022] The central processing unit is used to send function layer reset requests for the target function to the cache memory;
[0023] The cache memory is used to generate a drain request when a function layer reset request for a target function is received; send the drain request as the last off-chip access request corresponding to the target function to the off-chip host; and when the drain response data corresponding to the drain request is received, determine the target cache line corresponding to the target function from each cache line according to the function identifier of the target function and the tag value of each cache line in the cache memory, and invalidate the target cache line.
[0024] The aforementioned cache memory, cache reset method, and computer system involve the cache memory generating a drain request upon receiving a function layer reset request for a target function via a command processing module. This drain request is then sent to the off-chip host as the last off-chip access request corresponding to the target function. Upon receiving drain response data corresponding to the drain request, the drain module instructs the command processing module to generate an invalidation request containing the function identifier of the target function. The invalidation module receives the invalidation request from the command processing module, responds to the invalidation request, and determines the target cache line corresponding to the target function from among the cache lines based on the function identifier and the tag values of each cache line in the cache memory, and invalidates the target cache line. This approach ensures that all remaining access requests for the target function have been effectively processed by using the drain request, thus guaranteeing reliable invalidation while ensuring that the original accesses to the target function were processed normally. Furthermore, invalidating the target cache line corresponding to the target function based on its function identifier does not affect the use of cache lines for other functions and allows for targeted invalidation of the target cache line, significantly improving the flexibility of invalidation in response to FLR requests.
[0025] Other beneficial effects of this application will be further explained and illustrated in detail when combined with the accompanying drawings and specific embodiments. Attached Figure Description
[0026] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 This is a schematic diagram of the structure of a cache memory in one embodiment;
[0028] Figure 2 This is a schematic diagram of the structure of another type of cache memory in one embodiment;
[0029] Figure 3 This is a flowchart illustrating the process of generating an empty package in one embodiment;
[0030] Figure 4 This is a flowchart illustrating the process of handling a missed access request in one embodiment;
[0031] Figure 5 This is a schematic diagram of the FLR process performed on the cache memory in one embodiment.
[0032] Figure 6 This is a flowchart illustrating a cache reset method in one embodiment. Detailed Implementation
[0033] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that many specific details are set forth in the following description in order to provide a full understanding of this application, but this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0035] It is understandable that "at least one" refers to one or more, while "multiple" refers to two or more.
[0036] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.
[0037] The RoCE engine stores QPC, CQC, and descriptor information required for business operations in host memory. Accessing host memory via PCIe presents high latency issues, making it difficult to meet performance requirements. To achieve high-speed data transmission, a high-speed cache is needed within the network interface card (NIC) chip to temporarily store some data and information in host memory for the engine to access quickly.
[0038] When the network interface card chip experiences FLR, the ROCE engine employs a parallel internal resource clearing strategy. This means that the cache must process any remaining requests and simultaneously invalidate the corresponding cache lines.
[0039] In this system, access to the general cache (where tags are stored in memory) is based on the Addr, and the Roce engine invalidates cache lines one by one using the Addr. In practical applications, TCAM-based cache implementations store the Addr in the TCAM and perform invalidation based on it. However, the TCAM occupies 6 to 7 times the area of the memory in the cache, resulting in excessive resource overhead. Furthermore, the implementation of invalidating cache lines one by one using the Addr is complex to control, cannot be parallelized, is inefficient, and fails to meet FLR completion time requirements. Moreover, it currently does not support invalidation of cache lines for specific functions.
[0040] In summary, there is currently a lack of flexibility in handling invalid FLR requests.
[0041] In view of this, embodiments of this application provide a high-speed cache memory, a cache reset method, and a computer system. Using this high-speed cache memory, reliable invalidation processing can be achieved while ensuring that accesses originally targeting a specific function are processed normally. Furthermore, invalidation processing can be performed on the target cache line corresponding to the target function based on the function identifier of the target function. This avoids affecting the use of cache lines for other functions and allows for targeted invalidation of the target cache line, greatly improving the flexibility of invalidation processing in response to FLR requests. Moreover, this method can achieve batch invalidation processing of target cache lines corresponding to specific target functions without using TCAM, thus reducing resource overhead, latency, and efficiency.
[0042] It should be noted that, in one optional implementation, the high-speed cache memory provided in this application embodiment can be located in the network interface chip, such as a network card, etc., which is not fully exemplified here.
[0043] The cache memory includes a command processing module, a drain module, and an invalidation module. These modules can be implemented in the cache memory through software, hardware, or a combination of both.
[0044] In one embodiment, such as Figure 1 The diagram shows a schematic of a high-speed cache memory. The cache memory includes a command processing module, a drain module, and an invalidation module.
[0045] The command processing module is used to generate a drain request when a functional layer reset request for a target function is received; and to send the drain request as the last off-chip access request corresponding to the target function to the off-chip host.
[0046] In an optional embodiment of this application, the cache memory receives the function layer reset request for the target function from the processor. Optionally, the processor is a central processing unit (CPU). Alternatively, the cache memory receives the function layer reset request for the target function from the RoCE engine. Any method that allows the function layer reset request to be sent to the cache memory is acceptable; no complete example is provided here.
[0047] The cache memory includes multiple cache groups, each containing multiple ways, and each way corresponding to a cache line. Different cache groups can be divided to store data corresponding to different functions. In this embodiment, during FLR (Functionally Retrieved), the cache line corresponding to the target function can be invalidated, while data in cache lines for other non-target functions can still be accessed normally.
[0048] Optionally, there can be one or more target functions. For example, when there are multiple target functions, multiple threads can be used to receive function layer reset requests for each target function, and different threads can respond to each function layer reset request in parallel. That is, different threads can generate drain requests for each target function in parallel, and the drain module, upon receiving drain response data corresponding to the drain request, instructs the command processing module to generate an invalidation request containing the function identifier of the target function. The invalidation module receives the invalidation request sent by the command processing module, responds to the invalidation request, and, based on the function identifier and the tag value of each cache line in the cache memory, determines the target cache line corresponding to the target function from each cache line and invalidates the target cache line. For ease of understanding, the following explanation uses the response to a single target function's function layer reset request as an example.
[0049] In an optional embodiment of this application, the drain request can be a specific read request. For example, the drain request is a zero-length read request accessing the storage space of the target host. The target host is the host responding to the target function, and the target host's storage space can be used to store data related to the target function.
[0050] In one exemplary implementation, the target function is a "Function" in the PCIe specification, which refers to a "function" or "functional unit" and is an independent logical device.
[0051] In another exemplary implementation, the target function is a specific business module. Different business modules belong to different business scenarios.
[0052] Therefore, the cache line corresponding to a certain function or business module can be invalidated, making the invalidation process more flexible.
[0053] In this embodiment, after generating the drain request, the drain request is inserted into the entry point of the cache memory as the last off-chip access request corresponding to the target function. It can be understood that before the drain request, other access requests corresponding to the target function are received by the cache memory; these are the residual access requests corresponding to the target function and need to be processed normally.
[0054] The drain request is treated as the last off-chip access request. When the drain request is responded to, it is confirmed that the remaining requests have been processed normally. On this basis, invalidation processing is then performed, thereby ensuring that the preceding access requests are processed, that the target function is normal before invalidation processing, and that the timing of invalidation processing is correct.
[0055] The drain module is used to instruct the command processing module to generate an invalid processing request containing the function identifier of the target function when it receives drain response data corresponding to a drain request.
[0056] In one alternative implementation, the cache sends the drain request as the last off-chip access request corresponding to the target function to the off-chip host corresponding to the target function. The off-chip host receives the drain request, and since the drain request does not actually read data, it returns empty data as drain response data to the cache. The drain module in the cache receives this drain response data.
[0057] In another alternative implementation, an additional transmission device is provided between the cache memory and the off-chip host. This transmission device may be located in the network interface card (NIC) or between the NIC and the off-chip host. When a drain request is output from the cache memory, if the transmission device recognizes it as a drain request rather than another normal access request, it will not forward the drain request to the off-chip host, but will directly generate drain response data and return the drain response data to the drain module in the cache memory.
[0058] Optionally, after receiving the drain response data, the drain module sends a drain completion indication signal to the command processing module. Upon receiving the drain completion indication signal, the command processing module generates an invalidation request containing a function identifier of the target function and sends the invalidation request to the invalidation module to instruct the invalidation module to perform invalidation processing. For example, the drain completion indication signal can be a preset level signal or a signal containing preset flag information. It is understood that the drain module can also instruct the command processing module to generate an invalidation request containing a function identifier of the target function in other ways; these are not fully exemplified here.
[0059] The invalidation module is used to receive invalidation requests sent by the command processing module, respond to invalidation requests, determine the target cache line corresponding to the target function from each cache line according to the function identifier and the tag value of each cache line in the cache memory, and invalidate the target cache line.
[0060] The fixed fields in the tag value of a cache line include the function identifier corresponding to the function of the data stored in that cache line. In addition, the tag also includes other fields.
[0061] Therefore, the invalid module can compare the function identifier of the target function with the tag value of each cache line in the cache memory to determine the target cache line that matches the function. This indicates that the target cache line stores the data corresponding to the target function. Thus, invalidating the target cache line can achieve the response to the FLR request for the target function.
[0062] In this embodiment of the application, invalidating the target cache line means clearing or resetting the target cache line.
[0063] Non-target cache lines can be left unprocessed.
[0064] The aforementioned high-speed cache memory can utilize empty requests to ensure that all residual access requests for the target function have been effectively processed. Based on this, invalidation processing can reliably achieve invalidation while ensuring that the original accesses to the target function were processed normally. Furthermore, invalidation can be performed on the target cache line corresponding to the target function based on the function identifier of the target function. This avoids affecting the use of cache lines for other functions and allows for targeted invalidation of the target cache line, greatly improving the flexibility of invalidation processing in response to FLR requests. Moreover, this method can achieve batch invalidation of target cache lines corresponding to specific target functions without using TCAM, thus resulting in lower resource overhead, lower latency, and higher efficiency.
[0065] In optional embodiments of this application, such as Figure 2A schematic diagram of another high-speed cache memory structure is shown. The command processing module FLR_CTRL includes a request receiving unit FLR Filter, a request parsing unit FLR_Parse, a reset recording unit Func_ID Table, and a state machine unit FLR_FSM. The request receiving unit receives functional layer reset requests and other types of access requests; the request parsing unit confirms whether the received request is a functional layer reset request or other types of access request; the reset recording unit stores the reset record table; and the state machine unit maintains the working state of the state machine. The invalidation module Tag_ctrl includes a reset scan unit FLR Scan and an information storage unit Tag_Mem. The information storage unit performs normal tag information storage, Hit / Miss judgment, and replacement functions; the reset scan unit receives invalidation requests sent by the command processing module, responds to invalidation requests, determines the target cache line corresponding to the target function from each cache line based on the function identifier and the tag value of each cache line in the cache memory, and performs invalidation processing on the target cache line. The emptying module Miss_Table_Array maintains the miss request queues Entry0 to Entry m corresponding to each cache line. In an Entry, the state is the consistency state bit, and the opcode is the opcode.
[0066] Based on the above-mentioned units, each module can operate reliably. The following section uses this as an example to illustrate the process of invalidating the cache memory.
[0067] In one embodiment, such as Figure 3 This diagram illustrates the process of generating an empty package using the command processing module. The command processing module is specifically used to execute the following steps:
[0068] Step 301: Receive the initial request.
[0069] Step 302: Determine whether the initial request is a functional layer reset request.
[0070] The initial request refers to any type of request received by the command processing module. Therefore, it is necessary to determine whether the initial request is a functional layer reset request.
[0071] The command processing module can parse the initial request to determine its type, thereby determining whether it is a functional layer reset request. Optionally, the request parsing unit can be used to parse the initial request to determine whether it is a functional layer reset request.
[0072] Step 303: If the initial request is determined to be a functional layer reset request, determine whether the functional layer reset request is valid.
[0073] In this context, "functional layer reset request valid" means that the functional layer reset request is the first functional layer reset request for the target function received by the command processing module.
[0074] In this embodiment of the application, all received functional layer reset requests can be recorded, thereby facilitating the identification of whether subsequent received functional layer reset requests are valid.
[0075] In one exemplary implementation, the command processing module is specifically configured to: determine whether the function identifier of the target function included in the function layer reset request is recorded in the reset record table; if not, determine that the function layer reset request is valid and record the function identifier of the target function in the reset record table; if yes, determine that the function layer reset request is invalid.
[0076] If it is a functional layer reset request, the request will contain the function identifier of the target function.
[0077] Different functions have different function identifiers. For example, if the target function is the Function mentioned above, the function identifier can be the Function ID. If the target function is a business module mentioned above, the function identifier can be the module ID corresponding to that business module. For example, the function identifier can be the queue ID of the business queue corresponding to that business module. This is not a complete example.
[0078] The function identifier of the target function included in the functional layer reset request is obtained, and then the obtained function identifier is queried to see if it exists in the reset record table. For example, referring to the above, the reset record table can be queried from the reset record unit.
[0079] If the function identifier of the target function included in the function layer reset request is not recorded in the reset record table, the function layer reset request is considered valid. Furthermore, this means that this function layer reset request is the first function layer reset request for the target function received by the command processing module. To facilitate the filtering of subsequent duplicate function layer reset requests for the target function and avoid repeated execution of invalid processing, the function identifier of the target function is recorded in the reset record table for subsequent lookup.
[0080] Correspondingly, if the function identifier of the target function included in the function layer reset request is recorded in the reset record table, then the function layer reset request is determined to be invalid. This means that the function layer reset request for the target function is being responded to or has already been completed, and there is no need to respond again.
[0081] It is understandable that if invalidation is performed on multiple target functions, multiple function layer reset requests may be received, and each function layer reset request contains the function identifier of the corresponding target function. In this case, each function identifier is recorded in the reset record table.
[0082] Step 304: If the functional layer reset request is determined to be valid, a drain request is generated.
[0083] This avoids performing repeated emptying and invalidation processes, ensuring the reliability of invalidation processing.
[0084] In an optional embodiment of this application, the state machine maintenance state machine is initially in the idle state (IDLE). When a functional layer reset request is determined to be valid and a drain request is generated, the state machine switches to the state of sending a drain request. The drain module instructs the command processing module to generate an invalid processing request containing the functional identifier of the target function, and the state machine switches back to the invalid processing state. When the invalid processing is completed, the state machine switches to the FLR completion state. After reporting the result of the invalid processing completion to the upper layer, the state machine switches back to the idle state.
[0085] This uses a state machine to ensure the correct sequence of states in the command processing module and to maintain a stable and reliable invalidation process.
[0086] In one embodiment, the command processing module is further configured to: after generating the drain request, if other access requests containing the function identifier of the target function are received, then intercept other access requests.
[0087] Other access requests can be read requests, write requests, etc. It's understandable that once a drain request is generated, the invalidation process begins, and subsequent access requests are meaningless and can be intercepted.
[0088] Optionally, the above-mentioned request receiving unit performs the step of intercepting other access requests.
[0089] This avoids the cache memory from processing meaningless access requests, reducing the cache memory's power consumption and computing power usage.
[0090] The venting process is explained below.
[0091] In one embodiment, such as Figure 4 A flowchart illustrating the process of handling missed access requests using a drain module is shown. Before receiving the drain response data corresponding to the drain request, the drain module also performs the following steps:
[0092] Step 401: For each cache line in the cache memory, maintain the cache miss request queue corresponding to the cache line.
[0093] Optionally, for each cache line, maintain a queue of missed requests corresponding to that cache line. Alternatively, maintain a queue of missed requests for each cache line that contains missed requests.
[0094] Step 402: The missed request queue includes multiple missed access requests that missed cache lines.
[0095] Taking multiple missed access requests as an example, when the cache line is empty, any request accessing that cache line is a missed request. When the first missed access request occurs, it is sent to an external host for access. The external host responds to the first missed access request by returning corresponding response data, which is then written to the cache line. While the first missed access request is being sent to the external host and awaiting the response data, subsequent missed requests accessing the same cache line are written to a missed request queue. Thus, when the response data is returned, the missed requests in the queue can access the corresponding data from the cache line.
[0096] Step 403: Based on the storage status of the cache line and the function to which each missed access request belongs, determine whether to respond to each missed access request in the missed request queue.
[0097] The storage status of cache lines is used to indicate whether a cache line has been invalidated.
[0098] A missed access request could be a read request, a write request, or an invalid request used to invalidate the cache line.
[0099] In this embodiment, if a missed request is an invalid request, the corresponding cache line is invalidated. For example, while waiting for response data to return, if the next request in the queue is invalid, since no data needs to be read, the invalid request is responded to directly, and the cache line is invalidated. However, for other missed requests after the invalid request, if these are not invalid requests but normal access requests such as read or write requests, it is necessary to determine whether to respond to each missed access request in the missed request queue based on the storage state of the cache line and the function to which the missed access request belongs.
[0100] If the storage status of the cache line indicates that the cache line has been invalidated, and the function to which the missed access request belongs is the aforementioned target function, since the cache line corresponding to the target function should be invalidated, it means that the missed request does not need to be responded to, and the missed access request can be directly ignored.
[0101] Furthermore, for the target cache line, since the drain request is also sent to the off-chip host, if the drain request is after the first missed access request, when the response data of the first missed access request is returned, if other missed access requests in the missed request queue of the target cache line are responded to normally, and if the drain response data is returned during the process of responding to other missed access requests in the missed request queue of the target cache line, then after the drain module instructs the command processing module to generate an invalid processing request containing the function identifier of the target function, there are still missed access requests being responded to. At this time, the drain request is not the last request for the target function, the drain processing is invalid, and the normal progress of invalid processing is affected.
[0102] Therefore, in this embodiment, based on the storage status of the cache line and the function to which each missed access request belongs, it is determined whether to respond to each missed access request in the missed request queue, thereby ensuring that the emptied request is the last request corresponding to the target function. Invalidation processing is then performed based on this, ensuring the effectiveness and reliability of the invalidation process.
[0103] Optionally, for all cache lines, determine whether to respond to each missed access request in the missed request queue based on the storage status of the cache line and the function to which each access request belongs.
[0104] Alternatively, for the target cache line only, determine whether to respond to each missed access request in the missed request queue based on the storage state of the cache line and the function to which each access request belongs.
[0105] In one embodiment, the emptying module is specifically used to: when the storage status of a cache line is that the cache line has been invalidated, for each missed access request, determine whether the function identifier included in the missed access request is recorded in the reset record table.
[0106] It is understandable that, before the response function layer performs invalidation processing on the reset request, while waiting for the drain response data to return, the cache line may be invalidated by an invalid request.
[0107] Each missed access request includes a function identifier. Parse the function identifier in each missed access request, query the reset record table, and determine whether the function identifier included in the missed access request is recorded in the reset record table.
[0108] The drain module is specifically used to: if the function identifier included in the missed access request is not recorded in the reset record table, then, if data from the cache line is returned from the external host, respond to the missed access request based on the data in the cache line; if the function identifier included in the missed access request is recorded in the reset record table, then do not respond to the missed access request.
[0109] If the feature identifier included in the missed access request is not recorded in the reset record table, it means that the cache line is not invalidated, and therefore the missed access request needs to be responded to normally.
[0110] Conversely, if the function identifier included in the missed access request is recorded in the reset record table, it means that the cache line is the target cache line and needs to be invalidated after waiting for the empty packet to return. Therefore, the corresponding missed access request will not be responded to. Optionally, if the missed access request is not responded to, error data is generated and returned to the upper layer.
[0111] In this way, based on the use of memory storage for tags, the batch clearing of resources for the corresponding target cache line can be completed by responding to FLR requests through request emptying and invalidation handling mechanisms based on Function ID. The invalidation handling of each function can be performed independently, improving the flexibility of invalidation handling. Through a two-step table lookup mechanism of initial request filtering and missed request filtering, it is ensured that during the FLR request response, there are no residual access requests under the same Function and no request returns are missed.
[0112] The process of handling invalidation is explained below.
[0113] In one embodiment, the invalid module is specifically used to: for each cache line, match the function identifier with the tag value of the cache line; if the tag value of the cache line includes the function identifier, then determine that the tag value of the cache line matches the function identifier successfully; and take the successfully matched cache line as the target cache line.
[0114] That is, read the tag values of all cache lines in the cache memory, and match the function identifier with the tag values of each cache line.
[0115] Optionally, the function identifier can be matched with the tag value of the cache line one by one, or the function identifier can be matched with the tag value of multiple cache lines in parallel.
[0116] In one embodiment, the invalid module is specifically used to: determine the first cache line in the cache group indicated by the cache group number to be scanned; match the function identifier with the tag value of each first cache line; and take the first cache line that matches successfully as the target cache line.
[0117] In addition to the function identifier, the invalid processing request also includes the cache group number to be scanned.
[0118] Optionally, the cache group number to be scanned includes the cache group numbers of some cache groups that need to be scanned. Alternatively, the cache group number to be scanned includes the cache group numbers of all cache groups. Accordingly, the first cache line is either a cache line from some cache groups or all cache lines.
[0119] In this way, by scanning the label values of all cache lines, we can ensure that all target cache lines are filtered out and invalidated.
[0120] In an optional embodiment of this application, the invalidation processing time can be flexibly configured. During the invalidation processing cycle, each target cache line is scanned and invalidated. During non-invalidation processing cycles, the cache memory responds to access requests from other functions. When the next invalidation processing cycle arrives, the remaining target cache lines are scanned and invalidated.
[0121] This allows for high parallelism in FLR processing, supports configurable scan times, and enables adjustment of the conflict rate between normal access requests and FLR processing. During FLR request processing, the normal request processing flow is not interfered with, and invalid request processing fully utilizes the gaps in normal request processing, reducing the impact of FLR processing on normal performance.
[0122] In one embodiment, the invalidation module is further configured to send a completion signal to the command processing module after invalidating the target cache line.
[0123] Optionally, when the command processing module receives a completion signal, the state machine switches to the FLR completion state.
[0124] In one embodiment, the command processing module is further configured to return a reset response signal to the upper layer upon receiving a completion signal; wherein the reset response signal is used to indicate the end of invalidation processing. This allows the upper layer to clearly understand the progress of invalidation processing for the target function based on the reset response signal, and by returning the reset response signal, the upper layer can avoid repeatedly sending functional layer reset requests for the target function.
[0125] For ease of understanding, based on Figure 2 The cache memory shown below is illustrated with a complete embodiment to demonstrate the process of the cache memory handling FLR requests. This cache memory can perform batch matching and batch invalidation of cache lines by Function ID in an FLR scenario.
[0126] Overall, 1. The command processing module is responsible for FLR request parsing, state machine control, empty packet generation, and exception request interception. Upon receiving a request, the cache parses the command. If it's determined to be an FLR request and not in the FLR ID Table, it indicates a new FLR request. An entry for the Function ID is created in the FLR ID Table. If a subsequent request with the same Function ID is received, an error response is returned. When a new FLR request is parsed, the corresponding empty request for that Function is inserted. After processing any remaining misses for that Function, an invalidation request (Cache Scan) is generated. After the invalidation module (Tag_Ctrl) scans all cache groups and performs invalidation, the command processing module generates an FLR response and returns it upstream, and the state machine transitions to the idle state. 2. The invalidation module (Tag_Ctrl), compared to a general cache, adds an FLR Scan function to its normal tag information storage, Hit / Miss judgment, and replacement functions. Upon receiving an invalidation request, based on the cache group number and Function ID to be scanned contained in the invalidation request, the tag values of all ways within each cache group are read, the Function IDs are compared in parallel, and the cache lines corresponding to the successfully matching ways are invalidated. 3. The Miss_Table_Array module is used to handle miss requests. In the FLR process, after receiving an FLR request, it is necessary to return data from requests preceding the Function and block subsequent requests. The Miss_Table_Array module uses a miss packet mechanism to ensure that all Miss requests preceding the Function are processed, response data is returned in Cacheline order, and the FLR state machine then transitions to the invalidation state.
[0127] Please refer to Figure 5 The diagram shows a schematic of the FLR process performed by the cache memory.
[0128] The FLR request processing flow is as follows:
[0129] 1) When the cache receives a request, it first parses the command. If it's parsed as an FLR request and not in the FLR ID Table, it indicates a new FLR request. Upon receiving an FLR request, the cache stores the corresponding Function ID in the FLR ID Table for request interception and merging. Furthermore, if the cache receives a non-FLR request but it's in the FLR ID Table, it indicates a residual request from the requesting party. The cache intercepts this request, returns data, and marks it as an error, ensuring all requests receive a response. If it's an FLR request and it's in the FLR ID Table, it means the FLR request is already being processed; the request can be merged without needing a duplicate response.
[0130] 2) Generate a special zero-length host read request, i.e., a drain request, and insert the drain request into the cache entry.
[0131] 3) The empty request goes through all the request processing paths of the cache and finally sends a read request to the off-chip host, waiting for the empty response data to be returned.
[0132] 4) While waiting for the drain response data to return, if the Miss_Entry state machine returns to the "initiate off-chip read request state" when processing Miss Entry, it means that the cache line corresponding to the current Entry was invalidated by an invalid request. In this case, it is necessary to check whether the Function ID included in the missed request in the Entry is in the FLR ID Table. If it is, the missed request is not initiated, thus ensuring that the drain request is the last off-chip access request corresponding to this Function.
[0133] 5) When the empty response data is returned, it means that the request corresponding to the Function on the Host access request path has been processed.
[0134] 6) Generate an invalidation request and insert it into the request pipeline. During the response to this invalidation request, scan each cache line in the Tag memory cache group line by line. If the FunctionID in the Tag of a line matches the Function ID in the invalidation request, then invalidate that cache line.
[0135] 7) Once the line-by-line scan is complete, it means that the cache resources corresponding to the Function ID have been cleared, and a completion flag is returned.
[0136] The aforementioned high-speed cache effectively solves the problem that general-purpose caches cannot perform batch invalidation processing on partial domains within a tag. Moreover, it incurs minimal resource costs, requiring only the addition of related control logic and minimal storage resources. Compared to the TCAM implementation, the tag storage area is reduced by 70%, enabling large-scale calls in practical applications. Furthermore, it provides a robust protection mechanism, resulting in high robustness; FLR exception handling converges at the cache entry point, requiring only the requesting side to send the corresponding FLR request, reducing system design complexity. In addition to FLR processing, it can also be applied to applications such as Q destruction in network interface cards (NICs), making it scalable and versatile. It also supports multiple functions performing FLR processing in parallel, achieving high parallelism.
[0137] In one embodiment, such as Figure 6 As shown, a cache reset method is provided, which is applied to a cache memory as described in any of the above embodiments; the method includes:
[0138] Step 601: Upon receiving a functional layer reset request for the target function, generate a drain request.
[0139] Step 602: Send the drain request as the last off-chip access request corresponding to the target function to the off-chip host.
[0140] Step 603: Upon receiving the drain response data corresponding to the drain request, determine the target cache line corresponding to the target function from each cache line based on the function identifier of the target function and the tag value of each cache line in the cache memory, and invalidate the target cache line.
[0141] The solution provided by this method is similar to the solution described in the above-mentioned cache memory embodiments. Therefore, the specific limitations of one or more method embodiments can be found in the above-mentioned limitations of the cache memory, and will not be repeated here.
[0142] In one embodiment, a computer system is provided that includes a cache memory as described in any of the above embodiments.
[0143] The cache memory is used to generate a drain request when a function layer reset request for a target function is received; send the drain request as the last off-chip access request corresponding to the target function to the off-chip host; and when the drain response data corresponding to the drain request is received, determine the target cache line corresponding to the target function from each cache line according to the function identifier of the target function and the tag value of each cache line in the cache memory, and invalidate the target cache line.
[0144] Understandably, the central processing unit of this computer system is used to send a function layer reset request for the target function to the cache memory.
[0145] The solution provided by this computer system is similar to the solution described in the above-described cache memory embodiment. Therefore, the specific limitations of the one or more system embodiments provided can be found in the above-described limitations of the cache memory, and will not be repeated here.
[0146] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.
[0147] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.
[0148] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0149] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A cache memory, characterized by The cache memory comprises: a command processing module, configured to generate an evacuation request in a case where a function layer reset request for a target function is received; and send the evacuation request as a last off-chip access request of the target function to an off-chip host; an evacuation module, configured to instruct the command processing module to generate an invalidation processing request containing a function identifier of the target function in a case where evacuation response data corresponding to the evacuation request is received; an invalidation module, configured to receive the invalidation processing request sent by the command processing module, and in response to the invalidation processing request, determine a target cache line corresponding to the target function from each cache line in the cache memory according to the function identifier and a tag value of each cache line, and perform invalidation processing on the target cache line.
2. The cache memory of claim 1, wherein, The invalidation module is specifically configured to: for each cache line, perform matching processing on the function identifier and the tag value of the cache line, and if the function identifier is included in the tag value of the cache line, it is determined that the matching of the tag value of the cache line and the function identifier is successful; and the cache line with successful matching is taken as the target cache line.
3. The cache memory of claim 2, wherein, The invalidation processing request further comprises a to-be-scanned cache group number; and the invalidation module is specifically configured to: determine a first cache line in a cache group indicated by the to-be-scanned cache group number; perform matching processing on the function identifier and a tag value of each first cache line; and the first cache line with successful matching is taken as the target cache line.
4. The cache memory according to any one of claims 1 to 3, wherein, The command processing module is specifically configured to: receive an initial request; determine whether the initial request is a function layer reset request; in a case where it is determined that the initial request is a function layer reset request, determine whether the function layer reset request is valid; if it is determined that the function layer reset request is valid, generate the evacuation request.
5. The cache memory of claim 4, wherein, The command processing module is specifically configured to: determine whether a function identifier of the target function included in the function layer reset request is recorded in a reset record table; if not, it is determined that the function layer reset request is valid, and the function identifier of the target function is recorded in the reset record table; if yes, it is determined that the function layer reset request is invalid.
6. The cache memory of claim 5, wherein, Before receiving evacuation response data corresponding to the evacuation request, the evacuation module is further configured to: for each cache line in the cache memory, maintain a miss request queue corresponding to the cache line; the miss request queue comprises a plurality of miss access requests that miss the cache line; determine whether to respond to each miss access request in the miss request queue according to a storage state of the cache line and a function to which each miss access request belongs; wherein the storage state of the cache line is used to indicate whether the cache line is invalidated.
7. The cache memory of claim 6, wherein, The evacuation module is specifically configured to: in a case where the storage state of the cache line is that the cache line is invalidated, for each miss access request, determine whether a function identifier included in the miss access request is recorded in the reset record table; if the function identifier included in the miss access request is not recorded in the reset record table, responding to the miss access request based on data of the cache line in case that data of the cache line is returned from an off-chip host; if the function identifier included in the miss access request is recorded in the reset record table, not responding to the miss access request.
8. The cache memory of claim 7, wherein, The emptying module is further configured to: in case that the miss request is an invalid request, invalidating the corresponding cache line.
9. The cache memory according to any one of claims 1 to 3, wherein, The command processing module is further configured to: after the emptying request is generated, if another access request containing the function identifier of the target function is received, intercepting the another access request.
10. The cache memory according to any one of claims 1 to 3, wherein the invalidation module is further configured to send a completion signal to the command processing module after invalidating the target cache line is completed; the command processing module is further configured to return a reset response signal to an upper layer in case that the completion signal is received; wherein the reset response signal is used to indicate that the invalidation is completed.
11. A method of cache reset, comprising: The method is applied to the cache memory according to any one of claims 1 to 10; the method comprises: generating an emptying request in case that a function layer reset request for a target function is received; sending the emptying request as the last off-chip access request corresponding to the target function to an off-chip host; in case that emptying response data corresponding to the emptying request is received, determining a target cache line corresponding to the target function from each cache line according to a function identifier of the target function and a tag value of each cache line in the cache memory, and invalidating the target cache line.
12. A computer system, characterized by The computer system comprises the cache memory according to any one of claims 1 to 10.