A configuration circuit for a network-on-chip mounted IP edgeband signal communication

Abstract

The application discloses a kind of sideband signal communication configuration circuit for on-chip network mounting IP, belong to chip design field, comprising: low-speed protocol communication configuration interface module, AXB sideband communication interface module, on-chip network module.First, the request of reading and writing sideband signal register based on low-speed protocol of external equipment is received, protocol is converted into the request package of on-chip network form, is sent to each routing node by on-chip network module, then utilizes protocol decoding bypass mainband communication interface, enters the AXB sideband communication interface module of current node, connects the configuration bus of IP, controls the reading and writing request of IP sideband signal register, then when reading and writing request succeeds, original road returns reading and writing response to external equipment.The application can effectively improve the wiring congestion of large scale on-chip network, timing bottleneck, increase the bandwidth of data path and configuration path, reduce kernel address occupation, while also beneficial to the rapid expansion integration of on-chip network.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a sideband signal communication configuration circuit for on-chip network-attached IP. Background Technology

[0002] Since the advent of the post-Moore's Law era, in order to meet the ever-increasing computing demands of applications such as artificial intelligence and high-performance computing, the traditional approach of increasing the integration density of individual chips has led to a sharp increase in chip manufacturing costs. Furthermore, with the shrinking of process dimensions, the cost and development cycle of developing monolithic application-specific integrated circuits (ASICs) have become extremely high. Under these circumstances, building an integrated, high-performance network to achieve efficient communication between multiple functional units and multiple chips is also particularly important.

[0003] Over the past 20 years, Network on Chip (NoC) technology has undergone extensive research and significant development, especially in building large and complex systems, where NoC has become an indispensable system component, replacing traditional bus-based interconnect structures. NoC typically serves as a high-bandwidth data path for high-bandwidth data stream transmission with various mounted IPs. The numerous sideband registers of the IPs are configured using a single processor core and debugged online via an external host. However, this approach introduces several problems. As NoCs grow larger and the number of IPs increases, interconnections between the NoC, processor core, and various IPs become congested, significantly impacting bandwidth and timing optimization of data and configuration paths. Furthermore, each IP integration and expansion of the Network on Chip requires the core processor to reallocate base addresses, causing considerable inconvenience for designers. Summary of the Invention

[0004] The purpose of this invention is to provide a sideband signal communication configuration circuit for on-chip network-mounted IP, so as to solve the problems in the background art.

[0005] To address the aforementioned technical problems, this invention provides a sideband signal communication configuration circuit for on-chip network-mounted IP, comprising three parts:

[0006] The first part is a low-speed protocol communication configuration interface module, the second part is an AXB sideband communication interface module, and the third part is an on-chip network module; the low-speed protocol communication configuration interface module, the on-chip network module, and the AXB sideband communication interface module are connected in sequence.

[0007] The low-speed protocol communication configuration interface module receives the sideband signal read / write register request from the external device based on the low-speed protocol, then converts it into a request packet in the form of on-chip network protocol, sends the protocol packet to each routing node through the on-chip network module, and then uses protocol decoding to bypass the main band communication interface module to enter the AXB sideband communication interface module of the current node, connects to the IP configuration bus, and controls the read / write request of the IP sideband signal register.

[0008] When a read or write request to the IP sideband signal register is successful, the write or read response is returned to the current node of the on-chip network module through the AXB sideband communication interface module, and then routed to the corresponding low-speed protocol communication configuration interface module through the on-chip network protocol to notify the external device of the write or read response result.

[0009] The low-speed protocol communication configuration interface module includes a low-speed protocol interface module, a parsing and synchronization module, and an on-chip protocol conversion module, which are connected in sequence. The parsing and synchronization module decodes and analyzes the low-speed protocol data stream, realizes cross-clock synchronization, and adapts the frame length of the data stream. The on-chip protocol conversion module is responsible for converting the on-chip network protocol and the parsed read / write data stream. The internal structure of the on-chip protocol conversion module is a state machine for generating and unpacking on-chip network protocol packets.

[0010] The AXB sideband communication interface module includes an AXB interface module, a synchronization module, and an on-chip protocol conversion module, and the AXB interface module, the synchronization module, and the on-chip protocol conversion module are connected in sequence. The on-chip protocol conversion module is responsible for converting the on-chip protocol and the AXB protocol data stream before synchronization. The synchronization module includes cross-clock synchronization function.

[0011] In one implementation, the sideband signal communication configuration circuit defines the register write request data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, a DATA body microchip, and a tail microchip with a transmission type of CFG_WR_REQ.

[0012] In one implementation, the sideband signal communication configuration circuit defines the register write response data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, and a tail microchip with a transmission type of CFG_WR_RESP.

[0013] In one implementation, the sideband signal communication configuration circuit defines the register read request data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, and a tail microchip with a transmission type of CFG_RD_REQ.

[0014] In one implementation, the sideband signal communication configuration circuit defines the register read response data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, a DATA body microchip, and a tail microchip with a transmission type of CFG_RD_RESP.

[0015] In one implementation, the AXB sideband communication interface module selects to support the APB protocol and the AHB protocol as needed to complete the configuration of the IP's sideband signal registers.

[0016] The present invention also provides a sideband signal communication configuration system for on-chip network-mounted IP, including the above-described sideband signal communication configuration circuit for on-chip network-mounted IP and its application method.

[0017] This invention provides a sideband signal communication configuration circuit for IPs mounted on a network-on-chip (NOC). Using an external host, it performs sideband signal register read / write configuration on commonly available IPs mounted on the NOC via low-speed protocols (SPI, UART, I2C). This avoids wire-wound congestion when NoC, processor core, and various IPs are interconnected, improves timing bottlenecks in data and configuration paths, and increases the bandwidth of system data and configuration paths. At the same time, the integration and expansion of NOC IPs no longer requires the core processor to reallocate base addresses, which is beneficial for designers to expand and integrate NOC systems. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the sideband signal communication configuration circuit for on-chip network-mounted IP provided by the present invention.

[0019] Figure 2 This is a schematic diagram of a traditional on-chip network with IP sideband signal communication configuration circuit.

[0020] Figure 3 This is a schematic diagram of the low-speed protocol communication configuration interface module.

[0021] Figure 4 This is a schematic diagram of the AXB sideband communication interface module.

[0022] Figure 5(a) is a schematic diagram of an implementation example of the register write request data transmission format of the on-chip network of the present invention.

[0023] Figure 5(b) is a schematic diagram of an implementation example of the register write response data transmission format of the on-chip network of the present invention.

[0024] Figure 6(a) is a schematic diagram of an implementation example of the register read request data transmission format of the on-chip network of the present invention.

[0025] Figure 6(b) is a schematic diagram of an implementation example of the register read response data transmission format of the on-chip network of the present invention.

[0026] Figures 7(a) and 7(b) are specific examples of an application method of the SRIO IP communication configuration system for on-chip network and SPI protocol according to the present invention. Detailed Implementation

[0027] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a sideband signal communication configuration circuit for on-chip network-mounted IP. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] This invention provides a sideband signal communication configuration circuit for on-chip network-mounted IP, such as... Figure 1 As shown, the circuit comprises three parts: a low-speed protocol communication configuration interface module, an AXB sideband communication interface module, and an on-chip network module (NoC). These three modules are connected sequentially. The external device is a host device supporting low-speed protocols (SPI, UART, or I2C). The AXB sideband communication interface module configures the relevant sideband registers for the IP address attached to the current node. The same node also includes a mainband communication interface module; the location of the AXB sideband communication interface module is shown in the diagram to highlight its position and will not be described in detail. Additionally, as... Figure 2 The diagram shows a traditional on-chip network (NoC) IP sideband signal communication configuration circuit. It can be seen that the main data path for each IP is initiated by the host on the on-chip network, and an additional global processor is added to configure the sideband signal registers. When the scale of the NoC and IP expands in two dimensions, congestion will occur in both the main data path and the sideband configuration path, which is also detrimental to the rapid expansion of the entire on-chip network SoC system.

[0029] like Figure 3 As shown, the low-speed protocol communication configuration interface module, the low-speed protocol interface module, the parsing and synchronization module, and the on-chip protocol conversion module are connected in sequence. The parsing and synchronization module decodes and analyzes the low-speed protocol data stream, realizes cross-clock synchronization, and adapts the frame length of the data stream. The on-chip protocol conversion module is mainly responsible for the conversion between the on-chip network protocol and the parsed read / write data stream. The internal structure of the on-chip protocol conversion module is a state machine for generating and unpacking on-chip network protocol packets.

[0030] like Figure 4As shown, the AXB sideband communication interface module consists of an AXB interface module, a synchronization module, and an on-chip protocol conversion module connected in sequence. The on-chip protocol conversion module is mainly responsible for converting the on-chip protocol and the AXB protocol data stream before synchronization. The synchronization module is used to include cross-clock synchronization function. The AXB sideband communication interface module selects to support either the APB protocol or the AHB protocol according to the specific IP situation to complete the configuration of the IP's sideband signal registers.

[0031] To support protocols for on-chip networks, as shown in Figure 5(a), this invention defines a register write request data transmission format for on-chip networks, which includes a header micro-chip of transmission type CFG_WR_REQ (154b-148b is the header micro-chip identifier, 147b-145b is the virtual channel ID, 144b-121b is the real-time route ID, 49b-40b is the RG write request event, 39b-27b is the on-chip network ID, 26b-0b is the destination route ID, and the rest are reserved bits), and a LEN body micro-chip (154b-148b...). The following are the length micro-identifiers: 147b-145b is the virtual channel ID, 26b-0b is the length identifier (set to 1, transmits 2 words, the rest are reserved); ADDR body micro-identifier (154b-148b is the address micro-identifier, 147b-145b is the virtual channel ID, 39b-27b is the source address, 26b-0b is the destination address, the rest are reserved); DATA body micro-identifier (154b-148b is the data micro-identifier, 147b-145b is the virtual channel ID, 39b-0b is the data bits, the rest are reserved); and tail micro-identifier (1...). Bits 54b-148b are the tail chip identifier, bits 147b-145b are the virtual channel ID, and the rest are reserved. As shown in Figure 5(b), the register write response data transmission format of the on-chip network is defined, which includes a header chip of transmission type CFG_WR_RESP (bits 154b-148b are the header chip identifier, bits 147b-145b are the virtual channel ID, bits 144b-121b are the real-time route ID, bits 49b-40b are the RG write response event, bits 39b-27b are the on-chip network ID, bits 26b-0b are the destination route ID, and the remaining bits are reserved). The remaining bits are reserved. The LEN body chip (154b-148b is the length chip identifier, 147b-145b is the virtual channel ID, 26b-0b is the length identifier, set to 1 to transmit 2 words, the rest are reserved), the ADDR body chip (154b-148b is the address chip identifier, 147b-145b is the virtual channel ID, 39b-27b is the source address, 26b-0b is the destination address, the rest are reserved), and the tail chip (154b-148b is the tail chip identifier, 147b-145b is the virtual channel ID, the rest are reserved).

[0032] As shown in Figure 6(a), this invention defines the register read request data transmission format for on-chip networks, which includes a header micro-fragment of transmission type CFG_RD_REQ (154b-148b is the header micro-fragment identifier, 147b-145b is the virtual channel ID, 144b-121b is the real-time route ID, 49b-40b is the RG read request event, 39b-27b is the on-chip network ID, 26b-0b is the destination route ID, and the rest are reserved bits), and a LEN body micro-fragment (154b-148b is the length micro-fragment identifier, 147b-145b is the virtual channel ID). The on-chip network register read response data transmission format is also defined as follows: ID (26b-0b is the length identifier, set to 1, transmits 2 words, the rest are reserved); ADDR body microchip (154b-148b is the address microchip identifier, 147b-145b is the virtual channel ID, 39b-27b is the source address, 26b-0b is the destination address, the rest are reserved); and tail microchip (154b-148b is the tail microchip identifier, 147b-145b is the virtual channel ID, the rest are reserved). As shown in Figure 6(b), the on-chip network register read response data transmission format is also defined, which includes a transmission type of CFG_RD_RESP. The header microchip (154b-148b is the header microchip identifier, 147b-145b is the virtual channel ID, 144b-121b is the real-time route ID, 49b-40b is the RG read response event, 39b-27b is the on-chip network ID, 26b-0b is the destination route ID, and the rest are reserved), the LEN body microchip (154b-148b is the length microchip identifier, 147b-145b is the virtual channel ID, 26b-0b is the length identifier, set to 1, transmits 2 words, and the rest are reserved), and the ADDR body microchip (154b-148b is the address microchip). The data body consists of a data micro-part identifier (147b-145b is the virtual channel ID, 39b-27b is the source address, 26b-0b is the destination address, and the rest are reserved bits) and a tail micro-part identifier (154b-148b is the tail micro-part identifier, 147b-145b is the virtual channel ID, and the rest are reserved bits), and a DATA body micro-part identifier (154b-148b is the data micro-part identifier, 147b-145b is the virtual channel ID, 39b-0b is the data bits, and the rest are reserved bits) and a tail micro-part identifier (154b-148b is the tail micro-part identifier, 147b-145b is the virtual channel ID, and the rest are reserved bits).

[0033] As shown in Figure 7(a), the application method of the SRIO IP communication configuration system for on-chip network and SPI protocol is as follows: the low-speed protocol communication configuration interface module receives read / write registers from external devices based on the SPI protocol. The SPI data stream is defined as a write command for the sideband signal communication configuration circuit of the IP mounted on the on-chip network, and the data stream BBBB is a read command. The protocol is converted into a read request packet in the form of on-chip protocol. The protocol packet is sent to each routing node through the on-chip network, and then connected to the configuration bus of SRIO IP through the APB interface module to control the read / write requests of the SRIO IP sideband signal registers. As shown in Figure 7(b), when the read / write request of the SRIO IP sideband signal register is successful, the write response or read response will be returned to the current node of the on-chip network through the APB interface module, and then routed to the corresponding low-speed protocol communication configuration interface module through the on-chip protocol to notify the external device of the write response or read data result.

[0034] This invention designs a low-speed protocol communication configuration interface module and an AXB sideband communication interface module for on-chip networks. By using a low-speed protocol, it performs sideband signal register read and write configuration on commonly available IPs mounted on the on-chip network, avoiding the large amount of wired congestion that occurs when traditional on-chip networks, processor cores, and various IPs are interconnected. This can greatly optimize the timing bottlenecks of the main band data path and the sideband configuration path. At the same time, the IP integration and expansion of the on-chip network no longer requires the reallocation of base addresses, which is beneficial for designers to expand and integrate on-chip network systems.

[0035] In addition, some steps in the embodiments of the present invention are implemented using software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0036] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A sideband signal communication configuration circuit for on-chip network-mounted IP, characterized in that, It consists of three parts: The first part is a low-speed protocol communication configuration interface module, the second part is an AXB sideband communication interface module, and the third part is an on-chip network module; the low-speed protocol communication configuration interface module, the on-chip network module, and the AXB sideband communication interface module are connected in sequence. The low-speed protocol communication configuration interface module receives the sideband signal read / write register request from the external device based on the low-speed protocol, then converts it into a request packet in the form of an on-chip network protocol, sends the protocol packet to each routing node through the on-chip network module, and then uses protocol decoding to bypass the main band communication interface, selects the AXB sideband communication interface module to enter the current node, and connects to the IP configuration bus to control the read / write request of the IP sideband signal register. When the read or write request of the IP sideband signal register is successful, the write response or read response is returned to the current node of the on-chip network module through the AXB sideband communication interface module, and then routed to the corresponding low-speed protocol communication configuration interface module through the on-chip network protocol to notify the external device of the write response or read response result. The low-speed protocol communication configuration interface module includes a low-speed protocol interface module, a parsing and synchronization module, and an on-chip protocol conversion module, which are sequentially connected. The parsing and synchronization module decodes and analyzes the low-speed protocol data stream, achieves cross-clock synchronization, and adapts the frame length of the data stream. The on-chip protocol conversion module is responsible for converting the on-chip network protocol with the parsed read / write data stream. The internal structure of the on-chip protocol conversion module is a state machine for generating and unpacking on-chip network protocol packets. The AXB sideband communication interface module includes an AXB interface module, a synchronization module, and an on-chip protocol conversion module, and the AXB interface module, the synchronization module, and the on-chip protocol conversion module are connected in sequence. The on-chip protocol conversion module is responsible for converting the on-chip protocol and the AXB protocol data stream before synchronization. The synchronization module includes cross-clock synchronization function.

2. The sideband signal communication configuration circuit for on-chip network-mounted IP as described in claim 1, characterized in that, The sideband signal communication configuration circuit defines the register write request data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, a DATA body microchip, and a tail microchip with a transmission type of CFG_WR_REQ.

3. The sideband signal communication configuration circuit for on-chip network-mounted IP as described in claim 1, characterized in that, The sideband signal communication configuration circuit defines the register write response data transmission format of the on-chip network, which includes a header microchip, a LEN body microchip, an ADDR body microchip, and a tail microchip with a transmission type of CFG_WR_RESP.

4. The sideband signal communication configuration circuit for on-chip network-mounted IP as described in claim 1, characterized in that, The sideband signal communication configuration circuit defines the register read request data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, and a tail microchip with a transmission type of CFG_RD_REQ.

5. The sideband signal communication configuration circuit for on-chip network-mounted IP as described in claim 1, characterized in that, The sideband signal communication configuration circuit defines the register read response data transmission format of the on-chip network, including a header microchip, a LEN body microchip, an ADDR body microchip, a DATA body microchip, and a tail microchip with a transmission type of CFG_RD_RESP.

6. The sideband signal communication configuration circuit for on-chip network-mounted IP as described in claim 1, characterized in that, The low-speed protocol communication configuration interface module selects to support SPI, UART, or I2C protocols depending on the specific circumstances to complete the host adaptation.

7. The sideband signal communication configuration circuit for on-chip network-mounted IP as described in claim 1, characterized in that, The AXB sideband communication interface module selects to support either the APB protocol or the AHB protocol depending on the specific circumstances to complete the IP configuration.

8. A sideband signal communication configuration system for IP mounted on an on-chip network, characterized in that, Includes the sideband signal communication configuration circuit and its application method for attaching IP to an on-chip network as described in any one of claims 1-7.

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