FPGA logic comprehensive netlist optimization method based on Bayesian optimization and attention mechanism

Abstract

The invention discloses an FPGA logic comprehensive netlist optimization method based on Bayesian optimization and an attention mechanism, and the method comprises the steps: converting an original netlist of a to-be-optimized circuit into a graph structure, and carrying out the optimization; performing SAT check on the optimized AIG structure, and if the output function of the main output end is consistent with the function of the initial netlist, returning to the AIG structure after execution of the optimization command; mapping the optimized AIG structure to the LUT of the FPGA for evaluation, and judging whether the requirements are met or not; calculating and predicting a sequence-result space formed by different command combination sequences by using an improved Gaussian process regression model; calculating and selecting a next command sequence with the most potential according to an adaptive sampling function; and training until performance requirements are met. The method is low in cost loss and high in search efficiency.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design automation technology, and in particular relates to an FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanism. Background Technology

[0002] In the field of automated digital integrated circuit design, logic synthesis is an essential step. It is the means of converting high-level Hardware Description Language (HDL) code into gate-level or lower-level logic netlists, thus realizing the concrete functionality of the circuit. The difference between Field-Programmable Gate Array (FPGA) logic synthesis and Application-Specific Integrated Circuit (ASIC) logic synthesis lies in the fact that, when process-related mappings are involved, FPGA logic synthesis can map the netlist-converted graph into the FPGA's internal Look-Up Table (LUT), and then evaluate the FPGA's area, delay, and power consumption.

[0003] Logic synthesis netlist optimization aims to achieve precise logical equivalence transformations in the design process, ensuring that the optimized circuit is functionally identical to the original design. The methods used are generally based on traditional heuristic algorithms such as genetics and decision trees.

[0004] However, using these prior-free search methods to traverse circuit nodes one by one can easily lead to problems such as a huge search space and severe cost loss, resulting in low search efficiency. Summary of the Invention

[0005] The purpose of this invention is to solve the problems of huge search space and serious cost loss that easily occur when the prior-free search method proposed in the background traverses circuit nodes one by one.

[0006] This application provides an FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanism, the method including:

[0007] Step 1: Convert the original netlist of the circuit to be optimized into a graph structure and perform windowing, cut enumeration, and checks for irrelevant sets and external irrelevant sets;

[0008] Step 2: Perform Boolean rewriting, Boolean reconstruction, Boolean reorganization, and Boolean balancing operations on the netlist of the And-Inverter Graph (AIG) structure circuit after windowing and cutting enumeration;

[0009] Step 3: Perform a Satisfaction Checking (SAT) on the optimized AIG structure. If the output function of the main output terminal is consistent with the function of the initial netlist, return the AIG structure after the optimization command is executed.

[0010] Step 4: Map the optimized AIG structure to the FPGA LUT for area, delay, and power consumption evaluation to determine if it meets the requirements;

[0011] If the area, delay, and power consumption meet the preset requirements, the optimal results for area, delay, and power consumption are output. If the preset requirements are not met, the Bayesian optimization process begins.

[0012] Step 5: Input the current logic synthesis command optimization sequence and the values ​​of the mapped area, delay, power consumption and QoR output, and use the improved Gaussian process regression model to calculate and predict the sequence-result space composed of different command combination sequences;

[0013] Specifically, firstly, the discrete logic synthesis command sequence is mapped into a high-dimensional feature vector through an embedding layer. Then, a multi-head self-attention module is introduced to calculate the weight coefficients of different commands in the sequence. Through query and key similarity matching, the temporal constraints and resource mapping are quantified. The contribution of the optimized command to the output indicators, including area, delay, and power consumption, is optimized. The current logic synthesis command optimization sequence and the data and features of the mapped area, delay, power consumption, and QoR output are input. The improved Gaussian process regression model is used to calculate and predict the sequence-result space composed of different command combination sequences.

[0014] Step 6: Optimize the command sequence and QoR based on the netlist generated by the model update, and use the adaptive sampling function to calculate and select the next most promising command sequence.

[0015] The adaptive sampling function employs a phased dynamic switching strategy, triggered by the number of iterations and the improvement of the current optimal QoR: In the early stage of iteration, the Upper Confidence Bound (UCB) function is activated, prioritizing candidate sequences with high model uncertainty to achieve global exploration; in the middle stage of iteration, it switches to the Expected Improvement (EI) function, using moderate exploration parameters to calculate the expected improvement of candidate sequences relative to the current optimal solution, balancing exploration of unknown regions with utilization of known high-quality regions; in the later stage of iteration, the EI function is maintained but the exploration parameters are reduced to a low level, focusing on candidate sequences with high prediction mean and low uncertainty, and enhancing utilization through local fine-grained search to accelerate convergence to the command sequence corresponding to the global optimal QoR.

[0016] Step 7: Add the new sampling points and observations to the training dataset, retrain the improved Gaussian process regression model, and complete the sequence-result space construction for the logic synthesis command sequence.

[0017] Step 8: After the new command sequence selected in the new model is executed, a Boolean satisfiability check is performed. If it meets the requirements, it is mapped to the FPGA lookup table and the QoR of the circuit is calculated based on the area and delay.

[0018] Step 9: Iterate repeatedly, and after executing the pre-set number of rounds, output the optimal QoR, thereby outputting the optimal circuit netlist structure.

[0019] The significant advancement of this invention compared to existing technologies lies in:

[0020] This application uses the netlist to be optimized as input and employs a Bayesian optimization algorithm to evaluate the initial sequence of logic synthesis commands and their subsequent QoR to obtain initial data for the objective function. Next, an attention mechanism is used to extract and encode key features such as the position of the command sequence. Based on this encoded data, an improved Gaussian process regression model containing the predicted value and uncertainty of the objective function is constructed. The parameters of the improved Gaussian process regression model are automatically learned from observed data using maximum a posteriori estimation. Then, Bayesian optimization selects the next evaluation sequence through an adaptive sampling function, balancing the trade-off between exploration and utilization. Compared with existing traditional heuristic algorithms based on genetics and decision trees, this approach improves upon the problems of prior-free search methods that suffer from huge search space and severe cost incurment when traversing circuit nodes one by one, leading to low search efficiency.

[0021] To more clearly illustrate the functional characteristics and structural parameters of the present invention, further explanation is provided below in conjunction with the accompanying drawings and specific embodiments. Attached Figure Description

[0022] Figure 1 A framework diagram of an FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanism;

[0023] Figure 2 A diagram of the key architecture for logic synthesis based on improved Bayesian optimization;

[0024] Figure 3 The figure shows the experimental curves for FPGA logic synthesis netlist optimization based on Bayesian optimization and attention mechanism. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] Bayesian optimization is a global optimization method based on Bayes' theorem and Gaussian processes. It is primarily used to optimize objective functions that are costly, noisy, or lack a clear analytical form, thus addressing the high costs associated with the search space. Its basic principle is to construct a surrogate model to approximate the objective function and update the model using Bayes' theorem. Specifically, Bayesian optimization first randomly selects some points in the hyperparameter space for evaluation to obtain initial data for the objective function. Then, based on this data, a Gaussian process regression model is constructed. This model not only provides predictions of the objective function but also the uncertainty of those predictions. The parameters in the Gaussian process regression model are automatically learned from the observed data using maximum a posteriori estimation. Next, Bayesian optimization selects the next evaluation sequence through a sampling function, balancing the trade-off between exploration (evaluating in regions of high uncertainty) and exploitation (evaluating in regions with known high performance).

[0027] Attention mechanisms are techniques that enable models to dynamically focus on key parts when processing information. By assigning different levels of attention to different elements of the input, they efficiently capture important features and relationships. In the context of FPGA logic synthesis netlist optimization, combining attention mechanisms with Bayesian optimization allows Gaussian process regression models to learn and optimize by comparing the similarity of the input netlist sequence with the previous optimal sequence in terms of position, mean, and variance. This guides the sequence search towards the optimal direction for FPGA area, latency, and power consumption. When analyzing the logic netlist, higher attention is given to command sequences and their associated logic that are frequently called or play a decisive role in the timing path. Dynamically adjusting attention weights allows the model to prioritize exploring regions that contribute more to the quality of results (QoR) and reduce redundant computation in less important parts. Therefore, Bayesian optimization combined with attention mechanisms can more efficiently balance exploration and utilization, ensuring that the optimal command optimization sequence for the FPGA logic synthesis netlist is accurately located within a limited number of evaluations, resulting in more efficient hardware design.

[0028] By applying Bayesian optimization and attention mechanisms to the logic synthesis netlist optimization of FPGAs, and actively learning from observed data and dynamically adjusting the parameters in the model using a modified Gaussian process regression model, and performing posterior estimation based on prior knowledge, the optimal QoR for the area and delay of the FPGA circuit can be found within a finite number of iterations, thus achieving optimal logic synthesis netlist optimization for FPGAs.

[0029] Example 1:

[0030] This embodiment details the implementation process of the FPGA logic synthesis netlist optimization method based on Bayesian optimization.

[0031] Please see Figure 1 The FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanism is characterized by mainly including: logic synthesis netlist optimization sequence operation, process mapping and Bayesian optimization.

[0032] The logic synthesis netlist optimization sequence operation can receive an initial netlist file as input, convert the Boolean Language Interchange Format (BLIF) file into AIG format, and then perform windowing, segmentation enumeration, irrelevant set and external irrelevant set checks on the AIG structure of the circuit netlist. Then, according to the potential optimal command optimization sequence selected by Bayesian optimization, the netlist is subjected to logic synthesis, logic rewriting, logic reconstruction, logic replacement and logic balancing operations. If the executed structure meets the Boolean satisfiability requirement, that is, after adding test stimuli to the main input of the AIG structure, the output function of the main output is consistent with the function of the initial netlist, then the AIG structure after the optimization command is executed is returned.

[0033] The AIG structure includes main input, main output, nodes, edges, hierarchy, latches, AND gates, and NOT gates.

[0034] The optimization command actions include logical rewrite, zero-latency logical rewrite -z, logical resub, zero-latency logical resub, logical refactor, zero-latency logical refactor -z, and logical balance.

[0035] The process mapping step involves mapping the optimized AIG graph structure to the FPGA's lookup table (LUT), and then outputting information such as the mapped area, delay, and power consumption.

[0036] The Bayesian optimization process first updates the statistical model based on modified Gaussian process regression using the mapped area, delay, power consumption, and the netlist optimization command sequence. Then, it explores potential optimal optimization command sequences based on an adaptive sampling function. Finally, it returns the potential optimal optimization command sequence to the logic synthesis netlist optimization sequence operation process.

[0037] The improved Gaussian process regression statistical model is used to model the objective function. Combined with an attention mechanism kernel function, it enhances the focus on the position, mean, and variance of the network list optimization command sequence, enabling proactive learning and parameter optimization even when the objective function is unknown. The covariance matrix of the training data can be calculated based on the input historical observation data, and the posterior distribution of the new position can be derived using the properties of the Gaussian distribution. This posterior distribution not only provides a prediction of the mean of the function value at the new position but also indicates the uncertainty of the prediction.

[0038] The adaptive sampling function evaluates each possible candidate sequence, calculates its sampling function value, and then selects the candidate sequence with the largest sampling function value for sampling. Finally, the new sampled sequence and its QoR calculated in the FPGA are added to the training dataset to retrain the improved Gaussian process regression model and update the model's understanding of the objective function.

[0039] The acquisition function consists of an upper confidence bound function and an expectation boosting function. The upper confidence bound function is used for spatial exploration in the early stages of algorithm iteration, while the expectation boosting function is used for overall utilization in the later stages of algorithm iteration. The weighted combination of the two can achieve a balance between exploration and development. As the iteration progresses, the weights are gradually adjusted to reduce the impact of uncertainty, and candidate sequences with superior prediction performance and higher confidence intervals are selected first, thereby accelerating the optimization process and improving search efficiency.

[0040] After the modified Gaussian process regression and adaptive sampling function are completed, the potential optimal optimization command sequence is explored based on uncertainty, maximum expectation, etc. Finally, the potential optimal optimization command sequence is returned to the logic synthesis netlist optimization sequence operation stage.

[0041] The specific implementation steps are as follows:

[0042] Step 1: Convert the original netlist of the circuit to be optimized into a graph structure and perform windowing, cut enumeration, and checks for irrelevant sets and external irrelevant sets.

[0043] Step 2: Perform Boolean rewriting, Boolean reconstruction, Boolean reorganization, and Boolean balancing operations on the netlist of the And-Inverter Graph (AIG) structure circuit after windowing and cutting enumeration.

[0044] Step 3: Perform a Satisfiability Checking (SAT) on the optimized AIG structure. If the output function of the main output terminal is consistent with the function of the initial netlist, return the AIG structure after the optimization command is executed.

[0045] Step 4: Map the optimized AIG structure to the FPGA LUT for area, delay and power consumption evaluation to determine whether it meets the requirements.

[0046] If the area, delay, and power consumption meet the preset requirements, the optimal results for area, delay, and power consumption will be output. If the preset requirements are not met, the Bayesian optimization process will begin.

[0047] Step 5: Input the current logic synthesis command optimization sequence and the values ​​of the mapped area, delay, power consumption and QoR output, and use the improved Gaussian process regression model to calculate and predict the sequence-result space composed of different command combination sequences.

[0048] Specifically, firstly, the discrete logic synthesis command sequence is mapped into a high-dimensional feature vector through an embedding layer. Then, a multi-head self-attention module is introduced to calculate the weight coefficients of different commands in the sequence. Through query and key similarity matching, the temporal constraints and resource mapping are quantified. The contribution of the optimized command to the output indicators, including area, delay, and power consumption, is optimized. The current logic synthesis command optimization sequence and the data and features of the mapped area, delay, power consumption, and QoR output are input. The improved Gaussian process regression model is used to calculate and predict the sequence-result space composed of different command combination sequences.

[0049] Step 6: Optimize the command sequence and QoR based on the netlist generated by the model update, and use the adaptive sampling function to calculate and select the next most promising command sequence.

[0050] The adaptive sampling function employs a phased dynamic switching strategy, triggered by the number of iterations and the improvement of the current optimal QoR: In the early stage of iteration, the Upper Confidence Bound (UCB) function is activated, prioritizing candidate sequences with high model uncertainty to achieve global exploration; in the middle stage of iteration, it switches to the Expected Improvement (EI) function, using moderate exploration parameters to calculate the expected improvement of candidate sequences relative to the current optimal solution, balancing exploration of unknown regions with utilization of known high-quality regions; in the later stage of iteration, the EI function is maintained but the exploration parameters are reduced to a low level, focusing on candidate sequences with high prediction mean and low uncertainty, and enhancing utilization through local fine-grained search to accelerate convergence to the command sequence corresponding to the global optimal QoR.

[0051] Step 7: Add the new sampling points and observations to the training dataset, retrain the improved Gaussian process regression model, and complete the sequence-result space construction for the logic synthesis command sequence.

[0052] Step 8: After the new command sequence selected in the new model is executed, a Boolean satisfiability check is performed. If it meets the requirements, it is mapped to the FPGA lookup table and the QoR of the circuit is calculated based on the area and delay.

[0053] Step 9: Iterate repeatedly, and after executing the pre-set number of rounds, output the optimal QoR, thereby outputting the optimal circuit netlist structure.

[0054] Example 2

[0055] This embodiment details the FPGA logic synthesis netlist optimization method based on a modified Gaussian process regression model and an expected increase sampling function.

[0056] Step 1: Convert the original netlist of the circuit to be optimized into a graph structure (this embodiment uses the structure of a NAND graph AIG for illustration, and this method is also applicable to other directed acyclic graphs), and perform windowing, cut enumeration, irrelevant set and external irrelevant set checks on the NAND graph AIG structure circuit netlist.

[0057] Step 2: Use tools such as ABC (Academic Boolean Circuit) to perform logic rewriting, logic reconstruction, logic reorganization and logic balancing operations on the AIG structure circuit netlist after windowing and cutting enumeration, thereby reducing the redundant structure in the circuit netlist.

[0058] Step 3: Perform a SAT check on the optimized AIG structure. If the output function of the main output is consistent with the function of the initial netlist after adding test stimulus to the main input of the AIG structure, it means that the logical function of the optimized AIG structure has not changed, and return to the AIG structure after the optimization command is executed.

[0059] Step 4: Map the optimized AIG structure to the FPGA's lookup table (LUT). Evaluate the area, delay, and power consumption based on the mapped cell count, layer depth, etc. If these three metrics meet the preset requirements, output the optimal results for area, delay, and power consumption. If they do not meet the preset requirements, proceed to the Bayesian optimization stage.

[0060] Step 5: Input the current logic synthesis command optimization sequence and its mapped area, delay, power consumption, and The output values ​​are used to calculate the mean of the logical synthesis command combination sequence using a modified Gaussian process regression model. Covariance The observed data points are used to fit a function curve formed by different combinations of command sequences:

[0061] (1);

[0062] in This represents the data values ​​of i observation points. This indicates that the data values ​​at the observation points follow the mean. Covariance Matrix Gaussian distribution statistical model, Represents a sequence covariance matrix Each element is composed of covariance Calculated Here is the attention kernel function, used to describe the correlation between different data points. Its calculation method is as follows:

[0063] (2);

[0064] in Represents the basic kernel function. Represents the self-attention similarity matrix. It is a scaling factor. This represents element-wise multiplication; the calculation methods for the basic kernel function and the self-attention similarity matrix are as follows:

[0065] (3);

[0066] (4);

[0067] In formula 3 , representing a constant kernel function, whose value is adaptively adjusted as the modified Gaussian process regression agent collects data; Represents the smoothing kernel function. Represents the white noise kernel function. The radial basis function kernel is represented by the following three kernel functions, which are calculated as follows:

[0068] (5);

[0069] in Represents the gamma function; , representing the Euclidean distance between the input points; For length scale; For smoothing parameters; To correct the Bessel function;

[0070] (6);

[0071] in The noise level is represented by a value that is adaptively adjusted based on the data collected by the modified Gaussian process regression surrogate model.

[0072] (7);

[0073] in For length scale; Represents the Euclidean distance between input points;

[0074] In formula 4, , , These represent the weights of positional similarity, pattern similarity, and statistical similarity, respectively. Indicates positional similarity. Representing pattern similarity, The statistical similarity is represented by the following three similarity scores:

[0075] (8);

[0076] in It is an indicator function, when The kth element equals The value is 1 when it is the k-th element, and 0 otherwise.

[0077] (9);

[0078] in It is an indicator function, when The (k-1)th element equals The value is 1 when it is the (k-1)th element, and 0 otherwise;

[0079] (10);

[0080] in This represents the average value of the data collection points. Indicates the variance of the data collection points. This indicates a small positive number that prevents the denominator from being zero.

[0081] Step 6: After the modified Gaussian process regression is completed, the next sampling point is calculated using an adaptive sampling function. (See also...) Figure 2 The adaptive sampling function comprehensively considers both optimality and uncertainty; where optimality is determined by the mean of the predicted data points. The uncertainty is determined by the variance between the predicted data points. The decision, in Figure 2 The shaded area at EI(x) is used to select the next most promising sequence of logic synthesis commands:

[0082] (11);

[0083] in These are weighting coefficients that are continuously adjusted with the number of iterations; This is the exploration cycle, adjusted based on the QoR return value; This represents the current best value at the observation point; This represents the exploration factor; the larger the value, the more the algorithm tends to explore unknown areas. The cumulative distribution function representing the standard normal distribution; Let Z represent the probability density function of the standard normal distribution; where Z is calculated as follows:

[0084] (12).

[0085] Step 7: Add the new sampling points and observations to the training dataset, retrain the improved Gaussian process regression model, and automatically update the parameters in the mean function and covariance function according to the observations. After determining the final improved Gaussian process regression model, complete the fitting of the model to the logic synthesis command sequence function.

[0086] Step 8: After executing the new logic synthesis command combination sequence selected in the new model, a Boolean satisfiability check is performed on the AIG structure. If it meets the requirements, the optimized AIG structure is mapped into the FPGA lookup table (LUT). The circuit's performance is then calculated based on the area and delay. :

[0087] (13);

[0088] in This represents the original area size before optimization. This indicates the size of the optimized area. This indicates the original delay before optimization. This indicates the magnitude of the optimized delay. This indicates the weight of the area. This indicates the weight assigned to delay, and the netlist optimization with a bias towards area or delay can be performed by adjusting the weight.

[0089] Step 9: Iterate repeatedly until the pre-set number of rounds is completed, then output the optimal result. This outputs the optimal AIG format circuit netlist structure.

[0090] (14).

[0091] Example 3:

[0092] This embodiment uses the FPGA logic synthesis netlist optimization method based on Bayesian optimization described in this invention for experimental purposes.

[0093] In this embodiment, the adder, div, and hyp netlists provided by the EPFL (École Polytechnique Fédérale de Lausanne) combinational logic test benchmark are selected as the source files for high-level description. The source files are connected to the ABC open-source logic synthesis platform, and LUTs are selected as the mapping units to perform source file conversion, optimization and FPGA mapping.

[0094] Optionally, the implementation process of the FPGA logic synthesis netlist optimization method based on Bayesian optimization described in this invention is also applicable to the ASIC synthesis environment after the mapping object is changed.

[0095] The main algorithm in this embodiment is written in Python, while the corresponding logic synthesis commands are based on the Tool Command Language (TCL). The optimization algorithm selects optimization commands based on the actual situation and writes them into the corresponding TCL script, which is then sent to the logic synthesis platform for execution. Regular expression matching is used to read the delay and area data returned by the platform, guiding the subsequent algorithm optimization direction.

[0096] To compare the performance of the method of the present invention, an existing method was selected as a control (the control method is referred to "Grosnit, Antoine, et al. "Boils: Bayesian optimisation for logic synthesis." 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2022."), and experiments were conducted on the method of the present invention and the control method respectively.

[0097] In this embodiment, the self-attention kernel function is set with a position weight of 0.4, a mode weight of 0.3, a state weight of 0.3, and a small perturbation ε of 1×10⁻⁶. -8 The initial number of sequences for Bayesian optimization is 10, and the total number of iterations N is 100.

[0098] Table 1 clearly demonstrates the optimization effect of the FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanism compared to the initial netlist. As can be seen from the table, in most cases, the optimization effect of this method on area and delay is superior to the Bolls method. Furthermore, Figure 3 The optimization method described in this invention demonstrates that it significantly converges the QoR result trends for different netlists.

[0099] Table 1 Comparison of Original and Optimized Data in the Test Set

[0100]

[0101] This result demonstrates that the method of this invention can process various netlists with high efficiency and excellent stability. Experimental data shows that the performance fluctuation of the method is small, exhibiting stronger adaptability and robustness. This advantage enables the method of this invention to better cope with various complex situations that may arise in practical applications.

[0102] In summary, the FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanisms of this invention has significant advantages and practical value in the field of logic optimization. By effectively balancing the two key optimization objectives of area and delay, this invention provides a more efficient and accurate logic optimization solution for practical applications. Furthermore, its excellent adaptability and robustness make this invention an important reference and choice for future logic optimization work.

[0103] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A FPGA logic synthesis netlist optimization method based on Bayesian optimization and attention mechanism, characterized in that, The method comprises: Step 1: converting the original netlist of the circuit to be optimized into a graph structure and performing windowing, cut enumeration, irrelevant set and external irrelevant set checking; Step 2: performing Boolean rewriting, Boolean restructuring, Boolean recombination and Boolean balancing operations on the And-Inverter Graph (AIG) structure circuit netlist after windowing and cut enumeration are completed; Step 3: performing SAT (Satisfiability Checking) checking on the optimized AIG structure, and if the main output function is consistent with the initial netlist function, returning the AIG structure after the optimization command execution; Step 4: mapping the optimized AIG structure into the LUT of the FPGA for area, delay and power consumption evaluation to determine whether the requirements are met; If the area, delay and power consumption meet the pre-set requirements, the best results of area, delay and power consumption are output; if the pre-set requirements are not met, the Bayesian optimization link is entered; Step 5: inputting the current logic synthesis command optimization sequence and the mapped area, delay, power consumption and QoR output values, and using the improved Gaussian process regression model to calculate and predict the sequence-result space formed by different command combination sequences; Step 6: according to the model update generated netlist optimization command sequence and QoR, using an adaptive sampling function to calculate and select the next most potential command sequence; Step 7: adding the new sampling point and the observation value to the training data set, retraining the improved Gaussian process regression model, and completing the sequence-result space construction of the logic synthesis command sequence; Step 8: performing Boolean satisfiability checking after the new command sequence selected in the new model is executed, mapping to the FPGA lookup table according to the area and delay to calculate the QoR of the circuit; Step 9: repeatedly iterating, outputting the best QoR after executing the pre-set number of rounds, and thus outputting the best circuit netlist structure.

2. The method of claim 1, wherein, In step 3, the AIG structure comprises main inputs, main outputs, nodes, edges, levels, latches, AND gates and NOT gates; The optimization command actions include logic rewriting, zero-delay logic rewriting, logic resubstitution, zero-delay logic resubstitution, logic restructuring, zero-delay logic restructuring and logic balancing.

3. The method of claim 1, wherein, Step 5: inputting the current logic synthesis command optimization sequence and the mapped area, delay, power consumption and QoR output values, and using the improved Gaussian process regression model to calculate and predict the sequence-result space formed by different command combination sequences, comprising: Input the current logic synthesis command optimization sequence and its mapped area, delay, power and Output the numerical values, use the improved Gaussian process regression model to calculate the mean and covariance of the logic synthesis command combination sequence Fit the function curve composed of different command combination sequences with the observed data points: （1）； wherein denotes the data values of i observation points, denotes that the data values of the observation points follow a Gaussian distribution statistical model with mean and covariance matrix denotes the sequence , the covariance matrix each element of which is calculated from the covariance , and is an attention kernel function used to describe the correlation between different data points, which is calculated as follows:​ （2）； wherein denotes a base kernel function, denotes a self-attention similarity matrix, is a scaling factor, denotes an element-wise multiplication; the base kernel function, the self-attention similarity matrix are calculated as follows: （3）； （4）； In Equation 3 , represents a constant kernel function, the value of which is adjusted adaptively as the modified Gaussian process regression agent collects data; represents a smooth kernel function, represents a white noise kernel function, represents a radial basis kernel function, and the calculation methods of the three kernel functions are as follows: （5）； wherein denotes the gamma function; denotes the Euclidean distance between input points; is a length scale; is a smoothing parameter; is a modified Bessel function; （6）； wherein is a noise level, the value being adapted with data collected by the modified Gaussian process regression proxy model; （7）； wherein is a length scale; denotes the Euclidean distance between input points; In Equation 4, , , respectively represent the weights of the position similarity, the pattern similarity and the statistical similarity; represents the position similarity, represents the pattern similarity, represents the statistical similarity, and the calculation methods of the three similarities are as follows: （8）； wherein is an indicator function, when is 1 if the kth element of is 1, otherwise 0. （9）； wherein is an indicator function, when is 1 if the (k-1)th element of is 1, otherwise 0. （10）； wherein represents the mean of the collection points, represents the variance of the collection points, represents a small positive number to prevent the denominator from being zero.

4. The method of claim 3, wherein, Step 6: according to the model update generated netlist optimization command sequence and QoR, using an adaptive sampling function to calculate and select the next most potential command sequence, comprising: After the improved Gaussian process regression is completed, an adaptive sampling function is used to calculate a next point for sampling; the adaptive sampling function comprehensively considers optimality and uncertainty; wherein the optimality is determined by a mean value of predicted data points ; and the uncertainty is determined by a variance between the predicted data points to select a next most potential logical integrated command combination sequence; （11）； wherein is a weight coefficient that is constantly adjusted with the number of iterations; is an exploration period, adjusted according to the QoR return value; represents the current best value of the observation point; represents an exploration factor, the greater the value, the more the algorithm tends to explore unknown areas; represents the cumulative distribution function of the standard normal distribution; represents the probability density function of the standard normal distribution; wherein the Z calculation method is: （12）。 5. The method of claim 4, wherein, The QoR is determined by the following method: （13）； wherein represents the size of the original area before optimization, represents the size of the area after optimization, represents the size of the original delay before optimization, represents the size of the delay after optimization, represents the weight of the area, represents the weight of the delay, the weight is adjusted to perform the area or delay oriented netlist optimization.

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