Method for testing read interference of solid state disk

Abstract

The invention discloses a solid state disk read interference test method which comprises the following steps: S1, acquiring configuration information of a solid state disk, and setting test parameters according to the configuration information; s2, writing test data into all available spaces of the solid state disk; s3, deleting test data with a preset proportion in the solid state disk; s4, reading interference test circulation: S41, performing continuous reading operation on the residual test data after the step S3, and continuously applying reading interference; s42, when a preset verification interval is reached, pausing the continuous reading operation, executing a data verification operation, and obtaining error information related to read interference; s43, judging whether a preset test termination condition is met or not according to the error information; if yes, executing S5; if not, returning to S41 to continue the next test cycle; and S5, carrying out overall performance evaluation on the solid state disk according to a test result. The problems that in the prior art, read interference test conditions are idealized, and a scene is not read after real write-in are not combined are solved.

Description

Technical Field

[0001] This invention belongs to the field of solid-state drive testing technology and relates to a method for testing solid-state drive read interference. Background Technology

[0002] In the field of solid-state drive (SSD) testing, read disturbance is a critical issue. Traditional read disturbance tests typically employ simple data read operations to check for phenomena such as bit flips or read errors in adjacent blocks. However, this approach has some limitations: it does not incorporate real write-and-read scenarios, does not simulate the "read amplification" effect between chips or blocks, and the test conditions are too idealized.

[0003] Furthermore, some standard tests do not incorporate Error Correction Capability (ECC) and Flash Translation Layer (FTL) scheduling mechanisms, failing to fully reflect the impact of read interference on overall system reliability in real-world user scenarios. Additionally, existing technologies have relatively low thresholds for read interference, which can easily lead to increased write amplification across the entire SSD, affecting overall drive performance.

[0004] Therefore, there is an urgent need for a read interference testing method that is closer to real-world usage scenarios, to realistically simulate the interference caused to other blocks by "frequent reading of written data" during user operation, and to combine ECC capabilities and FTL scheduling mechanisms to comprehensively evaluate the impact of read interference on the overall system reliability, thereby providing SSD developers with more accurate reference indicators. Summary of the Invention

[0005] This invention provides a solid-state drive read interference testing method, which solves the problems of idealized read interference testing conditions and failure to incorporate real write-and-read scenarios in existing technologies. It also addresses the lack of automated testing tools and scripts in existing technologies.

[0006] Before describing the technical solution provided by this invention, the following explanations are given for the technical terms mentioned in the technical solution: LBA: Logical Block Address, also known as Logical Sector. LBA range: Logical block address range FTL: Flash Translation Layer. ECC: Error Correction Code. This invention provides a method for testing read interference in solid-state drives, comprising the following steps: S1. Test initialization phase: Obtain the configuration information of the solid-state drive and set the test parameters according to the configuration information; S2, Data Filling Stage: Write test data to all available space on the solid-state drive; S3, Data Deletion Stage: A preset proportion of test data is deleted from the solid-state drive to change the data distribution of the storage unit and trigger the internal management mechanism of the solid-state drive. S4, the read interference test loop phase, includes: S41, Interference Application Sub-stage: Continuously read the remaining test data after stage S3 and continuously apply read interference; S42, Interruption Detection Sub-stage: When the preset verification interval is reached, the continuous reading operation is paused, a data verification operation is performed, and error information related to reading interference is obtained; S43, Judgment Sub-stage: Determine whether the preset test termination condition is met based on the error information; if it is met, execute S5; if it is not met, return to S41 to continue the next test cycle; S5. Performance Evaluation Phase: Evaluate the overall performance of the solid-state drive based on the test results.

[0007] Furthermore, in step S1, the configuration information includes LBA range, NAND flash memory chip type, ECC strategy, and FTL mapping strategy, and the test parameters include test data deletion ratio, read cycle period, upper limit threshold for the number of errors, and verification interval.

[0008] Furthermore, in step S2, writing test data includes: writing unique data generated based on the address of each logical sector, and generating a corresponding check code and storing it in a check mapping table.

[0009] Furthermore, in step S3, deleting a preset proportion of test data from the solid-state drive includes: S31 calculates the range of LBAs to be deleted based on the preset test data deletion ratio; S32 selects the logical sectors to be deleted, simulating non-contiguous file deletion operations by users, increasing the complexity of FTL management; S33 issues a delete command to perform a data erasure operation; S34 monitors the erasure progress until erasure is complete.

[0010] Furthermore, in step S42, obtaining error information related to read interference includes parsing the read results within each verification interval to obtain the number of errors in the read data; it also includes reading the SMART attribute log of the solid-state drive to obtain the error correction count of the error correction code.

[0011] Furthermore, in step S43, the test termination condition includes at least one of the following: (1) The number of errors in reading data exceeds the preset upper limit threshold for the number of errors; (2) Uncorrectable errors were found during data validation operations; (3) The error correction count of the error correction code exceeds the preset upper limit threshold for the number of errors; (4) The cumulative number of read cycles reaches the preset read cycle period.

[0012] Furthermore, step S5 performs an overall performance evaluation of the solid-state drive; including: S51 calculates the read interference error rate; S52 determines whether the read interference error rate exceeds the upper limit threshold of the number of errors. If it exceeds the threshold, the solid-state drive is determined to be a defective product. If it does not exceed the threshold, the solid-state drive is determined to be a qualified product.

[0013] Furthermore, step S5 also includes: If the S50 test fails due to triggering the termination condition, the solid-state drive is determined to be a defective product.

[0014] Furthermore, in step S51, the read interference error rate includes a correctable read interference error rate; Among them, the correctable read interference error rate = total correctable errors / total amount of data read.

[0015] Furthermore, in step S41, the continuous reading operation of the remaining test data after stage S3 specifically involves continuously reading the remaining test data according to a preset reading cycle.

[0016] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention adopts a combination of "writing full → deleting part → continuous reading" to truly simulate the user's write, delete and update operations, overcome the limitations of the traditional test method of simply reading, and more realistically reflect the working state of SSD in actual use.

[0017] (2) By performing long-term continuous reading operations on the remaining data and combining the observation of error checking (ECC) capability and flash translation layer (FTL) scheduling mechanism, this invention comprehensively reflects the impact of read interference on the overall reliability of the system in real user scenarios, overcoming the shortcomings of existing technologies that do not combine ECC capability and FTL scheduling mechanism for joint observation.

[0018] (3) This invention realizes an automated testing process. From data filling and deletion to reading loops and performance evaluation, all can be automatically executed through scripts or dedicated tools, reducing manual intervention and improving testing efficiency and consistency. The automated design also supports batch testing and large-scale data collection, providing rich data support for SSD reliability modeling and lifespan prediction. In addition, the test results of this invention can be directly used for product improvement and optimization, helping manufacturers improve the overall quality and market competitiveness of SSDs. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the solid-state drive read interference testing method provided by the present invention.

[0021] Figure 2 yes Figure 1 The flowchart for step S2.

[0022] Figure 3 yes Figure 1 The flowchart for step S3.

[0023] Figure 4 yes Figure 1 The flowchart for step S4.

[0024] Figure 5 yes Figure 1 The flowchart for step S5. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] like Figure 1 As shown in the figure, an embodiment of the present invention provides a method for testing read interference of a solid-state drive, which includes the following steps: S1. Test initialization phase: Obtain the configuration information of the solid-state drive and set the test parameters according to the configuration information.

[0027] First, connect the SSD under test to the test host via the appropriate interface (such as NVMe or SATA) and ensure that the driver is loaded correctly. The test host should have sufficient processing power and memory resources to handle large amounts of test data and log records.

[0028] The acquisition of configuration information includes the following aspects: (1) LBA range: Obtain the logical block address range corresponding to the user's available capacity through the nvme id-ns (NVMe device) or hdparm -N (SATA device) commands.

[0029] (2) NAND flash memory chip type: obtained through manufacturer-specific commands or SMART attributes, such as TLC, QLC, etc. Different types of NAND have significantly different sensitivities to read interference.

[0030] (3) ECC strategy: Obtain error correction code type (BCH / LDPC) and error correction capability.

[0031] (4) FTL mapping strategy: Understand the mapping granularity of the flash translation layer (page level, block level or hybrid mapping).

[0032] Based on the above configuration information, set the following test parameters: (1) Test data deletion ratio: It is usually set between 30% and 70%, with 50% being the recommended value, which can achieve a balance between triggering garbage collection and retaining test data.

[0033] (2) Read cycle period: Defines the maximum number of read cycles for the test. Enterprise-grade SSDs can be set to 100,000-1,000,000 times, and consumer-grade SSDs can be set to 10,000-100,000 times.

[0034] (3) Error limit threshold: A tiered setting is adopted, with correctable errors set as the error rate threshold (e.g., 10 errors / GB), and uncorrectable errors adopting a zero-tolerance strategy.

[0035] (4) Verification interval: The verification is performed after every N data block reads are completed. The size of N is determined based on the total test data and the detection sensitivity requirements.

[0036] S2, Data Filling Stage: Write test data to all available space on the solid-state drive.

[0037] S3. Data deletion stage: A preset proportion of test data is deleted from the solid-state drive to change the data distribution of the storage unit and trigger the internal management mechanism of the solid-state drive.

[0038] S4, Interference Reading Test Cycle Phase (see below) Figure 4 (Detailed explanation).

[0039] S5. Performance Evaluation Phase: Based on the test results, perform an overall performance evaluation of the solid-state drive.

[0040] like Figure 2 As shown, step S2 writes test data to all available space on the solid-state drive, including: The S21 writes verifiable pseudo-random data to the entire available space of the solid-state drive via its I / O module.

[0041] A multi-threaded parallel write strategy is employed to ensure even data distribution across the entire disk. The following key metrics are monitored during the write process: Write throughput: Ensure write speeds close to the SSD's nominal speed.

[0042] Write latency: Detects abnormal latency fluctuations.

[0043] Write error rate: Ensures that the initial state is error-free.

[0044] Use tools such as fio to configure multiple write tasks, each task is responsible for a continuous LBA range, avoid the influence of file system caching, and use the O_DIRECT flag to ensure that data is written directly to the flash media.

[0045] S22 writes a unique data pattern based on its address and a preset seed value to each logical sector LBA, and simultaneously generates a CRC32 or MD5 checksum for the data, storing the correspondence between the checksum and the LBA in a checksum mapping table.

[0046] The data pattern generation algorithm uses: pattern = PRNG(LBA || seed) PRNG is a cryptographically secure pseudo-random number generator, and seed is a fixed seed value to ensure test repeatability. Each LBA's data is unique and deterministic, facilitating subsequent verification.

[0047] The checksum is generated using either CRC32 or MD5 algorithms, balancing storage overhead and checksum strength. The checksum mapping table is stored using an efficient data structure (such as a B+ tree or hash table) to support fast lookups. For large-capacity SSDs, a block storage strategy is adopted, dividing the checksum mapping table into multiple files according to LBA ranges to reduce memory pressure.

[0048] like Figure 3 As shown, in step S3, deleting a preset proportion of test data from the solid-state drive includes: S31 calculates the range of LBAs to be deleted based on the preset test data deletion ratio.

[0049] The deletion strategy is selected based on the test objective: Continuous deletion: Deletes consecutive LBA ranges, simulating large file deletion scenarios.

[0050] Random deletion: Use a uniformly distributed random number generator to select LBAs to be deleted, simulating fragmented deletion.

[0051] Interleaved deletion: Deleting LBAs at fixed intervals (such as all odd LBAs) balances complexity and accuracy.

[0052] S32 selects the logical sector LBA to be deleted, simulating a user's non-contiguous file deletion operation, increasing the complexity of FTL management.

[0053] A random deletion strategy is preferred, using the Mason twitch algorithm or other high-quality random number generators to produce the list of LBAs to be deleted. The deletion pattern design considers the mapping granularity of the FTL, ensuring that the deletion operation triggers an update across multiple mapping units.

[0054] S33 issues a delete command to perform a data erasure operation.

[0055] Use the appropriate command according to the interface protocol: SATA devices: Use the TRIM command NVMe devices: using the Deallocate command Ensure the delete command executes correctly, bypassing the write cache using the Forced Unit Access (FUA) flag, effective immediately.

[0056] S34 monitors the erasure progress until erasure is complete.

[0057] Monitor the deletion process using the following methods: Check the command completion status.

[0058] Query the available space ratio in the SMART attribute.

[0059] Monitor background garbage collection activities and wait for the SSD to recover to a stable state.

[0060] like Figure 4 As shown, step S4, the read interference test loop phase, includes: S41, Interference Application Sub-stage: The remaining test data after stage S3 is continuously read according to the preset reading cycle, and reading interference is continuously applied.

[0061] Key parameters for read operation configuration: Reading modes: sequential reading (maximizing interference between adjacent units) or random reading (simulating real access mode).

[0062] Queue depth: Set to 32-256 to maintain high concurrent read pressure.

[0063] Read block size: typically set to 128KB-1MB to balance efficiency and interference intensity.

[0064] During the read process, continuously monitor read throughput and latency, SSD temperature sensor data, and power consumption fluctuations.

[0065] S42, Interruption Detection Sub-stage: When the preset verification interval is reached, the continuous reading operation is paused, the data verification operation is performed, and error information related to read interference is obtained.

[0066] The step of obtaining error information related to read interference includes parsing the read results within each verification interval to obtain the number of errors in the read data; it also includes reading the SMART attribute log of the solid-state drive to obtain the error correction count of the error correction code.

[0067] The verification interval is set based on the amount of data, such as performing a verification after reading every 1TB of data. The verification process includes: (1) Data integrity verification: Reread all remaining data and compare it with the verification mapping table.

[0068] (2) Error classification: Distinguish between correctable errors (data mismatch but ECC can correct) and uncorrectable errors (data is permanently corrupted).

[0069] (3) SMART log analysis: Read key SMART attributes, including media and data integrity error count, ECC error correction count, and error message log entries.

[0070] Error messages record detailed context, including the LBA range at the time of the error, the error type and severity, the corresponding number of read loops, timestamps, and temperature data.

[0071] S43, Judgment Sub-stage: Determine whether the preset test termination condition is met based on the error information; if it is met, execute S5; if it is not met, return to S41 to continue the next test cycle.

[0072] The preset test termination conditions include at least one of the following: (1) The number of errors in reading data exceeds the preset upper limit threshold for the number of errors; (2) Uncorrectable errors were found during data validation operations; (3) The error correction count of the error correction code exceeds the preset upper limit threshold for the number of errors; (4) The cumulative number of read cycles reaches the preset read cycle period.

[0073] Test termination conditions are handled according to priority: def check_termination_conditions(): if unrecoverable_error_detected(): # Highest priority - terminate immediately return "FAIL_UE" elif ecc_error_rate>threshold: # Second priority - error rate exceeds the limit return "FAIL_ECC_RATE" elif read_cycles>= max_cycles: # Normal termination - test cycle reached return "PASS_COMPLETION" else: # Continue testing return "CONTINUE" like Figure 5 As shown, step S5 performs an overall performance evaluation of the solid-state drive; including: If the S50 test fails due to triggering the termination condition, the solid-state drive is determined to be a defective product.

[0074] S51 calculates read interference error rate The read interference error rate includes the correctable read interference error rate; uncorrectable errors are also recorded.

[0075] Among them, the correctable read interference error rate = total correctable errors / total amount of data read.

[0076] S52 determines whether the read interference error rate exceeds the upper limit threshold of the number of errors. If it exceeds the threshold, the solid-state drive is determined to be a defective product. If it does not exceed the threshold, the solid-state drive is determined to be a qualified product.

[0077] It should be noted that the steps listed above are not necessarily sequential. Some steps can be executed in parallel, such as data verification and SMART log reading, which can be performed simultaneously to improve testing efficiency.

[0078] The solid-state drive read interference test method of this invention realistically simulates the user's write, delete, and update operations, effectively triggering FTL's garbage collection (GC) and wear leveling (WL) mechanisms, while changing the data distribution inside the NAND storage cell. It overcomes the limitations of traditional test methods that only read data, and more realistically reflects the working state of the SSD in actual use.

[0079] During testing, through periodic verification and data comparison, this invention can capture correctable errors (CE) and uncorrectable errors (UE), and utilize SMART logs to obtain error correction counts, thereby quantifying the severity of read interference. This multi-dimensional error monitoring mechanism ensures the accuracy and repeatability of test results, helping to identify potential defects in SSDs.

[0080] This invention provides flexible test parameter configurations, including deletion ratio, read cycle time, error threshold, and verification interval, enabling the testing method to adapt to different SSD models and configurations. For example, for high-endurance enterprise-grade SSDs, longer read cycle times and higher error thresholds can be set; while for consumer-grade SSDs, more stringent test conditions can be used to quickly expose problems. This customizability makes this invention applicable not only to reliability verification during the R&D phase but also to quality control and product grading on the production line.

[0081] Example 1: The solid-state drive read interference testing method provided in this embodiment is a basic scheme based on cyclic reading and periodic verification. It focuses on evaluating the read interference effect through periodic data integrity verification. This read interference testing method is basic and efficient. The test environment is configured as follows: Test host: x86 server, 32 cores, 64GB memory, PCIe 4.0 interface Operating System: Linux Kernel 5.10+ Testing tools: Custom test scripts + fio + nvme-cli + smartmontools SSD under test: 1TB NVMe TLC enterprise-grade solid-state drive Step S1: Test Initialization and Parameter Setting Get SSD configuration information: LBA range: 0 - 1,953,525,167 (512B sectors) NAND type: 3D TLC ECC capability: LDPC, 120-bit / 1KB error correction capability FTL strategy: Hybrid mapping (page-level metadata, block-level user data) Set the key parameters for this test method based on the obtained SSD configuration information: (1) Test data deletion ratio: 50% It should be noted that the deletion ratio set in this embodiment is 50%. In other embodiments, the deletion ratio can also be set to 30% or other values.

[0082] The deletion ratio is set based on the fact that it can effectively trigger background garbage collection (GC) on most SSDs, while retaining enough data to apply read interference, thus better simulating the user's usage state.

[0083] (2) Reading cycle: 100,000 times (reads all retained data in each loop) (3) Upper limit threshold for the number of errors: Correctable errors: ≤15 errors / GB Uncorrectable errors: Zero tolerance (4) Verification interval: Verification is performed every 5TB of data read (approximately every 10 cycles).

[0084] Step S2, Data Filling Stage Populate data using the fio configuration file: [global] ioengine=libaio direct=1 thread=1 group_reporting=1 size=100% [write_test] numjobs=16 rw=write bs=1M filename= / dev / nvme0n1 Data pattern generation uses an AES-based algorithm to ensure the uniqueness of each LBA data. The verification mapping table is stored using LevelDB, supporting fast lookup and persistence.

[0085] Step S3, Data Deletion Stage A random deletion strategy is employed, using the Mersenne Twister algorithm to generate a list of LBAs to be deleted. Execute the command: nvme format / dev / nvme0n1 -s 1 -n 1 The monitoring has been deleted. Waiting for the SMART property Available Spare to stabilize.

[0086] Step S4, Interference Reading Test Cycle Phase The specific implementation steps are as follows: S41, Interference Application Sub-stage: Continuously read the remaining test data after stage S3 and continuously apply read interference.

[0087] The I / O module of the test host continuously reads all the remaining LBA data (i.e., the test data that has not been deleted) from step S3. The reading process continues and the number of loops is accumulated.

[0088] S42, Interruption Detection Sub-stage: After each reading loop of the verification interval is completed, the main reading thread is paused.

[0089] Start the data verification thread, read the LBA of all retained data again, and compare the read data with the original checksum stored in the verification mapping table.

[0090] During this period, the SSD's SMART logs (SMART attribute logs) are monitored synchronously using commands such as smartctl -a, with a focus on recording the growth of Media and Data Integrity Errors, Error Information Log Entries, and ECC error correction counts to obtain the number of errors when reading data.

[0091] S43, Judgment Sub-stage: Determine whether the preset test termination condition is met based on the error information; if it is met, execute S5; if it is not met, return to S41 to continue the next test cycle.

[0092] The test termination conditions include at least one of the following: (1) The number of errors in reading data exceeds the preset upper limit threshold for the number of errors; If the number of errors in reading data exceeds the preset upper limit threshold, then proceed to step S5.

[0093] (2) Uncorrectable errors were found during data validation operations; If any uncorrectable error is found during data comparison (data verification fails and SSD returns a read error), or if an uncorrectable error is reported in the SMART log, immediately proceed to step S5 and determine it as a failure.

[0094] (3) The error correction count of the error correction code exceeds the preset upper limit threshold for the number of errors; If the number of correctable errors (such as a surge in ECC count) exceeds the preset upper limit threshold for the number of errors, proceed to step S5.

[0095] (4) The cumulative number of read cycles reaches the preset read cycle period.

[0096] The test ends normally when the cumulative number of read cycles reaches the preset read cycle period (100,000 times) without triggering any termination conditions.

[0097] Step S5, Performance Evaluation Phase Test results: Total data read: ~50PB Errors correctable: 3,245 Uncorrectable errors: 0 times Error rate calculated: 0.065 errors / GB The result is: qualified (error rate is below the threshold of 15 errors / GB).

[0098] Example 2: This embodiment builds upon Embodiment 1 by incorporating a high-temperature environmental stress enhancement scheme. This embodiment introduces environmental stress to accelerate the manifestation of read interference effects, thereby enabling a more rigorous and rapid reliability assessment.

[0099] Environment configuration: Temperature control chamber: accuracy ±1°C, temperature range -40°C to +125°C.

[0100] Temperature monitoring: SSD built-in sensor + external thermocouple.

[0101] Test SSD: The same 1TB NVMe TLC enterprise-class solid-state drive.

[0102] The same content as in Example 1 will not be repeated in this example; only the content that differs from Example 1 will be described.

[0103] Step S1: Test Initialization and Parameter Setting High temperatures accelerate charge loss in NAND flash memory, significantly amplifying read interference and shortening test time. Key parameters are adjusted to accelerate testing. (1) Reading cycle: shortened to 20,000 times.

[0104] Because the high temperature accelerates the process, multiple cycles are not required.

[0105] (2) Verification interval: Verification is performed every 1TB of data read (more frequently).

[0106] Because failures may occur more quickly, more frequent testing is required.

[0107] (3) Upper limit threshold for the number of errors: Correctable errors: ≤5 errors / GB (more stringent) Uncorrectable errors: Zero tolerance Because any error occurring at high temperatures is a more serious signal, setting an upper limit threshold for the number of errors becomes more stringent.

[0108] Steps S2 and S3 are the same as in Example 1, and will not be repeated here.

[0109] Step S4, Interference Reading Test Cycle Phase After data filling and deletion, the SSD was placed in a temperature-controlled chamber and heated to 85°C at a rate of 5°C / minute, then held at that temperature for 30 minutes to achieve thermal stability. An S4 read interference test cycle was then performed under high temperature conditions. After the test, the SSD was cooled to room temperature at a rate of 3°C / minute, and a final full-disk data verification was performed.

[0110] Finally, a full data integrity check is performed to ensure that no additional data stability issues arise due to temperature changes during the cooling process.

[0111] The monitoring parameters are as follows: Core temperature: Monitored via NVMe Thermal Management Temperature fluctuations: Record maximum / minimum / average temperatures Temperature-related errors: Analysis errors related to temperature correlation Step S5, Performance Evaluation Phase After the test, the SSD was removed from the temperature-controlled chamber and allowed to return to room temperature.

[0112] The evaluation criteria are the same as in Example 1, but the conditions are more stringent. Passing this test means that the SSD has extremely high reliability.

[0113] Observations were made under high temperature conditions: Error rate growth accelerated: 0.12 errors / GB (compared to 0.065 errors / GB at room temperature).

[0114] Error distribution changes: At high temperatures, errors are more concentrated in specific physical blocks.

[0115] Performance degradation: Read latency increases by 15% at high temperatures.

[0116] The result is: qualified (the error rate is still lower than the high temperature threshold of 5 errors / GB).

[0117] Example 2, by introducing high-temperature environmental stress testing, further accelerates the manifestation of read interference effects, shortens testing time, and increases the stringency of the test. Under high-temperature conditions, NAND flash memory experiences accelerated charge loss, making read interference errors more easily triggered. This allows the present invention to quickly assess the reliability of SSDs under extreme conditions. This accelerated testing method is particularly suitable for product development cycles requiring rapid iteration and for SSD screening in high-reliability application scenarios (such as data centers and industrial control).

[0118] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for solid state drive read disturb test, characterized in that, The method comprises the following steps: S1, a test initialization stage: obtaining configuration information of the solid state disk, and setting test parameters according to the configuration information; S2, a data filling stage: writing test data to all available spaces of the solid state disk; S3, a data deletion stage: deleting a preset proportion of test data in the solid state disk to change the data distribution of the storage unit and trigger the internal management mechanism of the solid state disk; S4, a read interference test cycle stage, comprising: S41, an interference application sub-stage: continuously reading the test data remaining after the S3 stage to continuously apply read interference; S42, an interruption detection sub-stage: when a preset check interval is reached, the continuous reading operation is paused, a data check operation is performed, and error information related to read interference is obtained; S43, a judgment sub-stage: determining whether a preset test termination condition is met according to the error information; if yes, S5 is executed; if not, the next test cycle is returned to S41; S5, a performance evaluation stage: evaluating the overall performance of the solid state disk according to the test results.

2. The solid state drive read disturb test method of claim 1, wherein, In step S1, the configuration information includes LBA range, NAND flash particle type, ECC strategy, FTL mapping strategy, and the test parameters include test data deletion proportion, read cycle period, error number upper threshold, and check interval.

3. The solid state drive read disturb test method of claim 2, wherein, In step S2, the writing of test data includes: writing unique data generated based on the address of each logical sector, and generating corresponding check codes stored in a check mapping table.

4. The solid state drive read disturb test method of claim 2, wherein, In step S3, the deletion of a preset proportion of test data in the solid state disk comprises: S31, calculating the LBA range to be deleted according to the preset test data deletion proportion; S32, selecting logical sectors to be deleted to simulate user non-continuous file deletion operations and increase the complexity of FTL management; S33, issuing a deletion instruction to perform a data erasing operation; S34, monitoring the erasing progress until the erasing is completed.

5. The solid state drive read disturb test method of claim 2, wherein, In step S42, the error information related to read interference includes analyzing the read results in each check interval to obtain the number of read data errors; and further includes reading the S.M.A.R.T. attribute log of the solid state disk to obtain the error correction code error correction count.

6. The solid state drive read disturb test method of claim 5, wherein, In step S43, the test termination condition includes at least one of the following: (1) the number of read data errors exceeds the preset error number upper threshold; (2) uncorrectable errors are found in the data check operation; (3) the error correction code error correction count exceeds the preset error number upper threshold; (4) the cumulative read cycle number reaches the preset read cycle period.

7. The solid state drive read disturb test method of claim 6, wherein, Step S5 evaluates the overall performance of the solid state disk; comprising: S51, calculating the read interference error rate; S52, determining whether the read interference error rate exceeds the preset error number upper threshold; if yes, determining that the solid state disk is an unqualified product; if not, determining that the solid state disk is a qualified product.

8. The solid state drive read disturb test method of claim 7, wherein, Step S5 further comprises: S50, if the test fails due to triggering the termination condition, determining that the solid state disk is an unqualified product.

9. The solid state drive read disturb test method of claim 7, wherein, In step S51, the read disturb error rate comprises a correctable read disturb error rate. The correctable read disturb error rate = total correctable error number / total read data amount.

10. The solid state drive read disturb test method of claim 2, wherein, In step S41, the remaining test data after the S3 stage is continuously read, specifically: the remaining test data is continuously read according to a preset read cycle period.

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