Sequential logic control circuit for noise shaping SAR ADC
By designing a combination of analog signal acquisition, noise shaping, and clock control circuits, the noise shaping problem of SAR ADC is solved, the signal-to-noise ratio is improved, and the circuit can operate stably and efficiently, making it suitable for noise-sensitive scenarios.
Patent Information
- Application Number
- CN202511797843.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-02
- Publication Date
- 2026-03-06
AI Technical Summary
In existing technologies, the timing logic control circuit of SAR ADC cannot achieve noise shaping, resulting in quantization noise being uniformly distributed within the bandwidth without attenuation, directly superimposed on the output signal, increasing circuit complexity and power consumption, and making it difficult to meet the performance requirements of medical sensing and high-precision instrument measurement.
Design a timing logic control circuit that includes an analog signal acquisition circuit, a noise shaping circuit, and a clock control circuit. The analog signal acquisition circuit performs preprocessing, the noise shaping circuit performs spectrum shaping, and the clock control circuit coordinates the timing logic to ensure orderly connection of each link and reduce noise interference.
Significantly improves the signal-to-noise ratio, reduces noise interference in analog-to-digital conversion, ensures stable and efficient circuit operation, and meets the performance requirements of noise-sensitive scenarios.
Smart Images
Figure CN121618972A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of timing control technology, and more specifically, to a timing logic control circuit for noise-shaping SAR ADCs. Background Technology
[0002] The timing logic control circuit of the SAR ADC is the core unit responsible for coordinating the operation of its internal successive approximation register (SARRegister), digital-to-analog converter (DAC), and comparator. It starts the conversion at a preset clock tick, then controls the register to be set to 1 in order from the most significant bit to the least significant bit. The DAC converts the digital value into an analog voltage and compares it with the input signal. Based on the result, it decides whether to retain the bit. After all bits have been compared, the final digital result is output, thus ensuring the accuracy and efficiency of the analog-to-digital conversion.
[0003] In the existing technology, the timing control circuit cannot achieve noise shaping, which results in the quantization noise (the inherent noise caused by limited resolution) being uniformly distributed within the bandwidth without attenuation / redistribution mechanism. This noise is directly superimposed on the output signal, resulting in a limited overall signal-to-noise ratio. This not only significantly increases circuit complexity and power consumption, but also makes it difficult to meet performance requirements in noise-sensitive scenarios such as medical sensing and high-precision instrument measurement.
[0004] No effective solutions have yet been proposed to address the problems in the relevant technologies. Summary of the Invention
[0005] In view of the problems in related technologies, the present invention proposes a timing logic control circuit for noise shaping SAR ADC to overcome the above-mentioned technical problems existing in the prior art.
[0006] Therefore, the specific technical solution adopted by the present invention is as follows: A timing logic control circuit for a noise-shaping SAR ADC, the timing logic control circuit comprising: The analog signal acquisition circuit is used to receive the initial input signal and preprocess it to convert the initial signal into an analog signal suitable for noise shaping circuits. The noise shaping circuit is used to perform spectrum shaping on the quantization noise in the analog signal. It pushes the noise energy away from the effective bandwidth through a feedback loop to generate the noise-shaped analog signal. Successive approximation analog-to-digital converters are used to convert analog signals into digital signals step by step from the most significant bit to the least significant bit, based on the principle of successive approximation and generating a reference voltage through an internal DAC. Clock control circuit, used to coordinate the timing logic between analog signal acquisition circuit, noise shaping circuit and successive approximation analog-to-digital converter; The analog signal acquisition circuit is electrically connected to the noise shaping circuit, the noise shaping circuit is electrically connected to the successive approximation analog-to-digital converter, and the successive approximation analog-to-digital converter is electrically connected to the clock control circuit.
[0007] Preferably, the analog signal acquisition circuit includes resistors R1, R2, R3, R4, R5, R6, and R7, capacitors C1, C2, and C3, operational amplifier U1, and operational amplifier U2. The first pin of operational amplifier U1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to the initial input signal Vref1. The other end of resistor R2 is connected to the second pin of operational amplifier U1 and grounded. The third pin of operational amplifier U1 is connected to one end of resistor R3. The other end of resistor R3 is connected to the first pin of operational amplifier U2, one end of capacitor C2 and resistor R5. The other end of capacitor C2 is connected to the other end of resistor R5, the third pin of operational amplifier U2 and one end of resistor R6. The fourth pin of operational amplifier U1 is connected to one end of resistor R4. The other end of resistor R4 is connected to one end of resistor R7, one end of capacitor C1 and the second pin of operational amplifier U2. The other end of resistor R7 is connected to the other end of capacitor C1 and grounded. The other end of resistor R6 is connected to one end of capacitor C3 and the noise shaping circuit. The other end of capacitor C3 is grounded.
[0008] Preferably, the operational amplifier U1 is an isolation operational amplifier, which achieves electrical isolation of the initial input signal and performs preliminary buffering processing on the initial input signal.
[0009] Preferably, resistor R7 and capacitor C1 form a first-stage filter circuit; operational amplifier U2, resistor R5, and capacitor C2 form a second-stage filter circuit; resistor R6 and capacitor form a third-stage filter circuit, and the initial input signal passes through the first-stage filter circuit, the second-stage filter circuit, and the third-stage filter circuit in sequence to convert the initial signal into an analog signal that is compatible with the noise shaping circuit.
[0010] Preferably, the noise shaping circuit includes resistors R8, R9, R10, R11, R12, R13, and R14, operational amplifiers U3, U4, U5, and U6, transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8. In this configuration, one end of resistor R8 is connected to resistor R6 and the drain of transistor Q3. The source of transistor Q3 is connected to one end of capacitor C8 and the drain of transistor Q4. The source of transistor Q4 is grounded. The other end of capacitor C8 is connected to the source of transistor Q1 and the drain of transistor Q2. The drain of transistor Q1 is grounded. The gates of transistor Q1 and transistor Q3 are connected. The gates of transistor Q2 and transistor Q4 are connected. The other end of resistor R8 is connected to the drain of transistor Q7 and the drain of transistor Q8, respectively. The gate of transistor Q7 is connected to one end of resistor R13, the first and third pins of operational amplifier U4, respectively. The source of transistor Q7 is connected to the source of transistor Q2, the first pin of operational amplifier U3, and one end of capacitor C4, respectively. The second pin of operational amplifier U3 is grounded. The other end of capacitor C4 is connected to one end of resistor R9 and the third pin of operational amplifier U3, respectively. The other end of resistor R9 is connected to the second pin of operational amplifier U4 and one end of capacitor C5, respectively. The other end of capacitor C5 is grounded. The other end of resistor R13 is connected to the first pin of operational amplifier U6 and one end of resistor R14, respectively. One end of the resistor R14 is connected to the third pin of the operational amplifier U6, the gate of the transistor Q8, and the successive approximation analog-to-digital converter. The second pin of the operational amplifier U6 is connected to the gate of the transistor Q5, the gate of the transistor Q6, and the third pin of the operational amplifier U5. The first pin of the operational amplifier U5 is connected to the resistors R10 and R12. The other end of the resistor R12 is grounded. The other end of the resistor R10 is connected to one end of the resistor R11 and connected to the reference level input Vref2. The other end of the resistor R11 is connected to the second pin of the operational amplifier U5, the drain of the transistor Q5, and the drain of the transistor Q6. The source of the transistor Q5 is connected to the source of the transistor Q6 and grounded.
[0011] Preferably, the operational amplifier U3, capacitor C4, and resistor R9 form an integrating circuit, which integrates the input signal.
[0012] Preferably, transistors Q1, Q2, Q3, and Q4, together with capacitor C8, form a switched capacitor structure for sampling the input signal or storing charge.
[0013] Preferably, the clock control circuit includes a non-inverting buffer U7, a logic NOT gate U8, a dual-channel selector U9, a comparator U10, a resistor R16, a resistor R15, a capacitor C5, and a capacitor C7. The non-inverting buffer U7 is connected to one end of the NOT gate U8, the first pin of the dual-channel selector U9, and one end of the resistor R15. The other end of the non-inverting buffer U7 is connected to the clock signal Vref3. The other end of the NOT gate U8 is connected to the second pin of the dual-channel selector U9 and one end of the resistor R16. The other end of the resistor R16 is connected to the first pin of the comparator U10 and one end of the capacitor C6. The other end of the capacitor C6 is grounded. The other end of the resistor R15 is connected to the second pin of the comparator U10 and one end of the capacitor C7. The other end of the capacitor C7 is grounded. The third pin of the comparator U10 is connected to the third pin of the dual-channel selector U9. The fourth pin of the dual-channel selector U9 is connected to the successive approximation analog-to-digital converter.
[0014] Preferably, resistor R16 and capacitor C6, and resistor R15 and capacitor C7 respectively form two RC filter circuits to perform timing or phase conditioning on the clock signal Vref3.
[0015] Preferably, the output of comparator U10 is fed back to dual selector U9, which selects the clock signal path and coordinates the clock signal through the clock signal path, and outputs the coordinated clock signal to successive approximation analog-to-digital converter.
[0016] The beneficial effects of this invention are as follows: 1. This invention uses an analog signal acquisition circuit to receive the initial analog signal, avoids external interference through electrical isolation, optimizes the signal characteristics through multi-stage filtering, removes redundant noise, and finally outputs a stable signal that is compatible with the subsequent noise shaping circuit, laying a high-quality signal foundation for the entire conversion process. 2. This invention uses a noise shaping circuit and a feedback loop to reshape the spectrum of quantization noise in the signal, transferring the noise energy outside the effective bandwidth. Without increasing the hardware complexity, it significantly improves the signal-to-noise ratio and reduces the interference of noise on subsequent analog-to-digital conversion. 3. This invention generates and conditions clock signals through a clock control circuit. At the same time, through signal buffering, inversion, and comparison gating, it outputs a clock with strong synchronization, accurately coordinating the working timing of analog signal acquisition, noise shaping, and analog-to-digital conversion, ensuring orderly connection of each link, and thus ensuring the stable and efficient operation of the entire circuit. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic block diagram of a timing logic control circuit for a noise-shaping SAR ADC according to an embodiment of the present invention. Figure 2 This is a circuit diagram of a timing logic control circuit for a noise-shaping SAR ADC according to an embodiment of the present invention.
[0019] In the picture: 1. Analog signal acquisition circuit; 2. Noise shaping circuit; 3. Successive approximation analog-to-digital converter; 4. Clock control circuit. Detailed Implementation
[0020] To further illustrate the various embodiments, the present invention provides accompanying drawings, which are part of the disclosure of the present invention. These drawings are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these drawings, those skilled in the art should be able to understand other possible implementation methods and the advantages of the present invention.
[0021] According to an embodiment of the present invention, a timing logic control circuit for a noise-shaping SAR ADC is provided.
[0022] The present invention will now be further described in conjunction with the accompanying drawings and specific embodiments, such as... Figures 1-2 As shown, the timing logic control circuit for noise-shaping SAR ADC according to an embodiment of the present invention includes: Analog signal acquisition circuit 1 receives the initial input signal and preprocesses it to convert the initial signal into an analog signal suitable for noise shaping circuit 2. Noise shaping circuit 2 performs spectral shaping on the quantization noise in the analog signal, pushing the noise energy away from the effective bandwidth through a feedback loop to generate a noise-shaped analog signal. Successive approximation analog-to-digital converter 3 is based on the successive approximation principle and generates a reference voltage through an internal DAC. It compares the reference voltage bit by bit with the noise-shaped analog signal, gradually converting the analog signal to a digital signal from the most significant bit to the least significant bit. Clock control circuit 4 coordinates the timing logic between analog signal acquisition circuit 1, noise shaping circuit 2, and successive approximation analog-to-digital converter 3. The analog signal acquisition circuit 1 is electrically connected to the noise shaping circuit 2, the noise shaping circuit 2 is electrically connected to the successive approximation analog-to-digital converter 3, and the successive approximation analog-to-digital converter 3 is electrically connected to the clock control circuit 4.
[0023] It should be noted that the core component of the SAR ADC (Successive Approximation Analog-to-Digital Converter), the internal DAC, is composed of a capacitor array structure. This capacitor array generates a reference voltage corresponding to the digital code through different combinations of capacitors. During the successive approximation process, the control logic sequentially switches the connection state of the capacitor array, generating different reference voltages to compare with the input analog signal, gradually determining the digital value of each bit. This is the key structure for achieving high-precision voltage comparison and conversion. The working principle of the successive approximation ADC 3 is based on the successive approximation principle. It generates a reference voltage through the internal DAC, compares it bit by bit with the noise-shaped analog signal, and gradually determines the digital value of each bit from the most significant bit to the least significant bit, ultimately completing the conversion from analog signal to digital signal. Its operation is coordinated by the timing logic of the clock control circuit 4, which is existing technology and will not be elaborated on here.
[0024] The core component of the internal DAC (digital-to-analog converter) in a SAR ADC (successive approximation analog-to-digital converter) is a capacitor array. This array consists of multiple capacitors with different capacitance values (typically configured with binary weights, such as C, 2C, 4C…2ⁿ⁻¹C). Switches control the capacitors' states, such as grounding, connecting to a reference voltage, or connecting to the input signal. The principle of charge redistribution is used to generate an analog reference voltage corresponding to the digital code. During the successive approximation process, the control logic sequentially switches the connection states of the capacitor array, generating different reference voltages to compare with the input analog signal, gradually determining the digital value of each bit. This is existing technology and will not be elaborated upon further here.
[0025] In one embodiment, the analog signal acquisition circuit 1 includes resistors R1, R2, R3, R4, R5, R6, and R7, capacitors C1, C2, and C3, operational amplifier U1, and operational amplifier U2. The first pin of operational amplifier U1 is connected to one end of resistor R1 and one end of resistor R2. The other end of resistor R1 is connected to the initial input signal Vref1. The other end of resistor R2 is connected to the second pin of operational amplifier U1 and grounded. The third pin of operational amplifier U1 is connected to one end of resistor R3. The other end of resistor R3 is connected to the first pin of operational amplifier U2, one end of capacitor C2 and resistor R5. The other end of capacitor C2 is connected to the other end of resistor R5, the third pin of operational amplifier U2 and one end of resistor R6. The fourth pin of operational amplifier U1 is connected to one end of resistor R4. The other end of resistor R4 is connected to one end of resistor R7, one end of capacitor C1 and the second pin of operational amplifier U2. The other end of resistor R7 is connected to the other end of capacitor C1 and grounded. The other end of resistor R6 is connected to one end of capacitor C3 and noise shaping circuit 2. The other end of capacitor C3 is grounded.
[0026] Specifically, the working principle of the analog signal acquisition circuit 1 includes: the initial input signal Vref1 is input to the first pin of operational amplifier U1 via resistor R1, and works with resistor R2, one end of which is connected to the second pin of operational amplifier U1 and the other end is grounded. After preliminary processing by operational amplifier U1, the output signal of its third pin is transmitted to the first pin of operational amplifier U2 via resistor R3, and is also connected to one end of capacitor C2 and resistor R5; the fourth pin of operational amplifier U1 is connected to the second pin of operational amplifier U2 via resistor R4, and the other end of resistor R4 is also connected to one end of resistor R7 and capacitor C1. Resistor R7 and the other end of capacitor C1 are grounded, forming a feedback or filtering structure; after operational amplifier U2 processes the input signal, the output signal of its third pin is fed back via resistor R5 and capacitor C2, and output through resistor R6. After being filtered by capacitor C3 and grounded, the pre-processed analog signal is transmitted to noise shaping circuit 2.
[0027] In one embodiment, operational amplifier U1 is an isolation operational amplifier, which achieves electrical isolation of the initial input signal and performs preliminary buffering processing on the initial input signal. Resistor R7 and capacitor C1 form a first-stage filter circuit. Operational amplifier U2, resistor R5, and capacitor C2 form a second-stage filter circuit. Resistor R6 and capacitor form a third-stage filter circuit. The initial input signal passes through the first-stage filter circuit, the second-stage filter circuit, and the third-stage filter circuit in sequence to convert the initial signal into an analog signal that matches the noise shaping circuit 2.
[0028] In one embodiment, the noise shaping circuit 2 includes resistors R8, R9, R10, R11, R12, R13, and R14, operational amplifiers U3, U4, U5, and U6, transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8. In this configuration, one end of resistor R8 is connected to resistor R6 and the drain of transistor Q3. The source of transistor Q3 is connected to one end of capacitor C8 and the drain of transistor Q4. The source of transistor Q4 is grounded. The other end of capacitor C8 is connected to the source of transistor Q1 and the drain of transistor Q2. The drain of transistor Q1 is grounded. The gates of transistor Q1 and transistor Q3 are connected. The gates of transistor Q2 and transistor Q4 are connected. The other end of resistor R8 is connected to the drain of transistor Q7 and the drain of transistor Q8, respectively. The gate of transistor Q7 is connected to one end of resistor R13, the first and third pins of operational amplifier U4, respectively. The source of transistor Q7 is connected to the source of transistor Q2, the first pin of operational amplifier U3, and one end of capacitor C4, respectively. The second pin of operational amplifier U3 is grounded. The other end of capacitor C4 is connected to one end of resistor R9 and the third pin of operational amplifier U3, respectively. The other end of resistor R9 is connected to the second pin of operational amplifier U4 and one end of capacitor C5, respectively. The other end of capacitor C5 is grounded. The other end of resistor R13 is connected to the first pin of operational amplifier U6 and one end of resistor R14, respectively. One end of the resistor R14 is connected to the third pin of the operational amplifier U6, the gate of the transistor Q8, and the successive approximation analog-to-digital converter 3. The second pin of the operational amplifier U6 is connected to the gate of the transistor Q5, the gate of the transistor Q6, and the third pin of the operational amplifier U5. The first pin of the operational amplifier U5 is connected to the resistors R10 and R12. The other end of the resistor R12 is grounded. The other end of the resistor R10 is connected to one end of the resistor R11 and connected to the reference level input Vref2. The other end of the resistor R11 is connected to the second pin of the operational amplifier U5, the drain of the transistor Q5, and the drain of the transistor Q6. The source of the transistor Q5 is connected to the source of the transistor Q6 and grounded.
[0029] In one embodiment, operational amplifier U3, capacitor C4, and resistor R9 form an integrating circuit to integrate the input signal. Transistors Q1, Q2, Q3, and Q4, along with capacitor C8, form a switched capacitor structure for sampling or storing the input signal.
[0030] Specifically, the working principle of noise shaping circuit 2 includes: a switched capacitor structure consisting of transistors Q1, Q2, Q3, Q4, and capacitor C8 is used to sample or store the input signal; resistor R8 connects the drain of the preceding circuit to the drain of transistors Q7 and Q8; operational amplifier U3, capacitor C4, and resistor R9 form an integrating circuit to integrate the input signal; operational amplifier U4 further processes the integrated signal, and its output is transmitted to the subsequent circuit through resistor R13, controlling the gate of transistor Q7; operational amplifier U5, along with resistors R10, R11, and R12... A comparison or reference level processing circuit is formed, receiving the reference level Vref2 and outputting a signal to control the gates of transistors Q5 and Q6. Transistors Q5 and Q6 are used to switch and control the current or voltage in the circuit. Operational amplifier U6 and resistor R14 form an amplification or feedback circuit, and its output is connected to the successive approximation analog-to-digital converter 3 and the gate of transistor Q8 to achieve the final conditioning and output of the signal. Transistors Q7 and Q8, in cooperation with the various operational amplifiers and resistors, realize the signal path selection and level control. The whole system performs noise shaping through integration, comparison, feedback and other operations to improve the performance of the SAR ADC.
[0031] In this circuit, transistors Q1-Q4 and capacitor C8 form a switched-capacitor structure, which, together with resistor R8, receives the pre-processed analog signal. Operational amplifier U3, capacitor C4, and resistor R9 form an integrator circuit to integrate the signal and accumulate noise energy. Operational amplifier U4 further conditions the integrated signal and transmits it to subsequent circuits through resistor R13. Operational amplifier U5, resistors R10-R12, and reference level Vref2 form a reference circuit to control the switching states of transistors Q5-Q6 to provide a feedback reference. Operational amplifier U6 and resistor R14 form a feedback loop, feeding back the output of successive approximation analog-to-digital converter 3 to transistors Q7-Q8 to adjust the signal path and gain. Through the synergistic effect of integration, reference comparison, and feedback adjustment, a closed feedback loop is formed, pushing the quantization noise energy away from the effective bandwidth and ultimately generating a noise-shaped analog signal.
[0032] In one embodiment, the clock control circuit 4 includes a non-inverting buffer U7, a logic NOT gate U8, a dual-channel selector U9, a comparator U10, a resistor R16, a resistor R15, a capacitor C5, and a capacitor C7. The non-inverting buffer U7 is connected to one end of the NOT gate U8, the first pin of the dual-channel selector U9, and one end of the resistor R15. The other end of the non-inverting buffer U7 is connected to the clock signal Vref3. The other end of the NOT gate U8 is connected to the second pin of the dual-channel selector U9 and one end of the resistor R16. The other end of the resistor R16 is connected to the first pin of the comparator U10 and one end of the capacitor C6. The other end of the capacitor C6 is grounded. The other end of the resistor R15 is connected to the second pin of the comparator U10 and the capacitor C7. One end of the capacitor C7 is connected to the ground, and the other end of the capacitor C7 is grounded. The third pin of the comparator U10 is connected to the third pin of the dual-channel selector U9. The fourth pin of the dual-channel selector U9 is connected to the successive approximation analog-to-digital converter 3. Resistor R16 and capacitor C6, and resistor R15 and capacitor C7 respectively form two RC filter circuits to perform timing or phase conditioning on the clock signal Vref3. The output of the comparator U10 is fed back to the dual-channel selector U9, which selects the clock signal path and coordinates the clock signal through the clock signal path. The coordinated clock signal is then output to the successive approximation analog-to-digital converter 3.
[0033] Specifically, the working principle of the clock control circuit 4 includes: the clock signal Vref3 is input to the non-inverting buffer U7, and after processing, it is connected to one end of the NOT gate U8, the first pin of the dual-channel selector U9, and one end of the resistor R15; after the NOT gate U8 inverts the signal, its output is connected to the second pin of the dual-channel selector U9 and one end of the resistor R16; the resistor R16 and capacitor C6, and the resistor R15 and capacitor C7 respectively form two RC filter circuits, which perform timing or phase conditioning on the corresponding signals and input them to the first and second pins of the comparator U10; the comparator U10 feeds back the output of the two signals to the third pin of the dual-channel selector U9, and the dual-channel selector U9 selects the clock signal path according to the feedback. The coordinated clock signal is output to the successive approximation analog-to-digital converter 3 through the fourth pin, realizing the timing logic coordination of each circuit module.
[0034] To facilitate understanding of the above technical solutions of the present invention, the working principle or operation method of the present invention in actual process will be described in detail below.
[0035] In practical applications, the analog signal acquisition circuit 1 receives the initial input signal and preprocesses it using a circuit composed of internal resistors, capacitors, and operational amplifiers, converting the initial signal into an analog signal compatible with the noise shaping circuit 2. The noise shaping circuit 2 receives the preprocessed analog signal and uses a feedback loop consisting of integration, comparison, and feedback operations to perform spectrum shaping on the quantization noise in the signal, pushing the noise energy away from the effective bandwidth and generating a noise-shaped analog signal. Under clock control, the successive approximation analog-to-digital converter 3, based on the successive approximation principle, generates a reference voltage through its internal DAC and compares it bit by bit with the noise-shaped analog signal, gradually completing the conversion from analog signal to digital signal from the most significant bit to the least significant bit. The clock control circuit 4 buffers, inverts, performs RC filtering, and compares the input clock signal, selects an appropriate clock path using a dual-channel selector, and outputs a coordinated clock signal to synchronously control the operating timing of the analog signal acquisition circuit 1, the noise shaping circuit 2, and the successive approximation analog-to-digital converter 3, ensuring the orderly operation of the entire ADC system.
[0036] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "setting," "connection," "fixing," "screw connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.
[0037] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A timing logic control circuit for a noise-shaping SAR ADC, characterized by, The timing logic control circuit comprises: An analog signal acquisition circuit (1) is configured to receive an initial input signal and perform preprocessing to convert the initial signal into an analog signal suitable for a noise shaping circuit (2); The noise shaping circuit (2) is configured to perform frequency spectrum shaping on quantization noise in the analog signal, and push the noise energy away from the effective bandwidth through a feedback loop to generate an analog signal after noise shaping; A successive approximation type analog-digital converter (3) is configured to generate a reference voltage through an internal DAC based on the successive approximation principle, and perform bit-by-bit comparison with the analog signal after noise shaping to gradually complete the conversion of the analog signal into a digital signal from the highest bit to the lowest bit; A clock control circuit (4) is configured to coordinate the timing logic among the analog signal acquisition circuit (1), the noise shaping circuit (2) and the successive approximation type analog-digital converter (3); The analog signal acquisition circuit (1) is electrically connected with the noise shaping circuit (2), the noise shaping circuit (2) is electrically connected with the successive approximation type analog-digital converter (3), and the successive approximation type analog-digital converter (3) is electrically connected with the clock control circuit (4).
2. The timing logic control circuit for a noise-shaping SAR ADC of claim 1, wherein, The analog signal acquisition circuit (1) comprises resistors R1, R2, R3, R4, R5, R6, R7, capacitors C1, C2, C3, an operational amplifier U1 and an operational amplifier U2; The first pin of the operational amplifier U1 is connected with one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is connected with an initial input signal Vref1, the other end of the resistor R2 is connected with the second pin of the operational amplifier U1 and grounded, the third pin of the operational amplifier U1 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the first pin of the operational amplifier U2, one end of the capacitor C2 and one end of the resistor R5, the other end of the capacitor C2 is connected with the other end of the resistor R5, the third pin of the operational amplifier U2 and one end of the resistor R6, the fourth pin of the operational amplifier U1 is connected with one end of the resistor R4, the other end of the resistor R4 is connected with one end of the resistor R7, one end of the capacitor C1 and the second pin of the operational amplifier U2, the other end of the resistor R7 is connected with the other end of the capacitor C1 and grounded, the other end of the resistor R6 is connected with one end of the capacitor C3 and the noise shaping circuit (2), and the other end of the capacitor C3 is grounded.
3. The timing logic control circuit for a noise-shaping SAR ADC of claim 2, wherein, The operational amplifier U1 is an isolation operational amplifier, which realizes electrical isolation of the initial input signal and performs preliminary buffering of the initial input signal.
4. The timing logic control circuit for a noise-shaping SAR ADC of claim 3, wherein, The resistor R7 and the capacitor C1 form a first-stage filter circuit; the operational amplifier U2 and the resistor R5 and the capacitor C2 form a second-stage filter circuit; the resistor R6 and the capacitor form a third-stage filter circuit, and the initial input signal is sequentially filtered by the first-stage filter circuit, the second-stage filter circuit and the third-stage filter circuit, so as to convert the initial signal into an analog signal adapted to the noise shaping circuit (2).
5. The timing logic control circuit for a noise-shaping SAR ADC of claim 1, wherein, The noise shaping circuit (2) comprises a resistor R8, a resistor R9, a resistor R10, a resistor R11, a resistor R12, a resistor R13, a resistor R14, an operational amplifier U3, an operational amplifier U4, an operational amplifier U5, an operational amplifier U6, a transistor Q1, a transistor Q2, a transistor Q3, a transistor Q4, a transistor Q5, a transistor Q6, a transistor Q7 and a transistor Q8. One end of the resistor R8 is connected with the resistor R6 and the drain of the transistor Q3, the source of the transistor Q3 is connected with one end of the capacitor C8 and the drain of the transistor Q4, the source of the transistor Q4 is grounded, the other end of the capacitor C8 is connected with the source of the transistor Q1 and the drain of the transistor Q2, the drain of the transistor Q1 is grounded, the gate of the transistor Q1 is connected with the transistor Q3, and the gate of the transistor Q2 is connected with the transistor Q4. The other end of the resistor R8 is connected with the drain of the transistor Q7 and the drain of the transistor Q8 respectively, the gate of the transistor Q7 is connected with the one end of the resistor R13, the first pin and the third pin of the operational amplifier U4 respectively, the source of the transistor Q7 is connected with the source of the transistor Q2, the first pin of the operational amplifier U3 and the one end of the capacitor C4 respectively, the second pin of the operational amplifier U3 is grounded, the other end of the capacitor C4 is connected with the one end of the resistor R9 and the third pin of the operational amplifier U3 respectively, the other end of the resistor R9 is connected with the second pin of the operational amplifier U4 and the one end of the capacitor C5 respectively, the other end of the capacitor C5 is grounded, the other end of the resistor R13 is connected with the first pin of the operational amplifier U6 and the one end of the resistor R14 respectively, the other end of the resistor R14 is connected with the third pin of the operational amplifier U6 and the gate of the transistor Q8 and the successive approximation analog-to-digital converter (3) respectively, the second pin of the operational amplifier U6 is connected with the gate of the transistor Q5, the gate of the transistor Q6 and the third pin of the operational amplifier U5 respectively, the first pin of the operational amplifier U5 is connected with the resistor R10 and the resistor R12 respectively, the other end of the resistor R12 is grounded, the other end of the resistor R10 is connected with the one end of the resistor R11 and inputs a reference level Vref2, the other end of the resistor R11 is connected with the second pin of the operational amplifier U5, the drain of the transistor Q5 and the drain of the transistor Q6, the source of the transistor Q5 is connected with the source of the transistor Q6 and grounded.
6. The timing logic control circuit for a noise-shaping SAR ADC of claim 5, wherein, The operational amplifier U3, the capacitor C4 and the resistor R9 constitute an integration circuit, and the input signal is integrated by the integration circuit.
7. The timing logic control circuit for a noise-shaping SAR ADC of claim 6, wherein, The transistor Q1, the transistor Q2, the transistor Q3, the transistor Q4 and the capacitor C8 form a switched capacitor structure, which is used for sampling or charge storage of the input signal.
8. The timing logic control circuit for a noise-shaping SAR ADC of claim 1, wherein, The clock control circuit (4) comprises a same direction buffer U7, a logic NOT gate U8, a two-way gate U9, a comparator U10, a resistor R16, a resistor R15, a capacitor C5 and a capacitor C7. The non-inverting buffer U7 is connected with one end of the logic NOT gate U8, the first pin of the dual gate U9 and one end of the resistor R15, the other end of the non-inverting buffer U7 is connected with the clock signal Vref3, the other end of the logic NOT gate U8 is connected with the second pin of the dual gate U9 and one end of the resistor R16, the other end of the resistor R16 is connected with the first pin of the comparator U10 and one end of the capacitor C6, the other end of the capacitor C6 is grounded, the other end of the resistor R15 is connected with the second pin of the comparator U10 and one end of the capacitor C7, the other end of the capacitor C7 is grounded, the third pin of the comparator U10 is connected with the third pin of the dual gate U9, the fourth pin of the dual gate U9 is connected with the successive approximation analog-to-digital converter (3).
9. The timing logic control circuit for a noise-shaping SAR ADC of claim 8, wherein, The resistor R16 and the capacitor C6, the resistor R15 and the capacitor C7 respectively constitute two RC filter circuits to realize the timing or phase conditioning of the clock signal Vref3.
10. The timing logic control circuit for a noise-shaping SAR ADC of claim 9, wherein, The output of the comparator U10 is fed back to the dual gate U9, the clock signal path is selected by the dual gate U9, the clock signal is coordinated through the clock signal path, and the coordinated clock signal is output to the successive approximation analog-to-digital converter (3).