Multi-channel time-to-digital converter with on-chip optical noise suppression function

Abstract

The invention discloses a multi-channel time-to-digital converter with an on-chip optical noise suppression function, and belongs to the technical field of photon time-of-flight distance measurement. The multi-channel TDC circuit and the histogram circuit form a closed-loop feedback structure, invalid signals caused by dark counting and ambient light noise can be effectively shielded in a chip, the false triggering probability is reduced, and the distance measuring precision and the circuit efficiency are remarkably improved. The multi-channel TDC circuit comprises a control circuit, a multi-channel VCO circuit, a counter, an encoder and a selection circuit, and extraction and feedback of effective photon data are achieved by combining peak detection, storage and calibration mechanisms of the histogram circuit. The structure supports a single-event response mode and a multi-event response mode, noise data is dynamically suppressed according to a histogram feedback threshold value, high-precision distance measurement is kept, meanwhile, overall power consumption is reduced, the frame rate is improved, and adaptability in a high-dynamic, multi-target and low-power-consumption application scene is enhanced. The method can be widely applied to the fields of intelligent wearing, automatic driving and Internet of Things.

Description

Technical Field

[0001] This invention relates to the field of photon time-of-flight ranging technology, and in particular to a multi-channel time-to-digital converter with on-chip suppression of optical noise. Background Technology

[0002] A ToF (Time-of-Flight) sensor is a distance detection sensor based on the principle of photon time-of-flight measurement. It calculates the distance between the sensor and the target by precisely calculating the time it takes for a photon to travel from its emission to the target object and back to the receiver. It has been widely used in various fields such as smart wearable devices, autonomous driving systems, and the Internet of Things (IoT).

[0003] ToF sensors primarily consist of a Time-to-Digital Converter (TDC) and a front-end detection device. The detection device is typically a single-photon avalanche diode (SPAD), a key component of the receiver capable of detecting individual photons with extremely high sensitivity. However, due to its structure and manufacturing process, it can generate voltage pulses even in the absence of light, a phenomenon known as "dark counting." These dark counting pulses can easily be misinterpreted by subsequent circuits as valid photon response signals, leading to false triggering of the TDC circuit. Similarly, stray light or background light in the environment can interfere with the detection device, further increasing the probability of TDC false triggering and thus reducing the sensor's ranging accuracy.

[0004] To improve the ranging accuracy of ToF sensors, the current mainstream solution is an optimization scheme based on histogram statistics.

[0005] This scheme divides the original complete data into multiple segments, extracts the peak value of each segment through histogram statistics, and then combines the peak values ​​of multiple segments. Since the data processed by this scheme is quantized by TDC (Time-Digital Converter), it cannot suppress a large number of invalid triggers caused by dark counting or ambient light at the TDC front end. The TDC will still continuously output a large amount of invalid data and transmit it to the histogram module for statistical processing, leading to an increase in overall system power consumption, which is detrimental to the deployment of ToF sensors in low-power application scenarios. Furthermore, in the traditional architecture combining TDC and histogram circuitry, only one echo signal can be responded to per ranging cycle. In applications with high dynamic range, multi-target scenarios, or strict requirements for high frame rates, the system is prone to problems such as response lag and information loss, making it difficult to meet the dual requirements of real-time performance and accuracy. Summary of the Invention

[0006] To address the shortcomings and deficiencies of existing technologies, this invention proposes a multi-channel time-to-digital converter (TDC) with on-chip optical noise suppression. It innovatively integrates the TDC with a histogram circuit to form a feedback loop, effectively improving the TDC circuit's anti-interference capability. Employing a novel multi-channel voltage-controlled oscillator (VCO), it can adapt to diverse needs in various application environments. While improving data acquisition efficiency, it reduces system power consumption and enhances adaptability and scalability across different application scenarios.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] This solution proposes a multi-channel time-to-digital converter (TDC) with on-chip optical noise suppression. Its overall framework includes a multi-channel TDC circuit and a histogram circuit. The input terminals MOD, Vctrl, START, END, and STOP of the multi-channel TDC circuit are from external inputs, and the input terminal Th<2:0> is fed back by the histogram. Its output terminals DATA<7:0> and FINE<3:0> are connected to the input terminals DIN<7:0> and DIN<11:8> of the histogram circuit, respectively. The histogram output terminals are OUT<11:0> and a threshold signal Th<2:0>. OUT<11:0> is output as the final time measurement result to the external circuit, while Th<2:0> is fed back to the multi-channel TDC circuit to achieve noise shielding and threshold control.

[0009] The histogram circuit has inputs of DIN<7:0> and DIN<11:8>, and outputs of OUT<11:0> and Th<2:0>. It includes a peak detection circuit, histogram memory 1, histogram memory 2, histogram memory 3, a peak calibration combination circuit, and a three-bit subtractor. Inputs DIN<7:0> and DIN<11:8> are connected to the peak detection circuit to obtain DIN<11:0>. The peak detection circuit processes DIN<11:8>, DIN<7:4>, and DIN<3:0> and outputs them to histogram memory 1, histogram memory 2, and histogram memory 3, respectively. Histogram memory 1, histogram memory 2, and histogram memory 3 output the accumulated peak values ​​PEAK1<3:0>, PEAK2<3:0>, and PEAK3<3:0> to the peak calibration combination circuit. The peak calibration combination circuit outputs OUT<11:0> to the off-chip and outputs the high three bits OUT<11:9> of OUT<11:0> to the three-bit subtractor. The Th<2:0> signal is output by the three-bit subtractor.

[0010] The multi-channel TDC circuit has inputs of MOD, Th<2:0>, Vctrl, START, END, and STOP; and outputs of DATA<7:0> and FINE<3:0>. MOD is an externally input level signal that controls the circuit's operating mode; Th<2:0> is the threshold signal fed back to the multi-channel TDC circuit from the histogram circuit; Vctrl is an externally input control signal that controls the internal clock frequency; START and END are externally input control signals; and STOP is the pulse signal output by the external SPAD circuit after receiving the echo photon. The multi-channel TDC circuit consists of a control circuit, a multi-channel VCO circuit, counters, an encoder, and a selection circuit, with the three counters denoted as C1, C2, and C3.

[0011] The input terminals of the control circuit inside the multi-channel TDC circuit are MOD, START, END, STOP, and STOPEN, and the output terminals are EN1, EN2, and EN3. Among them, MOD, START, and END are external input signals; Th<2:0> is connected to the output terminal Th<2:0> of the histogram circuit; the STOPEN terminal is connected to the STOPEN terminal of the three counters; and the STOP signal is connected to the external STOP port.

[0012] The selection circuit inputs of the multi-channel TDC circuit are FINE1<3:0>, FINE2<3:0>, FINE3<3:0>, DATA1<7:0>, DATA2<7:0>, and DATA3<7:0>; the outputs are DATA<7:0> and FINE<3:0>. The inputs FINE1<3:0>, FINE2<3:0>, and FINE3<3:0> are connected to the encoder output F<3:0> and the multi-channel VCO outputs PHASE<11:8> and PHASE<15:12>, respectively. The inputs DATA1<7:0>, DATA2<7:0>, and DATA3<7:0> are connected to the outputs B<7:0> of counters C1, C2, and C3, respectively. The outputs DATA<7:0> and FINE<3:0> serve as the outputs of the multi-channel TDC circuit and are connected to the histogram circuit inputs DIN<7:0> and DIN<11:8>.

[0013] The input terminals of the multi-channel VCO circuit inside the multi-channel TDC circuit are Vctrl, VCOEN1, VCOEN2, VCOEN3, and SAMPLE; the output terminals are CLK1, CLK2, CLK3, PHASE<7:0>, PHASE<11:8>, and PHASE<15:12>. Vctrl is the external input control signal; input terminals VCOEN1, VCOEN2, and VCOEN3 are connected to the EN1, EN2, and EN3 terminals of the control circuit, respectively; input terminal SAMPLE and the input terminal STOP of the control circuit are synchronization signals, connected to the output terminal STOP of the SPAD circuit; output terminal CLK1 is connected to the input terminal CLK of counter C1; output terminal CLK2 is connected to the input terminal CLK of counter C2; output terminal CLK3 is connected to the input terminal CLK of counter C3; output terminal PHASE<7:0> is connected to the input terminal P<7:0> of the encoder; output terminals PHASE<11:8> and PHASE<15:12> are connected to the input terminals FINE2<3:0> and FINE3<3:0> of the selection circuit, respectively.

[0014] The input terminals of the counter inside the multi-channel TDC circuit are CLK, Th<2:0>, and START; the output terminals are B<7:0> and STOPEN. The input terminals START of counters C1, C2, and C3 are synchronization signals, input from an external signal. The Th<2:0> terminals of counters C1, C2, and C3 are also synchronization signals, connected to the output terminal Th<2:0> of the histogram. The input terminals CLK of counters C1, C2, and C3 are connected to the output terminals CLK1, CLK2, and CLK3 of the multi-channel VCO circuit, respectively. The output terminal STOPEN of counters C1, C2, and C3 is a synchronization signal, connected to the STOPEN terminal of the control circuit. The output terminal B<7:0> of counter C1 is connected to the input terminal DATA1<7:0> of the selection circuit; the output terminal B<7:0> of counter C2 is connected to the input terminal DATA2<7:0> of the selection circuit; and the output terminal B<7:0> of counter C3 is connected to the input terminal DATA3<7:0> of the selection circuit.

[0015] The encoder input terminal of the multi-channel TDC circuit is P<7:0>, and the output terminal is F<3:0>. The input terminal P<7:0> is connected to the output terminal PHASE<7:0> of the multi-channel VCO circuit; the output terminal F<3:0> is connected to the input terminal FINE1<3:0> of the selection circuit.

[0016] Furthermore, the multi-channel VCO circuit inside the multi-channel TDC circuit includes 16 differential units and 16 SAFF sampling circuits. The 16 differential units are respectively denoted as PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, and PD15, and the 16 SAFF sampling circuits are respectively denoted as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15. The 16 differential units and 16 SAFF sampling circuits form three oscillation loops: PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7 together with S0, S1, S2, S3, S4, S5, S6, S7 form loop 1; PD8, PD9, PD10, PD11 together with S8, S9, S10, S11 form loop 2; and PD12, PD13, PD14, PD15 together with S12, S13, S14, S15 form loop 3. In loop 1, the output VOUT+ of PD0 is connected to the input D of S0 and the input VIN+ of PD1; the output VOUT- of PD0 is connected to the input DN of S0 and the input VIN- of PD1; the output VOUT+ of PD1 is connected to the input D of S1 and the input VIN+ of PD2; the output VOUT- of PD1 is connected to the input DN of S1 and the input VIN- of PD2; PD0-PD7 and S0-S7 are connected in this order, which will not be described in detail; in the last stage, the output VOUT+ of PD7 is connected to the input D of S7 and the input VIN- of PD0; the output VOUT- of PD7 is connected to the input DN of S7 and the input VIN+ of PD0, thus completing the construction of loop 1. In loop 2, the output VOUT+ of PD8 is connected to the input D of S8 and the input VIN+ of PD9; the output VOUT- of PD8 is connected to the input DN of S8 and the input VIN- of PD9; the output VOUT+ of PD9 is connected to the input D of S9 and the input VIN+ of PD10; the output VOUT- of PD9 is connected to the input DN of S9 and the input VIN- of PD10; PD8-PD11 and S8-S11 are connected in this order, which will not be described in detail; in the last stage, the output VOUT+ of PD11 is connected to the input D of S11 and the input VIN- of PD8; the output VOUT- of PD11 is connected to the input DN of S11 and the input VIN+ of PD8, thus completing the construction of loop 2.In loop 3, the output VOUT+ of PD12 is connected to the input D of S12 and the input VIN+ of PD13; the output VOUT- of PD12 is connected to the input DN of S12 and the input VIN- of PD13; the output VOUT+ of PD13 is connected to the input D of S13 and the input VIN+ of PD14; the output VOUT- of PD13 is connected to the input DN of S13 and the input VIN- of PD14; PD12-PD15 are connected to S12-S15 in this order, which will not be described in detail; in the last stage, the output VOUT+ of PD15 is connected to the input D of S15 and the input VIN- of PD12; the output VOUT- of PD15 is connected to the input DN of S15 and the input VIN+ of PD12, thus completing the construction of loop 3. The input terminals of the multi-channel VCO circuit include Vctrl, VCOEN1, VCOEN2, VCOEN3, and SAMPLE; the output terminals are CLK1, CLK2, CLK3, PHASE<7:0>, PHASE<11:8>, and PHASE<15:12>. Vctrl and SAMPLE are global signals that simultaneously control three oscillation loops; VCOEN1, VCOEN2, and VCOEN3 are the enable signals for loop 1, loop 2, and loop 3, respectively. In loop 1, the output terminal VOUT+ of PD4 is selected as the output terminal CLK1 of the multi-channel VCO circuit, and the output terminals Q of S1, S2, S3, S4, S5, S6, and S7 are selected as the output signal PHASE<7:0>. In loop 2, the output terminal VOUT+ of PD9 is selected as the output terminal CLK2 of the multi-channel VCO circuit, and the output terminals Q of S8, S9, S10, and S11 are selected as the output signal PHASE<8:11>. In loop 3, the output terminal VOUT+ of PD13 is selected as the output terminal CLK3 of the multi-channel VCO circuit, and the output terminals Q of S12, S13, S14, and S15 are selected as the output signal PHASE<15:12>. In the multi-channel VCO circuit, PD0-PD15 all adopt the same differential structure. To ensure that the frequencies of loop 2 and loop 3 are consistent, the MOS transistors inside the differential units used in loop 2 and loop 3 are of the same size.

[0017] The differential unit includes 6 PMOS transistors and 3 NMOS transistors; the 6 PMOS transistors are designated M1, M2, M3, M4, M5, and M6; the 3 NMOS transistors are designated M7, M8, and M9. The upper 6 transistors are PMOS transistors (M1–M6), and the lower 3 transistors are NMOS transistors (M7–M9). M1 and M2 form a cross-coupled positive feedback structure. The source of M1 is connected to VDD, the drain to VOUT+, and the gate to VOUT-; the source of M2 is connected to VDD, the drain to VOUT-, and the gate to VOUT+. This combination enhances the switching speed and stability of the circuit. M3 and M4 are delay control transistors, with their sources connected to VDD, drains connected to VOUT+ and VOUT- respectively, and gates connected to the common control voltage VC for adjusting the delay. M5 and M6 are constant current source PMOS transistors, with their sources connected to VDD and gates grounded. The drains of M5 and M6 are connected to the VOUT+ and VOUT- nodes respectively, providing bias current for the differential output. M7 and M8 form a differential pair, with their sources connected to a common point and then to the drain of current source M9. The gate of M7 is connected to VIN+, and the gate of M8 is connected to VIN-. The drains of M7 and M8 are connected to VOUT+ and VOUT- respectively. M9 is a tail current source transistor, with its drain connected to the common point of the sources of M7 and M8, its source grounded, and its gate controlled by the control signal VCO_EN, acting as an on / off switch for the circuit. The entire circuit structure amplifies the input signal through the differential pair and controls the delay through the cross-positive feedback and VC above, realizing the function of a voltage-controlled delay unit.

[0018] The SAFF sampling circuit includes 9 PMOS transistors, 5 NMOS transistors, and 2 inverters. The 9 PMOS transistors are designated M10-M18, the 5 NMOS transistors are designated M19-M23, and the inverters are designated INV1 and INV2. The power supply VDD is located at the top of the circuit. The SAMPLE control signal is connected to the gates of M10, M13, and M23. Specifically, the source of M10 is connected to VDD, and its drain is connected to the drain node of M11, used to control the pre-charge of the left branch; the source of M13 is connected to VDD, and its drain is connected to the drain node of M12, used to control the pre-charge of the right branch. M23 is an NMOS transistor with its source grounded and its drain connected to the common differential node between M21 and M22, completing the pre-discharge during the sampling phase. The data input terminal D is connected to the gate of M21, and DN is connected to the gate of M22; M21 and M22 are both NMOS transistors with their sources connected together, and their drains connected to the drains of M16 and M17 respectively. The sources of M16 and M17 in the differential pair are connected to the drains of M11 and M12, respectively. M11 and M12 are PMOS transistors with their sources connected to VDD, forming a basic differential amplifier structure. Based on this, M14 and M15 form a cross-positive feedback unit: M14 is a PMOS transistor with its source connected to VDD, and its gate connected to the common node where the source of M17 and the drain of M12 are connected; the drain of M15 is also connected to the pull-down network of the subsequent stage. In the pull-down path, the drain of M15 is connected to the drain of M19, which is an NMOS transistor with its source connected to the drain of M20, and the source of M20 is grounded. M19 and M20 form a cascaded pull-down path, enhancing latch stability. M20 helps the circuit quickly complete the decision by controlling the pull-down current. Finally, the voltage on the drain of M15 is buffered by the inverter INV2 to obtain the OUT signal.

[0019] The counter inside the multi-channel TDC circuit includes a D flip-flop DFF1, a 2-to-1 selector MUX1, an asynchronous counting circuit composed of eight D flip-flops, and a three-digit comparator composed of gate circuits. The inputs are CLK, Th<2:0>, and START; the outputs are B<7:0> and STOPEN. The input CK of DFF1 is connected to the external input START signal, and the output Q is connected to the input D and the output Q is connected to the SEL terminal of MUX1. Port 0 of MUX1 is grounded, and port 1 is connected to the external input clock signal CLK (generated by the multi-channel VCO circuit). The output OUT of MUX1 is connected to the asynchronous counting circuit composed of eight D flip-flops; the asynchronous counting circuit is not described in detail here. The outputs of the asynchronous counting circuit are B<7:0>, where B... <7> B <6> B <5> Connect to a three-digit comparator. The inputs of the three-digit comparator are Th<2:0> and B<7:5>, where Th<2:0> is fed back from the histogram. <2> Connected to one input of NAND1 and AND4, Th <1> Connected to one input of NAND2 and AND6, Th <0> Connect to port 1 of MUX2; B <7> Connect to another input of NAND1 and one input of AND3, B <6> Connect to another input of NAND2 and one input of AND5, B <5> Connect to the SEL terminal of MUX2. The output of NAND1 is connected to the other input of AND3 and AND4; the output of NAND2 is connected to the other input of AND5 and AND6; the output of AND3 is connected to one input of NOR1 and OR1; the output of AND4 is connected to the other input of NOR1; the output of AND5 is connected to one input of AND7 and NOR2; the output of AND6 is connected to the other input of NOR2; the output of NOR1 is connected to the other input of AND7 and one input of AND8; the output of NOR2 is connected to the other input of AND8; the output of AND7 is connected to the other input of OR1; the output of AND8 is connected to one input of AND9; input 1 of MUX2 is connected to Th... <0> Input terminal 0 is grounded, and output terminal OUT is connected to the other input terminal of AND9. The output terminals of AND9 and OR1 are respectively connected to the two input terminals of OR2, and the output terminal of OR2 is the output signal STOP_EN. During the operation of the comparator, the two most significant bits are compared first. When the first two input signals B<7:6> are greater than the threshold Th<2:1>, OR1 outputs a high level, and the STOP_EN signal is directly set to a high level; if the first two signals are equal, OR1 outputs a low level, AND8 outputs a high level, and at this time, only the least significant bit signal B needs to be compared. <5> With threshold Th <0> Size.When B <5> When it is high, it indicates that B <5> It must be greater than or equal to Th <0> At this time, the MUX outputs a high level, and the STOP_EN signal also outputs a high level.

[0020] Beneficial effects:

[0021] (1) Reduced overall power consumption: This invention effectively shields optical noise and some dark counting at the TDC circuit level, significantly reducing the probability of false triggering of the TDC circuit, thereby improving the overall circuit efficiency. Compared with the traditional "TDC + histogram" combination structure, this invention can significantly reduce power consumption while maintaining ranging accuracy.

[0022] (2) Improved ToF ranging frame rate: Due to the improved robustness of the TDC circuit output, the number of accumulation steps required by the histogram circuit is significantly reduced, thus improving data processing efficiency. Furthermore, in multi-channel mode, this invention supports dual-channel ranging, effectively improving the overall frame rate of the system.

[0023] (3) Improve the accuracy of ToF ranging: By shielding optical noise at the TDC level, the present invention can transmit more reliable data to the histogram circuit, making the effective peak in the histogram more prominent, thereby improving the accuracy and stability of the final ranging result. Attached Figure Description

[0024] Figure 1 This is an overall block diagram of the present invention.

[0025] Figure 2 This is a histogram circuit block diagram of the present invention.

[0026] Figure 3 This is a block diagram of the multi-channel TDC circuit of the present invention.

[0027] Figure 4 This is a structural diagram of the multi-channel VCO circuit within the multi-channel TDC circuit of the present invention.

[0028] Figure 5 This is a differential unit structure diagram of the multi-channel VCO circuit of the present invention.

[0029] Figure 6 This is a structural diagram of the SAFF sampling circuit used in the multi-channel VCO circuit of the present invention.

[0030] Figure 7 This is a block diagram of the architecture of the presettable counter in the multi-channel TDC circuit of the present invention.

[0031] Figure 8 The circuit timing diagrams are shown for channel 1 in mode 1 and for channels 2 and 3 in mode 2. Detailed Implementation

[0032] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0033] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown, this embodiment provides a multi-channel time-to-digital converter with on-chip optical noise suppression, including:

[0034] Reference Figure 1 The input terminals MOD, Vctrl, START, END, and STOP of the multi-channel TDC circuit are from external inputs, and the input terminal Th<2:0> is fed back by the histogram circuit. Its output terminals DATA<7:0> and FINE<3:0> are connected to the input terminals DIN<7:0> and DIN<11:8> of the histogram circuit, respectively. The histogram output terminals are OUT<11:0> and the threshold signal Th<2:0>. OUT<11:0> is output to the external chip as the final time measurement result, and Th<2:0> is fed back to the multi-channel TDC circuit to achieve noise shielding and threshold control.

[0035] Reference Figure 2 The input terminals of the aforementioned histogram circuit are DIN<7:0> and DIN<11:8>; the output terminals are OUT<11:0> and Th<2:0>. It consists of a peak detection circuit, histogram memory 1, histogram memory 2, histogram memory 3, a peak calibration combination circuit, and a three-bit subtractor. The input terminals DIN<7:0> and DIN<11:8> are connected to the peak detection circuit to obtain DIN<11:0>. The peak detection circuit processes DIN<11:8>, DIN<7:4>, and DIN<3:0> and outputs them to histogram memory 1, histogram memory 2, and histogram memory 3, respectively. Histogram memory 1, histogram memory 2, and histogram memory 3 output the accumulated peak values ​​PEAK1<3:0>, PEAK2<3:0>, and PEAK3<3:0> to the peak calibration combination circuit. The peak calibration combination circuit outputs OUT<11:0> to the off-chip and outputs the high three bits OUT<11:9> of OUT<11:0> to the three-bit subtractor. The Th<2:0> signal is output by the three-bit subtractor.

[0036] Reference Figure 1 , Figure 3 The aforementioned multi-channel TDC circuit has inputs of MOD, Th<2:0>, Vctrl, START, END, and STOP; and outputs of DATA<7:0> and FINE<3:0>. MOD is an externally input level signal controlling the circuit's operating mode; Th<2:0> is the threshold signal fed back to the multi-channel TDC circuit from the histogram circuit; Vctrl is an externally input control signal controlling the internal clock frequency; START and END are externally input control signals; and STOP is the pulse signal output by the external SPAD circuit after receiving echo photons. As a preferred embodiment of the multi-channel time-to-digital converter with on-chip optical noise suppression as described in this invention, the multi-channel TDC circuit comprises a control circuit, a multi-channel VCO circuit, a counter, an encoder, and a selection circuit, wherein the three counters are denoted as C1, C2, and C3, respectively.

[0037] Reference Figure 3 The input terminals of the above selection circuit are FINE1<3:0>, FINE2<3:0>, FINE3<3:0>, DATA1<7:0>, DATA2<7:0>, and DATA3<7:0>; the output terminals are DATA<7:0> and FINE<3:0>. The input terminals FINE1<3:0>, FINE2<3:0>, and FINE3<3:0> are connected to the encoder output terminal F<3:0> and the multi-channel VCO circuit output terminals PHASE<11:8> and PHASE<15:12>, respectively. The input terminals DATA1<7:0>, DATA2<7:0>, and DATA3<7:0> are connected to the output terminals B<7:0> of counters C1, C2, and C3, respectively. The output terminals DATA<7:0> and FINE<3:0> serve as the outputs of the multi-channel TDC circuit and are connected to the histogram circuit input terminals DIN<7:0> and DIN<11:8>.

[0038] Reference Figure 3The input terminals of the multi-channel VCO circuit inside the aforementioned multi-channel TDC circuit are Vctrl, VCOEN1, VCOEN2, VCOEN3, and SAMPLE; the output terminals are CLK1, CLK2, CLK3, PHASE<7:0>, PHASE<11:8>, and PHASE<15:12>. Vctrl is the external input control signal; input terminals VCOEN1, VCOEN2, and VCOEN3 are connected to the EN1, EN2, and EN3 terminals of the control circuit, respectively; input terminal SAMPLE and input terminal STOP of the control circuit are synchronization signals; output terminal CLK1 is connected to the input terminal CLK of counter C1; output terminal CLK2 is connected to the input terminal CLK of counter C2; output terminal CLK3 is connected to the input terminal CLK of counter C3; output terminal PHASE<7:0> is connected to the input terminal P<7:0> of the encoder; output terminals PHASE<11:8> and PHASE<15:12> are connected to the input terminals FINE2<3:0> and FINE3<3:0> of the selection circuit, respectively.

[0039] The input terminals of the aforementioned counters are CLK, Th<2:0>, and START; the output terminals are B<7:0> and STOPEN. Specifically, the START input terminal of counters C1, C2, and C3 is a synchronization signal, input from an external signal. The Th<2:0> terminal of counters C1, C2, and C3 is also a synchronization signal, connected to the histogram output terminal Th<2:0>. The CLK input terminal of counters C1, C2, and C3 is connected to the output terminals CLK1, CLK2, and CLK3 of the multi-channel VCO circuit, respectively. The STOPEN output terminal of counters C1, C2, and C3 is a synchronization signal, connected to the STOPEN terminal of the control circuit. The B<7:0> output terminal of counter C1 is connected to the DATA1<7:0> input terminal of the selection circuit; the B<7:0> output terminal of counter C2 is connected to the DATA2<7:0> input terminal of the selection circuit; and the B<7:0> output terminal of counter C3 is connected to the DATA3<7:0> input terminal of the selection circuit.

[0040] The encoder's input terminal is P<7:0>, and its output terminal is F<3:0>. The input terminal P<7:0> is connected to the output terminal PHASE<7:0> of the multi-channel VCO circuit; the output terminal F<3:0> is connected to the input terminal FINE1<3:0> of the selection circuit.

[0041] Reference Figure 4The multi-channel VCO circuit inside the aforementioned multi-channel TDC circuit consists of 16 differential units and 16 SAFF sampling circuits. The 16 differential units are denoted as PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, and PD15, respectively, and the 16 SAFF sampling circuits are denoted as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, respectively. The 16 differential units and 16 SAFF sampling circuits form three oscillation loops. PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7 together with S0, S1, S2, S3, S4, S5, S6, S7 form loop 1; PD8, PD9, PD10, PD11 together with S8, S9, S10, S11 form loop 2; and PD12, PD13, PD14, PD15 together with S12, S13, S14, S15 form loop 3. In loop 1, the output VOUT+ of PD0 is connected to the input D of S0 and the input VIN+ of PD1; the output VOUT- of PD0 is connected to the input DN of S0 and the input VIN- of PD1; the output VOUT+ of PD1 is connected to the input D of S1 and the input VIN+ of PD2; the output VOUT- of PD1 is connected to the input DN of S1 and the input VIN- of PD2; PD0-PD7 and S0-S7 are connected in this order, which will not be described in detail; in the last stage, the output VOUT+ of PD7 is connected to the input D of S7 and the input VIN- of PD0; the output VOUT- of PD7 is connected to the input DN of S7 and the input VIN+ of PD0, thus completing the construction of loop 1. In loop 2, the output VOUT+ of PD8 is connected to the input D of S8 and the input VIN+ of PD9; the output VOUT- of PD8 is connected to the input DN of S8 and the input VIN- of PD9; the output VOUT+ of PD9 is connected to the input D of S9 and the input VIN+ of PD10; the output VOUT- of PD9 is connected to the input DN of S9 and the input VIN- of PD10; PD8-PD11 and S8-S11 are connected in this order, which will not be described in detail; in the last stage, the output VOUT+ of PD11 is connected to the input D of S11 and the input VIN- of PD8; the output VOUT- of PD11 is connected to the input DN of S11 and the input VIN+ of PD8, thus completing the construction of loop 2.In loop 3, the output VOUT+ of PD12 is connected to the input D of S12 and the input VIN+ of PD13; the output VOUT- of PD12 is connected to the input DN of S12 and the input VIN- of PD13; the output VOUT+ of PD13 is connected to the input D of S13 and the input VIN+ of PD14; the output VOUT- of PD13 is connected to the input DN of S13 and the input VIN- of PD14; PD12-PD15 are connected to S12-S15 in this order, which will not be described in detail; in the last stage, the output VOUT+ of PD15 is connected to the input D of S15 and the input VIN- of PD12; the output VOUT- of PD15 is connected to the input DN of S15 and the input VIN+ of PD12, thus completing the construction of loop 3. The input terminals of the multi-channel VCO circuit include Vctrl, VCOEN1, VCOEN2, VCOEN3, and SAMPLE; the output terminals are CLK1, CLK2, CLK3, PHASE<7:0>, PHASE<11:8>, and PHASE<15:12>. Vctrl and SAMPLE are global signals that simultaneously control three oscillation loops; VCOEN1, VCOEN2, and VCOEN3 are the enable signals for loop 1, loop 2, and loop 3, respectively. In loop 1, the output terminal VOUT+ of PD4 is selected as the output terminal CLK1 of the multi-channel VCO circuit, and the output terminals Q of S1, S2, S3, S4, S5, S6, and S7 are selected as the output signal PHASE<7:0>. In loop 2, the output terminal VOUT+ of PD9 is selected as the output terminal CLK2 of the multi-channel VCO circuit, and the output terminals Q of S8, S9, S10, and S11 are selected as the output signal PHASE<8:11>. In loop 3, the output terminal VOUT+ of PD13 is selected as the output terminal CLK3 of the multi-channel VCO circuit, and the output terminals Q of S12, S13, S14, and S15 are selected as the output signal PHASE<15:12>. In the multi-channel VCO circuit, PD0-PD15 all adopt the same differential structure. To ensure that the frequencies of loop 2 and loop 3 are consistent, the MOS transistors inside the differential units used in loop 2 and loop 3 are of the same size.

[0042] Reference Figure 5As a preferred embodiment of the multi-channel VCO circuit of the present invention, the differential unit includes 6 PMOS transistors and 3 NMOS transistors; the 6 PMOS transistors are designated M1, M2, M3, M4, M5, and M6; the 3 NMOS transistors are designated M7, M8, and M9. The upper 6 transistors are PMOS transistors (M1–M6), and the lower 3 transistors are NMOS transistors (M7–M9). M1 and M2 form a cross-coupled positive feedback structure. The source of M1 is connected to VDD, the drain to VOUT+, and the gate to VOUT-; the source of M2 is connected to VDD, the drain to VOUT-, and the gate to VOUT+. This combination enhances the switching speed and stability of the circuit. M3 and M4 are delay control transistors, with their sources connected to VDD, drains connected to VOUT+ and VOUT- respectively, and gates connected to the common control voltage VC for adjusting the delay. M5 and M6 are constant current source PMOS transistors, with their sources connected to VDD and gates grounded. The drains of M5 and M6 are connected to the VOUT+ and VOUT- nodes respectively, providing bias current for the differential output. M7 and M8 form a differential pair, with their sources connected to a common point and then to the drain of current source M9. The gate of M7 is connected to VIN+, and the gate of M8 is connected to VIN-. The drains of M7 and M8 are connected to VOUT+ and VOUT- respectively. M9 is a tail current source transistor, with its drain connected to the common point of the sources of M7 and M8, its source grounded, and its gate controlled by the control signal VCO_EN, acting as an on / off switch for the circuit. The entire circuit structure amplifies the input signal through the differential pair and controls the delay through the cross-positive feedback and VC above, realizing the function of a voltage-controlled delay unit.

[0043] Reference Figure 6The SAFF sampling circuit consists of 9 PMOS transistors, 5 NMOS transistors, and 2 inverters. The 9 PMOS transistors are designated M10-M18, the 5 NMOS transistors are designated M19-M23, and the inverters are designated INV1 and INV2. The power supply VDD is located at the top of the circuit, and the sources of all PMOS transistors are connected to VDD. The SAMPLE control signal is connected to the gates of M0, M3, and M13. Specifically, the source of M0 is connected to VDD, and its drain is connected to the source node of M1, used to control the pre-charge of the left branch; the source of M3 is connected to VDD, and its drain is connected to the source node of M2, used to control the pre-charge of the right branch. M13 is an NMOS transistor with its source grounded and its drain connected to the common differential node between M11 and M12, completing the pre-discharge during the sampling phase. The data input terminal D is connected to the gate of M11, and DN is connected to the gate of M12. M11 and M12 are both NMOS transistors, with their sources connected together and their drains connected to the drains of M6 and M7, respectively. M6 and M7 are differential input amplifier transistors; their sources are combined and connected to the drain of M8. M8 acts as a current source, with its source connected to VDD and its gate connected to the bias voltage, providing a stable current bias. The drains of the differential pair M6 and M7 are connected to the drains of M1 and M2, respectively. M1 and M2 are PMOS transistors, with their sources connected to VDD, forming a basic differential amplifier structure. Based on this, M4 and M5 form a cross-positive feedback unit: M4 is a PMOS transistor with its source connected to VDD and its drain connected to the common node of M7 and M2; M5 is a PMOS transistor with its source connected to VDD and its drain connected to the common node of M6 and M1. The drain of M5 is also connected to the pull-down network of the subsequent stage. In the pull-down path, the drain of M5 is connected to the drain of M9. M9 is an NMOS transistor, and its source is connected to the drain of M10. The source of M10 is grounded. M9 and M10 form a cascaded pull-down path, enhancing latch stability. M10 helps the circuit quickly complete the decision by controlling the pull-down current. Finally, the voltage on the drain of M5 is buffered by the inverter INV2 to obtain the OUT signal.

[0044] Reference Figure 7The counter inside the aforementioned multi-channel TDC circuit consists of a D flip-flop DFF1, a 2-to-1 selector MUX1, an asynchronous counting circuit composed of eight D flip-flops, and a three-digit comparator composed of gate circuits. The inputs are CLK, Th<2:0>, and START; the outputs are B<7:0> and STOPEN. The input CK of DFF1 is connected to the external input START signal, and the output Q is connected to the input D and the output Q is connected to the SEL terminal of MUX1. Port 0 of MUX1 is grounded, and port 1 is connected to the external input clock signal CLK (generated by the multi-channel VCO circuit). The output OUT of MUX1 is connected to the asynchronous counting circuit composed of eight D flip-flops; the asynchronous counting circuit is not described in detail here. The outputs of the asynchronous counting circuit are B<7:0>, where B... <7> B <6> B <5> Connect to a three-digit comparator. The inputs of the three-digit comparator are Th<2:0> and B<7:5>, where Th<2:0> is fed back from the histogram. <2> Connected to one input of NAND1 and AND4, Th <1> Connected to one input of NAND2 and AND6, Th <0> Connect to port 1 of MUX2; B <7> Connect to another input of NAND1 and one input of AND3, B <6> Connect to another input of NAND2 and one input of AND5, B <5> Connect to the SEL terminal of MUX2. The output of NAND1 is connected to the other input of AND3 and AND4; the output of NAND2 is connected to the other input of AND5 and AND6; the output of AND3 is connected to one input of NOR1 and OR1; the output of AND4 is connected to the other input of NOR1; the output of AND5 is connected to one input of AND7 and NOR2; the output of AND6 is connected to the other input of NOR2; the output of NOR1 is connected to the other input of AND7 and one input of AND8; the output of NOR2 is connected to the other input of AND8; the output of AND7 is connected to the other input of OR1; the output of AND8 is connected to one input of AND9; input 1 of MUX2 is connected to Th... <0> Input terminal 0 is grounded, and output terminal OUT is connected to the other input terminal of AND9. The output terminals of AND9 and OR1 are respectively connected to the two input terminals of OR2, and the output terminal of OR2 is the output signal STOP_EN. During the operation of the comparator, the two most significant bits are compared first. When the first two input signals B<7:6> are greater than the threshold Th<2:1>, OR1 outputs a high level, and the STOP_EN signal is directly set to a high level; if the first two signals are equal, OR1 outputs a low level, AND8 outputs a high level, and at this time, only the least significant bit signal B needs to be compared. <5> With threshold Th <0> Size.When B <5> When it is high, it indicates that B <5> It must be greater than or equal to Th <0> At this time, the MUX outputs a high level, and the STOP_EN signal also outputs a high level.

[0045] refer to Figure 8 When MOD is low, the circuit operates in single-response mode. After the START pulse signal is issued, the VCOEN1 signal is pulled high, and the TDC circuit begins time quantization via the CLK1 clock signal. When the STOP signal is low, the TDC circuit does not respond to the STOP signal; when the STOP signal is high, the TDC circuit responds to the STOP signal. When MOD is high, the circuit operates in multi-response mode, with the two loops alternately quantizing time.

[0046] Example 1:

[0047] When the control signal MOD is low, the circuit operates in single-event response mode by default.

[0048] (1) When the circuit starts working, there is no ranging data from the previous frame. The first frame of ranging without threshold needs to be measured first. After the first frame data is generated, the histogram feeds back the new threshold to the TDC circuit.

[0049] Step (1) specifically includes: the external input signal MOD is low, VCOEN2 and VCOEN3 are low in single-event response mode; the START signal generated outside the chip is input to the chip, when the START signal arrives, the output terminal VCOEN1 of the control circuit is high, VCOEN2 and VCOEN3 are low, and loop 1 starts to work. When the first frame is not output, the feedback value of the histogram to the presettable counter is 000, that is, no time threshold limit is required, and the STOP signal generated by SPAD can be directly output to the control circuit. The generation of each frame of the histogram requires TDC to perform multiple time-to-digital conversions. After the multiple conversions are completed, the histogram outputs the final result and transmits the Th<2:0> threshold information to the presettable counters C1, C2, and C3 after processing. The threshold information Th<2:0> is obtained by subtracting "1" from the histogram output information OUT<11:9>.

[0050] (2) TDC filters out obviously erroneous noise information based on the threshold data fed back by the histogram.

[0051] Reference Figure 1 , Figure 2 Figure 3When the first frame of data is generated, the processed feedback data Th<2:0> is transmitted to the presettable counter. When the laser is emitted, a START signal is generated, and loop 1 in the VCO starts timing. The VCOEN1 enable signal changes from low to high, and VCO loop 1 starts working, sending the clock signal generated by the oscillation circuit to the timer circuit. The counter starts timing asynchronously.

[0052] When the highest three bits of the timer reach the threshold size of the feedback from the previous frame, the STOPEN output is high. From this point until the full scale range, the STOPEN signal is high. That is, any STOP pulse signal that arrives from this point onward is considered a valid signal. The valid STOP signal is input to the VCO control circuit, and the VCO_EN signal changes from high to low. At the same time, the STOP pulse is input to the SAMPLE terminal of the SAFF. Each SAFF sampling circuit immediately samples and holds the phase information. At this time, because the VCO stops running, the coarse count in the asynchronous counter will no longer change. Each stage of the SAFF circuit latches the fine count, and the encoding circuit encodes it.

[0053] (3)Reference Figure 2 , Figure 3 The histogram receives TDC data and outputs and provides feedback on the data. After each timing period, the coarse count result DATA<7:0> and the fine count result FINE<3:0> are synchronously transmitted to the histogram circuit for accumulation processing. After histogram processing, the photon time-of-flight data result OUT<11:0> is output, and the threshold for the next frame is returned to the TDC circuit.

[0054] Example 2:

[0055] Multi-event response

[0056] (1) The first frame has no threshold for ranging, and the threshold is fed back to the TDC circuit from the histogram.

[0057] In a preferred embodiment of the present invention, step S1 specifically includes: the external input signal MOD is high, and VCOEN1 is low in multi-event response mode; the externally generated START signal is input to the internal circuit. When the START signal arrives, the output of the control circuit, VCOEN2, is high, and VCOEN3 is low, and loop 2 starts working. When the first STOP signal is generated, VCOEN2 is pulled low, loop 2 stops working, and VCOEN3 is pulled high, and loop 3 starts working. Before the END signal arrives, loop 2 and loop 3 work alternately. When loop 3 is working, the selection circuit outputs the data generated by the previous lighting loop 2 to the histogram circuit. When loop 2 is working, the selection circuit outputs the data generated by the previous lighting loop 3 to the histogram circuit. When the first frame is not output, the feedback value of the histogram to the presettable counter is 000, that is, no time threshold limit is required, and the STOP signal generated by SPAD can be directly output to the control circuit. The generation of each frame of the histogram requires multiple time-to-digital conversions by the TDC. After the multiple data conversions are completed, the histogram outputs the final result and transmits the Th<2:0> threshold information to preset value counters C1, C2, and C3 after processing. The threshold information Th<2:0> is obtained by subtracting "1" from the histogram output information OUT<11:9>.

[0058] (2) TDC filters out obviously erroneous noise information based on the threshold data fed back by the histogram.

[0059] After the first frame of data is generated, the processed feedback data Th<2:0> is input into a presettable counter. When laser emission begins, a START signal is generated, the output of the control circuit VCOEN2 goes high, and VCOEN3 goes low, starting loop 2. When the first STOP signal is generated, VCOEN2 is pulled low, loop 2 stops working, and VCOEN3 goes high, starting loop 3. Loop 2 and loop 3 alternate working until the END signal arrives. When loop 3 is working, the selection circuit outputs the data generated by the previous laser-emitting loop 2 to the histogram circuit; when loop 2 is working, the selection circuit outputs the data generated by the previous laser-emitting loop 3 to the histogram circuit.

[0060] When the highest three bits of the timer reach the threshold size of the feedback from the previous frame, the STOPEN output is high. From this point until the full scale range, the STOPEN signal is high, meaning that the STOP information from this point until the full scale range is considered valid. Subsequent STOP pulse signals are also considered valid and are input to the control circuit. The corresponding enable signal changes from high to low. The STOP pulse is simultaneously input to the SAMPLE pin of the SAFF. Each SAFF sampling circuit immediately samples and holds the phase information. At this time, because the VCO stops running, the coarse count in the asynchronous counter will no longer change. Each stage of the SAFF circuit latches the fine count, and the encoding circuit encodes it.

[0061] (3) The histogram receives TDC data and outputs and feeds back the data. After each timing period, the coarse and fine count results are synchronously transmitted to the histogram circuit for accumulation processing.

[0062] In summary, traditional Time-of-Flight (ToF) ranging not only consumes a large amount of TDC (Time-of-Difference Control) resources but also forces the histogram to accommodate more ToF data to filter out the correct data, significantly increasing circuit power consumption and area, resulting in unnecessary resource waste. This structure can directly shield data that deviates significantly from the true value on-chip, achieving efficient operation of both the TDC and histogram circuits. The on-chip noise suppression mechanism described in this invention can effectively improve the working efficiency of the TDC and enhance the working efficiency of the histogram circuit.

Claims

1. A multi-channel time-to-digital converter with on-chip optical noise suppression, characterized by, The multi-channel TDC circuit, the histogram circuit; the input end MOD, Vctrl, START, END, STOP of the multi-channel TDC circuit come from external input, the input end Th<2:0> is fed back by the histogram circuit; the output end is DATA<7:0> and FINE<3:0>, respectively connected to the input end DIN<7:0> and DIN<11:8> of the histogram circuit, the histogram output end is OUT<11:0> and threshold signal Th<2:0>, wherein OUT<11:0> is output as the final time measurement result to the outside of the chip, and Th<2:0> is fed back to the multi-channel TDC circuit to realize noise shielding and threshold control.

2. The multi-channel time-to-digital converter with on-chip rejection of light noise according to claim 1, characterized in that, The input end of the histogram circuit is DIN<7:0>, DIN<11:8>; the output end is OUT<11:0>, Th<2:0>; including peak detection circuit, histogram storage 1, histogram storage 2, histogram storage 3, peak calibration combination circuit, three-bit subtractor; the input end DIN<7:0>, DIN<11:8> is connected to the peak detection circuit, DIN<11:0> is obtained, the peak detection circuit outputs DIN<11:8>, DIN<7:4>, DIN<3:0> to histogram storage 1, histogram storage 2, histogram storage 3 after processing, histogram storage 1, histogram storage 2, histogram storage 3 output accumulated peak PEAK1<3:0>, PEAK2<3:0>, PEAK3<3:0> to the peak calibration combination circuit, OUT<11:0> is output to the outside of the chip through the peak calibration combination circuit, and the high three bits OUT<11:9> of OUT<11:0> is output to the three-bit subtractor, and Th<2:0> signal is output by the three-bit subtractor; The input end of the multi-channel TDC circuit is MOD, Th<2:0>, Vctrl, START, END, STOP; the output end is DATA<7:0>, FINE<3:0>, wherein MOD is an external input level signal, which controls the working mode of the circuit; Th<2:0> is a threshold signal fed back to the multi-channel TDC circuit by the histogram circuit; Vctrl is an external input control signal, which controls the internal clock frequency; START and END are external input control signals; STOP is a pulse signal output by the external SPAD circuit after receiving the echo photon; the multi-channel TDC circuit is composed of a control circuit, a multi-channel VCO circuit, a counter, an encoder and a selection circuit, wherein the three counters are respectively denoted as C1, C2 and C3.

3. The multi-channel time-to-digital converter with on-chip rejection of light noise according to claim 2, characterized in that, The input end of the control circuit inside the multi-channel TDC circuit is MOD, START, END, STOP, STOPEN, and the output end is EN1, EN2, EN3, wherein MOD, START, END are external input signals; Th<2:0> is connected with the output end Th<2:0> of the histogram circuit; the STOPEN end is connected to the STOPEN end of the three counters; the STOP signal is connected to the external STOP port; The input end of the selection circuit inside the multi-channel TDC circuit is FINE1<3:0>, FINE2<3:0>, FINE3<3:0>, DATA1<7:0>, DATA2<7:0>, DATA3<7:0>; the output end is DATA<7:0>, FINE<3:0>, wherein the input end FINE1<3:0>, FINE2<3:0>, FINE3<3:0> are connected with the output end F<3:0> of the encoder, the output end PHASE<11:8>, PHASE<15:12> of the multi-channel VCO respectively; the input end DATA1<7:0>, DATA2<7:0>, DATA3<7:0> are connected with the output end B<7:0> of the counter C1, the counter C2, the counter C3 respectively; the output end DATA<7:0>, FINE<3:0> are connected with the input end DIN<7:0>, DIN<11:8> of the histogram circuit as the output of the multi-channel TDC circuit; The input end of the multi-channel VCO circuit inside the multi-channel TDC circuit is Vctrl, VCOEN1, VCOEN2, VCOEN3, SAMPLE; the output end is CLK1, CLK2, CLK3, PHASE<7:0>, PHASE<11:8>, PHASE<15:12>, wherein Vctrl is an external input control signal; the input end VCOEN1, VCOEN2, VCOEN3 are connected with the EN1, EN2, EN3 end of the control circuit respectively; the input end SAMPLE and the input end STOP of the control circuit are synchronous signals, and are connected with the output end STOP of the SPAD circuit; the output end CLK1 is connected with the input end CLK of the counter C1; the output end CLK2 is connected with the input end CLK of the counter C2; the output end CLK3 is connected with the input end CLK of the counter C3; the output end PHASE<7:0> is connected with the input end P<7:0> of the encoder; the output end PHASE<11:8>, PHASE<15:12> are connected with the input end FINE2<3:0>, FINE3<3:0> of the selection circuit respectively; The input end of the counter inside the multi-channel TDC circuit is CLK, Th<2:0>, START; the output end is B<7:0>, STOPEN, wherein the input end START of the counter C1, the counter C2 and the counter C3 is a synchronous signal, which is input by an external signal, the Th<2:0> end of the counter C1, the counter C2 and the counter C3 is a synchronous signal, and is connected with the output end Th<2:0> of the histogram; the input end CLK of the counter C1, the counter C2 and the counter C3 is connected with the output end CLK1, CLK2 and CLK3 of the multi-channel VCO circuit respectively; the output end STOPEN of the counter C1, the counter C2 and the counter C3 is a synchronous signal, and is connected with the STOPEN end of the control circuit; the output end B<7:0> of the counter C1 is connected with the input end DATA1<7:0> of the selection circuit; the output end B<7:0> of the counter C2 is connected with the input end DATA2<7:0> of the selection circuit; the output end B<7:0> of the counter C3 is connected with the input end DATA3<7:0> of the selection circuit; The input end of the encoder inside the multi-channel TDC circuit is P<7:0>, and the output end is F<3:0>, wherein the input end P<7:0> is connected with the output end PHASE<7:0> of the multi-channel VCO circuit; the output end F<3:0> is connected with the input end FINE1<3:0> of the selection circuit.

4. The multi-channel time-to-digital converter with on-chip optical noise suppression function according to claim 2, wherein, The multi-channel VCO circuit inside the multi-channel TDC circuit comprises 16 differential units and 16 SAFF sampling circuits, the 16 differential units are respectively denoted as PD0, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14 and PD15, and the 16 SAFF sampling circuits are respectively denoted as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15, wherein PD0, PD1, PD2, PD3, PD4, PD5, PD6 and PD7 and S0, S1, S2, S3, S4, S5, S6 and S7 constitute a loop 1; PD8, PD9, PD10 and PD11 and S8, S9, S10 and S11 constitute a loop 2, and PD12, PD13, PD14 and PD15 and S12, S13, S14 and S15 constitute a loop 3; The output end VOUT+ of the PD0 in the loop 1 is connected with the input end D of the S0 and the input end VIN+ of the PD1, and the output end VOUT- of the PD0 is connected with the input end DN of the S0 and the input end VIN- of the PD1; the output end VOUT+ of the PD1 is connected with the input end D of the S1 and the input end VIN+ of the PD2, and the output end VOUT- of the PD1 is connected with the input end DN of the S1 and the input end VIN- of the PD2; the PD0-PD7 are connected with the S0-S7 in sequence, and details are not repeated; in the last stage, the output end VOUT+ of the PD7 is connected with the input end D of the S7 and the input end VIN- of the PD0, and the output end VOUT- of the PD7 is connected with the input end DN of the S7 and the input end VIN+ of the PD0, so that the loop 1 is completed; the output end VOUT+ of the PD8 in the loop 2 is connected with the input end D of the S8 and the input end VIN+ of the PD9, and the output end VOUT- of the PD8 is connected with the input end DN of the S8 and the input end VIN- of the PD9; the output end VOUT+ of the PD9 is connected with the input end D of the S9 and the input end VIN+ of the PD10, and the output end VOUT- of the PD9 is connected with the input end DN of the S9 and the input end VIN- of the PD10; the PD8-PD11 are connected with the S8-S11 in sequence, and details are not repeated; in the last stage, the output end VOUT+ of the PD11 is connected with the input end D of the S11 and the input end VIN- of the PD8, and the output end VOUT- of the PD11 is connected with the input end DN of the S11 and the input end VIN+ of the PD8, so that the loop 2 is completed; the output end VOUT+ of the PD12 in the loop 3 is connected with the input end D of the S12 and the input end VIN+ of the PD13, and the output end VOUT- of the PD12 is connected with the input end DN of the S12 and the input end VIN- of the PD13; the output end VOUT+ of the PD13 is connected with the input end D of the S13 and the input end VIN+ of the PD14, and the output end VOUT- of the PD13 is connected with the input end DN of the S13 and the input end VIN- of the PD14; the PD12-PD15 are connected with the S12-S15 in sequence, and details are not repeated; in the last stage, the output end VOUT+ of the PD15 is connected with the input end D of the S15 and the input end VIN- of the PD12, and the output end VOUT- of the PD15 is connected with the input end DN of the S15 and the input end VIN+ of the PD12, so that the loop 3 is completed; the input end Vctrl and the SAMPLE signal of the multi-channel VCO circuit are global signals, and simultaneously control the three oscillation loops; the VCOEN1, the VCOEN2 and the VCOEN3 are respectively the enable signals of the loop 1, the loop 2 and the loop 3; in the loop 1, the output end VOUT+ of the PD4 is the output end CLK1 of the multi-channel VCO circuit, and the output end Q of the S1, the output end Q of the S2, the output end Q of the S3, the output end Q of the S4, the output end Q of the S5, the output end Q of the S6 and the output end Q of the S7 are the output signals PHASE<7:0>;In loop 2, the output terminal VOUT+ of PD9 is the output terminal CLK2 of the multi-channel VCO circuit, and the output terminal Q of S8, the output terminal Q of S9, the output terminal Q of S10 and the output terminal Q of S11 are the output signal PHASE<8:11>; in loop 3, the output terminal VOUT+ of PD13 is the output terminal CLK3 of the multi-channel VCO circuit, and the output terminal Q of S12, the output terminal Q of S13, the output terminal Q of S14 and the output terminal Q of S15 are the output signal PHASE<15:12>; The PD0-PD15 all adopt the same differential structure, and the differential units inside the loop 2 and the loop 3 adopt the same MOS tube size, so as to ensure that the frequency of the loop 2 and the loop 3 is consistent.

5. The multi-channel time-to-digital converter with on-chip rejection of light noise according to claim 4, characterized in that, The differential unit includes 6 PMOS tubes, 3 NMOS tubes; 6 PMOS tubes are M1, M2, M3, M4, M5, M6 respectively; 3 NMOS tubes are M7, M8, M9 respectively, wherein the upper 6 are PMOS tubes (M1-M6), the lower 3 are NMOS tubes (M7-M9), M1 and M2 constitute a cross-coupled positive feedback structure, the source of M1 is connected to VDD, the drain is connected to VOUT+, and the gate is connected to VOUT-; the source of M2 is connected to VDD, the drain is connected to VOUT-, and the gate is connected to VOUT+, both of which enhance the switching speed and stability of the circuit; M3 and M4 are delay control tubes, the source is connected to VDD, the drain is connected to VOUT+ and VOUT- respectively, and the gate is commonly connected to the control voltage VC, for adjusting the delay; M5 and M6 are constant current source type PMOS tubes, the source is connected to VDD, and the gate is connected to ground, wherein the drain of M5 and the drain of M6 are connected to VOUT+ and VOUT- nodes respectively, providing bias current for differential output; M7 and M8 constitute a differential pair, the source is commonly connected to a point and connected to the drain of current source M9, the gate of M7 is connected to VIN+, the gate of M8 is connected to VIN-, and the drain of M7 and M8 is connected to VOUT+ and VOUT-; M9 is a tail current source tube, the drain is connected to the common point of the source of M7 and M8, the source is connected to ground, and the gate is controlled by the control signal VCO_EN to open or close the switch, playing a role of turning on or off the circuit.

6. The multi-channel time-to-digital converter with on-chip rejection of light noise according to claim 4, characterized in that, The SAFF sampling circuit includes 9 PMOS tubes, 5 NMOS tubes and two inverters; the 9 PMOS tubes are M10-M18 respectively, the 5 NMOS tubes are M19-M23 respectively, the inverters are INV1 and INV2 respectively, and the top of the circuit is a power supply VDD; a SAMPLE control signal is connected to the gate of M10, M13 and M23 respectively, the source of M10 is connected to VDD, and the drain is connected to the drain node of M11, for controlling the pre-charge of the left branch; the source of M13 is connected to VDD, and the drain is connected to the drain node of M12, for controlling the pre-charge of the right branch; M23 is an NMOS, the source is connected to the ground, and the drain is connected to a common differential node between M21 and M22, for completing the pre-discharge of the sampling phase; a data input end D is connected to the gate of M21, and DN is connected to the gate of M22; M21 and M22 are both NMOS, the sources are connected together, and the drains are connected to the drains of M16 and M17 respectively; the sources of the differential pair of M16 and M17 are connected to the drains of M11 and M12 respectively, M11 and M12 are PMOS, the sources are connected to VDD, forming a basic differential amplifier structure; M14 and M15 constitute a cross positive feedback unit, M14 is PMOS, the source is connected to VDD, and the gate is connected to the common node of the source of M17 and the drain of M12; the drain of M15 is connected to the pull-down network of the subsequent stage at the same time, in the pull-down path, the drain of M15 is connected to the drain of M19, M19 is NMOS, the source is connected to the drain of M20, the source of M20 is connected to the ground, M19 and M20 form a cascade pull-down path, and the stability of the latch is enhanced, M20 helps the circuit to complete the decision quickly by controlling the current down, finally, the voltage on the drain of M15 is buffered and output through the inverter INV2 to obtain the OUT signal.

7. The multi-channel time-to-digital converter with on-chip rejection of light noise according to claim 3, characterized in that, The counter inside the multi-channel TDC circuit comprises a D flip-flop DFF1, a two-way selector MUX1, an asynchronous counting circuit comprising eight D flip-flops, a three-bit number comparator comprising gate circuits; the input end is CLK, Th<2:0>, START; the output end is B<7:0>, STOPEN; the input end CK of DFF1 is connected with an external input START signal, and the output end Q is connected with the input end of MUX1 The input end D is connected with the output end Q connected to the SEL end of MUX1; the 0 port of MUX1 is grounded, and the 1 port is connected with the clock signal CLK generated by the multi-channel VCO circuit; the output end OUT of MUX1 is connected to the asynchronous counting circuit composed of 8 D flip-flops, which will not be described here; the output end of the asynchronous counting circuit is B<7:0>, wherein B<7>, B<6> and B<5> are connected to the three-bit comparator, the input end of the three-bit comparator is Th<2:0> and B<7:5>, wherein Th<2:0> is fed back by the histogram, Th<2> is connected to one input end of NAND1 and AND4, Th<1> is connected to one input end of NAND2 and AND6, and Th<0> is connected to the 1 port of MUX2; B<7> is connected to the other input end of NAND1 and one input end of AND3, B<6> is connected to the other input end of NAND2 and one input end of AND5, and B<5> is connected to the SEL end of MUX2; the output end of NAND1 is connected to the other input end of AND3 and AND4, and the output end of NAND2 is connected to the other input end of AND5 and AND6; the output end of AND3 is connected to one input end of NOR1 and OR1, and the output end of AND4 is connected to the other input end of NOR1; the output end of AND5 is connected to one input end of AND7 and NOR2, and the output end of AND6 is connected to the other input end of NOR2; the output end of NOR1 is connected to the other input end of AND7 and one input end of AND8, and the output end of NOR2 is connected to the other input end of AND8; the output end of AND7 is connected to the other input end of OR1, and the output end of AND8 is connected to one input end of AND9; the input end 1 of MUX2 is connected with Th<0>, the input end 0 is grounded, and the output end OUT is connected to the other input end of AND9; the output ends of AND9 and OR1 are respectively connected to two input ends of OR2, and the output end of OR2 is the output signal STOP_EN; during the working process of the comparator, firstly, the high two-bit values are compared; when the previous two-bit input signals B<7:6> are greater than the threshold values Th<2:1>, OR1 outputs high level, and the STOP_EN signal is directly set to high level; if the previous two-bit signals are equal, OR1 outputs low level, and AND8 outputs high level, at this time, it is only needed to continue comparing the size of the lowest bit signal B<5> and the threshold value Th<0>; when B<5> is high level, it is indicated that B<5> is necessarily greater than or equal to Th<0>, at this time, MUX outputs high level, and the STOP_EN signal also outputs high level.

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