High-integration digital-analog integrated acquisition board serial synchronization method based on mosaic digital array

Abstract

The invention discloses a high-integration digital-analog integrated acquisition board serial synchronization method based on a mosaic digital array. The method comprises the following steps: serially connecting a plurality of acquisition boards with complete processing capability; according to different task requirements, the acquisition boards distributed to the subsystems are initialized; a clock circuit of each subsystem acquisition board (1) selects a local clock as a reference clock, and a superior acquisition board provides a reference clock for a subordinate acquisition board to realize clock synchronization with the superior acquisition board; the upper computer issues an AD / DA synchronization instruction to the acquisition board (1), and sends a synchronization request to the lower level in sequence to realize AD / DA synchronization of each acquisition board; and finally, performing coarse and accurate time delay on each subsystem to realize accurate synchronization of data of each channel. The implementation method is flexible, not only can the whole be broken up into parts to reconstruct different system functions at the same time, but also the parts can be gathered into a whole to form a single function of an independent area array, the operating distance is increased, and the method can be widely applied to a distributed communication system to meet the synchronization of any specified digital array.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of distributed communication, and particularly relates to a high-integration digital-analog integrated acquisition board serial synchronization method based on a mosaic digital array. BACKGROUND

[0002] With the rapid development of electronic technology, communication systems are required to have multiple protocols, multiple frequency bands, reconfigurability and other characteristics, and the traditional single mode has been unable to meet various application scenarios. Most of the current communication systems have adopted a software radio architecture, which can dynamically reconfigure different communication functions by reloading different software as needed, greatly reducing hardware resources and improving the flexibility of equipment systems. However, such systems can only be reconfigured in time and cannot meet the simultaneous multi-function and long-distance use requirements, which to some extent limits the development of equipment.

[0003] Heterogeneous communication technology aims to achieve seamless connection and efficient resource utilization by integrating different protocols and architectures. However, traditional antennas have limitations in supporting multiple frequency bands, dynamic beam control, and interference management. Mosaic array, as a new type of antenna technology, can support multiple communication modes by flexibly configuring array elements, improve spectrum utilization and system performance, and use intelligent algorithms to weight the received signals of the configured array elements, enhance the signals of interest, and suppress the signals of interest, thereby achieving interference suppression, improving the signal-to-noise ratio of the distribution system, and improving signal quality.

[0004] The heterogeneous communication system based on the mosaic array takes the mosaic unit as the basis and distributed communication as the core, and each unit has complete processing capability, which is expanded into a variable digital array through serial splicing. According to the task requirements, this system can reconfigure different system functions at the same time by dividing the whole into parts, and also can form an independent surface array single function by combining the parts into a whole, thereby improving the action distance.

[0005] In the invention patent with the publication number “CN102955155B”, a distributed active phased array radar and its beam forming method are disclosed, which mentions that the front-end digital unit receives instructions and a common clock signal sent by the central processor, the clock signal adopts clock modulation technology, the synchronization trigger signal is transmitted through the clock network, and the synchronization clock and synchronization trigger signal are subjected to a special calibration algorithm to ensure the synchronization of the clock signals of each port. The invention only briefly mentions the clock synchronization of the distributed active phased array radar and does not provide detailed design description.

[0006] The invention patent with the publication number "CN118317419A" discloses a signal device for P-wave band signal synchronization in a distributed scenario, which comprises a synchronous clock source, a waveform generating DDS, and a feedback calibration ADC. The synchronous clock source responds to an external reference clock to output a reference clock required by each module and a radio frequency signal used for feedback calibration consistent with the radio frequency signal output by the DDS. The DDS transmits a radio frequency signal for external work and a radio frequency signal for calibration to the ADC. The ADC is used to monitor the phase of the radio frequency signal waveform. When initialized, the DDS compares the phase of the radio frequency signal output externally with the phase of the same radio frequency signal generated by the synchronous clock source to complete the phase calibration within the module. The invention uses zero delay phase-locked loop technology to realize clock synchronization, ensuring that the working clock of each functional chip in the module has a certain phase relationship with the external reference clock. However, the invention requires an external time and space synchronization device to provide a reference clock for each module synchronous clock source. In order to realize signal synchronization between modules, the external time and space synchronization device must also be designed with a synchronous clock circuit. The module itself also includes a synchronous clock source design, which increases the burden of system design. Moreover, the invention does not provide detailed design instructions for realizing the cascading synchronization mode between modules. SUMMARY

[0007] The purpose of the present application is to provide a high-integration digital-analog integrated acquisition board serial synchronization method and device based on a mosaic digital array.

[0008] The technical solution for achieving the purpose of the present application is as follows: a high-integration digital-analog integrated acquisition board serial synchronization method based on a mosaic digital array, comprising:

[0009] A plurality of acquisition boards are connected in series, and the acquisition boards are high-integration digital-analog integrated acquisition boards, each of which includes a clock circuit, an FPGA, and an AD / DA;

[0010] According to different task requirements, the plurality of acquisition boards are initialized, including initializing and configuring each chip of the acquisition board and issuing an acquisition board identifier;

[0011] The first acquisition board connected in series is used as a node for data interaction with the upper computer through the UDP network port;

[0012] The first acquisition board receives a query instruction from the upper computer, periodically sends a query request to the acquisition board with the identifier through the CAN bus, and each acquisition board transmits the current acquisition board real-time situation to the first acquisition board after receiving the query request to confirm the working state of the current acquisition board;

[0013] The first acquisition board receives a clock input / output selection identifier instruction, sends an input / output selection identifier to the acquisition board with the identifier through the CAN bus, and controls whether the clock circuit of each acquisition board has a reference clock input and a clock output;

[0014] The first acquisition board clock circuit selects a board clock as a reference clock, generates AD / DA sampling clock and FPGA processing clock required by the board, and provides a clock circuit reference clock and a synchronization pulse for the second acquisition board through the backplane, the second acquisition board generates AD / DA sampling clock and FPGA processing clock required by the board through input reference clock and provides a clock circuit reference clock and a synchronization pulse for the third acquisition board, and in this way, all acquisition board clock circuits are enabled for multi-chip synchronous input;

[0015] The host computer issues a clock circuit synchronization instruction to the first acquisition board, sends a synchronization request to the second acquisition board through the backplane, and after the second acquisition board receives the synchronization request, the FPGA sends a synchronization request to the clock circuit through the SPI bus, the clock circuit resets the seeding request after receiving the request, aligns the frequency divider phase, waits for 8 SYSREF periods, controls the query clock output phase state through GPOx, confirms that all outputs have reached their expected phases, completes the phase synchronization with a determinable delay of the input reference clock, and the second acquisition board clock circuit completes the synchronization operation with the first acquisition board and uploads the synchronization result to the host computer; when the second acquisition board completes the synchronization, the second acquisition board sends a synchronization request to the third acquisition board, and the third acquisition board repeats the operation of the second acquisition board until all acquisition boards complete the synchronization with the previous level.

[0016] After all acquisition board clocks complete the synchronization, the host computer issues an AD / DA synchronization instruction to the first acquisition board, and sends an AD / DA synchronization instruction to other acquisition boards through the CAN bus periodically, and after the AD / DA chip receives the synchronization instruction, the AD / DA chip synchronization first enables the multi-chip synchronization register operation, and then re-enables the SYSREF signal; the synchronization process is performed by four SYSREFs, all of which are started on the rising edge of SYSREF, the first two SYSREFs complete the chip internal clock divider synchronization, the third SYSREF completes the high-speed digital clock divider synchronization, and the last SYSREF completes the numerically controlled oscillator, JESD204B link local multi-frame clock and RF phase-locked loop phase synchronization;

[0017] After all acquisition board clock circuits and AD / DA acquisition chips are synchronized, the single-tone signal of the signal source is sent to each acquisition board AD channel through the power divider for signal acquisition, the data collected by each channel is processed through FFT, and the phases of each channel are compared, and the channels with a difference greater than a set threshold are further subjected to coarse and accurate delay, so that the data of each channel is accurately synchronized.

[0018] Compared with the prior art, the present application has the following advantages:

[0019] 1) all the collection plates of the present application are completely consistent, adopt a serial synchronization method, and can be intelligently configured by software according to task requirements, that is, can be divided into parts or combined into a whole, to meet the simultaneous multi-function and remote use requirements;

[0020] 2) the present application has a periodic query function, can real-time master the state of the collection plate required by the current task, can be dynamically configured, and is flexible to use;

[0021] 3) the synchronous design of the present application does not need an external reference clock board, only needs to define the first collection plate by software, the clock of the collection plate required by the current task is synchronized with the clock of the first collection plate, and the synchronization scheme is more universal and intelligent.

[0022] The present application can be widely applied to distributed communication systems, and simultaneously solves the problems of digital array time reconstruction and space reconstruction.

[0023] The present application will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a high-integration digital-analog integrated collection plate serial synchronization design block diagram based on a mosaic digital array in the present application.

[0025] Figure 2 is a main circuit composition block diagram of the high-integration digital-analog integrated collection plate in the present application.

[0026] Figure 3 is a reference clock and synchronization pulse composition block diagram in the present application.

[0027] Figure 4 is a collection plate clock circuit synchronization before and after process diagram according to the embodiment of the present application.

[0028] Figure 5 is a first collection plate and second collection plate clock circuit synchronization diagram according to the embodiment of the present application.

[0029] Figure 6 is a radio frequency transmission signal diagram after the collection plate is synchronized according to the embodiment of the present application.

[0030] Figure 7 is a radio frequency transmission signal diagram after the collection plate is synchronized and the coarse and fine delay is performed according to the embodiment of the present application. DETAILED DESCRIPTION

[0031] Those skilled in the art will appreciate that the embodiments described herein are presented for the purpose of aiding the reader in understanding the principles of the present application and should be understood as not limiting the scope of protection of the present application to such specific recitations and embodiments. Those skilled in the art can make various other specific modifications and combinations according to the technical spirit disclosed by the present application without departing from the essence of the present application, and these modifications and combinations are still within the scope of protection of the present application.

[0032] The embodiments of the present application will be further described below with reference to the accompanying drawings.

[0033] In combination Figure 1 As shown in the drawings, the present application is a high integration digital-analog integrated acquisition board serial synchronization method based on a mosaic digital array, comprising the following steps:

[0034] All acquisition boards are serially connected, and data interaction between the acquisition boards is performed in a CAN bus, SRIO bus, LVDS, GTX, etc. mode;

[0035] According to different task requirements, the assigned acquisition boards are initialized, and the initialization includes acquisition board chip initialization configuration and acquisition board identification issuing. The first acquisition board takes the UDP network port as a node for data interaction with the upper computer, sequentially identifies the acquisition boards as ①, ②, ③, …, N, and identifies the acquisition board clock circuit, AD / DA, clock input / output selection, and program running control, etc.

[0036] The first acquisition board ① receives the upper computer query instruction, periodically sends a query request to the acquisition board with the identification through the CAN bus, and each acquisition board returns the current acquisition board real-time situation to the first acquisition board ① after receiving the query request, and confirms the current acquisition board working state;

[0037] The first acquisition board ① receives the clock input / output selection identification instruction, sends an input / output selection identification to the acquisition board with the identification through the CAN bus, and controls whether the acquisition board clock circuit has a reference clock input and a clock output;

[0038] The first acquisition board ① clock circuit selects the local clock as the reference clock, generates the AD / DA sampling clock and FPGA processing clock required by the board, provides the clock circuit reference clock and synchronization pulse for the second acquisition board ② through the bottom plate, the second acquisition board ② generates the AD / DA sampling clock and FPGA processing clock required by the board through the input reference clock and provides the clock circuit reference clock and synchronization pulse for the third acquisition board ③, and so on, and enables the SYNC pin of the SPI of all acquisition board clock circuits for multi-chip synchronous input;

[0039] The host computer sends a clock circuit synchronization instruction to the first acquisition board ①, sends a synchronization request to the second acquisition board ② through the bottom plate, the second acquisition board ② receives the synchronization request, the FPGA sends a synchronization request to the clock circuit through the SPI bus, the clock circuit receives the request, resets the seeding request, aligns the frequency divider phase, waits for 8 SYSREF periods, controls the query clock output phase state through GPOx, confirms that the outputs have all reached their expected phases, completes the phase synchronization with the input reference clock with a determinable delay, the second acquisition board ② clock circuit completes the synchronization operation with the first acquisition board ①, and uploads the synchronization result to the host computer. When the second acquisition board ② completes the synchronization, the second acquisition board ② sends a synchronization request to the third acquisition board ③, the third acquisition board ③ repeats the operation of the second acquisition board ②, until all acquisition boards complete the synchronization with the previous level.

[0040] After the clock of all acquisition boards is synchronized, the host computer sends an AD / DA synchronization instruction to the first acquisition board ①, sends an AD / DA synchronization instruction to other acquisition boards through the CAN bus periodically, the AD / DA chip receives the synchronization instruction, the AD / DA chip synchronization first enables the multi-chip synchronization register operation, and then re-enables the SYSREF signal. The synchronization process is mainly performed by four SYSREFs, all of which are started on the rising edge of SYSREF, the first two SYSREFs complete the synchronization of the chip internal clock divider, the third SYSREF completes the synchronization of the high-speed digital clock divider, and the last SYSREF completes the phase synchronization of the numerically controlled oscillator (NCO), the JESD204B (note: high-speed serial interface standard protocol) link local multi-frame clock (LMFC) and the radio frequency phase-locked loop (RFPLL).

[0041] After the synchronization of the clock circuit and the AD / DA acquisition chip of all acquisition boards is completed, the power divider is used to send a single tone signal from a signal source into all AD channels for signal acquisition, the coarse and precise delay of the clock circuit is configured, the FFT processing is performed on the data collected by each channel, and the phases of each channel are compared. The channels with larger alignment differences continue to be coarse and precise delayed, and finally the data of each channel is accurately synchronized.

[0042] Further, the acquisition board mainly uses RF transceiver ADRV9009 as a front-end acquisition chip, clock circuit HMC7044 provides synchronous reference clock and SYSREF clock for the board and the next stage slave board, Xilinx Zynq-7000 XC7Z045, Kintex-7 XC7VX690T and TMS320C6678 are the core of the general software radio hardware platform. Among them, Zynq-7000 XC7Z045 mainly completes the control of the bottom layer driver program of each chip, Kintex-7 XC7VX690T mainly completes the data acquisition, preprocessing and data transmission of each AD / DA, and TMS320C6678 mainly completes the beam forming algorithm and transceiver base data coding.

[0043] Further, the acquisition board initialization specifically includes acquisition board ID allocation, all chip and interface bottom layer protocol, driver configuration, etc.; the number of the first acquisition board ① is determined by the number of tasks; the position of the first acquisition board ① is intelligently defined by software according to the number of tasks and the number of acquisition boards required by the current task, and the other serial numbers are sequentially sorted according to the number of acquisition boards required by the current task;

[0044] Further, the first acquisition board ① has no synchronization request, external reference clock and synchronization pulse input.

[0045] Further, the SYNC pin of the other acquisition boards is output by the clock circuit of the upper stage except the first acquisition board ①.

[0046] Further, the on-board clock uses voltage-controlled crystal oscillator CVHD-950X-100, and the frequency stability is ±25ppm.

[0047] Further, the clock circuit of the second acquisition board ② completes the synchronization operation with the first acquisition board ① mainly based on the two-stage phase-locked loop (PLL) synchronization integrated in the clock circuit HMC7044 of the second acquisition board ②. PLL1 is mainly used for locking the external VCXO to the reference clock, providing clock retention and reference frequency for the second high-performance PLL2 loop, and PLL2 is mainly used for high-frequency frequency multiplication to obtain the expected clock signal. The loop transfer function of PLL1 is:

[0048]

[0049] Among them, is the phase detector gain in PLL1, is the voltage-controlled oscillator gain in PLL1, is the Laplace operator, is the loop filter function.

[0050] Assume that the first acquisition board ① outputs a reference clock as a standard signal:

[0051]

[0052] The second acquisition board ② outputs a clock signal:

[0053]

[0054] wherein, , is the clock frequency output by the first acquisition board ① and ②, is the initial phase of the second acquisition board ②. Thus, is the phase difference of the clock output by the first acquisition board ① and ②.

[0055] Send into the phase discriminator inside PLL1, compare with the local VCXO in phase, detect the phase difference between the two, and obtain the phase difference signal:

[0056]

[0057] The voltage-controlled oscillator VCXO continuously adjusts the output frequency and phase according to the phase difference signal, that is:

[0058]

[0059] wherein, is the center frequency of the VCXO, is the automatic feedback adjustment voltage of the loop filter. The phase model can be obtained from the frequency-phase relationship as:

[0060]

[0061] When the system is stable, combining the loop transfer function of PLL1, at this time, the VCXO clock frequency of the second acquisition board ② is locked to the reference clock of the first acquisition board ①, realizing PLL1 synchronization. The second acquisition board ② has a determinable delay relative to the first acquisition board ①, and similarly, all serially connected clock circuits have a determinable delay relative to the clock circuit of the previous node, realizing the function of serial synchronization of acquisition board clocks.

[0062] Further, coarse delay is performed by configuring a clock circuit coarse digital delay register, which has 17 coarse delay steps, and each step adjusts the delay by 1 / 2 VCO period. Then, fine delay is performed by configuring a fine analog delay register, which has 24 fine delay steps, and each step adjusts the delay by 25 ps.

[0063] Furthermore, the maximum clock jitter of the clock circuit is 108fs / 12KHz~20MHz@2.8GHz, the clock skew is 30ps, the ADC sampling uncertainty is 50ps, the length difference of equal-length traces on the PCB is approximately ±0.3mm, and the delay difference is ±2ps. Therefore, the time synchronization accuracy (unit: ps / ns) is approximately...

[0064]

[0065] Furthermore, the maximum clock AD / DA chip uses the ADRV9009 wideband transceiver as the RF transceiver chip, supporting a 200MHz bandwidth within a frequency range of 75MHz to 6GHz. Based on the time synchronization accuracy, the phase synchronization accuracy can be obtained as follows:

[0066]

[0067] Substituting 75MHz to 6GHz into the above formula yields... Considering errors in the clock distribution system and signal links, the system's full-band synchronization accuracy is better than 3°. Figure 1 It can be seen that when the current task quantity is 1 and the number of collection boards required for the task is N, the N collection boards are arranged according to... Figure 1 The numbers are sorted as shown; when the current task quantity is 2, task 1 requires 2 collection boards, and task 2 requires N-2 collection boards, the N collection boards are arranged according to... Figure 1 The numbers are sorted as shown.

[0068] Combination Figure 2 As shown, Figure 2 A block diagram of the main circuit components of a highly integrated analog-to-digital data acquisition board is presented. The acquisition board mainly consists of a clock circuit, FPGA, DSP, ADC / DAC, data storage module, high-speed data interface, and power management module.

[0069] Combination Figure 3 As shown, Figure 3 A block diagram of the system reference clock and synchronization pulse is provided. Except for the first acquisition board, which uses the onboard clock source as the reference clock, all other clock circuits use the reference clock and synchronization pulse sent from the upper-level clock circuit as reference sources. This provides a reference clock source for the FPGA and ADC / DAC circuits on this board, and also outputs reference clocks and synchronization pulses to the lower-level clock circuits.

[0070] Example 1

[0071] The host computer sends a clock circuit synchronization instruction to the first acquisition board, sends a synchronization request to the second acquisition board ② through the backplane, and the second acquisition board ② receives the synchronization request. The FPGA sends a synchronization request to the clock circuit through the SPI bus. When the second acquisition board ② clock circuit detects the SYNC signal, the clock circuit enters a synchronization state, as shown in Figure 4 After receiving the request, the clock circuit resets the seeding request, aligns the frequency divider phase, waits for 8 SYSREF periods, controls the query clock output phase state through GPOx, confirms that the outputs have reached their expected phases, completes the phase synchronization with the input reference clock with a deterministic delay, and the second acquisition board ② clock circuit completes the synchronization operation with the first acquisition board, Figure 5 as shown.

[0072] Example 2

[0073] After the acquisition board clock completes synchronization, the host computer sends an ADRV9009 synchronization instruction to the first acquisition board, sends an ADRV9009 synchronization instruction to other acquisition boards through the CAN bus periodically, and the ADRV9009 receives the synchronization instruction. The ADRV9009 synchronization first enables the multi-chip synchronization register operation, and then re-enables the SYSREF signal. The synchronization process is mainly performed by four SYSREFs, all of which are started on the rising edge of SYSREF. The first two SYSREFs complete the synchronization of the internal clock divider, the third SYSREF completes the synchronization of the high-speed digital clock divider, and the last SYSREF completes the phase synchronization of the numerically controlled oscillator (NCO), the local multi-frame clock (LMFC) of the JESD204B link, and the radio frequency phase-locked loop (RFPLL). The ADRV9009 transmit end signal synchronization is as shown in Figure 6 .

[0074] The clock circuit coarse digital delay register is configured for coarse delay. The register has 17 coarse delay steps, and each step adjusts the delay by 1 / 2 VCO period. Then the fine analog delay register is configured for accurate delay. The register has 24 fine delay steps, and each step adjusts the delay by 25 ps. By configuring the coarse and accurate delay of the clock circuit, the ADRV9009 transmit end signal synchronization is finally achieved, as shown in Figure 7 . In the figure, after 245 times sampling of the oscilloscope, the phase mean square value sdev of the second acquisition board ② compared to the first acquisition board is 1.422°, and the phase mean square value sdev of the third acquisition board ③ compared to the first acquisition board is 1.169°, both of which are less than the theoretical calculation full-band synchronization accuracy, achieving the expected synchronization effect.

Claims

1. A serial synchronization method for a high-integration digital-analog integrated acquisition board based on a mosaic digital array, characterized in that, The application relates to a multi-chip synchronous sampling system. A plurality of acquisition boards are connected in series, the acquisition boards are high-integration digital-analog integrated acquisition boards, each acquisition board comprises a clock circuit, an FPGA and an AD / DA; According to different task requirements, a plurality of acquisition boards are initialized, including initialization configuration of chips of the acquisition boards and issuing of acquisition board identifiers; A first acquisition board connected in series is used as a node for data interaction with an upper computer through a UDP network port; The first acquisition board receives an upper computer query instruction, periodically sends a query request to acquisition boards with identifiers through a CAN bus, and each acquisition board returns real-time conditions of the acquisition boards to the first acquisition board to confirm working states of the acquisition boards; The first acquisition board receives a clock input-output selection identifier instruction, sends an input-output selection identifier to acquisition boards with identifiers through the CAN bus, and controls whether the clock circuits of the acquisition boards have reference clock inputs and clock outputs; The clock circuit of the first acquisition board selects a board-mounted clock as a reference clock, generates AD / DA sampling clocks and FPGA processing clocks required by the board, provides clock circuit reference clocks and synchronous pulses for a second acquisition board through a bottom plate, the second acquisition board generates AD / DA sampling clocks and FPGA processing clocks required by the board through input reference clocks and provides clock circuit reference clocks and synchronous pulses for a third acquisition board, and all acquisition board clock circuits are enabled for multi-chip synchronous input in this way; The upper computer issues a clock circuit synchronization instruction to the first acquisition board, sends a synchronization request to the second acquisition board through the bottom plate, the FPGA of the second acquisition board sends a synchronization request to the clock circuit through an SPI bus after receiving the synchronization request, the clock circuit resets the request after receiving the request, aligns a frequency divider phase, waits for 8 SYSREF periods, controls a query clock output phase state through GPOx, confirms that all outputs have reached respective expected phases, completes phase synchronization with a determinable delay of the input reference clock, the clock circuit of the second acquisition board completes synchronization operation with the first acquisition board, and the synchronization result is uploaded to the upper computer; when the second acquisition board completes synchronization, the second acquisition board sends a synchronization request to the third acquisition board, the third acquisition board repeats the operation of the second acquisition board, and all acquisition boards complete synchronization with the previous level; After all acquisition board clocks complete synchronization, the upper computer issues an AD / DA synchronization instruction to the first acquisition board, periodically sends the AD / DA synchronization instruction to other acquisition boards through the CAN bus, the AD / DA chip is synchronized after receiving the synchronization instruction, the AD / DA chip is first enabled for multi-chip synchronization register operation, and then the SYSREF signal is re-enabled; the synchronization process is executed by four SYSREFs, all of which are started on the SYSREF rising edge, the first two SYSREFs complete chip internal clock divider synchronization, the third SYSREF completes high-speed digital clock divider synchronization, and the last SYSREF completes digital control oscillator, local multi-frame clock of a JESD204B link and radio frequency phase-locked loop phase synchronization; After the clock circuit, AD / DA acquisition chip of all acquisition boards are synchronized, the single tone signal of the signal source is sent into each acquisition board AD channel through the power divider for signal acquisition, the data collected by each channel is processed by FFT, and the phases of each channel are compared, the channels with a difference greater than the set threshold are further processed by coarse and fine delay, and finally the data of each channel is accurately synchronized.

2. The serial synchronous method of high integration digital-analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The acquisition board uses RF transceiver ADRV9009 as the front-end acquisition chip, clock circuit HMC7044 provides synchronous reference clock and SYSREF clock for the board and the next stage slave board, Xilinx Zynq-7000 XC7Z045, Kintex-7 XC7VX690T and TMS320C6678 are the core of the general software radio hardware platform.

3. The serial synchronous method of high integration digital-analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The initialization of the acquisition board specifically includes acquisition board ID allocation, all chip and interface bottom layer protocol, and driver configuration; the number of the first acquisition board is determined by the number of tasks; the position of the first acquisition board is intelligently defined by software according to the number of tasks and the number of acquisition boards required by the current task, and the other serial numbers are sequentially sorted according to the number of acquisition boards required by the current task.

4. The serial synchronous method of high integration digital-analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The first acquisition board has no synchronization request, external reference clock and synchronization pulse input, and the SYNC pins of the other acquisition boards are output by the clock circuit of the upper stage.

5. The serial synchronous method of high integration digital-analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The clock circuit uses voltage-controlled crystal oscillator CVHD-950X-100, and the frequency stability is ±25ppm.

6. The serial synchronous method of high integration digital-analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The second acquisition board is synchronized with the first acquisition board through the two-stage phase-locked loop integrated in the second acquisition board clock circuit HMC7044, the first-stage phase-locked loop PLL1 is used to lock the external VCXO to the reference clock, and the second-stage phase-locked loop PLL2 is used to high-frequency frequency multiplication to obtain the expected clock signal; the loop transfer function of the first-stage phase-locked loop PLL1 is: ； wherein, is a phase detector gain in PLL1, is a voltage controlled oscillator gain in PLL1, is a Laplacian operator, is a loop filter function; Assuming that the reference clock output by the first acquisition board is a standard signal: ； The clock signal output by the second acquisition board is: ； wherein, , is the first acquisition board, the second acquisition board output clock frequency, is the second acquisition board initial phase, get is the first acquisition board and the second acquisition board output clock phase difference; The phase detector inside the first phase-locked loop PLL1, to local VCXO, detect the phase difference between the two, and obtain a phase difference signal: ； The voltage-controlled oscillator VCXO continuously adjusts the output frequency and phase according to the phase difference signal, that is: ； wherein, is the VCXO center frequency, is the loop filter automatic feedback regulation voltage; The phase model obtained from the frequency-phase relationship is: ； Combining the loop transfer function of the first phase-locked loop PLL1, when the system is stable, At this time, the second acquisition board VCXO clock frequency is locked to the first acquisition board reference clock, realizing PLL1 synchronization. The second acquisition board has a deterministic delay relative to the first acquisition board, and similarly, all serially connected clock circuits have a deterministic delay relative to the clock circuit of the previous node, realizing the function of serial synchronization of acquisition board clocks.

7. The serial synchronous method of high integration digital and analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The specific method for processing the data collected by each channel by configuring the coarse and fine delay of the clock circuit is as follows: coarse delay is performed by configuring the coarse digital delay register of the clock circuit, the coarse digital delay register has 17 coarse delay steps, and each step adjusts the delay by 1 / 2 VCO period, and then fine delay is performed by configuring the fine analog delay register, the fine analog delay register has 24 fine delay steps, and each step adjusts the delay by 25ps.

8. The serial synchronous method of high integration digital-analog integrated acquisition board based on mosaic digital array according to claim 1, characterized in that, The maximum clock jitter of the clock circuit is 108fs / 12KHz~20MHz@2.8GHz, and the clock skew is 30ps.

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