Resetting method based on UVM
By encapsulating the reset function in a virtual interface file within the UVM verification environment, the problems of inflexible reset and missed recovery in UVM verification are solved, achieving automated reset and recovery, and improving the flexibility and efficiency of testing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-03-10
Smart Images
Figure CN121635646A_ABST
Abstract
Description
[0001] This invention relates to the field of digital circuit verification, and more specifically to a UVM-based reset method. Background Technology
[0002] In typical verification processes, many test points usually need to be reset, and a reset is performed at the beginning of the top-level verification. However, if a reset is needed later, there are two common methods. One is to add a delay in the top-level verification or to reset at the corresponding time based on the internal signal of the design under test. This approach is inflexible and rigid because not all test cases need to be reset at this time, and repeated deletions may cause code disorder. The second method is to call the forced assignment function built into UVM to perform a forced reset. This method usually involves writing a forced statement in the test case to perform a forced reset operation on the reset signal. However, because there is no automatic recovery, it is easy to miss the recovery operation, resulting in the test case remaining in a reset state.
[0003] Therefore, it is necessary to provide a UVM-based reset method to overcome the above-mentioned shortcomings. Summary of the Invention
[0004] The purpose of this invention is to provide a UVM-based reset method. This UVM-based reset method can directly call the encapsulated reset function in the sequence initiated by the test case to complete one or more automatic reset operations. It is convenient, fast, highly portable, and has a wide range of applications.
[0005] To achieve the above objectives, the present invention provides a UVM-based reset method, which includes the following steps: a. Compile a virtual interface file containing a reset function, which is used to generate a reset signal; b. Instantiate the virtual interface file in the top-level verification and send the instantiated virtual interface file to the UVM verification environment through the UVM parameter passing mechanism; c. Write test cases according to the test requirements, call the proxy sequence macro in the corresponding sequence and declare the virtual interface file; d. According to the test requirements, start the corresponding sequence in the test case, and in the started sequence, assign the handle of the virtual interface file in the virtual sequence generator to the handle of the current virtual interface file; e. Call the reset function in the virtual interface file.
[0006] Preferably, after the reset function is called, the generated reset signal can be automatically reset and can be automatically restored after reset.
[0007] Preferably, in step b, while the virtual interface file is instantiated at the top level of the verification, a reference clock signal is generated and the reference clock is input into the virtual interface file.
[0008] Preferably, in step a, a reset signal and a reference clock are defined within the virtual interface file.
[0009] Preferably, during instantiation, the virtual interface file inputs complex signals to the verification top layer.
[0010] Preferably, the obtained virtual interface file is declared in the virtual sequence generator of the UVM verification environment, and the virtual interface file is obtained through the UVM parameter passing mechanism.
[0011] Preferably, when writing test cases, the proxy sequence macro is invoked in the startup sequence, and the name of the virtual sequencer is specified in the proxy sequence macro.
[0012] Preferably, in the startup sequence, the handle of the virtual interface file in the virtual sequence generator is assigned to the handle of the current virtual interface file using a specific type of sequencer handle.
[0013] Compared with existing technologies, the UVM-based reset method of the present invention encapsulates the reset function that can generate a reset signal into a virtual interface file before the test begins. Then, during the test, the reset function is directly called as needed to perform the reset, and the system can automatically restore the system to the state before the reset to complete one or more automatic reset operations. Moreover, this method can directly call the virtual interface file (reset function) at any time according to the test needs in various test cases to achieve the reset operation. It is convenient, fast, not limited by specific test cases, highly portable, and has a wide range of applications.
[0014] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description
[0015] Figure 1 This is a flowchart of the UVM-based reset method of the present invention. Detailed Implementation
[0016] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals represent similar elements. As described above, the present invention provides a UVM-based reset method. This UVM-based reset method can directly call the encapsulated reset function in the test case to complete one or more automatic reset operations, which is convenient, fast, highly portable, and widely applicable.
[0017] Please refer to Figure 1, Figure 1 This is a flowchart of the UVM-based reset method of the present invention. Figure 1 As shown, the UVM-based reset method of the present invention includes the following steps: Step S001 involves creating a virtual interface file containing a reset function to generate a reset signal. This step primarily encapsulates the reset function, which generates the reset signal, into a virtual interface file so that it can be directly called as needed during testing. Furthermore, the reset signal generated in this step can automatically reset and automatically recover after reset. That is, after the reset function is called and executed, the test case is automatically reset, and after completing the reset operation, it automatically recovers to the state before the reset, avoiding the test being in a constant reset state and ensuring normal test performance. Additionally, in this step, the reset signal is defined in the virtual interface file so that the virtual interface file can quickly and accurately identify the reset signal.
[0018] Step S002: In the verification top layer, the virtual interface file is instantiated, and the instantiated virtual interface file is sent to the UVM verification environment through the UVM parameter passing mechanism. In this step, by instantiating the virtual interface file in the verification top layer, the virtual interface file can be stored in the verification top layer and used by the verification top layer. Then, the verification top layer sends the instantiated virtual interface file to the UVM verification environment through the UVM parameter passing mechanism for use by the UVM verification environment. During this process, the verification top layer will also generate a reference clock signal and input the reference clock into the virtual interface file, so that the virtual interface file also has a reference clock during the verification process to ensure the accuracy of timing during the verification process. In addition, as a preferred embodiment of the present invention, in step S001, when writing the virtual interface file, the reference clock needs to be defined in the virtual interface file, so that when the verification top layer generates the reference clock, it can be directly input into the virtual interface file to improve the timeliness of transmission; at the same time, in this step, the virtual interface file inputs the reset signal to the verification top layer, so that the verification top layer can directly use the reset signal to perform the corresponding reset operation in the test process described later.
[0019] Furthermore, in this invention, after the UVM verification environment obtains the virtual interface file, the obtained virtual interface file is declared in the virtual sequence generator in the UVM verification environment to store the virtual interface file in the virtual sequence generator, so as to facilitate the virtual sequence generator to operate and call the virtual interface file; and the UVM verification environment specifically obtains the virtual interface file through the UVM parameter passing mechanism.
[0020] Step S003: Write test cases according to the test requirements and call the proxy sequence macro in the corresponding sequence; In this step, declare the virtual interface file in the virtual sequence generator of the verification environment, and enable the verification environment to obtain the virtual interface file through the UVM parameter passing mechanism. When writing test cases, call the proxy sequence macro in the sequence corresponding to the test cases according to the test requirements to specify the name of the virtual sequence generator and declare the virtual interface file.
[0021] Step S004: According to the test requirements, start the corresponding sequence in the test case, and assign the handle of the virtual interface file to the handle of the current virtual interface file in the started sequence. In this step, by assigning the handle of the virtual interface file to the handle of the current virtual interface file in the started sequence, the virtual interface file can be directly called in the subsequent test process. Specifically, the handle of the virtual interface file in the virtual sequence generator is assigned to the handle of the current virtual interface file.
[0022] Step S005: Call the reset function in the virtual interface file. In this step, the reset can be performed by calling the reset function in the virtual interface file. Since the reset signal generated by the reset function of the present invention can automatically reset and can automatically recover after the reset, the system automatically recovers to the state before the reset after the reset operation is completed, without affecting the continuation of the subsequent test process.
[0023] In summary, the UVM-based reset method of the present invention encapsulates a reset function that can generate a reset signal into a virtual interface file before the test begins. Then, during the test, the reset function is directly called as needed to perform a reset, and the system can automatically restore the system to its pre-reset state after the reset, thus completing one or more automatic reset operations. Moreover, this method can directly call the virtual interface file (reset function) at any time according to the test needs in various different test cases to perform the reset operation. It is convenient, fast, not limited by specific test cases, highly portable, and has a wide range of applications.
[0024] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.
Claims
1. A UVM-based reset method, characterized in that, The method comprises the following steps: a. writing a virtual interface file containing a reset function, the reset function being used to generate a reset signal; b. instantiating the virtual interface file in a verification top layer and sending the instantiated virtual interface file to a UVM verification environment through a UVM parameter passing mechanism; c. writing a test case according to a test requirement, and calling an agent sequence macro in a corresponding sequence; d. starting a corresponding sequence in the test case according to the test requirement, and assigning a handle of the virtual interface file in the started sequence to a handle of a current virtual interface file; e. calling the reset function in the virtual interface file.
2. The UVM-based reset method of claim 1, wherein, After the reset function is called, the generated reset signal can automatically reset and can automatically recover after resetting.
3. The UVM-based reset method of claim 2, wherein, In the step b, a reference clock signal is generated when the virtual interface file is instantiated in the verification top layer, and the reference clock is input to the virtual interface file.
4. The UVM-based reset method of claim 3, wherein, In the step a, the reset signal and the reference clock are defined in the virtual interface file.
5. The UVM-based reset method of claim 2, wherein, In the instantiation process, the virtual interface file inputs the reset signal to the verification top layer.
6. The UVM-based reset method of claim 2, wherein, The obtained virtual interface file is declared in a virtual sequencer in the UVM verification environment, and the virtual interface file is obtained through the UVM parameter passing mechanism.
7. The UVM-based reset method of claim 2, wherein, In the writing of the test case, the agent sequence macro is called in the started sequence, and the name of the virtual sequencer is indicated in the agent sequence macro.
8. The UVM-based reset method of claim 6, wherein, In the started sequence, the handle of the virtual interface file in the virtual sequencer is assigned to the handle of the current virtual interface file by using a specific type of sequencer handle.