Nonvolatile storage method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a nonvolatile storage method and device, electronic equipment and a storage medium, and relates to the technical field of data storage.The method comprises the steps that a DIMM interface and a PCIe AIC interface are integrated into a single module, and space layout and electrical connection are conducted on PCM particles, an ASIC chip, a temperature sensor and a power module; an RAM and NRAM protocol conversion module is integrated in the ASIC chip, and state detection and dynamic protocol conversion are carried out on the DIMM interface and the PCIe AIC interface in combination with a scheduling algorithm; zQ impedance calibration and write-in voltage calibration are integrated through a calibration module, and PCM write-in parameters are optimized in combination with an ECC error feedback mechanism; the dual-interface power supply requirement and PCB temperature distribution data are obtained, and real-time monitoring and dynamic parameter adjustment are performed through the shunt power supply design of the power supply module, the standby power unit and overcurrent protection in combination with the temperature sensing module. According to the method, the defects of the traditional storage technology in the aspects of data persistence, read-write speed and interface compatibility are effectively overcome, and the storage requirement in a high-performance scene is met.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and in particular to a non-volatile storage method, apparatus, electronic device, and storage medium. Background Technology

[0002] With the rapid development of technologies such as big data, cloud computing, and artificial intelligence, the requirements for storage systems in fields such as data centers, industrial control, and high-performance computing are becoming increasingly stringent. Although traditional DDR storage modules have high-speed read and write capabilities, data is easily lost after power failure, making it difficult to meet the needs of business scenarios with strict requirements for data persistence.

[0003] Traditional non-volatile memory technologies, such as NOR and NAND flash memory, while ensuring data integrity even when power is off, suffer from slow read and write speeds, making them unsuitable for high-performance computing. Phase-change memory (PCM), a novel type of non-volatile memory, exhibits read and write speeds approaching those of DRAM due to its unique phase-change material properties, while also possessing inherent non-volatility.

[0004] However, the protocol conversion logic of existing PCM-related solutions is only designed for a single interface, without a protocol scheduling mechanism for "dynamic switching of multiple interfaces", and is not optimized in combination with the characteristics of PCM media (such as phase change voltage sensitivity and limited write life). Data errors or media life decay are prone to occur in high temperature and high frequency scenarios.

[0005] Therefore, in order to solve the problems of high hardware deployment costs and low system expansion flexibility caused by poor interface compatibility of existing storage modules, there is an urgent need for a non-volatile storage method that can be compatible with multiple interfaces, efficiently adapt to PCM characteristics, and meet storage requirements. Summary of the Invention

[0006] The embodiments of this invention provide a non-volatile storage method to address the problems of data loss during power outages in existing DDR storage modules, slow read / write speeds in NOR and NAND flash memory, and the fact that PCM solutions are mostly designed for single interfaces, lacking dynamic switching and protocol scheduling across multiple interfaces, and are not fully adapted to PCM characteristics, leading to data errors and media lifespan degradation under high temperature and high frequency conditions. The technical solution is as follows: According to one aspect of the present invention, a non-volatile memory method includes: integrating a DIMM interface and a PCIe AIC interface into a single module; spatially arranging and electrically connecting the single module, PCM chips, an ASIC chip, a temperature sensor, and a power module through PCB design; integrating a RAM to NRAM protocol conversion module inside the ASIC chip, and performing status detection and dynamic protocol conversion of the DIMM interface and the PCIe AIC interface using a scheduling algorithm; integrating ZQ impedance calibration and write voltage calibration through a calibration module, and optimizing PCM write parameters using an ECC error feedback mechanism; acquiring dual-interface power supply requirements and PCB temperature distribution data, and implementing a power module branch power supply design, a backup power unit, and overcurrent protection, combined with real-time monitoring and dynamic parameter adjustment using a temperature sensing module.

[0007] In one embodiment, the DIMM interface and PCIe AIC interface are integrated into a single module. The spatial layout and electrical connection of the single module, PCM chips, ASIC chip, temperature sensor, and power module are achieved through PCB design via the following steps: The overall structural framework of the single module is designed according to the specifications of the DIMM interface and PCIe AIC interface; the spatial layout on the PCB board is planned; PCM chips are sequentially deployed horizontally on the front side of the PCB board; the structural framework includes the position, specifications, and pin definitions of the gold fingers; the ASIC chip is deployed on the right side of the PCB board, and the temperature sensor is deployed at a designated location on the PCB board; the PCM chips, DDR4 chips, temperature sensor, and main power module are deployed on the back side of the PCB board, and a signal matching circuit is designed.

[0008] In one embodiment, integrating the DIMM interface and PCIe AIC interface into a single module, and spatially arranging and electrically connecting the single module, PCM chips, ASIC chip, temperature sensor, and power module through PCB design, further includes the following steps: placing the PCM chips sequentially in a horizontal direction on the front side of the PCB according to the spatial layout, and deploying the ASIC chip at a predetermined position to the right of the PCM chips; the ASIC chip integrates a protocol conversion module, a scheduling module, and a calibration module; deploying the temperature sensor at the predetermined position, and electrically connecting the PCM chips, ASIC chip, and temperature sensor according to the signal matching circuit; the temperature sensor is used to monitor temperature changes in a specific area in real time.

[0009] In one embodiment, integrating the DIMM interface and PCIe AIC interface into a single module, and spatially arranging and electrically connecting the single module, PCM chips, ASIC chip, temperature sensor, and power module through PCB design, further includes the following steps: PCM chips are longitudinally deployed vertically on the back of the PCB according to a symmetrical layout principle, ensuring that they are electrically consistent with the PCM chips on the front of the PCB and share a set of DQ signals; DDR4 chips, temperature sensors, and main power modules are deployed at designated locations; and electrical connections are made between the PCM chips, DDR4 chips, temperature sensors, and main power modules on the back of the PCB according to the signal matching circuit, while also connecting them to components on both the back and front of the PCB.

[0010] In one embodiment, a RAM to NRAM protocol conversion module is integrated inside the ASIC chip. The status detection and dynamic protocol conversion of the DIMM interface and PCIe AIC interface, combined with a scheduling algorithm, are achieved through the following steps: The scheduling module, RAM protocol conversion module, and NRAM protocol conversion module are integrated inside the ASIC chip using integrated circuit design technology, while optimizing the chip layout and routing; dedicated detection pins are set at both ends of the DIMM interface and PCIe AIC interface, and pull-up resistors are used to connect them to the power supply to form an initial high-level state. When the interface is correctly inserted, the detection pins are connected to the motherboard, and the level is pulled low. The scheduling module collects the level values ​​of the detection pins at both ends in real time; only when both ends simultaneously detect a low level is the interface considered to have completed a reliable connection. The scheduling module outputs a control signal according to the connection status of the interface using a preset scheduling algorithm and starts the corresponding protocol conversion module; the detection pins are shorter than conventional pins.

[0011] In one embodiment, integrating a RAM to NRAM protocol conversion module within the ASIC chip, combined with a scheduling algorithm for status detection and dynamic protocol conversion of the DIMM interface and PCIe AIC interface, further includes the following steps: when the RAM protocol conversion module is activated, it converts the electrical signals of the DIMM interface into digital signals through the DDR PHY unit, and simultaneously receives write commands and data sent by the DDR controller. The write commands are parsed and encapsulated into custom DPT data through the DDR CTRL unit. Inside the ASIC, the DPT data is aggregated to the DPTH unit and mapped to a PCM physical address. The DDR data format is converted to a data format supported by the PCM chip, and the DDR control signals are converted to PCM control signals. The PCM physical address is then transmitted to the PCM control unit to generate PCM PHY executable instructions.

[0012] In one embodiment, the calibration module integrates ZQ impedance calibration and write voltage calibration, and optimizes PCM write parameters by combining an ECC error feedback mechanism. It acquires dual-interface power supply requirements and PCB temperature distribution data, and achieves this through a power module with branched power supply design, a backup power unit, and overcurrent protection. This is combined with real-time monitoring and dynamic parameter adjustment by a temperature sensing module. The process involves: the calibration module sending a start signal to the RAM protocol conversion module while simultaneously pulling the ZQ pin low for sampling; comparing the actual impedance of the DDR signal link with the ZQ reference resistor impedance to generate an impedance deviation value; adjusting the impedance based on this deviation value; the calibration module real-time acquiring the PCM chip's write status signal based on the voltage calibration signal feedback link, calculating the resistance change rate, adjusting the write voltage based on this rate, and receiving error feedback from the ECC module. If a single-bit error is concentrated in the PCM chip, the write voltage of that PCM chip is adjusted; the power module implements a branched power supply design based on the dual-interface power supply requirements, sets up a backup power unit, and integrates an overcurrent protection module; the temperature sensing module monitors PCB temperature distribution data in real time; and the scheduling module dynamically adjusts PCM read / write parameters based on the temperature data.

[0013] According to one aspect of the present invention, a non-volatile memory device includes: a dual-interface integrated module for integrating a DIMM interface and a PCIe AIC interface into a single module, and spatially arranging and electrically connecting the single module, PCM chips, an ASIC chip, a temperature sensor, and a power module through PCB design; a protocol conversion scheduling module for integrating a RAM and NRAM protocol conversion module inside the ASIC chip, and performing status detection and dynamic protocol conversion of the DIMM interface and the PCIe AIC interface in conjunction with a scheduling algorithm; a PCM parameter optimization module for integrating ZQ impedance calibration and write voltage calibration through a calibration module, and optimizing PCM write parameters in conjunction with an ECC error feedback mechanism; and a power supply and temperature control management module for acquiring dual-interface power supply requirements and PCB temperature distribution data, and performing real-time monitoring and dynamic parameter adjustment through power module branch power supply design, backup power unit, and overcurrent protection, combined with a temperature sensing module.

[0014] According to one aspect of the present invention, an electronic device includes at least one processor and at least one memory, wherein computer-readable instructions are stored on the memory; the computer-readable instructions are executed by one or more of the processors to cause the electronic device to implement the non-volatile storage method described above.

[0015] According to one aspect of the invention, a storage medium has computer-readable instructions stored thereon, which are executed by one or more processors to implement the non-volatile storage method described above.

[0016] The beneficial effects of the technical solution provided by this invention are: In the above technical solution, this invention first integrates the DIMM and PCIe AIC interfaces into a single module, optimizing space layout and electrical connections through PCB design. Secondly, it integrates a RAM and NRAM protocol conversion module within the ASIC chip, utilizing a scheduling algorithm to achieve interface status detection and dynamic protocol conversion, ensuring efficient data transmission. Furthermore, it integrates ZQ impedance calibration and PCM write voltage calibration through a calibration module, combining ECC error feedback to optimize PCM write parameters, improving data reliability and media lifespan. Simultaneously, it acquires dual-interface power supply requirements and PCB temperature distribution data, employing a power module branch power supply design, backup power unit, and overcurrent protection mechanism to ensure stable power supply; and it uses a temperature sensing module to monitor temperature in real time, dynamically adjusting PCM read / write parameters to suppress local hotspots. This method achieves a unified solution for multi-interface compatibility, high-speed read / write, and data persistence, significantly reducing hardware costs and operational complexity, enhancing system scalability and reliability, and effectively addressing the shortcomings of traditional storage technologies in data persistence, read / write speed, and interface compatibility, meeting the storage needs of high-performance scenarios such as data centers and industrial control. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and those skilled in the art can obtain other drawings based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a non-volatile storage method according to an exemplary embodiment; Figure 2 This is a schematic diagram of the framework of a non-volatile storage device in an exemplary embodiment; Figure 3 yes Figure 2 A front view of the hardware of the non-volatile storage device in the corresponding embodiment; Figure 4 yes Figure 2 A schematic diagram of the hardware back of the non-volatile storage device in the corresponding embodiment; Figure 5 This is a schematic diagram of the framework of a non-volatile storage device in another exemplary embodiment; Figure 6 yes Figure 5 A front view of the hardware of the non-volatile storage device in the corresponding embodiment; Figure 7 yes Figure 5 A schematic diagram of the hardware back of the non-volatile storage device in the corresponding embodiment; Figure 8 This is a schematic diagram of the architecture of an insertion detection circuit according to an exemplary embodiment; Figure 9 This is a block diagram of a power module according to an exemplary embodiment; Figure 10 This is a flowchart illustrating the application of non-volatile storage methods in a specific application scenario. Figure 11 This is a block diagram illustrating a non-volatile storage device according to an exemplary embodiment; Figure 12 This is a hardware structure diagram of an electronic device according to an exemplary embodiment; Figure 13 This is a block diagram illustrating an electronic device according to an exemplary embodiment. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this disclosure means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, “connected” or “coupled” as used herein can include wireless connections or wireless coupling. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0021] Dual In-line Memory Module (DIMM) is a standardized memory storage component used in computers and related electronic devices. Its core function is to serve as the physical and electrical interface between memory chips (such as DRAM, Dynamic Random Access Memory) and the device motherboard, enabling data interaction, instruction transmission, and power management between the memory chips and the motherboard chipset. It is a key hardware unit that constitutes the device's memory subsystem.

[0022] An expansion card (AIC), short for Add-In Card, is a hardware expansion component designed based on the PCIe (Peripheral Component Interconnect Express) bus standard. Its core function is to expand the hardware functions of the host through physical and electrical connection with the host's PCIe slot, and to realize high-speed data interaction with the host system through the PCIe bus. It is a key carrier for expanding the functions of the host system and is widely used in servers, industrial control and other fields.

[0023] Phase-change memory (PCM), also known as PRAM, is a novel type of non-volatile memory made of chalcogenide materials. It stores information by utilizing the reversible physical state changes of the material. Under certain conditions, the dielectric material of PCM transitions between an amorphous state and a crystalline state, exhibiting different resistive characteristics in each. Therefore, "0" and "1" can be used to represent the amorphous and crystalline states, respectively, to store data.

[0024] Application-Specific Integrated Circuit (ASIC) is an integrated circuit designed specifically for a particular application scenario or functional requirement. Compared with general-purpose integrated circuits (such as CPUs, GPUs, FPGAs, etc.), its core feature is "specialization"—achieving efficient optimization for specific tasks through the fixed design of hardware logic.

[0025] This invention provides a non-volatile storage method that integrates multiple protocol interfaces into a single module, along with core modules such as protocol conversion, dynamic scheduling, and calibration protection. It integrates dual interfaces for DIMM and PCIe AIC, in-chip protocol conversion and dynamic scheduling, PCM characteristic calibration, and coordinated power supply and temperature control management for both interfaces. This achieves dynamic conversion from PCM protocol to DDR / PCIe protocol, while ensuring signal integrity, data reliability, and PCM media lifespan in dual-interface scenarios. It also reduces hardware costs and improves system scalability. This unified storage method achieves high-speed read / write and persistent data storage, addressing the shortcomings of traditional storage in terms of performance, compatibility, and reliability. This non-volatile storage method is applicable to non-volatile storage devices, which can be electronic devices. The non-volatile storage method in this invention can be applied to various scenarios, such as non-volatile storage in data centers.

[0026] Please see Figure 1 This invention provides a non-volatile storage method applicable to electronic devices.

[0027] In the following method embodiments, for ease of description, the execution subject of each step of the method is an electronic device, but this does not constitute a specific limitation.

[0028] like Figure 1 As shown, the method may include the following steps: Step 110: Integrate the DIMM interface and PCIeAIC interface into a single module. Through PCB design, perform spatial layout and electrical connection of the single module, PCM chip, ASIC chip, temperature sensor and power module.

[0029] In one possible implementation, the overall structural framework of a single module is designed according to the specifications of the DIMM interface and PCIe AIC interface. The spatial layout on the PCB board is planned, and the PCM chip is deployed horizontally on the front of the PCB board, the ASIC chip is deployed on the right side of the PCB board, the temperature sensor is deployed at a designated position on the PCB board, and the PCM chip, DDR4 chip, temperature sensor and main power module are deployed on the back of the PCB board. A signal matching circuit is also designed.

[0030] In one possible implementation, PCM particles are placed sequentially in the horizontal direction on the front of the PCB board according to the spatial layout, and an ASIC chip is deployed at a predetermined position on the right side of the PCM particles; a temperature sensor is deployed at the predetermined position, and an electrical connection is made between the PCM particles, the ASIC chip and the temperature sensor according to a signal matching circuit.

[0031] The structural framework includes the location, specifications, and pin definitions of the gold fingers; the ASIC chip integrates a protocol conversion module, a scheduling module, and a calibration module; and the temperature sensor is used to monitor temperature changes in a specific area in real time.

[0032] In one possible implementation, PCM chips are arranged vertically on the back of the PCB board in a symmetrical layout to ensure that they are electrically consistent with the PCM chips on the front of the PCB board and share a set of DQ signals. DDR4 chips, temperature sensors, and main power modules are deployed at designated locations. The PCM chips, DDR4 chips, temperature sensors, and main power modules on the back of the PCB board are electrically connected according to the signal matching circuit, and are also connected to the components on both the back and front of the PCB board.

[0033] Specifically, the DIMM interface and PCIe AIC interface are integrated into a single module. The overall module structure is designed according to JEDEC and PCI-SIG specifications to ensure compatibility. The module's gold finger positions, specifications, and pin definitions are designed to ensure stable and reliable physical and electrical connections with the host system. PCM chips are horizontally deployed sequentially on the front of the PCB to form a PCM memory array, and an ASIC chip is deployed on the right side, integrating core modules such as protocol conversion, scheduling, and calibration.

[0034] PCM chips are symmetrically deployed vertically on the back of the PCB to ensure consistent electrical characteristics and a shared DQ signal. DDR4 chips, temperature sensors, and the main power module are also deployed. Signal matching circuitry is designed to ensure the integrity and stability of signal transmission between components. Temperature sensors are deployed in critical areas of the PCB to monitor temperature changes in real time, providing a basis for subsequent temperature control strategies.

[0035] In the above process, the embodiments of the present invention, through dual-interface integration and module design, achieve support for multiple interfaces by a single module, improving the compatibility and scalability of the storage system. Simultaneously, the optimized PCB layout and signal matching circuit design ensure the stability and reliability of signal transmission.

[0036] Step 120: Integrate a RAM to NRAM protocol conversion module inside the ASIC chip, and combine a scheduling algorithm to perform status detection and dynamic protocol conversion between the DIMM interface and the PCIe AIC interface.

[0037] In one possible implementation, an integrated circuit design technique is used within the ASIC chip to integrate a scheduling module, a RAM protocol conversion module, and an NRAM protocol conversion module, while optimizing the chip layout and routing. Dedicated detection pins are set at both ends of the DIMM interface and the PCIe AIC interface, and pull-up resistors are used to connect them to the power supply to form an initial high-level state. When the interface is correctly inserted, the detection pins are connected to the motherboard, and the level is pulled low. The scheduling module collects the level values ​​of the detection pins at both ends in real time. Only when both ends detect a low level simultaneously is the interface considered to have completed a reliable connection. The scheduling module outputs a control signal based on the connection status of the interface using a preset scheduling algorithm, and starts the corresponding protocol conversion module.

[0038] The detection pin is designed to be shorter than that of conventional pins to ensure that the physical contact sequence is completed last, effectively avoiding misjudgment in the half-insertion state.

[0039] Specifically, the insertion detection circuit, based on the detection pin level, ensures hot-plug functionality and interface connection stability. The design of the insertion detection circuit involves setting dedicated detection pins at both ends of the DIMM and PCIe AIC interfaces. These pins are connected to the power supply via pull-up resistors to form a high-level reference. When the interface is correctly inserted, the detection pin is connected to the motherboard's GND, pulling the level down to a low level. The scheduling module within the ASIC chip continuously monitors the pin levels at both ends. Only when both ends simultaneously detect a low level is the interface considered reliably connected, triggering the corresponding protocol conversion module to start.

[0040] The insertion detection circuit, through the combination of hardware level detection and intelligent scheduling algorithms, effectively ensures the reliability of hot-swapping, eliminates invalid communication in a connectionless state, and provides underlying connection status awareness capabilities for multi-protocol compatible storage systems. This electromechanical detection mechanism significantly improves system reliability: in hot-swapping scenarios, it can quickly identify the physical connection status of the interface, providing an accurate basis for the dynamic scheduling of the protocol conversion module; by replacing software polling with hardware level detection, zero-latency status awareness is achieved; and the short pin design ensures the timing accuracy of the detection signal from a physical structure level, forming the underlying foundation for interface reliability assurance and serving as the core technical support for non-volatile storage systems to achieve seamless hot-swapping and multi-protocol compatibility.

[0041] In one possible implementation, when the RAM protocol conversion module is started, it converts the electrical signals of the DIMM interface into digital signals through the DDR PHY unit. At the same time, it receives write commands and data sent by the DDR controller, parses the write commands through the DDRCTRL unit, separates the data, and encapsulates it into DPT data.

[0042] Furthermore, within the ASIC, DPT data is aggregated to the DPTH unit and mapped to a PCM physical address. The DDR data format is converted to a data format supported by the PCM chip. At the same time, the DDR control signals are converted to PCM control signals, and the PCM physical address is passed to the PCM control unit to generate PCM PHY executable instructions.

[0043] Specifically, integrated circuit design technology is employed to integrate core functional units such as a scheduling module, a RAM protocol conversion module, and an NRAM protocol conversion module within the ASIC chip. Chip layout and routing are optimized to reduce signal interference and improve chip performance. The interface connection status is determined by real-time acquisition of the detection pin levels at both ends of the DIMM and PCIe AIC interfaces. Based on the interface connection status, the scheduling module dynamically activates the corresponding protocol conversion module using a preset scheduling algorithm, realizing the conversion from DDR and PCIe protocols to the PCM protocol. The RAM protocol conversion module converts the electrical signals of the DIMM interface into digital signals through the DDR PHY unit, parses write commands and data, encapsulates them in DPT format, and performs address mapping, data format conversion, and control signal conversion. The NRAM protocol conversion module realizes the conversion from PCIe protocol to PCM protocol, optimizing signal integrity and throughput in high-speed PCIe scenarios.

[0044] In the above process, the embodiments of the present invention achieve seamless switching and efficient protocol conversion between multiple interfaces through protocol conversion and dynamic scheduling within the ASIC chip, thereby improving the flexibility and performance of the storage system. Simultaneously, the optimized protocol conversion logic ensures the accuracy and reliability of data transmission.

[0045] Step 130: The ZQ impedance calibration and write voltage calibration are integrated through the calibration module, and the PCM write parameters are optimized by combining the ECC error feedback mechanism.

[0046] In one possible implementation, a start signal is sent to the RAM protocol conversion module via the calibration module, while the ZQ pin is pulled low for sampling. The actual impedance of the DDR signal link is compared with the ZQ reference resistor impedance to generate an impedance deviation value, and the impedance is adjusted according to the impedance deviation value. The calibration module collects the write status signal of the PCM chip in real time according to the voltage calibration signal feedback link, calculates the resistance change rate, adjusts the write voltage according to the resistance change rate, and receives error feedback from the ECC module. If single-bit errors are concentrated in the PCM chip, the write voltage of the PCM chip is adjusted.

[0047] Specifically, during the initialization phase after DIMM interface insertion, the calibration module sends a start signal to the RAM protocol conversion module and pulls the ZQ pin low for sampling. The actual impedance of the DDR signal link is compared with the ZQ reference resistor impedance to generate an impedance deviation value. The impedance is adjusted to within ±2% to meet DDR's impedance matching requirements. The write status signal of the PCM chip is acquired in real time through the voltage calibration signal feedback link to calculate the resistance change rate. The write voltage is adjusted based on the resistance change rate to ensure sufficient PCM phase transition and undamaged lifespan. Simultaneously, combined with the ECC error feedback mechanism, targeted adjustments are made to PCM chips exhibiting concentrated single-bit errors.

[0048] In the above process, the embodiments of the present invention ensure the stability and lifespan of the PCM medium in high-speed read / write scenarios through PCM characteristic calibration and parameter optimization. ZQ impedance calibration improves signal integrity, and PCM write voltage calibration combined with ECC feedback mechanism effectively reduces data error rate and improves the reliability of the storage system.

[0049] Step 140: Obtain dual-interface power supply requirements and PCB temperature distribution data. Through power module branch power supply design, backup power unit and overcurrent protection, combined with real-time monitoring and dynamic parameter adjustment by temperature sensing module.

[0050] In one possible implementation, the power supply module is designed to provide power to the dual interfaces in a branched manner, a backup power unit is set up and an overcurrent protection module is integrated, the temperature sensor module monitors the PCB temperature distribution data in real time, and the scheduling module dynamically adjusts the PCM read and write parameters based on the temperature data.

[0051] Specifically, a split power supply design is implemented based on the power supply requirements of the dual interfaces to ensure the stability and independence of power supply to each component; a backup power unit and overcurrent protection module are integrated to prevent data loss or hardware damage caused by power outages or short circuits. A temperature sensing module is deployed to monitor PCB temperature distribution data in real time, and the PCM read / write parameters are dynamically adjusted in conjunction with the ASIC scheduling module; when the temperature exceeds the threshold, operations such as reducing the read / write pulse width, reducing the frequency, or resetting are taken to ensure the reliability of the PCM medium.

[0052] In the above process, the embodiments of the present invention ensure the stable operation of the storage system under different operating conditions through dual-interface power supply and temperature control collaborative management. The branch power supply design and backup power unit improve the reliability and safety of power supply, while the temperature sensing module and dynamic adjustment strategy effectively suppress local hot spots and extend the service life of the PCM media.

[0053] Through the above process, this embodiment of the invention achieves unified storage for high-speed read / write and data persistence by integrating dual interfaces and module design, ASIC chip-based protocol conversion and dynamic scheduling, PCM characteristic calibration and parameter optimization, and dual-interface power supply and temperature control collaborative management. This method not only improves the compatibility and scalability of the storage system but also significantly enhances its reliability and stability, meeting the storage needs of high-performance scenarios such as data centers and industrial control.

[0054] like Figure 2 As shown, in an exemplary embodiment, the ASIC chip device 100 includes: a scheduling module 110, a RAM protocol conversion module 111, an NRAM protocol conversion module 112, a data buffer module 113, an ECC module 114, a PCM channel management module 115, a clock management module 116, and a calibration module 117.

[0055] Specifically, the scheduling module 110 is used to detect the connection status of the DIMM and PCIe AIC interfaces in real time: it detects the pin level change through pull-up resistors (such as determining insertion when the DIMM interface pin6 / pin288 is low), and dynamically starts the RAM or NRAM protocol conversion module according to the detection result to avoid invalid communication and coordinate the working priority of multiple modules (such as responding to PCIe high-speed requests first when writing data).

[0056] RAM Protocol Conversion Module 111: Converts DDR protocols (such as DDR4 command / address / data signals) into PCM internal operation instructions; supports address mapping (logical address → PCM physical address) and data format conversion (DDR bit width → PCM bit width).

[0057] NRAM protocol conversion module 112: parses PCIe protocol (such as TLP packet decomposition), extracts read and write instructions and data, converts PCIe timing to PCM operation timing, and handles retransmission mechanisms (such as PCIe ACK / NAK response).

[0058] Data buffer module 113: Temporarily stores burst data during high-speed PCIe transmission, solving the mismatch between PCM write latency and PCIe bandwidth; works with DDR4 cache chips to achieve multi-level buffering and optimize data flow control.

[0059] ECC module 114: Implements error correction coding (such as Reed-Solomon code or LDPC code) on read and write data, detects and corrects bit errors caused by charge leakage in PCM cells, and improves data reliability.

[0060] PCM Channel Management Module 115: Dynamically allocates read and write channels for PCM storage granules, supports parallel operation of multiple granules, optimizes channel utilization based on load balancing algorithms, and reduces access conflicts.

[0061] Clock Management Module 116: Generates multi-frequency clock signals (such as PCIe reference clock, PCM operating clock, DDR clock, and supports clock spread spectrum to reduce EMI interference).

[0062] Calibration module 117: Dynamically adjusts the drive strength, swing and equalization parameters of the PCIe / DDR interface, and compensates for signal integrity degradation caused by temperature changes (e.g., by adjusting the drive current through feedback from the temperature sensing module).

[0063] like Figure 3 and Figure 4As shown, the device integrates five PCM memory chips on the front, each 14x18 in size, numbered 101-105, arranged in two horizontal rows (three in the top row and two in the bottom row), forming the main memory array. An additional ASIC chip 100, 16x16 in size, is directly integrated into the core area of ​​the PCB to optimize signal paths. A DDR4 cache chip 400 is deployed on the bottom right side of the back of the device for temporary data buffering. A DIMM interface 301 is located at the bottom of the PCB, connecting to the host memory slot via gold fingers, supporting DDR protocol communication. A PCIe AIC interface 300 is deployed on the top right side of the PCB, using a high-speed connector, supporting PCIe protocol communication. The two interfaces are dynamically switched via an internal scheduling module within the ASIC chip.

[0064] Furthermore, the back of the device also includes an independently partitioned power module 700, comprising: an ASIC power supply module: providing core voltage (e.g., 1.2V Core, 3.3V IO) for the ASIC chip; a PCM power supply module: providing stable write voltage for the PCM memory chips (supporting dynamic adjustment across multiple voltage domains); an overcurrent protection module: monitoring abnormal current in real time and triggering fuse or current limiting protection; a timing control unit: coordinating power-on timing to ensure the ASIC starts before the memory chips; and a backup power unit: integrating supercapacitors or small batteries to ensure data writing during abnormal power outages.

[0065] Through the above process, this embodiment achieves high compatibility (supporting memory and accelerator card forms), high reliability (ECC+ calibration), and low latency (fast protocol conversion) of non-volatile storage devices by integrating DIMM / PCIe dual interfaces, optimizing ASIC functional module layout, and dynamic scheduling mechanism, thus meeting the application needs of multiple scenarios.

[0066] like Figure 5 As shown, in an exemplary embodiment, the ASIC chip device 100 includes: a scheduling module 110, an ECC module 114, a PCM channel management module 115, a clock management module 116, and a calibration module 117.

[0067] Specifically, the scheduling module 110 detects the pin levels of the DIMM interface (pin6 / pin288) and the PCIe AIC interface (pin4 / pin78) through pull-up resistors, and determines that the interface is inserted when the level is low; according to the detection result, the RAM or NRAM protocol conversion module is started to avoid invalid communication when there is no connection; PCIe high-speed requests are responded to first to ensure performance in low-latency scenarios.

[0068] The ECC module 114 performs LDPC encoding on PCIe / DDR read / write data, detecting and correcting bit errors caused by PCM charge leakage. The PCM channel management module 115 allocates PCM read / write channels according to a load balancing algorithm, supporting parallel access. The clock management module 116 provides independent clocks for PCIe, DDR, and PCM, supporting spread spectrum and EMI reduction. The calibration module 117 adjusts the drive strength and balancing parameters of the PCIe / DDR interface through feedback from the temperature sensing module.

[0069] like Figure 6 As shown, the device integrates five PCM memory chips on the front, each 14x18 in size and numbered 101-105. They are arranged horizontally in a top row of three (101-103) and a bottom row of two (104-105), forming the main memory array. A data buffer module 201 is deployed on the bottom row of the front panel. An NRAM protocol conversion module 202 is independently deployed on the top right side of the front panel, responsible for converting the DDR protocol of the PCIe AIC interface to the internal PCM instructions. An ASIC chip 200, 16x16 in size, is deployed in the bottom right corner of the front panel.

[0070] like Figure 7 As shown, the RAM protocol conversion module 203 is independently deployed on the lower right side of the back of the device, responsible for converting the DDR protocol of the DIMM interface to the internal PCM instructions; the DDR4 cache chip 400 is located on the right side of the back, used for PCIe high-speed data buffering. The DIMM interface 301 is located at the bottom of the PCB and connects to the host memory slot via gold fingers, supporting DDR4 protocol communication. The PCIe AIC interface 300 is deployed on the top right side of the PCB, using a high-speed connector, supporting the PCIe 5.0 protocol, and implementing PCIe signal processing through the NRAM protocol conversion module inside the ASIC chip.

[0071] Furthermore, the back of the device also includes an independently partitioned power module 700, comprising: an ASIC power supply module: providing core voltage (e.g., 1.2V Core, 3.3V IO) for the ASIC chip; a PCM power supply module: providing stable write voltage for the PCM memory chips (supporting dynamic adjustment across multiple voltage domains); an overcurrent protection module: monitoring abnormal current in real time and triggering fuse or current limiting protection; a timing control unit: coordinating power-on timing to ensure the ASIC starts before the memory chips; and a backup power unit: integrating supercapacitors or small batteries to ensure data writing during abnormal power outages.

[0072] Specifically, the PCIe write process is as follows: The host sends a TLP packet through the PCIe AIC interface → the NRAM protocol conversion module parses the instruction → the data is temporarily stored in the data buffer module → the ASIC scheduling module allocates a PCM channel → the PCM channel management module executes the write operation → the ECC module verifies the data. The DIMM read process is as follows: The host sends a DDR command through the DIMM interface → the scheduling module detects the interface status and starts the RAM protocol conversion module → the address is mapped to the PCM physical address → the PCM channel reads the data → ECC error correction → the data is returned to the host.

[0073] Through the above process, this embodiment deploys the RAM protocol conversion module independently, while the NRAM protocol conversion module is integrated into the ASIC, balancing flexibility and signal integrity. The DIMM / PCIe dual interface supports seamless switching between memory and accelerator card forms. A data buffer module, ECC, and dynamic calibration ensure high-speed transmission and data integrity. The combination of a discrete protocol conversion module and ASIC integrated design optimizes the scalability and performance of non-volatile memory devices, making it suitable for mixed interface scenarios.

[0074] Specifically, the RAM protocol conversion architecture includes a DDR controller, a DDR PHY layer, a DPT protocol conversion module, a DPTH data hub, a PCM controller, a data buffer module, and a clock management module, which realizes the conversion and optimization of DDR protocol to PCM storage instructions.

[0075] Specifically, the DDR controller and PHY layer receive DDR command / address / data signals and parse them into memory operation instructions. The DPT module converts DDR protocol instructions (such as ACT, READ, WRITE) into the ASIC's internal DPT format, supporting the mapping from logical addresses to PCM physical addresses. The DPTH hub coordinates DDR and PCM data paths, optimizing read / write timings and channel allocation for multi-DIE memory chips. The data buffer module temporarily stores bursty DDR data, resolving the mismatch between PCM write latency and DDR's high bandwidth. The PCM controller and PHY layer execute PCM read / write operations, dynamically allocating memory channels to improve parallel access efficiency. The clock management module generates multi-frequency clock signals (such as DDR and PCM operation clocks), supporting spread spectrum to reduce EMI interference.

[0076] Through the above process, the RAM protocol conversion architecture achieves efficient collaboration between the DDR memory interface and PCM non-volatile memory by means of protocol adaptation, data buffering and timing optimization, ensuring the stability and low latency of data flow control.

[0077] Specifically, the NRAM protocol conversion architecture includes a PCIe controller, a PCIe PHY layer, a DPT protocol conversion module, a DPTH data hub, a PCM controller, an ECC module, and a calibration module, enabling efficient conversion from PCIe protocol to PCM storage instructions.

[0078] Specifically, the PCIe controller and PHY layer receive high-speed PCIe signals, parse them into TLP packets, and convert them into an internal data format. The DPT module extracts read / write instructions and data from the TLP packets and maps them to PCM physical addresses and operation instructions. The DPTH hub coordinates PCIe and PCM data flows, optimizing the timing of parallel access to multiple DIE memory chips. The PCM controller and PHY layer execute PCM read / write operations, supporting dynamic channel allocation and load balancing. The ECC module implements LDPC error correction coding on the written data, detecting and correcting bit errors caused by PCM charge leakage. The calibration module dynamically adjusts the PCIe PHY drive strength and equalization parameters to compensate for the impact of temperature changes on signal integrity.

[0079] Through the above process, the NRAM protocol conversion architecture achieves seamless integration between PCIe high-speed data and PCM non-volatile memory by performing layered parsing, format conversion, and error correction calibration, thus meeting the requirements for low latency and high reliability.

[0080] like Figure 8 As shown, the architecture of the insertion detection circuit is illustrated. The insertion detection circuit consists of DIMM and PCIe AIC interface detection pins, pull-up resistors, system board connections, and an ASIC scheduling module, which realizes real-time perception of the physical connection status of the interface and dynamic control of protocol conversion.

[0081] Specifically, the detection pin design includes dedicated pins at both ends of the DIMM and PCIe AIC interfaces, connected to the power supply via pull-up resistors, initially at a high level. The level detection logic is as follows: when the interface is inserted, the detection pin is connected to the motherboard's GND, pulling the level low; the ASIC scheduling module collects the levels at both ends in real time, and a low level indicates a reliable connection. A short pin protection mechanism ensures the detection pin is shorter than other signal pins, guaranteeing final contact during insertion and preventing accidental protocol conversion in a partially inserted state.

[0082] Through the above process, the insertion detection circuit accurately identifies the interface connection status through hardware level detection and short pin design, providing a reliable basis for dynamic protocol switching and serving as the core support for hot-plugging and multi-interface compatibility.

[0083] like Figure 9As shown, the architecture of the power module 700 is illustrated. The power module 700 includes an ASIC power supply module, a PCM power supply module, a timing control unit, an overcurrent protection module, a voltage monitoring module, and a backup power unit, realizing multi-voltage domain power supply, timing coordination, and abnormal protection functions.

[0084] Specifically, the ASIC power supply module provides the core voltage (e.g., 1.2V Core, 3.3V IO) for the ASIC chip, supporting dynamic adjustment to adapt to switching between high-performance and low-power modes. The PCM power supply module provides a stable write voltage for the PCM memory chips, supporting dynamic configuration of multiple voltage domains to ensure reliable data writing. The timing control unit strictly manages the power-on sequence, prioritizing the startup of the ASIC chip to prevent damage to the memory chips due to signal instability. The overcurrent protection module monitors the interface current in real time, triggering fuses or current-limiting mechanisms to prevent hardware overload damage. The voltage monitoring module dynamically monitors the stability of each voltage domain and feeds feedback to the calibration module to adjust parameters, ensuring power quality. The backup power unit integrates supercapacitors or batteries to provide instantaneous power during power outages, ensuring complete writing of cached data to the PCM.

[0085] Through the above process, the power module provides safe and stable power support for the ASIC, PCM and interfaces through a multi-level power supply design and protection mechanism, which is the basic guarantee for the reliable operation of the device.

[0086] like Figure 10 As shown, in a data center server, the non-volatile storage method and apparatus provided in this embodiment of the invention are used as a high-speed cache layer. The CPU memory controller is connected via a DIMM interface, and an accelerator card is connected via a PCIe AIC interface. The server needs to process DDR write requests from the CPU and PCIe write requests from the accelerator card, persistently storing data in the PCM granules.

[0087] Specifically, during power-on initialization: When the power module starts up, the timing control unit prioritizes powering the ASIC chip (1.2V Core, 3.3V IO), then provides a stable write voltage to the PCM memory chip. The backup power unit (supercapacitor) enters standby mode, and the overcurrent protection module monitors the current in real time. Protocol scheduling module: The scheduling module detects the pin levels of the DIMM interface (pin6 / pin288) and the PCIe AIC interface (pin4 / pin78) through an insertion detection circuit. If a low level is detected on the DIMM interface (insertion state), the RAM protocol conversion path is initiated; if a low level is detected on the PCIe AIC interface, the NRAM protocol conversion path is initiated. If both interfaces are inserted simultaneously, the PCIe high-speed request is responded to first.

[0088] Further, the DDR write operation process (path on the left): The DDR controller sends write commands: The CPU sends DDR4 write commands (such as ACT+WRITE) through the DIMM interface. After receiving the command, the DDR controller converts the signal into an internal digital format through the DDR PHY layer.

[0089] Signal reception and validity verification: The DDR PHY and DDR CTRL modules complete signal reception and timing conversion, and verify the legality of commands (such as address range and timing compliance). If invalid, the process terminates; if valid, it proceeds to the data reception stage.

[0090] DDR protocol data reception and conversion: DDR protocol data is mapped from logical address to PCM physical address via RAM protocol conversion module, and the DDR data bit width is converted into PCM internal format.

[0091] Central Scheduling and PCM Writing: Data is distributed to the target PCM storage particle channel via DPTH (Data Hub). PCMCTRL parses the instructions and drives the PHY layer to execute the write operation. The ECC module generates LDPC error correction codes in real time, which are written to the PCM unit along with the data.

[0092] Write verification and link recovery: After the PCM PHY returns a write completion signal, the ECC module verifies data integrity. If a bit error is detected (such as due to charge leakage), an error correction process is triggered; if the verification is successful, the DIMM interface link is restored to standby state.

[0093] Further, the PCIe write operation process (path on the right) The PCIe controller sends write commands: The accelerator card sends TLP write packets through the PCIe AIC interface. The PCIe controller parses the packet header and extracts the read / write instructions and data address.

[0094] Signal reception and validity verification: The PCIe PHY and PCIe CTRL modules perform signal deserialization and protocol parsing, verifying the integrity of the TLP packet (such as CRC check). If invalid, a NAK response is sent and the data is discarded; if valid, the data reception phase begins.

[0095] PCIe Protocol Data Conversion and Scheduling: The NRAM protocol conversion module converts PCIe timings into PCM operation timings. DPTH dynamically allocates storage particles based on the current PCM channel load to optimize parallel write efficiency.

[0096] PCM Writing and Error Correction: The PCM CTRL drives the PHY layer to perform data writing, and the ECC module performs Reed-Solomon encoding on the PCIe data to detect and correct potential errors in the PCM unit.

[0097] Link state recovery: After the write is completed, the calibration module adjusts the PCIe PHY drive strength according to the temperature feedback, restores the PCIe AIC interface to a low power state, and the backup power unit exits the power supply mode.

[0098] Through the above process, this invention achieves efficient data persistence for non-volatile storage devices in dual-interface scenarios, realizing dynamic protocol scheduling: interface status awareness based on hardware level detection, combined with priority control, ensures a balanced satisfaction of high-speed PCIe requests and low-latency DDR requirements. End-to-end data protection: the ECC module runs through the entire process of DDR / PCIe data reception and PCM writing, combined with LDPC / Reed-Solomon error correction codes, ensuring data reliability. Storage performance optimization: the DPTH central scheduling and PCM channel management module work together to achieve multi-granularity parallel access and load balancing, reducing access conflicts. Fault tolerance design: the power module backup power unit and overcurrent protection mechanism ensure that data is not lost and hardware is undamaged during power outages or overloads. This fully demonstrates the core advantages of this invention in high compatibility (DIMM / PCIe dual-mode), high reliability (ECC + power protection), and low latency (fast protocol conversion), making it suitable for mixed load scenarios.

[0099] The following are embodiments of the apparatus of the present invention, which can be used to execute the non-volatile storage method involved in the present invention. For details not disclosed in the embodiments of the apparatus of the present invention, please refer to the method embodiments of the non-volatile storage method involved in the present invention.

[0100] Please see Figure 11 This invention provides a non-volatile storage device 800.

[0101] The non-volatile storage device 800 includes, but is not limited to: a dual-interface integrated module 810, a protocol conversion and scheduling module 830, a PCM parameter optimization module 850, and a power supply and temperature control management module 870.

[0102] Among them, the dual-interface integrated module 810 is used to integrate the DIMM interface and the PCIe AIC interface into a single module. The PCB board design is used to arrange the spatial layout and electrical connection of the single module, PCM particle, ASIC chip, temperature sensor and power module.

[0103] The protocol conversion scheduling module 830 is used to integrate RAM and NRAM protocol conversion modules inside the ASIC chip, and to perform status detection and dynamic protocol conversion for the DIMM interface and PCIe AIC interface in combination with scheduling algorithms.

[0104] The PCM parameter optimization module 850 is used to integrate ZQ impedance calibration and write voltage calibration through the calibration module, and optimize PCM write parameters in conjunction with the ECC error feedback mechanism.

[0105] The power supply and temperature control management module 870 is used to acquire dual-interface power supply requirements and PCB temperature distribution data. It utilizes a power module branch power supply design, backup power unit and overcurrent protection, and combines temperature sensing module for real-time monitoring and dynamic parameter adjustment.

[0106] It should be noted that the non-volatile storage provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed. That is, the internal structure of the non-volatile storage device will be divided into different functional modules to complete all or part of the functions described above.

[0107] Furthermore, the embodiments of the non-volatile storage device and the non-volatile storage method provided in the above embodiments belong to the same concept, and the specific way in which each module performs operations has been described in detail in the method embodiments, and will not be repeated here.

[0108] Figure 12 A schematic diagram of the structure of an electronic device according to an exemplary embodiment is shown.

[0109] It should be noted that this electronic device is merely an example adapted to the present invention and should not be construed as providing any limitation on the scope of use of the present invention. Furthermore, this electronic device should not be interpreted as requiring or depending on having... Figure 12 One or more components of the exemplary electronic device 2000 shown.

[0110] The hardware structure of electronic devices 2000 can vary significantly due to differences in configuration or performance, such as... Figure 12 As shown, the electronic device 2000 includes: a power supply 210, an interface 230, at least one memory 250, and at least one central processing unit (CPU) 270.

[0111] Specifically, power supply 210 is used to provide operating voltage for various hardware devices on electronic device 2000.

[0112] Interface 230 includes at least one wired or wireless network interface 231 for interacting with external devices. Of course, in other examples adapted to this invention, interface 230 may further include at least one serial-to-parallel conversion interface 233, at least one input / output interface 235, and at least one USB interface 237, etc. Figure 12 As shown, this does not constitute a specific limitation.

[0113] The memory 250 serves as a carrier for resource storage and can be a read-only memory, random access memory, disk, or optical disk, etc. The resources stored on it include the operating system 251, application programs 253, and data 255, etc., and the storage method can be temporary storage or permanent storage.

[0114] The operating system 251 is used to manage and control the various hardware devices and application programs 253 on the electronic device 2000, so as to enable the central processing unit 270 to perform calculations and processing on the massive data 255 in the memory 250. It can be Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0115] Application 253 is a computer-readable instruction based on operating system 251 that performs at least one specific task, and may include at least one module ( Figure 12 (Not shown), each module may contain computer-readable instructions for electronic device 2000. For example, a non-volatile storage device may be considered as application program 253 deployed on electronic device 2000.

[0116] Data 255 may be signal information, etc., and is stored in memory 250.

[0117] The central processing unit 270 may include one or more processors and is configured to communicate with the memory 250 via at least one communication bus to read computer-readable instructions stored in the memory 250, thereby performing operations and processing on massive amounts of data 255 stored in the memory 250. For example, a non-volatile storage method can be implemented by the central processing unit 270 reading a series of computer-readable instructions stored in the memory 250.

[0118] Furthermore, the present invention can also be implemented through hardware circuits or a combination of hardware circuits and software. Therefore, the implementation of the present invention is not limited to any specific hardware circuit, software, or combination thereof.

[0119] Please see Figure 13 This invention provides an electronic device 4000, which may include: a desktop computer, a laptop computer, a server, etc., with sensor recognition capabilities.

[0120] exist Figure 13 In this context, the electronic device 4000 includes at least one processor 4001 and at least one memory 4003.

[0121] The data interaction between the processor 4001 and the memory 4003 can be achieved through at least one communication bus 4002. This communication bus 4002 may include a path for transmitting data between the processor 4001 and the memory 4003. The communication bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus 4002 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 13 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0122] Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0123] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computing functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0124] The memory 4003 may be a ROM (Read Only Memory) or other type of static storage device capable of storing static information and instructions, RAM (Random Access Memory) or other type of dynamic storage device capable of storing information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program instructions or code in the form of instructions or data structures and accessible by the electronic device 4000, but not limited thereto.

[0125] The memory 4003 stores computer-readable instructions, and the processor 4001 can read the computer-readable instructions stored in the memory 4003 through the communication bus 4002.

[0126] The computer-readable instructions are executed by one or more processors 4001 to implement the non-volatile storage methods in the above embodiments.

[0127] Furthermore, this embodiment of the invention provides a storage medium storing computer-readable instructions, which are executed by one or more processors to implement the non-volatile storage method described above.

[0128] This invention provides a computer program product including computer-readable instructions stored in a storage medium. One or more processors of an electronic device read the computer-readable instructions from the storage medium, load and execute the computer-readable instructions, thereby enabling the electronic device to implement the non-volatile storage method described above.

[0129] Compared with related technologies, the beneficial effects of the present invention are: 1. This invention can significantly reduce hardware costs; by integrating DIMM and PCIe AIC dual interfaces in a single module, it avoids the redundant investment of designing separate storage modules for different interfaces, improves hardware reuse rate, and reduces development and production investment.

[0130] 2. This invention has stronger compatibility and scalability; by designing the module interface in accordance with JEDEC and PCI-SIG specifications, the host system can be flexibly deployed according to its own interface type (DIMM or PCIe AIC) without the need for hardware modification of the motherboard, and the scope of adaptation is extended to existing devices and future high-performance computing scenarios.

[0131] 3. This invention can fully leverage the advantages of PCM media; through a protocol conversion module, it achieves dynamic conversion of PCM protocol to DDR / PCIe protocol, enabling the high-speed read / write and non-volatile characteristics of PCM to be effectively utilized in different interface scenarios, breaking through the limitations of traditional storage technology in high-performance computing.

[0132] 4. This invention offers higher data reliability; through the ECC error correction module and channel redundancy design, the data error rate is significantly reduced. Combined with the mechanism of automatic replacement of faulty particles by the backup PCM unit, it meets the stringent data integrity requirements of scenarios such as industrial control and financial data.

[0133] 5. This invention can effectively ensure power supply stability; through the power supply module's branch power supply design and multi-level protection mechanism (backup power unit, overcurrent protection, voltage monitoring), data loss is avoided during power outages or short circuits. In the event of a main power failure, a combination of tantalum capacitors can provide temporary power to ensure that incomplete write operations are executed normally.

[0134] 6. This invention has intelligent temperature control capabilities; it monitors the PCB temperature distribution in real time through a temperature sensing module, and dynamically adjusts PCM read / write parameters (such as reducing pulse width and frequency reduction) in conjunction with an ASIC scheduling module to suppress local hot spots, extend the service life of the PCM medium, and ensure stable operation of the system in high-temperature environments.

[0135] 7. This invention can optimize system operation and maintenance costs; the non-volatile nature of PCM media reduces the additional storage devices required for data persistence, and combined with wear leveling strategies, it extends the lifespan of the media, thereby reducing the average annual operation and maintenance costs in data center scenarios and demonstrating significant long-term benefits.

[0136] It should be understood that although the steps in the flowcharts of the accompanying figures are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the accompanying figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0137] The above description is only a partial embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A nonvolatile memory method, comprising: The method comprises: Integrating the DIMM interface and the PCIe AIC interface into a single module, and performing spatial layout and electrical connection of the single module, PCM particles, ASIC chips, temperature sensors, and power modules through PCB board design; Integrating RAM and NRAM protocol conversion modules inside the ASIC chip, and combining a scheduling algorithm to perform state detection and dynamic protocol conversion on the DIMM interface and the PCIe AIC interface; Integrating ZQ impedance calibration and write voltage calibration through a calibration module, and combining an ECC error feedback mechanism to optimize PCM write parameters; Obtaining dual-interface power supply requirements and PCB temperature distribution data, and performing shunt power supply design, backup power unit, and overcurrent protection through a power module, and combining a temperature sensing module to perform real-time monitoring and dynamic parameter adjustment.

2. The nonvolatile memory method according to claim 1, wherein, The integration of the DIMM interface and the PCIe AIC interface into a single module, and the spatial layout and electrical connection of the single module, PCM particles, ASIC chips, temperature sensors, and power modules through PCB board design, comprises: Designing the overall structure framework of the single module according to the specification standards of the DIMM interface and the PCIe AIC interface, planning the spatial layout on the PCB board, and deploying the PCM particles in sequence on the front side of the PCB board; the structure framework includes the position, specification, and pin definition of the gold finger; Deploying the ASIC chip on the right side of the PCB board, and deploying the temperature sensor at a set position on the PCB board, deploying the PCM particles, DDR4 particles, temperature sensor, and main power module on the back side of the PCB board, and designing a signal matching circuit.

3. The nonvolatile memory method of claim 2, wherein, The integration of the DIMM interface and the PCIe AIC interface into a single module, and the spatial layout and electrical connection of the single module, PCM particles, ASIC chips, temperature sensors, and power modules through PCB board design, further comprises: According to the spatial layout, placing the PCM particles in sequence along the horizontal direction on the front side of the PCB board, and deploying the ASIC chip at a set position on the right side of the PCM particles; the ASIC chip integrates a protocol conversion module, a scheduling module, and a calibration module; Deploying the temperature sensor at a set position, and electrically connecting the PCM particles, ASIC chip, and temperature sensor according to the signal matching circuit; the temperature sensor is used for real-time monitoring of temperature changes in a specific area.

4. The nonvolatile memory method of claim 2, wherein, The integration of the DIMM interface and the PCIe AIC interface into a single module, and the spatial layout and electrical connection of the single module, PCM particles, ASIC chips, temperature sensors, and power modules through PCB board design, further comprises: Deploying the PCM particles in sequence along the vertical direction on the back side of the PCB board according to the principle of symmetrical layout, ensuring that the PCM particles on the front side of the PCB board are consistent in electrical characteristics, and sharing a group of DQ signals; Deploying DDR4 particles, temperature sensors, main power modules at the set position, and electrically connecting the PCM particles, DDR4 particles, temperature sensors, and main power modules on the back of the PCB board according to the signal matching circuit, while connecting with the components on the back and front of the PCB board.

5. The nonvolatile memory method of claim 1, wherein, The RAM and NRAM protocol conversion modules are integrated in the ASIC chip, and a scheduling algorithm is combined to detect the state of the DIMM interface and the PCIe AIC interface and dynamically convert the protocol, including: An integrated circuit design technology is used to integrate a scheduling module, a RAM protocol conversion module, and an NRAM protocol conversion module in the ASIC chip, while optimizing the layout and wiring of the chip; Special detection pins are arranged at both ends of the DIMM interface and the PCIe AIC interface, and an upper pull resistor is connected to the power supply to form an initial high-level state. When the interface is correctly inserted, the detection pin is conductive to the mainboard, and the level is pulled down. The level value of the detection pin at both ends is collected in real time by the scheduling module; Only when low levels are detected at both ends at the same time, it is determined that the interface is reliably connected. The scheduling module outputs a control signal according to the connection state of the interface using a preset scheduling algorithm, and starts the corresponding protocol conversion module. The detection pin is shorter than the conventional pin.

6. The nonvolatile memory method of claim 1, wherein, The RAM and NRAM protocol conversion modules are integrated in the ASIC chip, and a scheduling algorithm is combined to detect the state of the DIMM interface and the PCIe AIC interface and dynamically convert the protocol, including: When the RAM protocol conversion module is started, the electrical signal of the DIMM interface is converted into a digital signal by the DDR PHY unit, and the write command and data sent by the DDR controller are received. The write command is parsed and packaged into a custom DPT data, i.e. Data-PCM Transition, by the DDR CTRL unit. The DPT data is aggregated in the ASIC to a custom DPTH, i.e. Data-PCM Transition Hub, unit, which is mapped to a PCM physical address. The DDR data format is converted into a data format supported by the PCM particle, and the DDR control signal is converted into a PCM control signal. The PCM physical address is transmitted to the PCM control unit to generate a PCM PHY executable instruction.

7. The nonvolatile memory method of claim 1, wherein, The ZQ impedance calibration and write voltage calibration are integrated by the calibration module, and the PCM write parameters are optimized by combining the ECC error feedback mechanism to obtain the dual-interface power supply requirements and PCB temperature distribution data. The power supply module is designed by shunt power supply, backup unit, and overcurrent protection, and the temperature sensing module is combined to monitor and dynamically adjust the parameters in real time, including: The calibration module sends a start signal to the RAM protocol conversion module, and the ZQ pin is pulled down for sampling. The actual impedance of the DDR signal link is compared with the impedance of the ZQ reference resistor to generate an impedance deviation value, and the impedance is adjusted according to the impedance deviation value. The write state signal of the PCM particle is collected in real time by the calibration module according to the voltage calibration signal, the resistance change rate is calculated, the write voltage is adjusted according to the resistance change rate, the error feedback of the ECC module is received, and if single-bit errors are concentrated in the PCM particle, the write voltage of the PCM particle is adjusted; The power supply module is designed for shunt power supply according to the power supply demand of the double interfaces, a backup power unit is set and an overcurrent protection module is integrated, the temperature distribution data of the PCB is monitored in real time by the temperature sensing module, and the read-write parameters of the PCM are dynamically adjusted by the scheduling module in combination with the temperature data.

8. A nonvolatile storage device, comprising: The device comprises: A double-interface integrated module is used to integrate the DIMM interface and the PCIe AIC interface into a single module, and the single module, the PCM particle, the ASIC chip, the temperature sensor and the power supply module are spatially laid out and electrically connected through PCB board design; A protocol conversion scheduling module is used to integrate the RAM and NRAM protocol conversion modules in the ASIC chip, and the state of the DIMM interface and the PCIe AIC interface is detected and dynamically protocol-converted by combining the scheduling algorithm; A PCM parameter optimization module is used to integrate the ZQ impedance calibration and the write voltage calibration by the calibration module, and the PCM write parameters are optimized by combining the ECC error feedback mechanism; A power supply and temperature control management module is used to obtain the power supply demand of the double interfaces and the PCB temperature distribution data, and the shunt power supply design, the backup power unit and the overcurrent protection are combined with the temperature sensing module for real-time monitoring and dynamic parameter adjustment.

9. An electronic device, comprising: It comprises: At least one processor and at least one memory, The computer readable instructions are stored on the memory; The computer readable instructions are executed by one or more processors to implement the non-volatile storage method of any one of claims 1 to 7.

10. A storage medium having stored thereon computer readable instructions, characterized in that, The computer readable instructions are executed by one or more processors to implement the non-volatile storage method of any one of claims 1 to 7.

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