Memory super-division method and device, electronic equipment and computer readable storage medium

Abstract

The invention provides a memory super-division method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of computers. The method comprises the following steps: responding to a cache application request, and sequentially distributing joint cache identifiers; in response to an outbound signal of an outbound memory direct access engine, determining an idle physical cache unit and a joint cache identifier of a corresponding request before the idle physical cache unit is released, then adding one to a round value in the joint cache identifier, and determining a target joint cache identifier; the inbound memory direct access engine responds to a target request corresponding to the target joint cache identifier, and data corresponding to the target request is written into a physical cache unit corresponding to the target joint cache identifier; a cyclic storage mode is established in the cache depending on the cache identifier and the round value of the physical cache unit, so that the time for waiting for cache release in a service control process is shortened, the rate of reading and writing IO and network messages is improved, and the area, the cost and the power consumption of a chip are controlled.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a memory super-division method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] Storage device controllers and network forwarding chips both need to support high concurrency. Within the chip, dozens or even hundreds of read / write I / Os and network packets can be processed concurrently, and these packets must also support variable-length read / write I / Os and network packets. Therefore, a high-speed SRAM cache of several megabytes to tens of megabytes is needed within the controller chip to temporarily store the data from these read / write I / Os and network packets. To improve the speed of read / write I / Os and network packets, a large-capacity controller chip is required, leading to increased chip area, cost, and power consumption. Summary of the Invention

[0003] The purpose of this invention is to provide a memory super-division method, apparatus, electronic device, and computer-readable storage medium. In the cache, a circular storage mode is established based on the cache identifier and round value of the physical cache unit, which reduces the time waiting for cache release in the business control process, improves the read and write I / O and network packet rate, and thus controls chip area, cost and power consumption.

[0004] In a first aspect, the present invention provides a memory super-division method, comprising: The hardware cache management unit responds to cache requests from external devices and allocates joint cache identifiers sequentially according to the request sequence; the joint cache identifier is determined by adding a round value to the cache identifier of the physical cache unit; The hardware cache management unit responds to the outbound signal from the outbound memory direct access engine, determines the free physical cache unit and the joint cache identifier of the request corresponding to the free physical cache unit before its release; The hardware cache management unit increments the round value in the union cache identifier of the request corresponding to the release of the idle physical cache unit by one, and then determines the target union cache identifier. The inbound memory direct access engine responds to the target request corresponding to the target federated cache identifier and writes the data corresponding to the target request into the physical cache unit corresponding to the target federated cache identifier.

[0005] In some preferred embodiments of the present invention, the step of allocating a combined cache identifier sequentially according to the timing of a request from an external device to request cache includes: Based on the timing of the received requests, the cache identifiers of the physical cache units are allocated sequentially according to a preset order; After all physical cache units have been allocated cache identifiers, the round number is incremented by one, and allocation starts again from the initial physical cache unit cache identifier.

[0006] In some preferred embodiments of the present invention, after the step of writing the data corresponding to the target request into the physical cache unit corresponding to the target federated cache identifier in response to the target request from the inbound memory direct access engine, the method further includes: After all the data corresponding to the target request has been written into the physical cache unit corresponding to the target federated cache identifier, the target federated cache identifier corresponding to the physical cache unit that has completed the data writing is added to the ready queue. Once the data in the physical cache unit has been moved, the corresponding target federated cache identifier will be marked as released.

[0007] In some preferred embodiments of the present invention, the method further includes: Once all federated cache identifiers within the same round are in a released state, the release round pointer is incremented by one.

[0008] In some preferred embodiments of the present invention, the round values ​​form a circular queue; the method further includes: Once the allocation rounds reach their maximum value, determine whether the release round pointer should move. If so, redistribute from the initial round.

[0009] In some preferred embodiments of the present invention, the method is applied to a storage device controller that supports at least one of the following interfaces: a high-speed peripheral component interconnect interface, a serial connection small computer system interface, a serial advanced technology accessory interface, a general flash memory interface, or an embedded multimedia card interface.

[0010] In some preferred embodiments of the present invention, the method is applied to a network forwarding chip that supports at least one of the following interfaces: an Ethernet interface, a fiber optic interface, or a high-speed peripheral component interconnection interface.

[0011] In a second aspect, the present invention provides a memory super-resolution device, comprising: The cache allocation module is used by the hardware cache management unit to respond to requests for cache from external devices and allocate joint cache identifiers sequentially according to the timing of the requests; wherein, the joint cache identifier is determined by adding a round value to the cache identifier of the physical cache unit; The physical cache unit processing module is used by the hardware cache management unit to respond to the outbound signal from the outbound memory direct access engine, determine the free physical cache unit and the joint cache identifier of the request corresponding to the release of the free physical cache unit; The target federated cache identifier processing module is used by the hardware cache management unit to determine the target federated cache identifier by incrementing the round value in the federated cache identifier of the request corresponding to the release of the idle physical cache unit by one. The request processing module is used to respond to the target request corresponding to the target federated cache identifier in the inbound memory direct access engine, and write the data corresponding to the target request into the physical cache unit corresponding to the target federated cache identifier.

[0012] Thirdly, the present invention provides an electronic device including a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the memory super-division method provided in the first aspect above.

[0013] Fourthly, the present invention provides a computer-readable storage medium storing computer-executable instructions, which, when invoked and executed by a processor, cause the processor to implement the memory super-division method provided in the first aspect.

[0014] This invention brings the following beneficial effects: This invention provides a memory super-division method, apparatus, electronic device, and computer-readable storage medium. The method includes: a hardware cache management unit responding to a cache request from an external device and sequentially allocating a joint cache identifier according to the request's timing; wherein the joint cache identifier is determined by adding a round value to the cache identifier of a physical cache unit; the hardware cache management unit responding to an outbound signal from an outbound memory direct access engine, determining an idle physical cache unit and the joint cache identifier of the request corresponding to the release of the idle physical cache unit; the hardware cache management unit incrementing the round value in the joint cache identifier of the request corresponding to the release of the idle physical cache unit by one to determine a target joint cache identifier; the inbound memory direct access engine responding to a target request corresponding to the target joint cache identifier and writing the data corresponding to the target request into the physical cache unit corresponding to the target joint cache identifier; establishing a circular storage mode in the cache based on the cache identifier and round value of the physical cache unit reduces the time waiting for cache release in the business control process, improves the read / write I / O and network packet rates, thereby controlling chip area, cost, and power consumption. Attached Figure Description

[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the cache resource allocation process within the controller in the existing technology; Figure 2A flowchart of a memory super-resolution method provided in an embodiment of the present invention; Figure 3 This invention provides a flowchart of a memory super-multiplexing allocation process. Figure 4 This is a schematic diagram of a cache release and reclamation mechanism provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a memory super-resolution device provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0017] Icons: 310 - Cache allocation module; 320 - Physical cache unit processing module; 330 - Target federated cache identification processing module; 340 - Request processing module; 400 - Memory; 401 - Processor; 402 - Bus; 403 - Communication interface. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0024] See Figure 1 The diagram shown illustrates the cache resource allocation process within the controller in the prior art. This process includes: Step 1: The front-end interface receives the input / output command from the host and then notifies the central processing unit that a new input / output request has arrived; Step 2: The central processing unit requests cache resources from the memory management unit. In this step, it's possible that cache resources cannot be obtained for the current input / output command because other parts of the process may not have released them yet. Step 3: The central processing unit sends the configuration information for direct memory access to the direct memory access engine; Step 4: The direct memory access engine moves data from the host's memory to the chip's internal static random access memory cache; Step 5: After receiving data from the entry direct memory access, the central processing unit configures the exit direct memory access. Step 6: Configure the backend output of the central processing unit and start data transmission; Step 7: After the data transmission is complete, the cache can be released directly from memory access at the exit point, or the cache can be released by the central processing unit.

[0025] In step 7, the cache resources are released. In the next IO step 2, the resources are obtained. In step 3, they are configured for direct memory access. In the next step 4, data transmission begins. There is idle buffer in the middle, and the cache is not utilized to the maximum extent, which affects the read and write IO and network packet speed.

[0026] This invention provides a memory super-division method that establishes a circular storage mode in the cache based on the cache identifier and round value of the physical cache unit. This reduces the time waiting for cache release in the business control process, improves the read / write I / O and network packet speed, and can thus reduce chip area, cost and power consumption.

[0027] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] Example 1 This invention provides a memory super-division method, see [link to relevant documentation]. Figure 2 The flowchart shown in this embodiment of the invention provides a memory super-resolution method, which includes: In step S102, the hardware cache management unit responds to the request for cache from the external device and allocates joint cache identifiers sequentially according to the timing of the requests; wherein, the joint cache identifier is determined based on adding a round value to the cache identifier of the physical cache unit.

[0029] Specifically, the round value is generally not restricted to a specific position. In this embodiment of the invention, the round value is placed in the high-order bits of the cache identifier. The calculation method for the joint cache identifier is: Joint cache identifier = [round value] << (shift bits) + [physical cache identifier]. When the firmware or microcode requests cache for the currently processed input / output, the hardware cache management module changes the memory allocation mechanism from the original method of determining whether the cache is free before allocating the identifier, to not determining whether the cache is free, and allocating according to the order of physical cache identifiers from smallest to largest. The core innovation of this allocation mechanism is that it delays the resource availability check from the allocation stage to the usage stage. Regardless of whether the currently allocated cache is free or already allocated, a status check mechanism is used during actual hardware use to ensure data integrity.

[0030] Furthermore, in some preferred embodiments of the present invention, the step of responding to a request from an external device to request caching and sequentially allocating joint cache identifiers according to the timing of the requests includes: sequentially allocating cache identifiers of physical cache units in a preset order according to the timing of the received requests; after allocating cache identifiers of all physical cache units, incrementing the round value by one, and then re-allocating from the initial cache identifier of the physical cache unit.

[0031] Specifically, the preset order can be from smallest to largest, and the cache identifier of the initial physical cache unit is the cache identifier of the smallest physical cache unit. See [link to relevant documentation]. Figure 3 The flowchart of the memory super-reuse allocation provided in this embodiment of the invention illustrates that after allocating one round of physical cache identifiers (N), the allocation round number is incremented by one, and allocation restarts from the smallest physical cache identifier. This cyclic allocation mechanism allows limited physical cache resources to be logically expanded, achieving memory super-reuse. Through this sequential allocation mechanism, even when cache resources are insufficient, joint cache identifiers can continue to be allocated to the next input / output command request step, significantly alleviating the problem of firmware or microcode suspension due to insufficient resources. This allocation strategy ensures that even in high-concurrency scenarios, each input / output request can obtain a logical cache identifier, allowing the business process to continue and avoiding performance bottlenecks caused by waiting for idle cache in traditional methods. Simultaneously, the sequential allocation mechanism simplifies hardware implementation complexity and improves allocation efficiency.

[0032] It is important to emphasize that the preset order can be from largest to smallest, and the cache identifier of the initial physical cache unit is the cache identifier of the largest physical cache unit.

[0033] In step S104, the hardware cache management unit responds to the outbound signal from the outbound memory direct access engine and determines the free physical cache unit and the joint cache identifier of the request corresponding to the free physical cache unit before its release.

[0034] Specifically, when other chips or firmware modules notify the hardware cache management module to release a certain joint cache identifier, the hardware cache management module accurately identifies reusable physical cache units based on a fine-grained state tracking mechanism. After the release signal is triggered, the hardware cache management module marks the corresponding joint cache identifier calculated in the next round as idle. This process is implemented through a hardware state machine to ensure the atomicity and real-time nature of state transitions.

[0035] In step S106, the hardware cache management unit increments the round value in the combined cache identifier of the request corresponding to the release of the idle physical cache unit by one, and then determines the target combined cache identifier.

[0036] Specifically, the hardware cache management module employs an advanced state update algorithm, setting the combined cache identifier corresponding to [round value + 1] << (shift bit) + [physical cache identifier] to an idle state. This marking mechanism based on the next round ensures timely reclamation and availability of cache resources while avoiding resource conflicts between different rounds. The state update process is processed in parallel by hardware and can be completed in nanoseconds, greatly improving resource reclamation efficiency.

[0037] In step S108, the inbound direct memory access engine responds to the target request corresponding to the target federated cache identifier and writes the data corresponding to the target request into the physical cache unit corresponding to the target federated cache identifier.

[0038] Specifically, the inbound direct memory access engine can only be used when the union cache flag is in a released or idle state. This mechanism is implemented through hardware-level state verification circuitry, ensuring that only truly usable cache resources are put into use. Once the corresponding physical cache flag is released, the hardware immediately notifies the inbound part of the state update via a dedicated notification link, making the direct memory access triggering condition ready and achieving low-latency hardware-level notification. This hardware coordination mechanism reduces the latency from resource readiness to usage from microseconds to nanoseconds, significantly improving the turnaround efficiency of cache resources.

[0039] Furthermore, in some preferred embodiments of the present invention, after the inbound memory direct access engine responds to the target request corresponding to the target federated cache identifier and writes the data corresponding to the target request into the physical cache unit corresponding to the target federated cache identifier, the method further includes: after all the data corresponding to the target request has been written into the physical cache unit corresponding to the target federated cache identifier, adding the target federated cache identifier corresponding to the physical cache unit that has completed the data writing to the ready queue; and after the data in the physical cache unit has been moved, indicating the corresponding target federated cache identifier as released.

[0040] Specifically, the entry control submodule in the Direct Memory Access (DMI) module, through hardware queue management circuitry, sets the entry using the combined cache identifier to the ready state from the waiting queue upon receiving notification of a cache resource status change, or moves it to the ready queue via the hardware scheduler. After the preceding entry completes its data transfer, the DMI engine uses a round-robin or priority scheduling algorithm to automatically select an entry from the ready state or the ready queue to begin data transfer. This complete pipelined processing mechanism ensures the efficiency and continuity of data transfer.

[0041] Furthermore, in some preferred embodiments of the present invention, the method further includes: after all the joint cache identifiers in the same round are in a released state, the release round pointer is incremented by one.

[0042] For details, please refer to [link / reference]. Figure 3 The hardware cache management module precisely tracks the status of all union cache identifiers within each round using a bitmap or counter mechanism. After all union cache identifiers in the current round are released, the release round pointer inside the hardware cache management module is automatically incremented by one, indicating that the current round has been completely released and can be reallocated. This mechanism is implemented through a hardware state machine to ensure the accuracy and efficiency of round management.

[0043] Furthermore, in some preferred embodiments of the present invention, the round values ​​form a circular queue; the method further includes: when the allocation round reaches the maximum value of the round value, determining whether the release round pointer has moved; if so, re-allocating from the initial round.

[0044] For details, please refer to [link / reference]. Figure 3 The allocation rounds are used to form a circular buffer through modulo operations. After the allocation rounds reach their maximum value (M) and all combined cache identifiers have been allocated, the hardware checks the release round pointer status through a comparator circuit. If all combined cache identifiers from the initial round have been released (i.e., the release round pointer has moved up), the allocation round can point to the initial round and continue allocation. The allocation condition is implemented through hardware logic circuitry: (allocation rounds + 1); the maximum number of rounds cannot be equal to the release round. This condition ensures that resources that have not yet been released will not be overwritten, guaranteeing data security.

[0045] For example, see Figure 4 The diagram illustrates a cache release and reclamation mechanism provided by an embodiment of the present invention. Cache units with round number 6 and cache identifier 2, round number 7 and cache identifier 3, round number 7 and cache identifier 6, round number 6 and cache identifier 11, and round number 5 and cache identifier 14 are to be released. A combined cache identifier with the same round number plus one is marked as idle. When a combined cache identifier becomes idle, the chip internally notifies the direct memory access engine that the combined cache identifier can now be used to allocate to its corresponding direct memory access entry. Upon receiving the notification of the cache resource status change, the direct memory access entry control submodule in the direct memory access module sets the entry using the combined cache identifier to the ready state from the queue, or moves it to the ready queue. After the preceding entry completes data migration, the direct memory access engine selects an entry from the ready state or the ready queue and automatically begins data transmission.

[0046] Furthermore, in some preferred embodiments of the present invention, the method is applied to a storage device controller that supports at least one of the following interfaces: Peripheral Component Interconnect Express (PCIe), Serial Attached Small Computer System Interface (SAS), Serial Advanced Technology Attachment (SATA), Universal Flash Storage (UFS), or embedded MultiMediaCard (eMMC).

[0047] Specifically, the storage device controller processes input / output commands issued by the host and performs data transfer between host memory and the on-chip static random access memory cache via a direct memory access engine. In this solution, the storage controller, through an innovative memory super-division mechanism, can support higher input / output concurrency with limited on-chip cache resources while maintaining low access latency. Especially when handling bursty input / output loads, this solution effectively avoids performance degradation due to insufficient cache resources.

[0048] Furthermore, in some preferred embodiments of the present invention, the method is applied to a network forwarding chip that supports at least one of the following interfaces: Ethernet interface (ETH), FC fiber optic interface, or high-speed peripheral component interconnect interface (PCIe).

[0049] Specifically, the network forwarding chip is used to receive and send network packets, and performs data transfer between the interface and the chip's internal static random access memory cache through a direct memory access engine. In network forwarding scenarios, this solution uses a memory super-division mechanism to enable limited cache resources to serve more concurrent network flows, thereby improving packet forwarding throughput. Simultaneously, a hardware-level fast resource reclamation mechanism ensures that latency-sensitive network applications receive timely resource allocation.

[0050] This invention achieves a significant increase in cache identifier resources by extending the high-order bits of the cache identifier to a round-robin field, supporting memory over-division and reuse, and reducing the blocking of firmware or microcode business processes due to insufficient cache resources. This logical identifier extension mechanism is implemented through simple bit operations, with minimal hardware overhead but significant effects. A chip-level hardware notification mechanism enables fully automated management of cache resources from release to reuse, minimizing software involvement and accelerating the rotation speed of cache resource usage. Real-world testing shows that under typical workloads, this solution can improve cache resource utilization to 2-3 times that of traditional methods.

[0051] This invention is particularly suitable for cost-sensitive embedded systems and data center scenarios that prioritize high resource utilization. By streamlining the static random access memory (SRAM) cache size to just meet business needs, chip area can be reduced by approximately 15%-30%, while achieving significant gains in chip cost and power consumption. The power reduction primarily stems from the reduction in SRAM area and optimization of dynamic power consumption.

[0052] This invention achieves a balance between performance, flexibility, and cost by rationally dividing the work between software and chips. Software handles the logical allocation of resources, while hardware manages their real-time status and facilitates rapid recycling. This collaborative software-hardware design allows the solution to adapt to diverse business needs while providing near-hardware performance.

[0053] This invention allocates the same physical memory to multiple read / write input / output or forwarding packets; through the expansion of logical cache identifiers and a hardware-based fast reclamation mechanism, it achieves efficient reuse of physical memory. This innovative spatiotemporal reuse design allows physical memory resources to be shared by multiple logical entities in the time dimension, significantly improving resource utilization. Simultaneously, the hardware-protected isolation mechanism ensures data security and integrity between different logical entities.

[0054] This invention provides a memory super-division method, comprising: a hardware cache management unit responding to a cache request from an external device and sequentially allocating a joint cache identifier according to the timing of the request; wherein, the joint cache identifier is determined by adding a round value to the cache identifier of the physical cache unit; the hardware cache management unit responding to an outbound signal from an outbound memory direct access engine and determining an idle physical cache unit and the joint cache identifier of the request corresponding to the release of the idle physical cache unit; the hardware cache management unit incrementing the round value in the joint cache identifier of the request corresponding to the release of the idle physical cache unit by one to determine a target joint cache identifier; the inbound memory direct access engine responding to a target request corresponding to the target joint cache identifier and writing the data corresponding to the target request into the physical cache unit corresponding to the target joint cache identifier; establishing a circular storage mode in the cache based on the cache identifier and round value of the physical cache unit reduces the time waiting for cache release in the business control process, improves the read / write IO and network packet rates, thereby controlling chip area, cost, and power consumption.

[0055] Example 2 Based on the above embodiments, this invention provides a memory super-resolution device, see [link to previous embodiment]. Figure 5 The diagram shown is a structural schematic of a memory super-resolution device according to an embodiment of the present invention. The device includes: The cache allocation module 310 is used by the hardware cache management unit to respond to the cache request from the external device and allocate joint cache identifiers sequentially according to the timing of the request; wherein, the joint cache identifier is determined based on adding a round value to the cache identifier of the physical cache unit; The physical cache unit processing module 320 is used by the hardware cache management unit to respond to the outbound signal of the outbound memory direct access engine, determine the idle physical cache unit and the joint cache identifier of the request corresponding to the release of the idle physical cache unit; The target federated cache identifier processing module 330 is used by the hardware cache management unit to determine the target federated cache identifier by incrementing the round value in the federated cache identifier of the request corresponding to the release of the idle physical cache unit by one. The request processing module 340 is used to respond to the target request corresponding to the target federated cache identifier in the inbound memory direct access engine and write the data corresponding to the target request into the physical cache unit corresponding to the target federated cache identifier.

[0056] Furthermore, in some preferred embodiments of the present invention, the cache allocation module 310 is used to allocate cache identifiers of physical cache units sequentially according to the timing of the received requests and in a preset order; after all the cache identifiers of all physical cache units have been allocated, the round value is incremented by one, and allocation starts again from the cache identifier of the initial physical cache unit.

[0057] Furthermore, in some preferred embodiments of the present invention, the apparatus further includes: a cache release processing module, used to add the target combined cache identifier corresponding to the physical cache unit that has completed data writing to the ready queue after all the data corresponding to the target request has been written into the physical cache unit corresponding to the target combined cache identifier; and to indicate the corresponding target combined cache identifier as released after the data in the physical cache unit has been moved.

[0058] Furthermore, in some preferred embodiments of the present invention, the cache release processing module is also used to increment the release round pointer by one after all the joint cache identifiers in the same round are in the released state.

[0059] Furthermore, in some preferred embodiments of the present invention, the round values ​​form a circular queue; the cache allocation module 310 is also used to determine whether the release round pointer has moved after the allocation round reaches the maximum value of the round value; if so, the allocation starts again from the initial round.

[0060] Furthermore, in some preferred embodiments of the present invention, the apparatus is applied to a storage device controller that supports at least one of the following interfaces: a high-speed peripheral component interconnect interface, a serial connection small computer system interface, a serial advanced technology accessory interface, a general flash memory interface, or an embedded multimedia card interface.

[0061] Furthermore, in some preferred embodiments of the present invention, the device is applied to a network forwarding chip that supports at least one of the following interfaces: an Ethernet interface, a fiber optic interface, or a high-speed peripheral component interconnection interface.

[0062] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the memory super-division device described above can be referred to the corresponding process in the aforementioned embodiments of the memory super-division method, and will not be repeated here.

[0063] Example 3 This invention also provides an electronic device for running a memory super-resolution method; see [link to related documentation]. Figure 6 The schematic diagram of an electronic device provided by the embodiment of the present invention shown below includes a memory 400 and a processor 401. The memory 400 is used to store one or more computer instructions, which are executed by the processor 401 to implement the above-mentioned memory super-division method.

[0064] Furthermore, Figure 6 The electronic device shown also includes a bus 402 and a communication interface 403. The processor 401, the communication interface 403 and the memory 400 are connected via the bus 402.

[0065] The memory 400 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 403 (which can be wired or wireless), such as the Internet, wide area network, local area network, metropolitan area network, etc. The bus 402 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0066] Processor 401 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of processor 401 or by instructions in software form. Processor 401 can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this invention can be directly manifested as execution by a hardware decoding processor, or execution by a combination of hardware and software modules in the decoding processor. The software module can reside in a readily available storage medium in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 400, and processor 401 reads information from memory 400 and, in conjunction with its hardware, completes the steps of the method described in the foregoing embodiments.

[0067] This invention also provides a computer-readable storage medium storing computer-executable instructions. When these computer-executable instructions are called and executed by a processor, they cause the processor to implement the above-described memory super-division method. For specific implementation details, please refer to the method embodiments, which will not be repeated here.

[0068] The computer program products of the memory super-division method, apparatus and electronic device provided in the embodiments of the present invention include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the methods in the preceding method embodiments. For specific implementation, please refer to the method embodiments, which will not be repeated here.

[0069] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the system and / or device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0070] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0071] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory overcommitment method, characterized by, The method comprises the following steps: The hardware cache management unit determines the idle physical cache unit and the joint cache identifier corresponding to the request before the idle physical cache unit is released in response to the outbound signal of the outbound memory direct access engine. The hardware cache management unit determines the target joint cache identifier after adding one to the round value in the joint cache identifier corresponding to the request before the idle physical cache unit is released. The inbound memory direct access engine writes data corresponding to the target request into the physical cache unit corresponding to the target joint cache identifier in response to the target request corresponding to the target joint cache identifier. The step of assigning the joint cache identifier in sequence according to the time sequence of the request in response to the request of the external device for cache application comprises the following steps:

2. The memory overcommitment method of claim 1, wherein, The cache allocation module is configured to assign the cache identifier of the physical cache unit in sequence according to the preset order according to the time sequence of the received request. When all the cache identifiers of the physical cache units are assigned, the round value is added by one, and the assignment of the cache identifier is restarted from the initial cache identifier of the physical cache unit. After the step of writing the data corresponding to the target request into the physical cache unit corresponding to the target joint cache identifier in response to the target request corresponding to the target joint cache identifier by the inbound memory direct access engine, the method further comprises the following steps:

3. The memory overcommitment method of claim 1, wherein, After the data corresponding to the target request is completely written into the physical cache unit corresponding to the target joint cache identifier, the target joint cache identifier corresponding to the physical cache unit where the data writing is completed is added to the ready queue. When the data in the physical cache unit is completely moved, the corresponding target joint cache identifier is indicated as a release state. The method further comprises the following steps:

4. The memory overcommitment method of claim 3, wherein, After all the joint cache identifiers in the same round are in the release state, the release round pointer is added by one. The round value forms a ring queue, and the method further comprises the following steps:

5. The memory overcommitment method of claim 4, wherein, When the assignment round reaches the maximum value of the round value, it is determined whether the release round pointer is moved. If yes, the assignment of the round is restarted from the initial round. The method is applied to a storage device controller, and the storage device controller supports at least one of the following interfaces: a peripheral component interconnect express interface, a serial advanced technology attachment interface, a universal flash storage interface, or an embedded multimedia card interface.

6. The memory overcommitment method according to any of claims 1 to 5, characterized in that, The method is applied to a network forwarding chip, and the network forwarding chip supports at least one of the following interfaces: an Ethernet interface, a fiber interface, or a peripheral component interconnect express interface.

7. The memory overcommitment method according to any of claims 1 to 5, characterized in that, The method comprises the following steps:

8. A memory overcommitment device, comprising: The cache allocation module is configured to assign the joint cache identifier in sequence according to the time sequence of the request in response to the request of the external device for cache application by the hardware cache management unit; wherein the joint cache identifier is determined based on adding a round value to the cache identifier of the physical cache unit. ​ A physical cache unit processing module, configured to determine an idle physical cache unit and a corresponding joint cache identifier of the request before the idle physical cache unit is released by the hardware cache management unit in response to an outbound signal of the outbound memory direct access engine. A target joint cache identifier processing module, configured to determine a target joint cache identifier by adding one to a round value in the corresponding joint cache identifier of the request before the idle physical cache unit is released by the hardware cache management unit. A request processing module, configured to write data corresponding to a target request into a physical cache unit corresponding to the target joint cache identifier in response to the target request corresponding to the target joint cache identifier by the inbound memory direct access engine.

9. An electronic device, comprising: A processor and a memory, the memory stores computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the memory oversubscription method in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer executable instructions, and the computer executable instructions, when invoked and executed by a processor, cause the processor to implement the memory oversubscription method in any one of claims 1 to 7.

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