Driving circuit, display panel and driving method

Abstract

The invention discloses a driving circuit, a display panel and a driving method. The driving circuit comprises a plurality of cascaded shift registers. The shift register comprises a starting signal end, a first output unit and a second output unit. The first output unit is configured to generate a cascade signal according to a starting signal and serve as a starting signal of a next-stage shifting register. The second output unit is configured to output the driving signal according to the starting signal. In the first mode, the driving signal is configured to drive the pixel circuit, and the cascade signal is consistent with the driving signal, and in the second mode, the driving signal is configured to be a modulation signal of the touch sensor, and the cascade signal is not consistent with the driving signal. The cascade signal and the driving signal are separated signals so as to adapt to the working requirement of the display panel in an intra-frame touch driving mode (Long H), and the situation that a modulation signal of a touch sensor serves as the cascade signal to be transmitted to a next-stage shifting register in advance, and consequently potential drift occurs in the next-stage shifting register is avoided.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and more specifically, to a driving circuit, a display panel, and a driving method. Background Technology

[0002] In related technologies, the gate-on-array (GOA) circuit includes multiple shift registers. These shift registers operate in a cascaded manner. The output signal of one shift register, in addition to serving as the driving signal for the pixel circuit, can also be transmitted to the next shift register in a cascaded manner and used as the start signal for the next shift register.

[0003] When the display panel is operating in intra-frame touch drive mode (Long H), the operating time of the touch sensor is inserted into the period of the display frame. The drive signal of a certain shift register is first used as the modulation signal of the touch sensor, and then as the drive signal of the pixel circuit. At this time, the modulation signal of the touch sensor is transmitted to the next shift register in advance as a cascaded signal, causing potential drift in the next shift register and affecting its performance. Summary of the Invention

[0004] The present invention provides a driving circuit, a display panel, and a driving method.

[0005] The driving circuit provided in this application includes multiple cascaded shift registers. Each shift register includes a start signal terminal, a first output unit, and a second output unit. The first output unit is configured to generate a cascaded signal based on the start signal and use it as the start signal for the next-stage shift register. The second output unit is configured to output a driving signal based on the start signal. In a first mode, the driving signal is configured to drive the pixel circuit, and the cascaded signal is consistent with the driving signal. In a second mode, the driving signal is configured as a modulation signal for the touch sensor, and the cascaded signal is inconsistent with the driving signal.

[0006] The cascaded signal generated by the first output unit and the drive signal provided by the second output unit can be separate signals to adapt to the operating requirements of the display panel in intra-frame touch drive mode (Long H). When the display panel is displaying an image, the cascaded signal and the drive signal are consistent. When the touch sensor is working, the cascaded signal and the drive signal are inconsistent to prevent the modulation signal of the touch sensor from being transmitted to the next-stage shift register as a cascaded signal in advance, thereby avoiding potential drift in the next-stage shift register.

[0007] In some embodiments, the driving circuit further includes a first clock line and a second clock line. The first clock line is configured to provide a first clock signal. The second clock line is configured to provide a second clock signal. The first output unit is configured to generate the cascaded signal based on the first clock signal and the start signal, and the second output unit is configured to output the driving signal based on the second clock signal and the start signal. In the first mode, the first clock signal is consistent with the second clock signal; in the second mode, the first clock signal is inconsistent with the second clock signal.

[0008] In some embodiments, the first output unit includes a first transistor and a first output terminal, with a first terminal of the first transistor connected to the first clock line. A second terminal of the first transistor is connected to the first output terminal. The second output unit includes a second transistor and a second output terminal, with a first terminal of the second transistor connected to the second clock line and a second terminal connected to the second output terminal. The first and second transistors are configured to be turned on according to the activation signal, causing the first output terminal to output a first clock signal and the second output terminal to output a second clock signal.

[0009] In some embodiments, the driving circuit includes a storage capacitor connected in series between the start signal terminal and the control electrode of the first transistor, or connected in series between the start signal terminal and the control electrode of the second transistor.

[0010] In some embodiments, the driving circuit further includes a first signal line and a second signal line. The first signal line is configured to provide a first modulation signal. The second signal line is configured to provide a second modulation signal. The first output unit is configured to output the first modulation signal or the first clock signal, and the second output unit is configured to output the second modulation signal or the second clock signal. In the first mode, the first modulation signal and the second modulation signal are consistent; in the second mode, the first modulation signal and the second modulation signal are inconsistent.

[0011] In some embodiments, the first output unit includes a third transistor, the first terminal of which is connected to the first signal line, and the second terminal of which is connected to the first output terminal. The second output unit includes a fourth transistor, the first terminal of which is connected to the second signal line, and the second terminal of which is connected to the second output terminal. When the third transistor is turned on, the first output terminal outputs a first modulation signal; when the fourth transistor is turned on, the second output terminal outputs a second modulation signal.

[0012] In some embodiments, the driving circuit further includes a third signal line and a fourth signal line. The third signal line is configured to provide a third modulation signal. The fourth signal line is configured to provide a fourth modulation signal. The third transistor includes a first sub-transistor and a second sub-transistor, the first terminal of the first sub-transistor is connected to the first terminal of the second sub-transistor and the first clock line, and the second terminal of the first sub-transistor is connected to the second terminal of the second sub-transistor and the first output terminal. The fourth transistor includes a third sub-transistor and a fourth sub-transistor, the first terminal of the third sub-transistor is connected to the first terminal of the fourth sub-transistor and the second clock line, and the second terminal of the third sub-transistor is connected to the second terminal of the fourth sub-transistor and the second output terminal. The control terminals of the first and third sub-transistors are connected to the third signal line, and the control terminals of the second and fourth sub-transistors are connected to the fourth signal line.

[0013] In some embodiments, the driving circuit further includes a fifth transistor and a sixth transistor, wherein the first terminal of the fifth transistor is connected to the third signal line, the first terminal of the sixth transistor is connected to the fourth signal line, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the second signal line, and the control terminal of the fifth transistor is connected to the control terminal of the sixth transistor and the start signal terminal.

[0014] In some implementations, during the first working cycle of the first mode, the first-level shift register outputs the drive signal and the cascade signal; during the second working cycle of the second mode, the first-level shift register outputs the drive signal and stops outputting the cascade signal.

[0015] In some embodiments, during a first operating cycle of the first mode, the first-stage shift register outputs a drive signal and is configured to drive the pixel circuit; during a second operating cycle of the second mode, the first-stage shift register outputs a drive signal and is configured to modulate the touch sensor signal; the first operating cycle is shorter than the second operating cycle. During the second operating cycle, the previous-stage shift register continuously outputs the cascaded signal, which serves as the start signal for the first-stage shift register.

[0016] In some implementations, during the first working cycle, the level of the cascaded signal output by the previous shift register is a first level, and during the second working cycle, the level of the cascaded signal output by the previous shift register is a second level, wherein the first level is greater than the second level.

[0017] The display panel of this application includes the driving circuit, pixel circuit and touch sensor of the above embodiments. In a first mode, the driving circuit is configured to drive the pixel circuit. In a second mode, the driving circuit is configured to provide a modulation signal of the touch sensor.

[0018] The driving method of this application includes: acquiring a start signal of a shift register; generating a cascaded signal according to the start signal, and using the cascaded signal as the start signal of the next-level shift register; outputting a driving signal according to the start signal. In a first mode, the driving signal is configured to drive a pixel circuit, and the cascaded signal is consistent with the driving signal. In a second mode, the driving signal is configured to be a modulation signal of the touch sensor, and the cascaded signal is inconsistent with the driving signal.

[0019] In the driving circuit, display panel, and driving method provided in the embodiments of the present invention, the driving circuit includes multiple cascaded shift registers. Each shift register includes a start signal terminal, a first output unit, and a second output unit. The first output unit is configured to generate a cascaded signal based on the start signal and use it as the start signal for the next-stage shift register. The second output unit is configured to output a driving signal based on the start signal. In a first mode, the driving signal is configured to drive a pixel circuit, and the cascaded signal is consistent with the driving signal. In a second mode, the driving signal is configured as a modulation signal for a touch sensor, and the cascaded signal is inconsistent with the driving signal.

[0020] The cascaded signal generated by the first output unit and the drive signal provided by the second output unit can be separate signals to adapt to the operating requirements of the display panel in intra-frame touch drive mode (Long H). When the display panel is displaying an image, the cascaded signal and the drive signal are consistent. When the touch sensor is working, the cascaded signal and the drive signal are inconsistent to prevent the modulation signal of the touch sensor from being transmitted to the next-stage shift register as a cascaded signal in advance, thereby avoiding potential drift in the next-stage shift register.

[0021] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0022] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0023] Figure 1 This is a schematic diagram of the driving circuit according to an embodiment of the present invention;

[0024] Figure 2This is a schematic diagram of the display panel and display device according to an embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a shift register in related technologies;

[0026] Figure 4 It is a timing diagram of certain shift register signals in related technologies;

[0027] Figure 5 This is a schematic diagram of a shift register according to an embodiment of this application;

[0028] Figure 6 This is a schematic diagram of a shift register according to an embodiment of this application;

[0029] Figure 7 This is a timing diagram of certain shift register signals according to an embodiment of this application;

[0030] Figure 8 This is a timing diagram of some shift register signals in an embodiment of this application.

[0031] Key component symbols: Drive circuit 1000, shift register 100, start signal terminal 10, storage capacitor 11, first output unit 20, first output terminal 21, second output unit 30, second output terminal 31, first transistor 41, second transistor 42, third transistor 43, fourth transistor 44, fifth transistor 45, sixth transistor 46, first clock line 51, second clock line 52, first signal line 61, second signal line 62, third signal line 63, fourth signal line 64, pixel circuit 2000, touch sensor 3000, display panel 10000. Detailed Implementation

[0032] Embodiments of the present invention are described in detail below, and these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0033] In related technologies, the gate-on-array (GOA) circuit includes multiple shift registers. These shift registers operate in a cascaded manner. The output signal of one shift register, in addition to serving as the driving signal for the pixel circuit, can also be transmitted to the next shift register in a cascaded manner and used as the start signal for the next shift register.

[0034] When the display panel is operating in intra-frame touch drive mode (Long H), the operating time of the touch sensor is inserted into the period of the display frame. The drive signal of a certain shift register is first used as the modulation signal of the touch sensor, and then as the drive signal of the pixel circuit. At this time, the modulation signal of the touch sensor is transmitted to the next shift register in advance as a cascaded signal, causing potential drift in the next shift register and affecting its performance.

[0035] Reference Figure 1 as well as Figure 2 This application provides a driving circuit 1000 and a display panel 10000. The driving circuit 1000 provides a cascaded signal and a driving signal separation design to adapt to the operating requirements of the display panel 10000 in intra-frame touch driving mode (Long H).

[0036] The display panel 10000 provided in this application includes a driving circuit 1000, a pixel circuit 2000, and a touch sensor 3000. In a first mode, the driving circuit 1000 is configured to drive the pixel circuit 2000, and in a second mode, the driving circuit 1000 is configured to provide a modulation signal to the touch sensor 3000.

[0037] This application also provides a driving method for a display panel 10000, which can be implemented by a driving circuit 1000. The driving method may include: acquiring a start signal of a shift register 100; generating a cascaded signal based on the start signal, and using the cascaded signal as the start signal of the next-level shift register 100; outputting a driving signal based on the start signal. In a first mode, the driving signal is configured to drive a pixel circuit 2000, and the cascaded signal is consistent with the driving signal. In a second mode, the driving signal is configured to be a modulation signal of a touch sensor 3000, and the cascaded signal is inconsistent with the driving signal.

[0038] The driving circuit 1000 provided in this application includes multiple cascaded shift registers 100. Each shift register 100 includes a start signal terminal 10, a first output unit 20, and a second output unit 30. The first output unit 20 is configured to generate a cascaded signal based on the start signal and serve as the start signal for the next-stage shift register 100. The second output unit 30 is configured to output a driving signal based on the start signal. In a first mode, the driving signal is configured to drive the pixel circuit 2000, and the cascaded signal is consistent with the driving signal. In a second mode, the driving signal is configured as a modulation signal of the touch sensor 3000, and the cascaded signal is inconsistent with the driving signal.

[0039] The cascaded signal generated by the first output unit 20 and the driving signal provided by the second output unit 30 can be separate signals to adapt to the operating requirements of the display panel 10000 in the intra-frame touch driving mode (Long H). When the display panel 10000 displays an image, the cascaded signal and the driving signal are consistent. When the touch sensor 3000 is working, the cascaded signal and the driving signal are inconsistent to prevent the modulation signal of the touch sensor 3000 from being transmitted to the next-level shift register 100 as a cascaded signal in advance, thereby preventing potential drift in the next-level shift register 100.

[0040] Specifically, the N-1, N, and N+1 level shift registers 100 of the display panel 10000 are GOAn-1, GOAn, and GOAn+1, respectively. The driving signal provided by GOAn can first be used as the modulation signal of the touch sensor 3000, and then as the driving signal of the pixel circuit 2000.

[0041] In related technologies, the circuit diagram of shift register 100 can be found in [reference needed]. Figure 3 The shift register 100 can receive a start signal through its Input terminal. After receiving the start signal, the signal connected to the Input terminal is written to node PU. When node PU is written with a high-level voltage, GOAn outputs a cascade signal through its oc terminal, and a drive signal can be output through its Gout terminal.

[0042] Reference Figure 4 The signal TP_EN can be an enable signal sent by the display panel 10000. During time T2, the signal TP_EN is at a high level. The drive signal provided by the Nth-level shift register 100 can first be used as the modulation signal for the touch sensor 3000, and then as the drive signal for the pixel circuit 2000. Time T1 can be set to the time period during which the drive signal output by the Nth-level shift register 100 modulates the touch sensor 3000, and time T3 can be set to the time period during which the drive signal output by the Nth-level shift register 100 drives the pixel circuit 2000.

[0043] In the display panel 10000, the pixel circuit 2000 can be located in the display area, and the touch sensor 3000 can be located in the non-display area. The pixel circuit 2000 and the touch sensor 3000 can use transistors of different materials; correspondingly, the driving signals provided by the driving circuit 1000 when driving the pixel circuit 2000 and modulating the touch sensor 3000 can be different. The signal output by the Gout terminal of GOAn during time T1 is different from the signal output during time T3.

[0044] Input-N can be represented as the level of the signal input to the Input terminal of GOAn, PU-N can be represented as the level of the PU node of GOAn being written to, oc-N can be represented as the level of the output of the oc terminal of GOAn, and Gout-N can be represented as the level of the output of the Gout terminal of GOAn.

[0045] After a high-level signal is applied to the Input terminal of GOAn, a high-level voltage is written to the PU node of GOAn. GOAn outputs a cascaded signal through its OC terminal, which is consistent with the drive signal output through its Gout terminal. Within time T1, both the OC and Gout terminals of GOAn output modulation signal levels. The signal output from the Gout terminal modulates the touch sensor 3000, while the modulation signal output from the OC terminal is provided to the Input terminal of GOAn+1, causing a potential drift in the PU node of GOAn+1.

[0046] In the driving circuit 1000 provided in the embodiments of this application, the circuit diagram of the shift register 100 can be referred to Figure 5 as well as Figure 6 The first output unit 20 and the second output unit 30 can be independent output units. The first output unit 20 can output a cascaded signal through the first output terminal 21, and the second output unit 30 can output a drive signal through the second output terminal 31. The input terminal can be the start signal terminal 10 of the shift register 100, the oc terminal can be the first output terminal 21, and the Gout terminal can be the second output terminal 31. The oc terminal and the Gout terminal are designed separately, and the cascaded signal output from the oc terminal and the drive signal output from the Gout terminal are separate signals.

[0047] Reference Figure 7 The signal TP_EN can be the enable signal sent by the display panel 10000. During time T2, the signal TP_EN is at a high level. The drive signal provided by the Nth-level shift register 100 can first be used as the modulation signal of the touch sensor 3000, and then as the drive signal of the pixel circuit 2000. Time T1 can be set as the time period during which the drive signal output by the Nth-level shift register 100 modulates the touch sensor 3000. Time T3 can be set as the time period during which the drive signal output by the Nth-level shift register 100 drives the pixel circuit 2000. Input-N can represent the level of the signal input to the Input terminal of GOAn, PU-N can represent the level at which the node PU of GOAn is written, oc-N can represent the level output by the oc terminal of GOAn, and Gout-N can represent the level output by the Gout terminal of GOAn.

[0048] After a high-level signal is applied to the Input terminal of GOAn, a high-level voltage is written to the PU node of GOAn. The cascaded signal output by GOAn through the OC terminal is inconsistent with the driving signal output through the Gout terminal. During time T1, the Gout terminal of GOAn outputs a modulation signal, which modulates the touch sensor 3000. The OC terminal does not output a signal to GOAn+1, thus preventing potential drift in the PU node of GOAn+1. During time T3, the signal output by the Gout terminal of GOAn is used to drive the pixel circuit 2000. The signal output by the OC terminal is consistent with that of the Gout terminal and is provided to GOAn+1 as its activation signal.

[0049] By comparison Figure 4 as well as Figure 7 It can be determined that in the driving circuit 1000 provided in the embodiments of this application, the cascade signal and the driving signal are designed to be separate. When the touch sensor 3000 is working, the modulation signal of the touch sensor 3000 can be prevented from being transmitted to the next-level shift register 100 as a cascade signal in advance, thereby avoiding potential drift in the next-level shift register 100.

[0050] In some implementations, during the first working cycle of the first mode, the first-level shift register 100 outputs a drive signal and a cascade signal, and during the second working cycle of the second mode, the first-level shift register 100 outputs a drive signal and stops outputting the cascade signal.

[0051] Specifically, within time T1, the drive circuit 1000 operates in the first mode, and time T1 can be the first working cycle. Within time T3, the drive circuit 1000 operates in the second working mode, and time T3 can be the second working cycle.

[0052] Reference Figure 4 Within time T1, the Gout terminal of GOAn outputs a modulation signal level signal. The drive signal output by the Gout terminal modulates the touch sensor 3000. The oc terminal will not output a cascade signal to GOAn+1, and will not cause the node PU of GOAn+1 to experience potential drift.

[0053] Reference Figure 3 In related technologies, the CLK terminal can receive a clock signal. The Gout terminal provides a drive signal based on the clock signal received by the CLK terminal, and the oc terminal provides a cascading signal based on the clock signal received by the CLK terminal.

[0054] Reference Figure 4During time T1, the voltage level input to the CLK terminal of GOAn is the level of the modulation signal, and the voltage levels output by the Gout and oc terminals of GOAn are also the level of the modulation signal. During time T3, the voltage level input to the CLK terminal of GOAn is higher than the level of the modulation signal, and the voltage levels output by the Gout and oc terminals are both higher than the level of the modulation signal.

[0055] Reference Figure 5 as well as Figure 6 In some embodiments, the drive circuit 1000 includes a first clock line 51 and a second clock line 52. The first clock line 51 is configured to provide a first clock signal, and the second clock line 52 is configured to provide a second clock signal. A first output unit 20 is configured to generate a cascaded signal based on the first clock signal and a start signal, and a second output unit 30 is configured to output a drive signal based on the second clock signal and the start signal. In a first mode, the first clock signal and the second clock signal are synchronized. In a second mode, the first clock signal and the second clock signal are not synchronized.

[0056] Specifically, the first clock line 51 is connected to the CLK1 terminal, the second clock line 52 is connected to the CLK2 terminal, the oc terminal provides a cascading signal based on the clock signal input to the CLK1 terminal, and the Gout terminal provides a drive signal based on the clock signal input to the CLK2 terminal.

[0057] Reference Figure 7 During time T1, the first clock signal input to CLK1 of GOAn is inconsistent with the second clock signal input to CLK2. The voltage level input to CLK2 of GOAn is the level of the modulation signal of touch sensor 3000, while the voltage level input to CLK1 is lower than the modulation signal level of touch sensor 3000. The voltage level output by Gout of GOAn is the level of the modulation signal of touch sensor 3000, and OC of GOAn may not output a cascaded signal. During time T3, the voltage levels input to CLK1 and CLK2 of GOAn are higher than the modulation signal level of touch sensor 3000, and the voltage levels output by Gout and OC are both higher than the modulation signal level of touch sensor 3000.

[0058] Reference Figure 5 as well as Figure 6In some embodiments, the first output unit 20 includes a first transistor 41 and a first output terminal 21. The first terminal of the first transistor 41 is connected to a first clock line 51, and the second terminal of the first transistor 41 is connected to the first output terminal 21. The second output unit 30 includes a second transistor 42 and a second output terminal 31. The first terminal of the second transistor 42 is connected to a second clock line 52, and the second terminal of the second transistor 42 is connected to the second output terminal 31. The first transistor 41 and the second transistor 42 are configured to be turned on according to a start signal, so that the first output terminal 21 outputs a first clock signal, and the second output terminal 31 outputs a second clock signal.

[0059] Specifically, the first transistor 41 can be transistor M1, and the second transistor 42 can be transistor M2. Transistor M1 can be connected between the CLK1 terminal and the oc terminal, and transistor M2 can be connected between the CLK2 terminal and the Gout terminal. The control terminals of transistors M1 and M2 can both be coupled to the Input terminal and turned on or off according to the start signal input to the Input terminal.

[0060] When the start signal connected to the Input terminal is at a high level, both transistors M1 and M2 are turned on. The signal output from the oc terminal is the first clock signal connected to the CLK1 terminal, and the signal output from the Gout terminal is the second clock signal connected to the CLK2 terminal.

[0061] Reference Figure 7 After the input signal level of GOAn is pulled high, the write level of the node PU of GOAn is also pulled high, making the output level of GOAn's oc terminal consistent with the first clock signal connected to CLK1 terminal, and the output level of GOAn's Gout terminal consistent with the second clock signal connected to CLK2 terminal.

[0062] In some implementations, the shift register 100 may further include a transistor M0. The first terminal and the control terminal of the transistor M0 are connected, the first terminal of the transistor M0 is connected to the Input terminal, and the second terminal of the transistor M0 is connected to the node PU.

[0063] Transistor M0 can be equivalent to a diode. For example, transistor M0 can be an NMOS transistor. When the gate and source of an NMOS transistor are connected, it can be equivalent to a diode that allows current to flow from the source to the drain. The anode of the equivalent diode is connected to the Input terminal, and the cathode of the equivalent diode is connected to the node PU to avoid the influence of the writing level of node PU.

[0064] Reference Figure 5 as well as Figure 6In some embodiments, the driving circuit 1000 includes a storage capacitor 11, which is connected in series with the start signal terminal 10 and the control electrode of the first transistor 41, or connected in series with the start signal terminal 10 and the control electrode of the second transistor 42.

[0065] Specifically, the storage capacitor 11 can be a capacitor element Cst. The capacitor element Cst can be connected in series between node PU and the control electrode of transistor M1, and the capacitor element Cst can also be connected in series between node PU and the control electrode of transistor M2. When the start signal input at the Input terminal is high, the level of the write to node PU is pulled high, and the capacitor element Cst can charge the control electrodes of transistors M1 and M2, causing transistors M1 and M2 to conduct.

[0066] After the input level is pulled low, the capacitor Cst can maintain the level of the control electrodes of node PU, transistor M1 and transistor M2, so that transistor M1 and transistor M2 can remain in the conducting state.

[0067] Reference Figure 7 After the input level of GOAn is pulled low, the capacitor Cst can maintain the level of node PU, so that the level of node PU will not be pulled low quickly, and transistors M1 and M2 can remain on for time T1.

[0068] In related technologies, refer to Figure 3 The shift register 100 may include a VGL terminal and an LVGL terminal. The modulation signal line of the touch sensor 3000 can provide the modulation signal of the touch sensor 3000 to the VGL terminal and the LVGL terminal. The Gout terminal can provide a drive signal according to the signal input to the VGL terminal, and the oc terminal can provide a cascade signal according to the signal input to the LVGL terminal.

[0069] Reference Figure 4 Within time T1, the voltage levels of the VGL and LVGL terminals of GOAn are the voltage levels of the modulation signal of the touch sensor 3000, and the voltage levels of the Gout and oc terminals of GOAn are the voltage levels of the modulation signal of the touch sensor 3000.

[0070] Reference Figure 5 as well as Figure 6In some embodiments, the driving circuit 1000 may include a first signal line 61 and a second signal line 62. The first signal line 61 is configured to provide a first modulation signal. The second signal line 62 is configured to provide a second modulation signal. A first output unit 20 is configured to output the first modulation signal or a first clock signal, and a second output unit 30 is configured to output the second modulation signal or a second clock signal. In a first mode, the first modulation signal and the second modulation signal are the same; in a second mode, the first modulation signal and the second modulation signal are not the same.

[0071] Specifically, the first signal line 61 can be connected to the LVGL terminal and provide a first modulation signal to the LVGL terminal. The second signal line 62 can be connected to the VGL terminal and provide a second modulation signal to the VGL terminal. The oc terminal can output the signal input to the CLK1 terminal or the signal input to the LVGL terminal. The Gout terminal can output the signal input to the CLK2 terminal or the signal input to the VGL terminal.

[0072] Reference Figure 7 During time T1, the clock signal input to the VGL terminal of GOAn is inconsistent with the modulation signal input to the LVGL terminal. The voltage level input to the VGL terminal of GOAn is the same as the modulation signal level of the touch sensor 3000, while the voltage level input to the LVGL terminal is lower than the modulation signal level. The voltage level output by the Gout terminal of GOAn is the same as the modulation signal level of the touch sensor 3000, and the oc terminal of GOAn may not output a cascaded signal. During time T3, the voltage levels input to the VGL and LVGL terminals of GOAn are higher than the modulation signal level of the touch sensor 3000, and the voltage levels output by the Gout and oc terminals are both higher than the modulation signal level of the touch sensor 3000.

[0073] Reference Figure 5 as well as Figure 6 In some embodiments, the first output unit 20 includes a third transistor 43, the first terminal of which is connected to the first signal line 61, and the second terminal of which is connected to the first output terminal 21. The second output unit 30 includes a fourth transistor 44, the first terminal of which is connected to the second signal line 62, and the second terminal of which is connected to the second output terminal 31. When the third transistor 43 and the fourth transistor 44 are turned on, the first output terminal 21 outputs a first modulation signal, and the second output terminal 31 outputs a second modulation signal.

[0074] Specifically, the third transistor 43 may include transistors M3A and M3B, and the fourth transistor 44 may include transistors M4A and M4B.

[0075] Transistors M3A and M3B can be connected between the LVGL terminal and the oc terminal, and transistors M4A and M4B can be connected between the VGL terminal and the Gout terminal. When either transistor M3A or M3B is turned on, the signal output from the oc terminal is the first modulation signal input to the LVGL terminal. When either transistor M4A or M4B is turned on, the signal output from the Gout terminal is the second modulation signal input to the VGL terminal.

[0076] Reference Figure 7 Within time T1, the signals input to CLK2 and VGL are both modulation signals from the touch sensor 3000. Gout can output either the signal input to CLK2 or VGL, ensuring that Gout can output the modulation signal from the touch sensor 3000. The signals input to CLK1 and LVGL are both low-level signals. oc can output either the signal input to CLK1 or LVGL, ensuring that oc does not output cascaded signals.

[0077] Reference Figure 5 as well as Figure 6 In some embodiments, the drive circuit 1000 further includes a third signal line 63 and a fourth signal line 64. The third signal line 63 is configured to provide a third modulation signal, and the fourth signal line 64 is configured to provide a fourth modulation signal. The third transistor 43 includes a first sub-transistor and a second sub-transistor. The first terminal of the first sub-transistor is connected to the first terminal of the second sub-transistor and a first clock line 51, and the second terminal of the first sub-transistor is connected to the second terminal of the second sub-transistor and a first output terminal 21. The fourth transistor 44 includes a third sub-transistor and a fourth sub-transistor. The first terminal of the third sub-transistor is connected to the first terminal of the fourth sub-transistor and a second clock line 52, and the second terminal of the third sub-transistor is connected to the second terminal of the fourth sub-transistor and a second output terminal 31. The control terminals of the first and third sub-transistors are connected to the third signal line 63, and the control terminals of the second and fourth sub-transistors are connected to the fourth signal line 64.

[0078] Specifically, the first sub-transistor can be transistor M3A, the second sub-transistor can be transistor M3B, the third sub-transistor can be transistor M4A, and the fourth sub-transistor can be transistor M4B. The third signal line 63 can be connected to the VDDO terminal and provide a third modulation signal to the VDDO terminal. The fourth signal line 64 can be connected to the VDDE terminal and provide a fourth modulation signal to the VDDE terminal.

[0079] The control terminals of transistors M3A and M4A can be connected to node PD_O, and the control terminals of transistors M3B and M4B can be connected to node PD_E. When node PD_O is written with a high level, transistors M3A and M4A are turned on, and the oc terminal can output the signal connected to the LVGL terminal, while the Gout terminal can output the signal connected to the VGL terminal. When node PD_E is written with a high level, transistors M3B and M4B are turned on, and the oc terminal can output the signal connected to the LVGL terminal, while the Gout terminal can output the signal connected to the VGL terminal.

[0080] When the level of the third modulation signal is high, the level of the fourth modulation signal can be low. When the level of the fourth modulation signal is high, the level of the third modulation signal can be low, ensuring that one of the nodes PD_O and PD_E is written with a high level.

[0081] In some embodiments, the drive circuit 1000 further includes a fifth transistor 45 and a sixth transistor 46. The first terminal of the fifth transistor 45 is connected to the third signal line 63, the first terminal of the sixth transistor 46 is connected to the fourth signal line 64, the second terminal of the fifth transistor 45 is connected to the second terminal of the sixth transistor 46 and the second signal line 62, and the control terminal of the fifth transistor 45 is connected to the control terminal of the sixth transistor 46 and the start signal terminal 10.

[0082] Specifically, the fifth transistor 45 may include transistor M5B, and the sixth transistor 46 may include transistor M6B. Transistor M5B may be connected between node PD_O and the LVGL terminal, and transistor M6B may be connected between node PD_E and the VGL terminal. The control terminals of transistors M5B and M6B may be connected to node PU.

[0083] When node PU is written with a high level, transistors M1, M2, M5B, and M6B will all conduct. The conduction of transistors M5B and M6B shorts the PD_O and LVGL terminals, and the PD_E and VGL terminals, causing transistors M3A, M3B, M4A, and M4B to de-conduct. The oc terminal can output the signal input to CLK1, and the Gout terminal can output the signal input to CLK2.

[0084] When node PU is written with a low level, transistors M1, M2, M5B, and M6B can all be de-conducted. While transistors M5B and M6B are de-conducted, since one of nodes PD_O and PD_E is written with a high level, one of transistors M3A and M3B, and one of transistors M4A and M4B, are on. The oc terminal can output the signal connected to the LVGL terminal, and the Gout terminal can output the signal connected to the VGL terminal.

[0085] In some embodiments, the shift register 100 may further include transistors M5A and M6A. The first terminal and control terminal of transistor M5A are connected, the first terminal of transistor M5A is connected to the VDDO terminal, and the second terminal of transistor M5A is connected to node PD_O. The first terminal and control terminal of transistor M6A are connected, the first terminal of transistor M6A is connected to the VDDE terminal, and the second terminal of transistor M5A is connected to node PD_E.

[0086] Transistors M5A and M6A can be considered equivalent to a diode. For example, transistors M5A and M6A can be NMOS transistors. When the gate and source of an NMOS transistor are connected, it can be considered equivalent to a diode that allows current to flow from the source to the drain. The anode of the equivalent diode of transistor M5A is connected to the VDDO terminal, and the cathode is connected to node PD_O to avoid the influence of the writing level at node PD_O. The anode of the equivalent diode of transistor M6A is connected to the VDDE terminal, and the cathode is connected to node PD_E to avoid the influence of the writing level at node PD_E.

[0087] In some embodiments, the shift register 100 further includes transistors M8 and M9, an RST terminal, and a T-RST terminal. Transistor M8 is connected in series between node PU and LVGL, transistor M9 is connected in series between node PU and LVGL, the RST terminal is connected to the control electrode of transistor M8, and the T-RST terminal is connected to the control electrode of transistor M9. Both the RST terminal and the T-RST terminal can be set as reset terminals for the write level of node PU.

[0088] With transistor M8 or M9 turned on, the low level input to LVGL can be written to node PU to reset shift register 100.

[0089] Reference Figure 4 In related technologies, within time T1, the drive circuit 1000 operates in the first mode, and time T1 can be the first working cycle. Within time T3, the drive circuit 1000 operates in the second working mode, and time T3 can be the second working cycle.

[0090] The Input terminal of GOAn is connected to the cascaded signal output from the OC terminal of GOAn-1, and the timing of the cascaded signal output from the OC terminal of GOAn-1 coincides with time T3. Since time T3 is less than time T1, the start signal connected to the Input terminal of GOAn cannot maintain a high level within time T1, thus causing the level written to node PU to be pulled low. Within time T3, the transistor connecting the CLK terminal and the Gout terminal is not fully turned on, affecting the waveform output from the Gout terminal of GOAn.

[0091] In some implementations, during the first operating cycle of the first mode, the first-level shift register 100 outputs a drive signal and is configured to drive the pixel circuit 2000; during the second operating cycle of the second mode, the first-level shift register 100 outputs a drive signal and is configured to modulate the touch sensor 3000. The first operating cycle is shorter than the second operating cycle. During the second operating cycle, the previous-level shift register 100 continuously outputs a cascaded signal, which serves as the start signal for the first-level shift register 100.

[0092] Specifically, refer to Figure 8 During time T1, the cascade signal output from the OC terminal of GOAn-1 can continuously output the cascade signal, allowing the Input terminal of GOAn to continuously receive the start signal, ensuring that the write level of the PU node of GOAn remains high. During time T3, the transistor M2 connecting the CLK2 and Gout terminals is turned on, ensuring that the waveform output from the Gout terminal of GOAn is consistent with the waveform of the signal input from the CLK2 terminal, thus improving the waveform output from the Gout terminal of GOAn and consequently improving the display defect of display panel 10000.

[0093] In some implementations, during the first working cycle, the level of the cascaded signal output by the previous shift register 100 is a first level, and during the second working cycle, the level of the cascaded signal output by the previous shift register 100 is a second level, wherein the first level is greater than the second level.

[0094] Specifically, refer to Figure 8 During time T1, the cascade signal output from the OC terminal of GOAn-1 can continuously output the cascade signal, allowing the GOAn's Input terminal to continuously receive the start signal, ensuring that the writing level of the GOAn's PU node remains at the first level. During time T3, the writing level of the PU node is further pulled high, and the writing level of the PU node is the second level, which is greater than the first level.

[0095] In some embodiments, the display panel 10000 may also include a modulation chip, which can provide the first clock signal and the second clock signal described in the above embodiments to set the operating mode of the driving circuit 1000, so that the display panel 10000 can be applied to different working scenarios.

[0096] In the description of this specification, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0097] Furthermore, the term "connection" should be interpreted broadly. For example, it can include fixed connections, detachable connections, or integral connections; it can include direct connections or indirect connections through an intermediate medium; and it can also include internal communication between two elements. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0098] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0099] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0100] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A drive circuit characterized by comprising: The driving circuit comprises a plurality of cascaded shift registers, and the shift registers comprise: an enable signal terminal configured to access an enable signal; a first output unit configured to generate a cascade signal according to the enable signal and serve as the enable signal of a next stage shift register; a second output unit configured to output a driving signal according to the enable signal, wherein in a first mode, the driving signal is configured to drive a pixel circuit, the cascade signal is consistent with the driving signal, and in a second mode, the driving signal is configured to be a modulation signal of a touch sensor, and the cascade signal is inconsistent with the driving signal.

2. The drive circuit according to claim 1, characterized by The driving circuit further comprises: a first clock line configured to provide a first clock signal; a second clock line configured to provide a second clock signal; the first output unit is configured to generate the cascade signal according to the first clock signal and the enable signal, and the second output unit is configured to output the driving signal according to the second clock signal and the enable signal, wherein in the first mode, the first clock signal is consistent with the second clock signal, and in the second mode, the first clock signal is inconsistent with the second clock signal.

3. The drive circuit according to claim 2, characterized in that, The first output unit comprises a first transistor and a first output terminal, a first electrode of the first transistor is connected with the first clock line, a second electrode of the first transistor is connected with the first output terminal, the second output unit comprises a second transistor and a second output terminal, a first electrode of the second transistor is connected with the second clock line, and a second electrode of the second transistor is connected with the second output terminal; the first transistor and the second transistor are configured to be turned on according to the enable signal, so that the first output terminal outputs the first clock signal and the second output terminal outputs the second clock signal.

4. The drive circuit according to claim 3, characterized in that, The driving circuit comprises a storage capacitor connected in series between the enable signal terminal and a control electrode of the first transistor or connected in series between the enable signal terminal and a control electrode of the second transistor.

5. The drive circuit according to claim 3, characterized by The driving circuit further comprises: a first signal line configured to provide a first modulation signal; a second signal line configured to provide a second modulation signal; the first output unit is configured to output the first modulation signal or the first clock signal, and the second output unit is configured to output the second modulation signal or the second clock signal, wherein in the first mode, the first modulation signal is consistent with the second modulation signal, and in the second mode, the first modulation signal is inconsistent with the second modulation signal.

6. The drive circuit according to claim 5, characterized in that, The first output unit comprises a third transistor, a first electrode of the third transistor is connected with the first signal line, and a second electrode of the third transistor is connected with the first output terminal, the second output unit comprises a fourth transistor, a first electrode of the fourth transistor is connected with the second signal line, and a second electrode of the fourth transistor is connected with the second output terminal; The first output terminal outputs a first modulation signal when the third transistor is turned on, and the second output terminal outputs a second modulation signal when the fourth transistor is turned on.

7. The drive circuit according to claim 6, characterized in that, The driving circuit further comprises: a third signal line configured to provide a third modulation signal; a fourth signal line configured to provide a fourth modulation signal; The third transistor comprises a first sub-transistor and a second sub-transistor, a first electrode of the first sub-transistor is connected with a first electrode of the second sub-transistor and the first clock line, a second electrode of the first sub-transistor is connected with a second electrode of the second sub-transistor and the first output terminal, the fourth transistor comprises a third sub-transistor and a fourth sub-transistor, a first electrode of the third sub-transistor is connected with a first electrode of the fourth sub-transistor and the second clock line, a second electrode of the third sub-transistor is connected with a second electrode of the fourth sub-transistor and the second output terminal, a control electrode of the first sub-transistor is connected with a control electrode of the third sub-transistor and the third signal line, and a control electrode of the second sub-transistor is connected with a control electrode of the fourth sub-transistor and the fourth signal line.

8. The drive circuit according to claim 7, characterized in that, The driving circuit further comprises a fifth transistor and a sixth transistor, a first electrode of the fifth transistor is connected with the third signal line, a first electrode of the sixth transistor is connected with the fourth signal line, a second electrode of the fifth transistor is connected with a second electrode of the sixth transistor and the second signal line, and a control electrode of the fifth transistor is connected with a control electrode of the sixth transistor and the start signal terminal.

9. The drive circuit according to any one of claims 1 to 8, characterized by In a first working period of the first mode, a stage of the shift register outputs the driving signal and the cascade signal, and in a second working period of the second mode, the stage of the shift register outputs the driving signal and stops outputting the cascade signal.

10. The drive circuit according to any one of claims 1 to 8, characterized by In a first working period of the first mode, a stage of the shift register outputs a driving signal and is configured to drive a pixel circuit, and in a second working period of the second mode, the stage of the shift register outputs a driving signal and is configured to output a modulation signal of a touch sensor, the first working period being less than the second working period. In the second working period, a previous stage of the shift register continuously outputs the cascade signal and serves as a start signal of the stage of the shift register.

11. The drive circuit according to claim 10, characterized in that, In the first working period, the cascade signal output by the previous stage of the shift register has a first level, and in the second working period, the cascade signal output by the previous stage of the shift register has a second level, the first level being greater than the second level.

12. A display panel, characterized by, The display panel comprises the driving circuit, the pixel circuit and the touch sensor of any one of claims 1-11, in a first mode, the driving circuit is configured to drive the pixel circuit, and in a second mode, the driving circuit is configured to provide a modulation signal of the touch sensor.

13. A driving method of a display panel, characterized by, The method comprises: obtaining a start signal of a shift register; generating a cascade signal according to the start signal, and taking the cascade signal as the start signal of the next stage of the shift register; outputting a driving signal according to the start signal, in a first mode, the driving signal is configured to drive a pixel circuit, the cascade signal is consistent with the driving signal, in a second mode, the driving signal is configured to be a modulation signal of a touch sensor, the cascade signal is inconsistent with the driving signal.

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