Display panel and display device

Abstract

The invention discloses a display panel and a display device, the display panel comprises a plurality of data multiplexing modules, each data multiplexing module is electrically connected with data lines included in at least two adjacent data groups along a first direction, and at least one data line is connected with a plurality of sub-pixels of two adjacent second pixel groups along the first direction. The plurality of sub-pixels located in the same first pixel group are electrically connected with the scanning lines included in one scanning group. Each data multiplexing module comprises at least two data multiplexing units, a plurality of data lines included in each data group are electrically connected with different data multiplexing units, and each data multiplexing unit is configured to transmit data signals transmitted by the same data bus to the data lines located in different data groups in a time-sharing manner; the plurality of data lines located in the same data group receive the corresponding data signals in the same time period, so that the same data bus is used for transmitting the corresponding data signals for the plurality of data lines, the number of source channels of the data signals is reduced, and the cost is reduced.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] The 1 Gate 1 Data (1G1D) architecture requires a data line for each column of sub-pixels, thus necessitating multiple source drivers for the display panel to transmit corresponding data signals to multiple data lines, which is not conducive to cost reduction. Summary of the Invention

[0003] This application provides a display panel and display device for reducing costs.

[0004] To achieve the above objectives, this application provides a display panel including multiple pixel units, multiple scan groups, multiple data groups, and multiple data multiplexing modules. The multiple pixel units are arranged in an array, each pixel unit including at least two sub-pixels; the multiple pixel units are arranged along a first direction to form a first pixel group, and the multiple pixel units are arranged along a second direction to form a second pixel group, the second direction intersecting the first direction. The multiple scan groups are arranged along the second direction, each scan group including at least two scan lines arranged along the second direction; multiple sub-pixels of the same first pixel group are electrically connected to the scan lines included in a scan group, each first pixel group being located between two scan lines. The multiple data groups are arranged along the first direction, each data group including at least two data lines arranged along the first direction, at least one data line being connected to multiple sub-pixels of two adjacent second pixel groups along the first direction, each second pixel group being located between two data lines. Each data multiplexing module is electrically connected to at least two adjacent data groups along a first direction. Each data multiplexing module includes at least two data multiplexing units. Multiple data lines included in each data group are electrically connected to different data multiplexing units. Each data multiplexing unit is configured to transmit data signals transmitted on the same data bus in a time-division manner to data lines located in different data groups. Multiple data lines located in the same data group receive corresponding data signals in the same time period.

[0005] This application also provides a display device including any of the above-described display panels.

[0006] In the above technical solution, by including multiple data multiplexing modules in the display panel, and electrically connecting each data multiplexing module to the data lines of at least two adjacent data groups along the first direction, at least one data line to multiple sub-pixels of two adjacent second pixel groups along the first direction, and multiple sub-pixels in the same first pixel group to the scan lines of a scan group, each data multiplexing module includes at least two data multiplexing units. Multiple data lines in each data group are electrically connected to different data multiplexing units. Each data multiplexing unit is configured to transmit data signals transmitted on the same data bus in a time-division manner to data lines in different data groups. Multiple data lines in the same data group receive corresponding data signals at the same time period. By utilizing the same data bus to transmit corresponding data signals to multiple data lines, the number of data signal source channels can be reduced, thereby reducing the number of source drivers required for the display panel and thus reducing costs. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0009] Figures 1A-1B This is a schematic diagram of the structure of the display panel provided in an embodiment of this application; Figures 2A-2B This is a schematic diagram of the data voltage polarity distribution corresponding to the sub-pixel provided in the embodiments of this application; Figure 3 This is a timing diagram of the clock signal and scan signal provided in an embodiment of this application; Figures 4A-4B This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0010] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0011] It should be noted that the electrical connection referred to in this application can include both direct and indirect connections. Indirect connections can include connections between connected modules, devices, and nodes achieved through electrical components, wired or wireless media, etc. An electrical connection can refer to a physically existing connection or a connection established through signals.

[0012] Furthermore, descriptions involving "first," "second," etc., in the embodiments of this application are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified. Additionally, the embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict. Each technical feature in this application can be applied to achieve different combinations, and is not limited to the technical solutions formed by the combinations listed in the embodiments. Technical solutions between various embodiments can be combined, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. The terms "optionally" and "in some embodiments" used in this application indicate that the technical content they refer to can be selectively configured.

[0013] Furthermore, the descriptions provided in the Background section should not be presumed to be prior art simply because they are mentioned in or associated with the description in the Background section. The Background section may include information describing one or more aspects of the subject matter, and the description in this section does not limit the invention.

[0014] Figures 1A-1B This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. This application provides a display panel including multiple pixel units SU, multiple scan groups LU, multiple data groups DU, and multiple data multiplexing modules DM.

[0015] Multiple pixel units SU are arranged in an array, each pixel unit SU including at least two sub-pixels Spx. The multiple pixel units SU are arranged along a first direction Dr1 to form a first pixel group SG1, and the multiple pixel units SU are arranged along a second direction Dr2 to form a second pixel group SG2, the second direction Dr2 intersecting the first direction Dr1.

[0016] Multiple scan groups LU are arranged along a second direction Dr2, and each scan group LU includes at least two scan lines arranged along the second direction Dr2. Multiple sub-pixels Spx of the same first pixel group SG1 are electrically connected to the scan lines included in a scan group LU, and each first pixel group SG1 is located between two scan lines.

[0017] Multiple data groups DU are arranged along a first direction Dr1. Each data group DU includes at least two data lines arranged along the first direction Dr1. At least one data line is connected to multiple sub-pixels Spx of two adjacent second pixel groups SG2 along the first direction Dr1. Each second pixel group SG2 is located between the two data lines.

[0018] Each data multiplexing module DM is electrically connected to at least two data groups DU adjacent along the first direction Dr1. Each data multiplexing module DM includes at least two data multiplexing units. Multiple data lines in each data group DU are electrically connected to different data multiplexing units. Each data multiplexing unit is configured to transmit data signals transmitted on the same data bus to data lines located in different data groups DU in a time-division manner. Multiple data lines in the same data group DU receive corresponding data signals at the same time. Utilizing the same data bus to transmit corresponding data signals to multiple data lines reduces the number of data signal source channels, thereby reducing the number of source drivers required for the display panel and thus lowering costs. Furthermore, because multiple data lines in the same data group DU receive corresponding data signals at the same time, multiple sub-pixels Spx connected to multiple data lines in the same data group DU and arranged along the first direction Dr1 can receive corresponding data signals at the same time, thereby shortening the scanning time for each first pixel group SG1.

[0019] It should be noted that the first direction Dr1 can be either the row direction or the column direction, and the second direction Dr2 can be either the row direction or the column direction. Figures 1A-1B The illustration uses only the first direction Dr1 as the row direction and the second direction Dr2 as the column direction as an example, but this should not be construed as a limitation of this application.

[0020] In some embodiments, each pixel unit SU includes two sub-pixels Spx, which include a first sub-pixel SpxA and a second sub-pixel SpxB, such as... Figure 1AAs shown. The emission color of the first sub-pixel SpxA is different from the emission color of the second sub-pixel SpxB. Two adjacent pixel units SU along the first direction Dr1 include a first pixel unit and a second pixel unit. The second sub-pixel SpxB of the first pixel unit is adjacent to the first sub-pixel SpxA of the second pixel unit along the first direction Dr1. The emission color of the first sub-pixel SpxA of the second pixel unit is different from the emission colors of the first sub-pixel SpxA and the second sub-pixel SpxB in the first pixel unit. The emission color of the second sub-pixel SpxB of the second pixel unit is the same as the emission color of the first sub-pixel SpxA in the first pixel unit. Specifically, the emission colors of the first sub-pixel SpxA and the second sub-pixel SpxB in the first pixel unit, and the emission color of the first sub-pixel SpxA in the second pixel unit, are red, green, and blue, respectively.

[0021] In other embodiments, each pixel unit SU includes three sub-pixels Spx, which include a first sub-pixel SpxA, a second sub-pixel SpxB, and a third sub-pixel SpxC, such as... Figure 1B As shown. The emission color of the first sub-pixel SpxA is different from the emission colors of the second sub-pixel SpxB and the third sub-pixel SpxC. The emission color of the second sub-pixel SpxB is different from the emission color of the third sub-pixel SpxC. Pixel unit SU includes three sub-pixels Spx, whose emission colors can be red, green, and blue, respectively.

[0022] Optionally, each data multiplexing unit includes n switching devices, each of which is connected to a data bus and a data line. The n switching devices are configured to control the time-division multiplexing of a current path between the data bus and the n data lines according to n clock signals. Wherein, n≥2.

[0023] In some embodiments, each data multiplexing unit includes two switching devices electrically connected between a data bus and two data lines. Each switching device is connected to a data line and is configured to control a time-division multiplexing current path between the data bus and the two data lines according to a clock signal.

[0024] like Figures 1A-1B In the example of n=2, each data multiplexing module DM includes two data multiplexing units, namely the first data multiplexing unit DM1 and the second data multiplexing unit DM2.

[0025] The first data multiplexing unit DM1 includes a first switching device Ts1 and a second switching device Ts2. The first switching device Ts1 is configured to control the signal transmission between the first data bus Ds1 and the first data line DLA according to the first clock signal CK1 transmitted by the first clock line CL1. The second switching device Ts2 is configured to control the signal transmission between the first data bus Ds1 and the second data line DLB according to the second clock signal CK2 transmitted by the second clock line CL2.

[0026] The second data multiplexing unit DM2 includes a third switching device Ts3 and a fourth switching device Ts4. The third switching device Ts3 is configured to control the signal transmission between the second data bus Ds2 and the third data line DLC according to the third clock signal CK3 transmitted by the third clock line CL3. The fourth switching device Ts4 is configured to control the signal transmission between the second data bus Ds2 and the fourth data line DLD according to the fourth clock signal CK4 transmitted by the fourth clock line CL4.

[0027] In this configuration, the first data bus Ds1 and the second data bus Ds2 are respectively configured to transmit corresponding data signals. The first data line DLA and the third data line DLC are located in the same data group DU, and the second data line DLB and the fourth data line DLD are located in the same data group DU. The first clock signal CK1 and the third clock signal CK3 have the same frequency and the same phase, and the second clock signal CK2 and the fourth clock signal CK4 have the same frequency and the same phase. There is a phase difference between the first clock signal CK1 and the second clock signal CK2, so that the data signals transmitted on the same data bus are transmitted to the data lines located in different data groups DU in a time-division manner, and multiple data lines located in the same data group DU receive the corresponding data signals at the same time period.

[0028] Optionally, multiple sub-pixels Spx located in the same pixel unit SU are electrically connected to different scan lines so that multiple sub-pixels Spx in the same pixel unit SU receive corresponding data signals at different time periods, thereby reducing the risk of mischarging of sub-pixels Spx.

[0029] In some embodiments, each pixel unit SU includes two sub-pixels Spx, which are a first sub-pixel SpxA and a second sub-pixel SpxB. Each scan group LU includes two scan lines, which are a first scan line SLA and a second scan line SLB, as shown below. Figure 1AAs shown. In the same pixel unit SU, the first sub-pixel SpxA and the second sub-pixel SpxB are electrically connected to the same data line. The first sub-pixel SpxA is connected to one of the first scan line SLA and the second scan line SLB, and the second sub-pixel SpxB is connected to the other of the first scan line SLA and the second scan line SLB. This allows the two sub-pixels Spx in the same pixel unit SU to receive the signal transmitted by the same data line at different time periods according to the two scan signals, thereby reducing the risk of mischarging of the sub-pixel Spx.

[0030] like Figure 1A As shown, in the first pixel group, the first sub-pixel SpxA in the 3x+1 pixel unit, the second sub-pixel SpxB in the 3x+2 pixel unit, and the second sub-pixel SpxB in the 3x+3 pixel unit are electrically connected to the first scan line (i.e., the first scan line SLA in the first scan group), and the second sub-pixel SpxB in the 3x+1 pixel unit, the first sub-pixel SpxA in the 3x+2 pixel unit, and the first sub-pixel SpxA in the 3x+3 pixel unit are electrically connected to the second scan line (i.e., the second scan line SLB in the first scan group). In the second first pixel group, the first sub-pixel SpxA in the 3x+1 pixel unit, the second sub-pixel SpxB in the 3x+2 pixel unit, and the second sub-pixel SpxB in the 3x+3 pixel unit are electrically connected to the third scan line (corresponding to the first scan line SLA in the second scan group). The second sub-pixel SpxB in the 3x+1 pixel unit, the first sub-pixel SpxA in the 3x+2 pixel unit, and the first sub-pixel SpxA in the 3x+3 pixel unit are electrically connected to the fourth scan line (corresponding to the second scan line SLB in the second scan group). This process is repeated for the remaining first pixel groups SG1, where x ≥ 0. This allows two sub-pixels Spx in the same pixel unit SU to receive signals transmitted by the same data line at different times based on the two scan signals, reducing the risk of mischarging of sub-pixels Spx.

[0031] In some embodiments, each pixel unit SU includes three sub-pixels Spx, namely a first sub-pixel SpxA, a second sub-pixel SpxB, and a third sub-pixel SpxC. Each scan group LU includes three scan lines, namely a first scan line SLA, a second scan line SLB, and a third scan line SLC. In the same pixel unit SU, the first sub-pixel SpxA and the third sub-pixel SpxC are electrically connected to the same data line, while the first sub-pixel SpxA and the second sub-pixel SpxB are connected to different data lines. The first sub-pixel SpxA is connected to the first scan line SLA, the second sub-pixel SpxB is connected to the second scan line SLB, and the third sub-pixel SpxC is connected to the third scan line SLC. This allows the three sub-pixels Spx of the same pixel unit SU to receive signals transmitted by the two data lines at different times according to the three scan signals, thereby reducing the risk of mischarging of the sub-pixels Spx.

[0032] like Figure 1B As shown, in the first pixel group, the first sub-pixel SpxA in each pixel unit SU is electrically connected to the first scan line (corresponding to the first scan line SLA in the first scan group), the second sub-pixel SpxB in each pixel unit SU is electrically connected to the second scan line (corresponding to the second scan line SLB in the first scan group), and the third sub-pixel SpxC in each pixel unit SU is electrically connected to the third scan line (corresponding to the third scan line SLC in the first scan group). In the second pixel group, the first sub-pixel SpxA in each pixel unit SU is electrically connected to the fourth scan line (corresponding to the first scan line SLA in the second scan group), the second sub-pixel SpxB in each pixel unit SU is electrically connected to the fifth scan line (corresponding to the second scan line SLB in the second scan group), and the third sub-pixel SpxC in each pixel unit SU is electrically connected to the sixth scan line (corresponding to the third scan line SLC in the second scan group). This process continues, resulting in the connection settings between the multiple sub-pixels Spx in the remaining first pixel groups SG1 and their corresponding scan lines. In this way, the three sub-pixels Spx of the same pixel unit SU can receive the signals transmitted by the two data lines at different times according to the three scan signals, thereby reducing the risk of mischarging of the sub-pixel Spx.

[0033] In some embodiments, the sub-pixel Spx and the corresponding scan line are electrically connected via a switching transistor. Specifically, the control terminal of the switching transistor is electrically connected to the corresponding scan line, the first source-drain terminal of the switching transistor is connected to the corresponding data line, and the second source-drain terminal of the switching transistor is electrically connected to the corresponding sub-pixel Spx. The control terminal can correspond to the gate of the transistor, the first source-drain terminal can correspond to one of the source and drain of the transistor, and the second source-drain terminal can correspond to the other of the source and drain of the transistor.

[0034] Optionally, multiple sub-pixels Spx located in the same pixel unit SU are electrically connected to the same data line, two adjacent pixel units SU along the first direction Dr1 in the same first pixel group SG1 are electrically connected to different data lines, and multiple pixel units SU in the same second pixel group SG2 are alternately electrically connected to two data lines, so that multiple sub-pixels Spx in the same pixel unit SU share the same data line to receive the corresponding data signal, and multiple pixel units SU in the same second pixel group SG2 share two data lines to receive the corresponding data signal, thereby reducing the number of data lines, thereby reducing the number of data signal source channels and reducing costs.

[0035] like Figure 1A As shown, in the first second pixel group, the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+1th pixel unit are electrically connected to the first data line DLA, and the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+2th pixel unit are electrically connected to the third data line DLC. In the second second pixel group, the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+1th pixel unit are electrically connected to the third data line DLC, and the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+2th pixel unit are electrically connected to the second data line DLB. In the third second pixel group, the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+1th pixel unit are electrically connected to the second data line DLB, and the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+2nd pixel unit are electrically connected to the fourth data line DLD. In the fourth second pixel group, the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+1th pixel unit are electrically connected to the fourth data line DLD, and the first sub-pixel SpxA and the second sub-pixel SpxB in the 2y+2th pixel unit are electrically connected to the first data line DLA corresponding to another data multiplexing module DM. Then, referring to the design of the data lines used by the first to fourth second pixel groups SG2 and their corresponding data multiplexing modules DM, the connection settings between the multiple sub-pixels Spx of the remaining second pixel groups SG2 and their corresponding data lines can be obtained. Where y ≥ 0.

[0036] Optionally, multiple sub-pixels Spx located in the same pixel unit SU are electrically connected to two data lines, and adjacent pixel units SU along the first direction Dr1 are electrically connected to the same data line, so that multiple sub-pixels Spx of the same pixel unit SU share two data lines to receive the corresponding data signal, and two adjacent pixel units SU along the first direction Dr1 can share the signal transmitted by one data line, thereby reducing the number of data lines, and thus reducing the number of data signal source channels and reducing costs.

[0037] In some embodiments, each pixel unit SU includes a first sub-pixel SpxA, a second sub-pixel SpxB, and a third sub-pixel SpxC. Within the same pixel unit SU, the first sub-pixel SpxA and the third sub-pixel SpxC are electrically connected to the same data line, while the first sub-pixel SpxA and the second sub-pixel SpxB are electrically connected to different data lines. Specifically, the first sub-pixel SpxA of multiple pixel units SU arranged along the second direction Dr2 is alternately electrically connected to two data lines, and the second sub-pixel SpxB of multiple pixel units SU arranged along the second direction Dr2 is alternately electrically connected to two data lines. In two adjacent pixel units SU along the first direction Dr1, the first sub-pixel SpxA of one pixel unit SU and the second sub-pixel SpxB of the other pixel unit SU are connected to the same data line, so that multiple sub-pixels Spx of the same pixel unit SU share two data lines to receive corresponding data signals. The signals transmitted by adjacent pixel units SU along the first direction Dr1 share the same data line, thereby reducing the number of data lines, and consequently reducing the number of data signal source channels, thus reducing costs.

[0038] like Figure 1BAs shown, in the first second pixel group, the first sub-pixel SpxA and the third sub-pixel SpxC in the 2y+1th pixel unit, and the second sub-pixel SpxB in the 2y+2th pixel unit are electrically connected to the first data line DLA, and the second sub-pixel SpxB, the first sub-pixel SpxA, and the third sub-pixel SpxC in the 2y+1th pixel unit are electrically connected to the third data line DLC. In the second second pixel group, the first sub-pixel SpxA and the third sub-pixel SpxC in the 2y+1st pixel unit, and the second sub-pixel SpxB in the 2y+2nd pixel unit are electrically connected to the third data line DLC, and the second sub-pixel SpxB, the first sub-pixel SpxA, and the third sub-pixel SpxC in the 2y+1st pixel unit are electrically connected to the second data line DLB. In the third second pixel group, the first sub-pixel SpxA and the third sub-pixel SpxC in the 2y+1 pixel unit, and the second sub-pixel SpxB in the 2y+2 pixel unit are electrically connected to the second data line DLB. The second sub-pixel SpxB in the 2y+1 pixel unit, and the first sub-pixel SpxA and the third sub-pixel SpxC in the 2y+2 pixel unit are electrically connected to the fourth data line DLD. In the fourth second pixel group, the first sub-pixel SpxA and the third sub-pixel SpxC in the 2y+1 pixel unit, and the second sub-pixel SpxB in the 2y+2 pixel unit are electrically connected to the fourth data line DLD. The second sub-pixel SpxB in the 2y+1 pixel unit, and the first sub-pixel SpxA and the third sub-pixel SpxC in the 2y+2 pixel unit are electrically connected to the first data line DLA of another data multiplexing module DM. Then, referring to the design of the data lines used by the first to fourth second pixel groups SG2 and the corresponding data multiplexing module DM, the connection settings between the multiple sub-pixels Spx of the remaining second pixel groups SG2 and their corresponding data lines can be obtained. Where y ≥ 0.

[0039] In some embodiments, within the same frame, the data signal transmitted by the first data bus Ds1 corresponds to a data voltage with a first polarity, and the data signal transmitted by the second data bus Ds2 corresponds to a data voltage with a second polarity. The first polarity is either positive or negative, and the second polarity is either positive or negative, to ensure better display performance and reduce the likelihood of flickering and crosstalk issues on the display panel.

[0040] It should be noted that a positive data voltage refers to a data voltage greater than the common voltage applied to the display panel, while a negative data voltage refers to a data voltage less than the common voltage. That is, each data line transmits a data signal, and the data signal can have voltage variations. The voltage of the data signal received by each sub-pixel Sp in each frame is the data voltage. The data voltage received by each sub-pixel Sp in two adjacent frames can be different. For example, in some embodiments, the data voltage received by a sub-pixel Sp in one of two adjacent frames is less than the common voltage, while the data voltage received by the same sub-pixel Sp in the other of two adjacent frames is greater than the common voltage.

[0041] In some embodiments, the data lines electrically connected to the first data multiplexing unit DM1 and the data lines electrically connected to the second data multiplexing unit DM2 are alternately arranged along the first direction Dr1 so that the polarity of the data voltage corresponding to the sub-pixel Spx is cross-distributed within the same frame, which is beneficial to improving the effect of reducing flicker and crosstalk of the display panel.

[0042] In some embodiments, within the same frame, multiple sub-pixels Spx in the same pixel unit SU receive data voltages with the same polarity; two adjacent pixel units SU along the first direction Dr1 receive data voltages with different polarities; and two adjacent pixel units SU along the second direction Dr2 receive data voltages with different polarities. In two adjacent frames, each sub-pixel Spx receives data voltages with different polarities, so that the display panel has a polarity-reversed design with the sub-pixels Spx included in the pixel unit SU as units.

[0043] In some embodiments, each pixel unit SU includes a first sub-pixel SpxA, a second sub-pixel SpxB, and a third sub-pixel SpxC, with the second sub-pixel SpxB located between the first sub-pixel SpxA and the third sub-pixel SpxC. Within the same frame, the polarity of the received data voltages corresponding to the first sub-pixel SpxA and the third sub-pixel SpxC in the same pixel unit SU is the same, while the polarity of the data voltage corresponding to the second sub-pixel SpxB is different from the polarity of the data voltage corresponding to the first sub-pixel SpxA. Specifically, within the same frame, the polarity of the data voltages received by the first sub-pixel SpxA in two adjacent pixel units SU along the first direction Dr1 is different, and the polarity of the data voltages received by the first sub-pixel SpxA in two adjacent pixel units SU along the second direction Dr2 is different. In two adjacent frames, the polarity of the received data voltages corresponding to each sub-pixel Spx is different, enabling the display panel to implement a dot-inversion design to improve the effect of reducing display panel flicker and crosstalk problems.

[0044] In some embodiments, to enable each sub-pixel Spx to receive the corresponding data signal, a first clock signal has an effective level and a second clock signal has an effective level during the period when the scan signal transmitted on any scan line has an effective level. The periods when the first clock signal has an effective level and the periods when the second clock signal has an effective level do not overlap.

[0045] Figures 2A-2B This is a schematic diagram of the data voltage polarity distribution corresponding to the sub-pixel provided in an embodiment of this application. Figure 3 This is a timing diagram of the clock signal and scan signal provided in an embodiment of this application. For ease of understanding this application, [the diagram is shown below]. Figures 2A-2B and Figure 3 The working principle of a single data multiplexing module (DM) will be explained using an example. Figures 2A-2B In this context, "+" indicates that the data voltage is positive, and "-" indicates that the data voltage is negative.

[0046] Please see Figure 2A and Figure 3 In the first time period tA of the p-th frame, the first scan signal Scan1, the first clock signal CK1, and the third clock signal CK3 transmitted by the first scan line SL1 are valid pulses, and the first switching device Ts1 and the third switching device Ts3 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the first sub-pixel SpxA of the first pixel unit electrically connected to the first data line DLA receives the corresponding data signal, and the second sub-pixel SpxB of the second pixel unit electrically connected to the third data line DLC receives the corresponding data signal. Therefore, the data voltage corresponding to the first sub-pixel SpxA of the first pixel unit is negative, and the data voltage corresponding to the second sub-pixel SpxB of the second pixel unit is positive.

[0047] During the second time period tB of frame p, the first scan signal Scan1, the second clock signal CK2, and the fourth clock signal CK4 transmitted by the first scan line SL1 are valid pulses, and the second switching device Ts2 and the fourth switching device Ts4 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the second sub-pixel SpxB of the third pixel unit electrically connected to the second data line DLB receives the corresponding data signal, and the first sub-pixel SpxA of the fourth pixel unit electrically connected to the fourth data line DLD receives the corresponding data signal. Consequently, the data voltage corresponding to the second sub-pixel SpxB of the third pixel unit is negative, and the data voltage corresponding to the first sub-pixel SpxA of the fourth pixel unit is positive.

[0048] During the third time period tC of frame p, the second scan signal Scan2, the first clock signal CK1, and the third clock signal CK3 transmitted by the second scan line SL2 are valid pulses, and the first switching device Ts1 and the third switching device Ts3 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the second sub-pixel SpxB of the first pixel unit electrically connected to the first data line DLA receives the corresponding data signal, and the first sub-pixel SpxA of the second pixel unit electrically connected to the third data line DLC receives the corresponding data signal. Consequently, the data voltage corresponding to the second sub-pixel SpxB of the first pixel unit is negative, and the data voltage corresponding to the first sub-pixel SpxA of the second pixel unit is positive.

[0049] During the fourth time period tD of frame p, the second scan signal Scan2, the second clock signal CK2, and the fourth clock signal CK4 transmitted by the second scan line SL2 are valid pulses, and the second switching device Ts2 and the fourth switching device Ts4 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the first sub-pixel SpxA of the third pixel unit electrically connected to the second data line DLB receives the corresponding data signal, and the second sub-pixel SpxB of the fourth pixel unit electrically connected to the fourth data line DLD receives the corresponding data signal. Consequently, the data voltage corresponding to the first sub-pixel SpxA of the third pixel unit is negative, and the data voltage corresponding to the second sub-pixel SpxB of the fourth pixel unit is positive.

[0050] Therefore, the first time period tA and the second time period tB are the periods during which the first scan signal transmitted by the first scan line SLA corresponding to the first first pixel group SG11 has valid pulses, and the third time period tC and the fourth time period tD are the periods during which the second scan signal transmitted by the second scan line SLB corresponding to the first first pixel group SG11 has valid pulses. Referring to the relevant descriptions of the first time period tA to the fourth time period tD, the data signals received by other first pixel groups in the p-th frame can also be obtained.

[0051] In frame p+1, the scan signals transmitted by multiple scan lines still have Figure 3The data signals transmitted via the data bus are in the same form, but with opposite polarities. Therefore, in the (p+1)th frame, the data voltages corresponding to the first sub-pixel SpxA and the second sub-pixel SpxB of the first pixel unit in the first pixel group SG11 are positive; the data voltages corresponding to the first sub-pixel SpxA and the second sub-pixel SpxB of the second pixel unit are negative; the data voltages corresponding to the first sub-pixel SpxA and the second sub-pixel SpxB of the third pixel unit are positive; and the data voltages corresponding to the first sub-pixel SpxA and the second sub-pixel SpxB of the fourth pixel unit are negative. And so on, the data signals received by other first pixel groups SG1 in the (p+1)th frame can also be obtained. Where p ≥ 1.

[0052] Please see Figure 2B and Figure 3 In the first stage t1 of the p-th frame, the first scan signal Scan1, the first clock signal CK1, and the third clock signal CK3 transmitted by the first scan line SL1 are valid pulses, and the first switching device Ts1 and the third switching device Ts3 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the first sub-pixel SpxA of the first pixel unit electrically connected to the first data line DLA receives the corresponding data signal, and the first sub-pixel SpxA of the second pixel unit electrically connected to the third data line DLC receives the corresponding data signal. Therefore, the data voltage corresponding to the first sub-pixel SpxA of the first pixel unit is positive, and the data voltage corresponding to the first sub-pixel SpxA of the second pixel unit is negative.

[0053] In the second stage t2 of frame p, the first scan signal Scan1, the second clock signal CK2, and the fourth clock signal CK4 transmitted by the first scan line SL1 are valid pulses, and the second switching device Ts2 and the fourth switching device Ts4 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the first sub-pixel SpxA of the third pixel unit electrically connected to the second data line DLB receives the corresponding data signal, and the first sub-pixel SpxA of the fourth pixel unit electrically connected to the fourth data line DLD receives the corresponding data signal. Therefore, the data voltage corresponding to the first sub-pixel SpxA of the third pixel unit is positive, and the data voltage corresponding to the first sub-pixel SpxA of the fourth pixel unit is negative.

[0054] In the third stage t3 of frame p, the second scan signal Scan2, the first clock signal CK1, and the third clock signal CK3 transmitted by the second scan line SL2 are valid pulses, and the first switching device Ts1 and the third switching device Ts3 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the second sub-pixel SpxB of the first pixel unit electrically connected to the third data line DLC receives the corresponding data signal, and the data voltage corresponding to the second sub-pixel SpxB of the first pixel unit is negative.

[0055] In the fourth stage t4 of frame p, the second scan signal Scan2, the second clock signal CK2, and the fourth clock signal CK4 transmitted by the second scan line SL2 are valid pulses, and the second switching device Ts2 and the fourth switching device Ts4 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the second sub-pixel SpxB of the second pixel unit electrically connected to the second data line DLB receives the corresponding data signal, and the second sub-pixel SpxB of the third pixel unit electrically connected to the fourth data line DLD receives the corresponding data signal. The data voltage corresponding to the second sub-pixel SpxB of the third pixel unit is positive, and the data voltage corresponding to the second sub-pixel SpxB of the fourth pixel unit is negative.

[0056] In the fifth stage t5 of frame p, the third scan signal Scan3, the first clock signal CK1, and the third clock signal CK3 transmitted by the third scan line SL3 are valid pulses, and the first switching device Ts1 and the third switching device Ts3 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the third sub-pixel SpxC of the first pixel unit electrically connected to the first data line DLA receives the corresponding data signal, and the third sub-pixel SpxC of the second pixel unit electrically connected to the third data line DLC receives the corresponding data signal. The data voltage corresponding to the third sub-pixel SpxC of the first pixel unit is positive, and the data voltage corresponding to the third sub-pixel SpxC of the second pixel unit is negative.

[0057] In the sixth stage t6 of frame p, the third scan signal Scan3, the second clock signal CK2, and the fourth clock signal CK4 transmitted by the third scan line SL3 are valid pulses, and the second switching device Ts2 and the fourth switching device Ts4 in the data multiplexing module DM are turned on. Therefore, in the first pixel group SG11, the third sub-pixel SpxC of the third pixel unit electrically connected to the second data line DLB receives the corresponding data signal, and the fourth sub-pixel Spx of the fourth pixel unit electrically connected to the fourth data line DLD receives the corresponding data signal. The data voltage corresponding to the third sub-pixel SpxC of the third pixel unit is positive, and the data voltage corresponding to the third sub-pixel SpxC of the fourth pixel unit is negative.

[0058] Therefore, the first stage t1 and the second stage t2 are the periods when the first scan signal transmitted by the first scan line SLA corresponding to the first first pixel group SG11 has valid pulses; the third stage t3 and the fourth stage t4 are the periods when the second scan signal transmitted by the second scan line SLB corresponding to the first first pixel group SG11 has valid pulses; and the fifth stage t5 and the sixth stage t6 are the periods when the third scan signal transmitted by the third scan line SLC corresponding to the first first pixel group SG11 has valid pulses. Referring to the relevant descriptions of the first stage t1 to the sixth stage t6, the data signals received by other first pixel groups SG1 in the p-th frame can also be obtained.

[0059] In frame p+1, the scan signals transmitted by multiple scan lines still have Figure 3 The data signals transmitted via the data bus are in the same form, but with opposite polarities. Therefore, in the (p+1)th frame, the data voltages corresponding to the first sub-pixel SpxA and the third sub-pixel SpxC of the first pixel unit in the first pixel group SG11 are negative, and the data voltage corresponding to the second sub-pixel SpxB of the first pixel unit is positive. The data voltages corresponding to the first sub-pixel SpxA and the third sub-pixel SpxC of the second pixel unit are positive, and the data voltage corresponding to the second sub-pixel SpxB of the second pixel unit is negative. The data voltages corresponding to the first sub-pixel SpxA and the third sub-pixel SpxC of the third pixel unit are negative, and the data voltage corresponding to the second sub-pixel SpxB of the third pixel unit is positive. The data voltages corresponding to the first sub-pixel SpxA and the third sub-pixel SpxC of the fourth pixel unit are positive, and the data voltage corresponding to the second sub-pixel SpxB of the second pixel unit is negative. And so on, the data signals received by other first pixel groups SG1 in the (p+1)th frame can also be obtained. Where p ≥ 1.

[0060] It should be noted that different data multiplexing modules (DMs) are electrically connected to different data buses. For example... Figures 1A-1BWhen each data multiplexing module (DM) includes two data multiplexing units, the first data multiplexing module is connected to data buses Ds1 and Ds2, and the second data multiplexing module (DM) is connected to data buses Ds3 and Ds4. Similarly, the connection designs between other data multiplexing modules (DM) and their corresponding data buses can be derived.

[0061] It should be understood that, Figures 1A-1B and Figures 2A-2B This explanation uses an example where each data multiplexing module (DM) comprises two data multiplexing units, and each data multiplexing unit comprises two switching devices. However, in practical applications, each data multiplexing module (DM) can include more than two data multiplexing units, and each data multiplexing unit can include more than two switching devices. The working principle of each data multiplexing module (DM) can be found in [reference needed]. Figures 2A-2B and Figure 3 The relevant explanations have been obtained and will not be repeated here.

[0062] In some embodiments, multiple data multiplexing modules (DMs) are located between the display area and the fan-out area of ​​the display panel to avoid mutual interference between the clock lines transmitting multiple clock signals and the fan-out lines, and to avoid the problem of multiple data multiplexing modules (DMs) occupying fan-out area space, thus affecting the fan-out area wiring design.

[0063] It should be noted that the aforementioned switching device can be a transistor. The switching device can be fabricated synchronously with the transistors in the display area, and the clock lines that transmit multiple clock signals can be fabricated on the same layer as the scan lines, so as to utilize existing fabrication techniques and reduce costs.

[0064] Figures 4A-4B This is a schematic diagram of the structure of a display device provided in an embodiment of this application. This application also provides a display device including any of the above-described display panels.

[0065] The display device also includes a source driver and a gate driver circuit. The source driver is connected to multiple data lines and is configured to output multiple data voltages to the multiple data lines. The gate driver circuit is connected to multiple scan lines and is configured to output multiple scan signals to the multiple scan lines.

[0066] Optionally, the display device may further include at least one of a timing controller, a graphics processor, a central processing unit, etc., to provide the necessary control signals to the source driver and gate driver circuits, and control the display panel to perform display. The source driver may correspond to a source driver chip.

[0067] Optionally, the display device may further include a first circuit board, a control circuit board, and a main control circuit board. The first circuit board is electrically connected to the display panel, the control circuit board is electrically connected to the first circuit board, and the main control circuit board is electrically connected to the control circuit board. At least one of the central processing unit and the graphics processor may be located on the main control circuit board, and the timing controller may be located on the control circuit board. The timing controller is electrically connected to the gate drive circuit and the source driver through the first circuit board.

[0068] In some embodiments, the first circuit board and the source driver and gate driver circuits can be electrically connected via flexible circuit boards or other devices, and the control circuit board can be electrically connected to the first circuit board and the main control circuit board via flexible circuit boards or other devices. A fan-out region can be provided between the source driver and the aforementioned multiple clock lines.

[0069] It should be understood that since the display device of this application includes any of the aforementioned display panels, the display device of this application has all the technical effects corresponding to the aforementioned display panels, which will not be repeated here.

[0070] In the above embodiments, the descriptions of each embodiment have different focuses. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized by, The display panel comprises: a plurality of pixel units arranged in an array, each of the pixel units comprising at least two sub-pixels; a plurality of the pixel units arranged into a first pixel group along a first direction, and a plurality of the pixel units arranged into a second pixel group along a second direction, the second direction intersecting the first direction; a plurality of scan groups arranged along the second direction, each of the scan groups comprising at least two scan lines arranged along the second direction; a plurality of the sub-pixels of the same first pixel group being electrically connected to the scan lines comprised in a scan group, each of the first pixel groups being located between two of the scan lines; a plurality of data groups arranged along the first direction, each of the data groups comprising at least two data lines arranged along the first direction, at least one of the data lines being connected to a plurality of the sub-pixels of two of the second pixel groups adjacent along the first direction, each of the second pixel groups being located between two of the data lines; and a plurality of data multiplexing modules, each of the data multiplexing modules being electrically connected to at least two of the data groups adjacent along the first direction, each of the data multiplexing modules comprising at least two data multiplexing units, a plurality of the data lines comprised in each of the data groups being electrically connected to different data multiplexing units, each of the data multiplexing units being configured to transmit data signals transmitted by a same data bus to the data lines located in different data groups in time division, a plurality of the data lines located in a same data group receiving corresponding data signals in a same time period.

2. The display panel of claim 1, wherein, Each of the data multiplexing modules comprises a first data multiplexing unit and a second data multiplexing unit; the first data multiplexing unit comprises a first switch device and a second switch device, the first switch device being configured to control signal transmission between a first data bus and a first data line according to a first clock signal, the second switch device being configured to control signal transmission between the first data bus and a second data line according to a second clock signal; the second data multiplexing unit comprises a third switch device and a fourth switch device, the third switch device being configured to control signal transmission between a second data bus and a third data line according to a third clock signal, the fourth switch device being configured to control signal transmission between the second data bus and a fourth data line according to a fourth clock signal; wherein the first data bus and the second data bus are respectively configured to transmit corresponding data signals; the first data line and the third data line are located in a same data group, the second data line and the fourth data line are located in a same data group, the first clock signal and the third clock signal have a same frequency and a same phase, the second clock signal and the fourth clock signal have a same frequency and a same phase, and the first clock signal and the second clock signal have a phase difference.

3. The display panel of claim 2, wherein, In a same frame, the data signals transmitted by the first data bus correspond to data voltages having a first polarity, and the data signals transmitted by the second data bus correspond to data voltages having a second polarity. The first polarity is one of a positive polarity and a negative polarity, and the second polarity is the other of the positive polarity and the negative polarity.

4. The display panel of claim 3, wherein, The plurality of sub-pixels in the same pixel unit are electrically connected with different scanning lines, and the data lines electrically connected with the first data multiplexing unit and the data lines electrically connected with the second data multiplexing unit are arranged alternately along the first direction.

5. The display panel of claim 4, wherein, The plurality of sub-pixels in the same pixel unit are electrically connected with the same data line, two pixel units adjacent along the first direction in the same first pixel group are electrically connected with different data lines, and the plurality of pixel units in the same second pixel group are electrically connected with two data lines alternately.

6. The display panel of claim 5, wherein, In the same frame, the polarities of the data voltages corresponding to the plurality of sub-pixels in the same pixel unit are the same, the polarities of the data voltages corresponding to two pixel units adjacent along the first direction are different, and the polarities of the data voltages corresponding to two pixel units adjacent along the second direction are different. In adjacent two frames, the polarities of the data voltages corresponding to each sub-pixel are different.

7. The display panel of claim 4, wherein, Each pixel unit comprises a first sub-pixel, a second sub-pixel and a third sub-pixel; in the same pixel unit, the first sub-pixel and the third sub-pixel are electrically connected with the same data line, and the first sub-pixel and the second sub-pixel are electrically connected with different data lines. In the plurality of pixel units arranged along the second direction, the first sub-pixels included in the pixel units are electrically connected with two data lines alternately, and the second sub-pixels included in the pixel units are electrically connected with two data lines alternately; in two pixel units adjacent along the first direction, the first sub-pixel included in one pixel unit is electrically connected with the second sub-pixel included in the other pixel unit with the same data line.

8. The display panel of claim 7, wherein the second sub-pixel is located between the first sub-pixel and the second sub-pixel; In the same frame, the polarities of the data voltages corresponding to the first sub-pixel and the third sub-pixel in the same pixel unit are the same, and the polarity of the data voltage corresponding to the second sub-pixel is different from the polarity of the data voltage corresponding to the first sub-pixel. In the same frame, the polarities of the data voltages corresponding to the first sub-pixels included in two pixel units adjacent along the first direction are different, and the polarities of the data voltages corresponding to the first sub-pixels included in two pixel units adjacent along the second direction are different; in adjacent two frames, the polarities of the data voltages corresponding to each sub-pixel are different.

9. The display panel of claim 2, wherein, In a period when the scanning signal transmitted by any scanning line has an effective level, the first clock signal has an effective level, and the second clock signal has an effective level. The period when the first clock signal has an effective level does not overlap with the period when the second clock signal has an effective level.

10. A display device, characterized by comprising: The display panel comprises any one of the display panels of claims 1-9.

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