Electronic device

Abstract

The electronic device includes a display device including a data driver integrated circuit converting interface data into second data and a display panel displaying an image based on the second data; and a processor that processes the raw image data to provide the interface data to the display device. The processor also maintains a resolution of the interface data at a first resolution in a first mode, the first resolution being a resolution of the original image data, changes the resolution of the interface data to a second resolution different from the first resolution in a second mode different from the first mode, and maintains a frequency of the interface data constant.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0118810, filed on September 2, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to electronic devices. Background Technology

[0004] Electronic devices may include processors and display devices. The display device may include a data driver integrated circuit (“IC”), which includes a timing controller and a data driver. The processor and display device (or the timing controller and data driver) can send and receive signals desired by the electronic device (or display device) through an interface. Summary of the Invention

[0005] When driving electronic devices (or display devices) via an interface, unexpected power consumption may occur when the display device displays a high-resolution image, depending on the frequency of the data signals exchanged between components. Therefore, it is desirable to control the resolution and frequency of the data signals according to the driving mode.

[0006] The present disclosure is characterized by providing an electronic device in which the driving power consumption of the electronic device can be relatively reduced by controlling the resolution of the data signals exchanged between the processor and the display device according to the driving mode.

[0007] The electronic device in embodiments of this disclosure includes a display device comprising a data driver integrated circuit (“IC”) for converting interface data into second data and a display panel for displaying an image based on the second data display; and a processor for processing raw image data to provide the interface data to the display device. The processor also maintains the resolution of the interface data at a first resolution in a first mode, the first resolution being the resolution of the raw image data, changes the resolution of the interface data to a second resolution different from the first resolution in a second mode different from the first mode, and maintains a constant frequency for the interface data.

[0008] In an embodiment, the original image data may include a plurality of first line data corresponding to a plurality of pixel rows arranged in one direction in the display panel, the second data may include a plurality of second line data corresponding to the plurality of pixel rows, and in a first mode, each of the plurality of first line data may have the same data value as the data value of the corresponding second line data in the plurality of second line data.

[0009] In an embodiment, in the second mode, the values ​​of the first line data in odd-numbered rows among the plurality of first line data and the values ​​of the second line data in odd-numbered rows among the plurality of second line data can be the same, and the values ​​of the first line data in even-numbered rows among the plurality of first line data and the values ​​of the second line data in even-numbered rows among the plurality of second line data can be different from each other.

[0010] In an embodiment, in the second mode, the multiple second line data may include the 2_1 line data and the 2_2 line data corresponding to the next line of the 2_1 line data, and the values ​​of the 2_1 line data and the 2_2 line data may be the same.

[0011] In an embodiment, the processor may include: a graphics processing unit that converts raw image data into rendering data; a first memory that generates first data based on the rendering data; and an interface unit that converts the first data into interface data and outputs the interface data to a data driver IC.

[0012] In one embodiment, the graphics processing unit may convert the resolution of the rendered data to a second resolution in a second mode.

[0013] In an embodiment, the second resolution may have a lower vertical resolution than the first resolution.

[0014] In an embodiment, in a first mode, the first memory can read each of a plurality of first line data from the rendering data to generate first data.

[0015] In an embodiment, in the second mode, the first memory can read the first line data corresponding to the odd-numbered rows from a plurality of first line data from the rendering data to generate the first data.

[0016] In one embodiment, the processor may supply mode data about the driving mode to the display device.

[0017] The electronic device in embodiments of this disclosure includes: a display device, the display device including a data driver IC for converting interface data into second data and a display panel for displaying an image based on the second data display; and a processor that processes raw image data to provide the interface data to the display device. The data driver IC also maintains the resolution of the second data at a first resolution in a first mode, the first resolution being the resolution of the raw image, and changes the resolution of the second data to a second resolution different from the first resolution in a second mode different from the first mode.

[0018] In one embodiment, the processor may supply mode data about the driving mode to the data driver IC.

[0019] In an embodiment, the data driver IC may include: a second memory that generates fill data based on interface data; and a scaler that generates second data based on the fill data and pattern data.

[0020] In an embodiment, in the second mode, the scaler can scale the padding data to change the resolution of the padding data to a second resolution, and generate second data based on the padding data.

[0021] In an embodiment, the first resolution may have a resolution of 1080 by 2160.

[0022] In an embodiment, the second resolution may have a resolution of 1440 by 1440. Attached Figure Description

[0023] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept.

[0024] Figure 1 This is a block diagram illustrating an embodiment of the display system.

[0025] Figure 2 This is a block diagram illustrating an embodiment of a display device according to the present disclosure.

[0026] Figure 3 It is shown that it includes Figure 2 A circuit diagram of an embodiment of pixels in a display device.

[0027] Figure 4 It is used to interpret the connection included Figure 2 A diagram illustrating an embodiment of the data clock signal lines and common signal lines of the timing controller and data driver in a display device.

[0028] Figure 5 It shows from Figure 4 A diagram illustrating an embodiment of the signals supplied by the timing controller to the data driver.

[0029] Figure 6 It is shown Figure 1 A block diagram of the components of the processor and data driver integrated circuit (“IC”).

[0030] Figure 7 This is a diagram showing the data signals exchanged between the processor and the data driver IC in the first mode.

[0031] Figure 8 It is a graph showing the line data values ​​of the original image data and the second data according to the first mode.

[0032] Figure 9 This is a diagram showing the data signals exchanged between the processor and the data driver IC in the second mode.

[0033] Figure 10 It is a graph showing the line data values ​​of the original image data and the second data according to the second mode.

[0034] Figure 11 This is a diagram illustrating an embodiment of data signals exchanged between a processor and a data driver IC in a second mode according to the present disclosure.

[0035] Figure 12 This is a diagram illustrating a component of a processor and a display device, and an embodiment of data signals exchanged between the component of the processor and the display device in a first mode.

[0036] Figure 13 This is a diagram illustrating a component of a processor and a display device, and an embodiment of data signals exchanged between the component of the processor and the display device in a second mode.

[0037] Figure 14 It is shown Figure 1 The display system is implemented as a perspective view of an embodiment of a smartphone.

[0038] Figure 15 It is shown Figure 1 The display system is implemented as a perspective view of an embodiment of a tablet personal computer (“PC”). Detailed Implementation

[0039] In the following, preferred embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts expected to operate according to the present disclosure are described, and descriptions of other parts will be omitted so as not to obscure the subject matter of the disclosure. Furthermore, the present disclosure is not limited to the embodiments described herein and can be implemented in various forms. However, the embodiments described herein are provided for detailed explanation so that those skilled in the art can readily practice the technical spirit of the invention.

[0040] Throughout this specification, when a first part is referred to as being connected or coupled to a second part, this includes not only cases where the first and second parts are directly connected or coupled, but also cases where the first and second parts are indirectly connected or coupled via another element between them. The terminology used herein is for describing illustrative embodiments and is not intended to limit this disclosure. Throughout this specification, unless the context clearly indicates otherwise, when a part includes a component, it means that the part may also include other components, rather than excluding other components. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or any combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term "and / or" can include any combination of one or more corresponding elements.

[0041] Although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the scope of this disclosure, the first element discussed below may be referred to as the second element.

[0042] For descriptive purposes, spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” and “over” may be used herein. By doing so, as illustrated in the accompanying drawings, the relationship between one element or feature and another element (or feature) or feature (or feature) is explained. In addition to the directions depicted in the drawings, spatial relative terms are also intended to include other orientations in use, operation, and / or manufacture. For example, when the device shown in the drawings is flipped upside down, the element depicted as “below” or “under” other elements or features is positioned “above” said other elements or features. Thus, in embodiments, the term “below” can include both “above” and “below” orientations. Furthermore, the device may be oriented in other directions (e.g., rotated 90 degrees or in other orientations). Therefore, the spatial relative terms used herein can be interpreted accordingly.

[0043] As used herein, terms such as “cell,” “processor,” and “scaler” are intended to refer to hardware components such as circuits that perform predetermined functions. For example, hardware components may include field-programmable gate arrays (“FPGAs”) or application-specific integrated circuits (“ASICs”).

[0044] Various embodiments are described with reference to the accompanying drawings, which schematically illustrate preferred embodiments. Therefore, it will be anticipated that their shapes may vary depending on, for example, tolerances and / or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the predetermined shapes shown in the drawings. In embodiments, it should be interpreted as including shape variations due to manufacturing processes. Thus, the shapes shown in the drawings may not represent the actual shape of a region of the device, and the enumerated embodiments are not limited thereto.

[0045] Figure 1 This is a block diagram illustrating an embodiment of the display system DS.

[0046] Reference Figure 1 The display system DS may include a display device 1000 and a processor 2000.

[0047] The processor 2000 can perform various tasks and calculations. In some embodiments, the processor 2000 may include an application processor, a graphics processor, a microprocessor, or a central processing unit (“CPU”), etc. The processor 2000 can be connected to other components of the display system DS via a bus system to control them.

[0048] The processor 2000 can send first data DATA1 and control signal CTRL to the display device 1000. The display device 1000 can display an image based on the first data DATA1 and control signal CTRL. The processor 2000 can be configured (e.g., installed) within the display device 1000.

[0049] First data DATA1 and control signal CTRL can be sent and received between processor 2000 and display device 1000 via an interface (e.g., serial programming interface (“SPI”), internal integrated circuit (“I2C”), or mobile industrial processor interface (“MIPI”).

[0050] The display system DS may include a computing system that provides image display capabilities, such as an electronic device (e.g., a smartwatch, mobile phone, smartphone, portable computer, tablet PC, watch phone, car display, smart glasses, portable multimedia player (“PMP”), navigation system, or ultra-mobile personal computer (“UMPC”)). Furthermore, the display system DS may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0051] Figure 2 This is a block diagram illustrating an embodiment of the display device 1000 according to the present disclosure.

[0052] Reference Figure 2The display device 1000 in the embodiments of this disclosure may include a pixel unit (or display panel) 100, a timing controller 200, a data driver 300, and a scan driver 400.

[0053] Pixel unit 100 may include multiple scan lines SL1, SL2, ... and SLn, multiple data lines DL1, DL2, ... and DLm, and multiple pixels PX, where n and m may each be an integer greater than 0.

[0054] Pixel PX can be connected to at least one of scan lines SL1 to SLn and at least one of data lines DL1 to DLm. Each pixel PX can emit light with a brightness corresponding to the data signal provided through the corresponding data line in response to a scan signal provided through the corresponding scan line. A voltage of a first power supply VDD and a voltage of a second power supply VSS can be supplied to the pixel PX from the outside. Here, the voltage of the first power supply VDD and the voltage of the second power supply VSS can be the voltages desired to drive the pixel PX. In an embodiment, for example, the first power supply VDD can have a voltage level higher than the voltage level of the second power supply VSS.

[0055] The timing controller 200 can be accessed from an external source (e.g., Figure 1 The processor 2000 shown receives the control signal CTRL and the first data DATA1. Here, the control signal CTRL may include a clock signal, a vertical synchronization signal, or a horizontal synchronization signal, etc.

[0056] The timing controller 200 can generate a scan control signal SCS based on the control signal CTRL and supply the scan control signal SCS to the scan driver 400.

[0057] Furthermore, the timing controller 200 can generate second data DATA2 based on the control signal CTRL and the first data DATA1, and supply the second data DATA2 to the data driver 300 via the data clock signal line DPL. In some embodiments, the timing controller 200 can generate a data control signal based on the control signal CTRL, generate frame data based on the control signal CTRL and the first data DATA1, configure the data control signal and the frame data as a second data DATA2 as a group of data, and supply the second data DATA2 to the data driver 300 via the data clock signal line DPL.

[0058] Data control signals may include signals desired for the initialization operation of the data driver 300, such as clock training signals. Clock training signals may include clock training modes. Furthermore, frame data may include pixel data, etc.

[0059] The timing controller 200 can supply a training notification signal SFC to the data driver 300 via a common signal line SSL to notify the interval (or clock training interval) of the clock training mode in which the clock training signal is supplied. In an embodiment, for example, the timing controller 200 can supply a first level (or logic low level) training notification signal SFC to the data driver 300 in response to a clock training interval, and can supply a second level (or logic high level) training notification signal SFC higher than the first level to the data driver 300 in response to other intervals.

[0060] Data driver 300 can determine the clock training interval during the vertical blanking period of a frame based on a training notification signal SFC of a first level (or logic low level) provided from timing controller 200 via common signal line SSL. Data driver 300 can generate (or recover) a clock signal based on second data DATA2 during the clock training interval. In embodiments, for example, data driver 300 may include clock data recovery (“CDR”) circuitry. The clock data recovery circuitry can generate a clock signal based on the clock training signal of second data DATA2 during the clock training interval.

[0061] The data driver 300 can generate a data signal based on the second data DATA2 within a valid data period of one frame. In an embodiment, for example, the data driver 300 can generate a data signal based on frame data included in the second data DATA2 and a clock signal generated (or recovered) during a clock training interval.

[0062] The vertical blanking period and valid data period of the clock signal and data signal generated by the data driver 300 can correspond to the second period (or data period).

[0063] Therefore, the data driver 300 can supply data signals to data lines DL1 to DLm.

[0064] The scan driver 400 can receive a scan control signal SCS from the timing controller 200 and supply scan signals to scan lines SL1 to SLn based on the scan control signal SCS. In an embodiment, for example, the scan signals can be supplied sequentially to scan lines SL1 to SLn.

[0065] The scan signal can be set to a gate on-state voltage (e.g., a relatively low voltage or a relatively high voltage). When the scan signal is supplied, the transistor receiving the scan signal can be turned on.

[0066] exist Figure 2In this embodiment, components that supply signals or voltages to the display panel 100 (e.g., timing controller 200, data driver 300, and scan driver 400) are categorized solely based on their function. In some embodiments, for example, the timing controller 200, data driver 300, and scan driver 400 may be formed within a single integrated circuit. In other words, the timing controller 200, data driver 300, and scan driver 400 may be implemented as a single data driver integrated circuit (Data Driver IC) DDI (see reference). Figure 6 ).

[0067] Figure 3 It is shown that it includes Figure 2 A circuit diagram of an embodiment of pixel PX in display device 1000.

[0068] Reference Figure 3 A pixel PX may include a light-emitting element LD and a driving circuit DC connected to the light-emitting element LD to drive the light-emitting element LD.

[0069] The first electrode (e.g., the anode electrode) of the light-emitting element LD can be connected to a first power supply VDD via a drive circuit DC, and the second electrode (e.g., the cathode electrode) of the light-emitting element LD can be connected to a second power supply VSS. The light-emitting element LD can emit light with a brightness corresponding to the amount of drive current controlled by the drive circuit DC.

[0070] Light-emitting elements (LDs) can include organic light-emitting diodes (“OLEDs”) or inorganic light-emitting diodes (such as micro light-emitting diodes (“LEDs”) or quantum dot light-emitting diodes (“QDs”). Furthermore, LDs can be light-emitting elements composed of composites of organic and inorganic materials. Figure 3 In this embodiment, a pixel PX is shown as comprising a single light-emitting element LD, but in other embodiments, a pixel PX may comprise multiple light-emitting elements LD, and the multiple light-emitting elements LD may be connected in series, in parallel, or in a series-parallel connection.

[0071] The first power supply VDD and the second power supply VSS can have different potentials. In an embodiment, for example, the voltage applied through the first power supply VDD can be greater than the voltage applied through the second power supply VSS.

[0072] The driving circuit DC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0073] The first electrode of the first transistor (also called the driving transistor) T1 can be connected to the first power supply VDD, and the second electrode of the first transistor T1 can be electrically connected to the first electrode (e.g., the anode electrode) of the light-emitting element LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the amount of driving current supplied to the light-emitting element LD in response to a data signal supplied to the first node N1 via the data line DL.

[0074] The first electrode of the second transistor (also called the switching transistor) T2 can be connected to the data line DL, and the second electrode of the second transistor T2 can be connected to the first node N1. The gate electrode of the second transistor T2 can be connected to the scan line SL.

[0075] When a scan signal with a conduction voltage (e.g., gate turn-on voltage) is supplied from the scan line SL, the second transistor T2 can be turned on to connect the data line DL and the first node N1. In this case, the data signal of the corresponding frame can be supplied to the data line DL, and therefore, the data signal can be sent to the first node N1. The voltage corresponding to the data signal sent to the first node N1 can be stored in the storage capacitor Cst.

[0076] One electrode of the storage capacitor Cst can be connected to the first node N1, and the other electrode of the storage capacitor Cst can be connected to the first electrode of the light-emitting element LD. The storage capacitor Cst can be charged with a voltage corresponding to the data signal supplied to the first node N1, and can maintain the charging voltage until the data signal of the next frame is supplied.

[0077] For ease of description, Figure 3 A pixel PX with a relatively simple structure is shown, but the structure of the driving circuit DC can be varied in various ways. In an embodiment, the driving circuit DC may also include various transistors (such as a compensation transistor for compensating the threshold voltage of the first transistor T1, an initialization transistor for initializing the first node N1, and / or an emission control transistor for controlling the emission time of the light-emitting element LD) and other circuit elements such as a boost capacitor for boosting the voltage of the first node N1.

[0078] In addition, Figure 3 In the diagram, the transistors included in the drive circuit DC (e.g., the first transistor T1 and the second transistor T2) are shown as N-type transistors, but this disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the drive circuit DC may be changed to a P-type transistor.

[0079] Figure 4 It is used to interpret the connection included Figure 2A diagram of an embodiment of the data clock signal line DPL and common signal line SSL of the timing controller 200 and data driver 300 in the display device 1000. Figure 5 It shows from Figure 4 A diagram of an embodiment of the signals supplied by the timing controller 200 to the data driver 300.

[0080] Reference Figure 4 The data driver 300 may include a data driver circuit 310. Here, the data driver circuit 310 may also be referred to as a driver IC (“D-IC”) or a source IC.

[0081] Data driver circuit 310 can be connected to at least one of the data lines DL1 to DLm. In an embodiment, for example, when the data driver 300 includes only one data driver circuit 310, the data driver circuit 310 and the data driver 300 can be the same. In this case, all data lines DL1 to DLm can be connected to one data driver circuit 310. In another embodiment, when the data driver 300 includes multiple data driver circuits 310, the data lines DL1 to DLm can be grouped, and each group of data lines can be connected to a corresponding data driver circuit 310. In an embodiment, for example, the data driver 300 can include m data driver circuits 310, the same number as the data lines DL1 to DLm. In this case, each group of data lines can include one data line, and the m data driver circuits 310 can be connected to each of the m data lines DL1 to DLm (or the data line groups). In another embodiment, the data driver circuit 310 can include m divided by j (m / j) data driver circuits 310, where j can be an integer greater than or equal to 2 and less than m. In this case, each data line group may include j data lines, and m / j data drive circuits 310 may be connected to j data lines (or data line groups) from m data lines DL1 to DLm respectively.

[0082] The timing controller 200 and the data driver 300 can be connected to each other via the data clock signal line DPL and the common signal line SSL.

[0083] In one embodiment, the timing controller 200 can be connected to each of the data driving circuits 310 included in the data driver 300 via a data clock signal line DPL. In another embodiment, for example, the method by which the timing controller 200 is connected to the data driving circuits 310 included in the data driver 300 via the data clock signal line DPL can be a point-to-point method. Here, the data clock signal line DPL can include the same number of sub-data clock signal lines as the number of data driving circuits 310. In this case, the timing controller 200 can be connected to each of the data driving circuits 310 via the sub-data clock signal lines.

[0084] The data clock signal line DPL may correspond to an interface used to send second data DATA2 provided from the timing controller 200 to the data driver 300 (or data driver circuit 310). In embodiments, for example, the data clock signal line DPL may be a high-speed serial interface. In embodiments, for example, the data clock signal line DPL may be a Universal Serial Interface (“USI”), a Universal Serial Interface for Televisions (“USI-T”), a Hyperpath Interface (“UPI”), or a Universal Description, Discovery and Integration (“UDDI”) device, etc.

[0085] The second data DATA2 can be data with a built-in clock. In an embodiment, as shown in reference... Figure 2 For example, the second data DATA2 may include data control signals (clock training signals) and frame data. In this case, since the timing controller 200 and each of the data driving circuits 310 included in the data driver 300 are connected via the data clock signal line DPL, the timing controller 200 can supply the second data DATA2 corresponding to each of the data driving circuits 310 via the data clock signal line DPL.

[0086] In addition, as referenced Figure 2 The common signal line SSL can correspond to a signal transmission channel used to send the training notification signal SFC provided by the timing controller 200 to the data driver 300 (or data driver circuit 310).

[0087] In one embodiment, the timing controller 200 can be publicly connected to the data drive circuitry 310 included in the data driver 300 via a common signal line SSL. In another embodiment, for example, the method by which the timing controller 200 is connected to the data drive circuitry 310 via the common signal line SSL can be a multi-point method.

[0088] Since the timing controller 200 and the data driver circuit 310 are connected to the common ground via a common signal line SSL, during the clock training interval, the timing controller 200 can simultaneously supply a training notification signal SFC of the first level (or logic low level) that notifies the supply of the clock training signal to all data driver circuits 310 via a common signal line SSL.

[0089] Reference Figure 5 The frame period of each image frame may include a vertical blanking period and an effective data period. In an embodiment, for example, the nth frame period FRPn may include the nth vertical blanking period VBPn and the nth effective data period ADPn.

[0090] The nth valid data period ADPn can be the period that supplies the grayscale values ​​that constitute the image frames to be displayed on the display panel 100. The grayscale values ​​can be included in the pixel data PXD (or image data).

[0091] The nth vertical blanking period (VBPn) can be set before the nth valid data period (ADPn) of the current frame. During the nth vertical blanking period (VBPn), clock training, frame setup, and dummy data feeding can be performed. The nth vertical blanking period (VBPn) may include (for example, sequentially including) the period for feeding dummy data (DMD), the period for feeding clock training mode (CTP), the period for feeding frame data (FRD), and the period for feeding dummy data (DMD).

[0092] The timing controller 200 can notify the data driver 300 that the clock training mode CTP is being supplied to the data clock signal line DPL by applying a low logic level L clock training signal to the shared signal line SFCL during the nth vertical blanking cycle VBPn. When no clock training mode CTP is supplied, the timing controller 200 can apply a high logic level H clock training signal to the shared signal line SFCL.

[0093] During the nth valid data period ADPn, the line start group SOL, line setup group CONF, image data group (e.g., pixel data PXD, frame data FRD, or dummy data DMD) and horizontal blanking period group HBP can be supplied sequentially in pixel rows.

[0094] The line start grouping SOL can have the function of notifying the data drive circuit 310 that it has started to supply signals for the changed pixel rows.

[0095] Frame data (FRD) can be data that has been synchronized. In other words, frame data (FRD) can be synchronized by a clock training signal.

[0096] The horizontal blanking period grouping (HBP) can have the function of notifying the data driving circuit 310 that the pixel row (e.g., pixels connected to the same scan line) corresponding to the image data group such as pixel data (PXD) has changed.

[0097] The line setting group CONF may include operational options for the data driving circuitry 310. In an embodiment, for example, the line setting group CONF may indicate whether subsequent data is pixel data (PXD) or dummy data (DMD).

[0098] Figure 6 It is shown Figure 1 Block diagram of the components of the processor 2000 and data driver integrated circuit DDI.

[0099] Reference Figure 6 The processor 2000 may include a graphics processing unit 2100, a first memory 2200, and an interface unit 2300.

[0100] Raw image data (IMG) can be supplied to the graphics processing unit 2100. The graphics processing unit 2100 can render the supplied raw image data (IMG). In other words, the graphics processing unit 2100 can generate rendering data (RDATA) in which the raw image data (IMG) is rendered.

[0101] The first memory 2200 can generate first data DATA1 based on the rendering data RDATA. In an embodiment, for example, the first memory 2200 can generate different first data DATA1 based on the rendering data RDATA according to the driving mode. (See below for further details.) Figures 7 to 11 This will be described in detail.

[0102] Interface unit 2300 can convert first data DATA1 received from first memory 2200 into interface data INT_DATA and output the interface data INT_DATA to an external source. In an embodiment, for example, interface unit 2300 can output the interface data INT_DATA to a data driver integrated circuit (DDI). In this case, interface unit 2300 can form an interface system between processor 2000 and data driver integrated circuit (DDI). That is, interface unit 2300 can interface (connect) the signals exchanged between interface processor 2000 and data driver integrated circuit (DDI). In this case, when the frequency of the signal provided from processor 2000 to data driver integrated circuit (DDI) changes, it may affect the driving of display device 1000 (see reference 1000). Figure 1 Unexpected power consumption may occur. Therefore, it may be desirable to keep the frequency of the interface data INT_DATA exchanged between the processor 2000 and the data driver integrated circuit DDI constant.

[0103] Interface unit 2300 can provide mode data MD to data driver integrated circuit DDI. Mode data MD can include information about display device 1000 (see reference). Figure 1 The information pertains to the driving mode of the display device 1000. In an embodiment, for example, the display device 1000 may be driven in a first mode that displays an image at a conventional resolution. The display device 1000 may also be driven in a second mode that displays an image at a relatively higher resolution than the first mode. In this case, the driving logic of the display device 1000 can vary depending on the driving mode, and the display device 1000 can be driven according to different driving logic based on the input mode data MD.

[0104] The data driver integrated circuit (DDI) can be provided with mode data MD and interface data INT_DATA. Therefore, the data driver integrated circuit (DDI) can generate second data DATA2 based on the mode data MD and interface data INT_DATA. In an embodiment, for example, the data driver integrated circuit (DDI) can process the second data DATA2 according to the driving mode and supply the second data DATA2 to the display panel 100 (see reference). Figure 2 In this case, the second data DATA2 can be compared with the reference. Figure 4 and Figure 5 The second data DATA2 described corresponds to this.

[0105] exist Figure 6 , Figure 7 , Figure 9 and Figure 10 The present invention illustrates an embodiment in which interface unit 2300 sends pattern data MD to data driver integrated circuit DDI, but the present disclosure is not limited thereto. In an embodiment, for example, another component of processor 2000 may send pattern data MD to data driver integrated circuit DDI.

[0106] Figure 7 This is a diagram showing the data signal DATA exchanged between the processor 2000 and the data driver integrated circuit DDI in the first mode. Figure 8 It is a graph showing the line data values ​​of the original image data IMG and the second data DATA2 according to the first mode. Figure 9 This is a diagram showing the data signal DATA exchanged between the processor 2000 and the data driver integrated circuit DDI in the second mode. Figure 10 This is a graph showing the line data values ​​of the original image data IMG and the second data DATA2 according to the second mode.

[0107] Figure 7 and Figure 9The focus is on the resolution of the data signal DATA exchanged between the processor 2000 and the data driver integrated circuit DDI in both the first and second modes. Furthermore, it can be similar to... Figure 6 The graphics processing unit 2100, the first memory 2200, the interface unit 2300, and the data driver integrated circuit DDI are used to describe this. Figure 7 and Figure 9 The graphics processing unit 2100, the first memory 2200, the interface unit 2300, and the data driver integrated circuit DDI are included.

[0108] First, refer to Figure 7 In the first mode, the resolution value corresponding to the data signal DATA can be constant. In an embodiment, for example, in the first mode, the resolution values ​​corresponding to the original image data IMG, the rendered data RDATA, the first data DATA1, the interface data INT_DATA, and the second data DATA2 can have a first resolution RES1 value.

[0109] Reference Figure 2 and Figure 8 The raw image data IMG can include data from the display panel 100 (see reference). Figure 2 ) pixels PX (refer to) Figure 2 The first line data LD1 corresponds to the pixel row of the pixel. In an embodiment, for example, the pixel row of the pixel PX of the display panel 100 may have n rows. In this case, each pixel row of the pixel PX can be driven based on the (1_1)th line data LD1_1, the (1_2)th line data LD1_2, the (1_3)th line data LD1_3, the (1_4)th line data LD1_4, ..., the (1_n-1)th line data LD1_n-1 and the (1_n)th line data LD1_n.

[0110] Furthermore, the second data DATA2 may include second line data LD2 corresponding to the pixel rows of pixel PX of display panel 100. In an embodiment, for example, the pixel rows of pixel PX of display panel 100 may have n rows. In this case, each pixel row of pixel PX may be driven based on the (2_1)th line data LD2_1, the (2_2)th line data LD2_2, the (2_3)th line data LD2_3, the (2_4)th line data LD2_4, ..., the (2_n-1)th line data LD2_n-1 and the (2_n)th line data LD2_n.

[0111] The first line data LD1 and the second line data LD2 may include any one of the first data values ​​V1 to the nth data value Vn. In this case, it can be assumed that each of the first data values ​​V1 to the nth data value Vn corresponds to a data value of a predetermined color of the pixel (e.g., a red data value corresponding to a red sub-pixel, a blue data value corresponding to a blue sub-pixel, or a green data value corresponding to a green sub-pixel).

[0112] In the first mode, the line data values ​​of the original image data IMG and the second data DATA2 can be the same. In an embodiment, for example, in the first mode, the first line data LD1 and the second line data LD2 can be the same. In other words, the (1_1)th line data LD1_1 to the (1_n)th line data LD1_n can each have the same data value as the (2_1)th line data LD2_1 to the (2_n)th line data LD2_n. Therefore, in the first mode, the resolution corresponding to the original image data IMG and the resolution corresponding to the second data DATA2 can be the same as the first resolution RES1.

[0113] Reference Figure 9 In the second mode, the graphics processing unit 2100 can convert the raw image data IMG into rendering data RDATA'. Therefore, the first memory 2200 can generate first data DATA1' based on the rendering data RDATA'. Subsequently, the interface unit 2300 can convert the first data DATA1' into interface data INT_DATA' and supply the interface data INT_DATA' to the data driver integrated circuit DDI. The data driver integrated circuit DDI can generate second data DATA2' based on the interface data INT_DATA' and the mode data MD. Therefore, the display panel 100 (refer to...) Figure 2 This can display the image corresponding to the second data DATA2'.

[0114] In the second mode, the resolution of the data signal DATA can be converted from a first resolution RES1 to a second resolution RES2. In an embodiment, for example, the resolution value corresponding to the original image data IMG can have the value of the first resolution RES1. The resolution values ​​corresponding to the rendering data RDATA', the first data DATA1', the interface data INT_DATA', and the second data DATA2' can have the value of the second resolution RES2. In other words, the graphics processing unit 2100 can convert the resolution of the rendering data RDATA' to the second resolution RES2 and render the original image data IMG. Therefore, the resolution value corresponding to the subsequently generated data signal DATA can be the value of the second resolution RES2.

[0115] Refer to together Figure 9 andFigure 10 In the second mode, the value of the second line data LD2 in odd-numbered rows can be the same as the value of the first line data LD1 in odd-numbered rows. In an embodiment, for example, the (2_1)th line data LD2_1 can have a first data value V1, and the (1_1)th line data LD1_1 can also have a first data value V1. Furthermore, the (2_3)th line data LD2_3 can have a third data value V3, and the (1_3)th line data LD1_3 can also have a third data value V3. Additionally, the (2_n-1)th line data LD2_n-1 can have a (n-1)th data value Vn-1, and the (1_n-1)th line data LD1_n-1 can also have a (n-1)th data value Vn-1.

[0116] In the second mode, the value of the second line data LD2 in even-numbered rows can be different from the value of the first line data LD1 in even-numbered rows. In an embodiment, the (2_2)th line data LD2_2 can have a first data value V1, and the (1_2)th line data LD1_2 can have a second data value V2. Furthermore, the (2_4)th line data LD2_4 can have a third data value V3, and the (1_4)th line data LD1_4 can have a fourth data value V4. Additionally, the (2_n)th line data LD2_n can have an (n-1)th data value Vn-1. The (1_n)th line data LD1_n can have an nth data value Vn.

[0117] In the second mode, the graphics processing unit 2100 can generate rendering data RDATA' such that the values ​​of the first line data LD1 and the second line data LD2 are different from each other. In an embodiment, for example, the graphics processing unit 2100 can generate rendering data RDATA' such that the vertical resolution of the rendering data RDATA' (or the second data DATA2') is relatively lower than the vertical resolution of the original image data IMG. In an embodiment, for example, when processing the second line data LD2 of odd-numbered rows, the graphics processing unit 2100 can generate rendering data RDATA' with the same data value as the first line data LD1. When processing the second line data LD2 of even-numbered rows, the graphics processing unit 2100 can generate rendering data RDATA' with the same data value as the first line data LD1 of the preceding row. Therefore, the original image data IMG can have a first resolution RES1, and the rendering data RDATA' (or the second data DATA2') can have a second resolution RES2. For ease of description, Figure 10 The second data DATA2' (or rendering data RDATA') is shown, but any of the data signals DATA can be described similarly. In an embodiment, for example, the first data DATA1' and the interface data INT_DATA' can also be described similarly.

[0118] In embodiments of this disclosure, the amount of time required to drive the display device 1000 (see reference 1000) can be reduced. Figure 2 Unexpected power consumption during operation. In an embodiment, for example, the power consumption driving the display device 1000 may increase when the display device 1000 displays a high-resolution image. In an embodiment, for example, the power consumption driving the display device 1000 may increase relatively when the frequency of the data signal DATA (e.g., interface data INT_DATA') generated between the processor 2000 and the display device 1000 changes. In this case, the frequency of the interface data INT_DATA' can be kept constant by the graphics processing unit 2100 changing the resolution of the rendering data RDATA'. Therefore, the power consumption of driving the display device 1000 can be reduced.

[0119] Figure 11 This is a diagram illustrating an embodiment of the data signal DATA exchanged between the processor 2000 and the data driver integrated circuit DDI in a second mode according to the present disclosure.

[0120] Figure 11 The graphics processing unit 2100, the first memory 2200, the interface unit 2300, and the data driver integrated circuit DDI can be similar to Figure 6 The graphics processing unit 2100, the first memory 2200, the interface unit 2300, and the data driver integrated circuit DDI are described.

[0121] Reference Figure 11 In the second mode, the graphics processing unit 2100 can convert the raw image data IMG into rendered data RDATA. Therefore, the first memory 2200 can generate first data DATA1' based on the rendered data RDATA. In this case, the first memory 2200 can read the line data of the odd-numbered rows in the second line data LD2 of the rendered data RDATA to generate the first data DATA1'. Therefore, the first data DATA1' can include... Figure 10 The second data DATA2' shown is essentially the same line data.

[0122] Subsequently, the interface unit 2300 can convert the first data DATA1' into interface data INT_DATA' and supply the interface data INT_DATA' to the data driver integrated circuit DDI. The data driver integrated circuit DDI can generate the second data DATA2' based on the interface data INT_DATA' and the mode data MD. Therefore, the display panel 100 (refer to...) Figure 2 This can display the image corresponding to the second data DATA2'.

[0123] In the second mode, the resolution of the data signal DATA can be converted from a first resolution RES1 to a second resolution RES2. In an embodiment, the resolution value corresponding to the original image data IMG can have the value of the first resolution RES1. The resolution values ​​corresponding to the first data DATA1', the interface data INT_DATA', and the second data DATA2' can have the value of the second resolution RES2.

[0124] Figure 12 This is a diagram illustrating an embodiment of the components of the processor 2000 and the display device 1000, and the data signal DATA exchanged between the components of the processor 2000 and the display device 1000 in a first mode. Figure 13 This is a diagram illustrating an embodiment of the components of the processor 2000 and the display device 1000, and the data signal DATA exchanged between the components of the processor 2000 and the display device 1000 in a second mode.

[0125] Reference Figure 12 The processor 2000 can generate interface data INT_DATA based on the original image data IMG and supply the interface data INT_DATA to the display device 1000.

[0126] The display device 1000 may include a second memory MEM2, a scaler SCR, and a display panel 100. In this case, it can be similar to... Figure 2 The display panel 100 is used to describe Figure 12 and Figure 13 The display panel 100.

[0127] The second memory MEM2 can generate padding data PDATA based on interface data INT_DATA. In an embodiment, the second memory MEM2 can be a hardware-implemented padding circuit, including logic circuits or memory elements, etc. In an embodiment, for example, the padding value can be determined based on an offset value stored based on interface data INT_DATA. The offset value can be preset during the manufacturing process of the display device 1000 or provided from an external device (e.g., a separate input terminal for setting). The determined padding value can be added to the first line data LD1 (refer to...). Figure 8 This generates fill data PDATA. The second memory MEM2 can provide fill data PDATA to the scaler SCR.

[0128] The scaler SCR can generate second data DATA2 based on the padding data PDATA. In an embodiment, the scaler SCR can transform the resolution of the data signal DATA by scaling to generate the second data DATA2. In an embodiment, in a first mode, the scaler SCR can generate the second data DATA2 without transforming the resolution of the data signal DATA. In an embodiment, for example, the second data DATA2 can be generated such that the resolution of the data signal DATA remains at a third resolution RES3. The scaler SCR can provide the second data DATA2 to the display panel 100, and the display panel 100 can display an image based on the second data DATA2.

[0129] The processor 2000 can provide pattern data (MD) to the scaler (SCR). This can be similar to... Figure 6 Using pattern data MD to describe Figure 12 The pattern data MD.

[0130] Reference Figure 13 In the second mode, the scaler SCR can generate second data DATA2. In this case, the scaler SCR can receive mode data MD and scale the padding data PDATA to generate second data DATA2. In an embodiment, for example, the scaler SCR can receive mode data MD and scale the padding data PDATA to a size corresponding to the fourth resolution RES4 to generate second data DATA2.

[0131] In an embodiment, the third resolution RES3 may have a resolution of 1080 by 2160 (1080 × 2160). The fourth resolution RES4 may have a resolution of 1440 by 1440 (1440 × 1440). However, this is merely an illustrative embodiment, and the present disclosure is not limited thereto.

[0132] Figure 14 It is shown Figure 1 The display system is implemented as a perspective view of an embodiment of a smartphone. Figure 15 It is shown Figure 1 The display system is implemented as a perspective view of an embodiment of a tablet personal computer (“PC”).

[0133] Reference Figure 14 In embodiments of this disclosure, a display device 1000 (see reference 1000) is included. Figure 1 The 1400 smartphone can relatively reduce power consumption.

[0134] Reference Figure 15 In the embodiments of this disclosure, the tablet PC 1500, which includes the display device 1000, can relatively reduce driving power consumption.

[0135] In embodiments of this disclosure, by controlling the resolution of the data signals exchanged between the processor and the display device according to the driving mode, the driving power consumption of the electronic device can be relatively reduced.

[0136] The effects in the embodiments of this disclosure are not limited to those described above, and various other effects are included in the specification.

[0137] Although illustrative embodiments and applications have been described herein, other embodiments and modifications can be derived from the above description. Therefore, the spirit of this disclosure is not limited to these embodiments, but extends to the scope of the claims, various obvious modifications, and equivalents.

Claims

1. An electronic device, comprising: The electronic device includes: a display device including: a data driver integrated circuit that converts interface data into second data; and a display panel that displays an image based on the second data; and a processor configured to: process original image data, and provide the interface data to the display device, in a first mode, maintain a resolution of the interface data at a first resolution that is a resolution of the original image data, in a second mode different from the first mode, change the resolution of the interface data to a second resolution different from the first resolution, and maintain a frequency of the interface data constant. 2.The electronic device of claim 1, wherein, The original image data includes a plurality of first line data corresponding to a plurality of pixel rows arranged in one direction in the display panel, wherein the second data includes a plurality of second line data corresponding to the plurality of pixel rows, and wherein, in the first mode, each of the plurality of first line data has a same data value as a data value of a corresponding second line data of the plurality of second line data. 3.The electronic device of claim 2, wherein, In the second mode, values of first line data among the plurality of first line data in odd-numbered rows and values of second line data among the plurality of second line data in the odd-numbered rows are identical to each other, and values of first line data among the plurality of first line data in even-numbered rows and values of second line data among the plurality of second line data in the even-numbered rows are different from each other. 4.The electronic device of claim 3, wherein, In the second mode, the plurality of second line data includes 2_1 line data and 2_2 line data corresponding to a next row of a row of the 2_1 line data, and wherein a value of the 2_1 line data and a value of the 2_2 line data are identical to each other. 5.The electronic device of claim 2, wherein, The processor includes: a graphics processing unit that converts the original image data into rendering data; a first memory that generates first data based on the rendering data; and an interface unit that converts the first data into the interface data, and outputs the interface data to the data driver integrated circuit. 6.The electronic device of claim 5, wherein, The graphics processing unit converts a resolution of the rendering data into the second resolution in the second mode. 7.The electronic device of claim 6, wherein, The second resolution has a lower vertical resolution than the first resolution. 8.The electronic device of claim 5, wherein, In the first mode, the first memory reads each of the plurality of first line data from the rendering data to generate the first data. 9.The electronic device of claim 5, wherein In the second mode, the first memory reads first line data corresponding to odd-numbered rows among the plurality of first line data from the rendering data to generate the first data. 10.The electronic device of claim 1, wherein The processor supplies mode data about a driving mode to the display device.

11. An electronic device, wherein, The electronic device includes: a display device including: a data driver integrated circuit that converts interface data into second data; and a display panel that displays an image based on the second data; and a processor configured to: process original image data, and provide the interface data to the display device, in a first mode, maintain a resolution of the interface data at a first resolution that is a resolution of the original image data, in a second mode different from the first mode, change the resolution of the interface data to a second resolution different from the first resolution, and maintain a frequency of the interface data constant. The original image data includes a plurality of first line data corresponding to a plurality of pixel rows arranged in one direction in the display panel, wherein the second data includes a plurality of second line data corresponding to the plurality of pixel rows, and wherein, in the first mode, each of the plurality of first line data has a same data value as a data value of a corresponding second line data of the plurality of second line data. In the second mode, values of first line data among the plurality of first line data in odd-numbered rows and values of second line data among the plurality of second line data in the odd-numbered rows are identical to each other, and values of first line data among the plurality of first line data in even-numbered rows and values of second line data among the plurality of second line data in the even-numbered rows are different from each other. In the second mode, the plurality of second line data includes 2_1 line data and 2_2 line data corresponding to a next row of a row of the 2_1 line data, and wherein a value of the 2_1 line data and a value of the 2_2 line data are identical to each other. The processor includes: a graphics processing unit that converts the original image data into rendering data; a first memory that generates first data based on the rendering data; and an interface unit that converts the first data into the interface data, and outputs the interface data to the data driver integrated circuit. The graphics processing unit converts a resolution of the rendering data into the second resolution in the second mode. The second resolution has a lower vertical resolution than the first resolution. In the first mode, the first memory reads each of the plurality of first line data from the rendering data to generate the first data. In the second mode, the first memory reads first line data corresponding to odd-numbered rows among the plurality of first line data from the rendering data to generate the first data. The processor supplies mode data about a driving mode to the display device. a processor that processes original image data and provides the interface data to the display device, wherein the data driver integrated circuit is configured to, in a first mode, maintain a resolution of the second data at a first resolution, the first resolution being a resolution of the original image data, and in a second mode different from the first mode, change the resolution of the second data to a second resolution different from the first resolution. 12.The electronic device of claim 11, wherein, The processor supplies mode data about a driving mode to the data driver integrated circuit. 13.The electronic device of claim 12, wherein, The data driver integrated circuit includes: a second memory that generates padding data based on the interface data; and a scaler that generates the second data based on the padding data and the mode data. 14.The electronic device of claim 13, wherein, In the second mode, the scaler scales the padding data to change a resolution of the padding data to the second resolution, and the scaler generates the second data based on the padding data. 15.The electronic device of claim 14, wherein, The first resolution has a resolution of 1080 by 2160. 16.The electronic device of claim 15, wherein, The second resolution has a resolution of 1440 by 1440.

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