Digital multi-phase filter design method based on coefficient expansion
By employing a coefficient-expanded digital polyphase filter design method, and through parallel expansion and combined optimization of multiplier resources, the problem of high hardware resource consumption and insufficient frequency in high-speed signal filters in FPGA devices is solved, achieving efficient hardware resource utilization and frequency enhancement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-04
- Publication Date
- 2026-03-10
AI Technical Summary
When implementing high-speed signal filtering in FPGA devices, existing digital FIR filters have high hardware resource requirements and insufficient operating frequency, making it difficult to meet real-time requirements.
A digital polyphase filter design method based on coefficient expansion is adopted. By expanding the input signal into multiple branches in parallel, sub-filter banks are designed for parallel processing, and finally the output is combined in parallel to optimize the utilization of multiplier resources.
It effectively saves multiplier resources inside the FPGA, improves circuit operating frequency and signal processing performance, and is suitable for implementing high-speed signal filtering under limited resource conditions.
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Figure CN121643697A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of digital filter design technology, specifically to a digital polyphase filter design method based on coefficient extension, and particularly to a high-speed digital FIR filter implementation method in digital signal processing algorithms on digital signal processing chips such as FPGAs. Background Technology
[0002] In digital signal processing, digital FIR filters are frequently used to improve signal quality by filtering digital signals. Commonly used digital devices include DSPs, FPGAs, and ASICs, with the latter two being more suitable for applications with high real-time requirements, such as high-speed signal filtering after sampling in electronic systems. Currently, the sampling frequency of digital signal sampling devices exceeds 2GHz, while the operating frequency of FPGA devices is difficult to exceed 500MHz. High-speed signals after sampling are typically represented in polyphase form within FPGA devices. Filtering high-speed signals usually requires the use of digital polyphase filters. Digital polyphase filters are more complex in structure than single-phase filters, and implementing high-speed signal filtering typically requires significant hardware resources. Therefore, researching digital polyphase filter implementation methods is essential to effectively utilize FPGA internal resources to save hardware costs or improve signal processing performance under limited resource conditions.
[0003] Digital FIR filters can be categorized into time-domain and frequency-domain processing methods. Generally, time-domain processing has lower latency but requires more multiplier resources, while frequency-domain processing requires fewer multiplier resources but has higher latency. From the perspective of input and output sampling frequencies, digital FIR filters can be classified into single-rate filters, decimation filters, and interpolation filters. Single-rate filters have the same output sampling frequency as their input sampling frequency, decimation filters have an output sampling frequency lower than their input sampling frequency, and interpolation filters have an output sampling frequency higher than their input sampling frequency. The FPGA internal resources required for implementing digital polyphase filters mainly include multipliers and adders. Multipliers are more complex than adders, operate at lower frequencies, and are fewer in number. Optimizing the structure of digital polyphase filters can appropriately reduce the required multiplier resources, thereby fully utilizing the FPGA's internal resources and simultaneously improving the circuit's operating frequency.
[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] This invention provides a design method for digital polyphase filters based on coefficient extension, which can overcome the defects existing in the prior art to a certain extent.
[0006] Other features and advantages of the invention will become apparent from the following detailed description, or may be learned in part by practice of the invention.
[0007] According to a first aspect of the present invention, a method for designing a digital polyphase filter based on coefficient extension is provided, the method comprising: The original input signal is extended in parallel into multiple parallel branches; Design sub-filter banks to filter multiple parallel branches; The outputs of the sub-filter banks are combined in parallel to obtain the filter output.
[0008] In some exemplary embodiments, the parallel expansion specifically refers to: The original input data is either 1 channel or 2. M Road sampling rate 1 / 2 M Multiphase data parallel expansion yields 3 M Road sampling 1 / 2 M The sampling data; Uses a 2-input adder, 2 M The path tree adder has a delay of M clock cycles; in 3 M In each extended branch, for terms with a sum less than 2 M The branch is delayed, making 3 M Each extended branch has an output delay of M clock cycles during parallel extended processing.
[0009] In some exemplary embodiments, the number of sub-filters in the sub-filter bank is P=3. N-M The sub-filter coefficient length is 2 N-M The filter coefficient length is 2 N , where N is an integer not less than 1, and M is an integer less than or equal to N.
[0010] In some exemplary implementations, all sub-filters have the same structure but different coefficients.
[0011] In some exemplary embodiments, the method further includes when the coefficient length is less than 2 N At this time, zero-padding can be performed to expand the filter coefficient length to 2. N Parallel extended processing will 2 N Each filter coefficient is expanded to 3 M Road coefficient.
[0012] In some exemplary embodiments, the sub-filter is implemented using a single-rate FIR filter structure or by calling an IP core provided by a software development tool.
[0013] In some exemplary embodiments, the parallel combination specifically refers to: When M=1, the parallel combination inputs 3 data channels and outputs 2 data channels, namely the odd sequence and even sequence output by the filter; when M=2, the parallel combination is processed in 2 stages: the first stage inputs 9 data channels and outputs 6 data channels, and the second stage inputs 6 data channels and outputs 4 data channels; when M=3, the parallel combination is processed in 3 stages: the first stage inputs 27 data channels and outputs 18 data channels, the second stage inputs 18 data channels and outputs 12 data channels, and the third stage inputs 12 data channels and outputs 8 data channels; and so on, for 3... M The output data of the path filter is processed in parallel, divided into M stages. The number of data paths is reduced to 2 / 3 in each stage, resulting in a final output of 2. M Multiphase data.
[0014] According to a second aspect of the present invention, a storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the coefficient-extended digital polyphase filter design method described in the first aspect above.
[0015] According to a third aspect of the present invention, a computer program product is provided, on which a computer program is stored, wherein when the computer program is executed by a processor, it implements the coefficient-extended digital polyphase filter design method described in the first aspect above.
[0016] According to a fourth aspect of the present invention, an electronic device is provided, comprising: Processor; and Memory for storing the executable instructions of the processor; The processor is configured to implement the coefficient-extended digital polyphase filter design method described in the first aspect above by executing the executable instructions.
[0017] The digital polyphase filter design method based on coefficient expansion provided in the embodiments of the present invention expands one source of original data and its corresponding filter coefficients in parallel to three sources through iterative processes. M The sampling rate was reduced to 2% of the original rate for each branch. M Each filter coefficient is 2 N-M From another perspective, this method uses 3 M The length of each coefficient is 2. N-M The sampling rate is 2 M One-third of the sub-filters implements a coefficient length of 2 N The filtering process reduces the number of multiplication operations required for filtering to 3 / 4 of the original amount per unit time.M times.
[0018] This invention relates to software design for FPGA processing, and its concepts can also be extended to ASIC design. The main design idea is to reuse the common parts of multiphase filter branches, thereby saving computational resources. The more multiphase branches there are, the more common parts are reused, and the more significant the computational savings become. In extreme cases, the length of the multiphase branch sub-filter is only 1 (containing only one coefficient), minimizing multiplier resources. The method presented in this invention uses time-domain processing and can perform frequency-domain processing on the segmented sub-filters, further reducing hardware resources, and the processing latency is close to that of conventional time-domain processing methods. Furthermore, the circuit designed using this method can operate at higher frequencies.
[0019] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description
[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0021] Figure 1 is a flowchart of the method of the present invention; Figure 2 shows the filter structure; Figure 3 shows the two-way parallel decomposition FIR structure; Figure 4 shows the parallel expansion when M=1; Figure 5 shows the parallel expansion when M=2; Figure 6 shows the parallel expansion when M=3; Figure 7 shows the block diagram of the parallel expansion implementation when M=2; Figure 8 shows the structure of a single-rate FIR filter; Figure 9 shows the parallel combination when M=1; Figure 10 shows the parallel combination when M=2; Figure 11 shows the parallel combination when M=3. Detailed Implementation
[0022] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the invention will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
[0023] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0024] To address the shortcomings and deficiencies of existing technologies, this example embodiment provides a digital polyphase filter design method based on coefficient expansion. The digital filter designed by this method mainly consists of parallel expansion of input data, sub-filter banks, and parallel data combination. When the input data is in a polyphase parallel form, the parallel expansion module of input data can be simplified.
[0025] refer to Figure 1 As shown, the specific steps may include: Step S1: Perform parallel expansion on the original input signal, expanding it into multiple parallel branches; Step S2: Design a sub-filter bank to filter multiple parallel branches; Step S3: Perform parallel combination of the sub-filter bank outputs to obtain the filter output.
[0026] Furthermore, the parallel expansion method is as follows. The polyphase filter has two parallel inputs. M When M=1, the input consists of two parallel data streams: an odd sequence and an even sequence of the original input data. Parallel expansion generates three data streams: an odd sequence, an even sequence, and an odd sequence plus an even sequence. Figure 3 As shown. When M=2, the input 4 parallel data streams are 1 / 4 sample sequences of the original data. Based on M=1, iterative processing is performed to generate 9 parallel data streams, as shown. Figure 4 As shown. When M=3, the input 8 parallel data streams are 1 / 8 sampled sequences of the original data. Based on M=2, iterative processing generates 27 parallel data streams, as shown below. Figure 5 As shown. Considering circuit operation speed during algorithm implementation, parallel expansion processing is simplified as follows. In 3... MThe maximum number of terms to add in each of the extended branches is 2. M It can be done through 2 M The calculation is performed using a tree-shaped adder. To improve the speed of the arithmetic circuit, a 2-channel input adder is used in the design. M The path-tree adder has a delay of M clock cycles. In 3 M In each extended branch, for terms with a sum less than 2 M The branch is delayed, making 3 M Each extended branch has an output delay of M clock cycles during parallel extended processing. When M=2, the block diagram for parallel extended implementation is as follows: Figure 6 As shown.
[0027] Furthermore, regarding 3 M The filter bank contains 3 extended branches for FIR filtering. M There are several sub-filters, all with identical structures, differing only in their coefficients. Sub-filters can be implemented using a conventional single-rate FIR filter structure or by utilizing IP cores provided by software development tools. The sub-filter coefficient calculation method is the same as the data expansion principle. This method requires a filter coefficient length of 2. N Where N is an integer not less than 1. When the coefficient length is less than 2... N At this time, zero-padding can be performed to expand the filter coefficient length to 2. N Parallel extended processing will 2 N Each filter coefficient is expanded to 3 M Each path filter coefficient has a length of 2. N-M , where N is an integer not less than M. When M=N, the sub-filter coefficient length is 1, and the number of multiplication operations required for the filter is minimized.
[0028] Furthermore, regarding 3 M The output data of the path filter are combined in parallel. The original input data is 2. M When multiple phases are processed in parallel, the parallel combined output is 2. M Parallel multiphase data processing. The parallel combination method is as follows. When M=1, the outputs of the 3 parallel filters are combined into 2 paths, which are the odd-numbered sequence and the even-numbered sequence of the filter outputs, respectively, as follows. Figure 7 As shown. Odd-numbered sequences are the output of sub-filter 1 plus the output of sub-filter 3 delayed by one clock cycle; even-numbered sequences are the output of sub-filter 2 minus the outputs of sub-filter 1 and sub-filter 3. When M=2, the 9 sub-filter outputs need to be combined in two stages. The first stage combines the 9 parallel data streams into 3 two-phase data streams, and the second stage combines the 3 two-phase data streams into 1 four-phase data stream. The parallel combination principle is the same as when M=1, as shown... Figure 8As shown. When M=3, the outputs of the 27 sub-filters need to be combined in three stages. The first stage combines the 27 data streams into 9 two-phase data streams; the second stage combines the 9 two-phase data streams into 3 four-phase data streams; and the third stage combines the 3 four-phase data streams into 1 eight-phase data stream. The parallel combination principle is the same as when M=1, as shown below. Figure 9 As shown.
[0029] When the filter input is 2 M In the case of multiphase paths, parallel extended processing can be simplified, and the computation of 3 M Each branch requires M and a delay. This circuit can operate under the same operating clock, thereby improving the operating speed.
[0030] When the input data is a single channel, it can be converted into a polyphase form through decimation. Then, by using this design method, the operating frequency of the sub-filter can also be higher than the input sampling frequency of the sub-filter.
[0031] 3 M When the outputs of the branch sub-filters are combined in parallel, M stages of processing are required. The number of output branches in each stage is two-thirds of the number of input branches, ultimately resulting in 2... M The filtering results in the multiphase form.
[0032] The filter designed by this method can be used not only for real number filtering operations, but also for complex number filtering operations after the multiplication and addition operation units are extended.
[0033] The steps in this exemplary embodiment will now be described in more detail with reference to the accompanying drawings and embodiments.
[0034] Figure 2 This is a filter structure, mainly composed of three parts: parallel expansion, sub-filter banks, and parallel combination. The parallel expansion part expands the original signal input to the polyphase filter into multiple parallel branches. The sub-filter banks filter these multiple parallel branches, and the parallel combination part combines the outputs of the sub-filter banks to obtain the filter output. (Polyphase filter output sequence) y (n) is the input sequence x (n) and the original filter coefficients h Convolution of (n).
[0035] The principle of parallel expansion is as follows: First, the original input sequence is... x Let (n) be divided into odd and even sequences, and represented by their Z-transforms as X0 and X1, respectively. Similarly, let the original filter coefficients h(n) be divided into odd and even sequences, and represented by their Z-transforms as H0 and H1, respectively. Let the original output sequence y(n) be divided into odd and even sequences, and represented by their Z-transforms as Y0 and Y1, respectively. It can be proven that the following relationship exists.
[0036] (1) (2) Rewrite (2) as follows: (3) Observation reveals that calculating the filter output using the combination of methods (1) and (2) requires calculating four filters, namely the combinations of X0 and X1 with H0 and H1, while calculating the filter output using the combination of methods (1) and (3) requires calculating three filters, namely the combinations of X0 and X1 with H0 and H1. Therefore, the original filter can be decomposed into two parallel paths as shown in Figure 3. Thus, the two-way parallel decomposition method in Figure 3 reduces the multiplication computation of the original filter to 3 / 4 of its original value. It follows that if the two-way parallel decomposition method is applied N times repeatedly, the multiplication computation of the original filter will be reduced to (3 / 4) of its original value. N Therefore, this invention combines a polyphase filter structure to provide a filter design method with low computational complexity.
[0037] Based on the idea of two-way parallel decomposition, the original filter is decomposed into three channels, resulting in a sampling rate that is reduced to half of the original sampling rate. Figure 4 As shown. At this time, the polyphase filter inputs two parallel data streams, which are the odd and even sequences of the original input data, respectively. The parallel expansion generates three data streams, which are the odd sequence, the even sequence, and the odd sequence plus the even sequence.
[0038] Based on the idea of two-way parallel decomposition, the original filter is decomposed into four channels, resulting in nine data channels with a sampling rate reduced to one-quarter of the original sampling rate. Figure 5 As shown. At this time, the polyphase filter inputs two parallel data streams, which are four data streams with a sampling rate of 1 / 4 of the original input data. The parallel expansion generates three data streams, which are iterations based on the three-stream expansion.
[0039] Similarly, by decomposing the original filter into 8 channels, 27 channels of data are obtained, with the sampling rate reduced to 1 / 8 of the original sampling rate. Figure 6 As shown. At this time, the 8 parallel data inputs of the polyphase filter are 8 data points with a sampling rate of 1 / 8 of the original input data, and the parallel expansion generates 27 data points, which are iterations based on the 9-channel expansion.
[0040] Therefore, the following conclusion is drawn: The original input data is either 1 channel data or 2... M Road sampling rate 1 / 2 M Multiphase data parallel expansion will result in 3M sampling 1 / 2 M The sampled data. This method requires a filter coefficient length of 2. N Where N is an integer not less than 1. When the coefficient length is less than 2...N At this time, zero-padding can be performed to expand the filter coefficient length to 2. N Parallel extended processing will 2 N Each filter coefficient is expanded to 3 M Path coefficient, number of sub-filters P=3 N-M The sub-filter coefficient length is 2 N-M , where M is an integer less than or equal to N. When M=N, the sub-filter coefficient length is 1, and the number of multiplication operations required by the filter is minimized.
[0041] The following describes a parallel expansion implementation using M=2 and a polyphase filter, as follows: Figure 7 As shown, the polyphase filter takes 4 parallel data inputs and outputs 9 parallel data outputs after parallel expansion processing.
[0042] In this invention, all sub-filters in the sub-filter bank have the same structure, differing only in their coefficients. The sub-filters can be implemented using a conventional single-rate FIR filter structure or by calling IP cores provided by software development tools. A conventional single-rate FIR filter structure is as follows: Figure 8 As shown. The calculation method for sub-filter coefficients is the same as the data expansion principle, as illustrated below. The original polyphase filter inputs 4 data streams, and the original filter coefficients total 16, namely: h(1), h(2), h(3), ..., h(16). Then each sub-filter has 4 coefficients, and the 9 sub-filter coefficients are shown in the table below.
[0043] Table 1 Sub-filter coefficients
[0044] The sub-filter outputs are then combined in parallel. In principle, the parallel combination process is the reverse of the parallel expansion process, but for ease of multiphase processing and to maintain the signal sampling rate, only channel combining is performed. When M=1, the parallel combination inputs three data channels and outputs two data channels, namely the odd-numbered sequence and the even-numbered sequence from the filter output, respectively. Figure 9 As shown. When M=2, the parallel combination is processed in two stages. The first stage of parallel combination takes 9 data inputs and outputs 6 data outputs. The second stage of parallel combination takes 6 data inputs and outputs 4 data outputs, as shown. Figure 10 As shown. When M=3, the parallel combination is processed in 3 stages. The first stage of parallel combination inputs 27 data channels and outputs 18 data channels. The second stage of parallel combination inputs 18 data channels and outputs 12 data channels. The third stage of parallel combination inputs 12 data channels and outputs 8 data channels, as shown. Figure 11 As shown.
[0045] Based on the above inferences, the following applies to 3. M The output data of the path filter is processed in parallel, divided into M stages. The number of data paths is reduced to 2 / 3 in each stage, and finally outputs 2.M Multiphase data.
[0046] In conclusion, this invention presents a polyphase filter design method. Based on the concept of channel expansion, this method saves on multiplication operations by multiplexing the common multiplication parts of sub-filters and exhibits low processing latency. When the input data is in polyphase form, all multipliers and adders in this method can operate at the same clock frequency, allowing the corresponding circuits to operate at higher frequencies, resulting in a high data throughput for the polyphase filter structure. When the input data is single-channel, it can be converted into a polyphase form through decimation, and then, using this design method, the operating frequency of the sub-filters can also be higher than the sub-filter input sampling frequency.
[0047] It should be noted that, as another aspect, this application also provides a storage medium, which may be included in an electronic device or may exist independently without being assembled into the electronic device. The storage medium carries one or more programs, which, when executed by an electronic device, cause the electronic device to perform the methods described in the following embodiments.
[0048] In one embodiment, this application provides a computer program product including a computer program that, when executed by a processor, implements the steps in the above-described method embodiments.
[0049] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.
[0050] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the claims.
[0051] It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the invention is defined only by the appended claims.
Claims
1. A method for designing a digital polyphase filter based on coefficient spreading, characterized by, The method comprises: parallelly extending an input original signal into a plurality of parallel branches; designing a sub-filter bank, the sub-filter bank filtering the plurality of parallel branches; parallelly combining sub-filter bank outputs to obtain filter outputs.
2. The method of claim 1, wherein, The parallel extension specifically is: The original input data is either 1 channel or 2. M Road sampling rate 1 / 2 M Multiphase data parallel expansion yields 3 M Road sampling 1 / 2 M The sampling data; The 2-way input adder, 2 M way tree adder delay is M clock cycles; in 3 M extended branches, the branch with the sum less than 2 M is delayed, so that the 3 M extended branches output a delay of M clock cycles during parallel expansion processing.
3. The method of claim 2, wherein, The number of sub-filters in the sub-filter bank P = 3 N-M The sub-filter coefficient length is 2 N-M The filter coefficient length is 2 N Wherein, N is an integer not less than 1, and M is an integer less than or equal to N.
4. The method of claim 3, wherein, all sub-filters have the same structure and different coefficients.
5. The method of claim 4, wherein, The method further comprises, when the coefficient length is less than 2 N , performing 0 padding to expand the filter coefficient length to 2 N ; and performing parallel extension processing to expand 2 N filter coefficients into 3 M filter coefficients.
6. The method of claim 5, wherein, The sub-filter implementation adopts a single-rate FIR filter structure or an IP core provided by a software development tool.
7. The method of claim 6, wherein, The parallel combination specifically is: When M=1, parallel combination input 3-way data, output 2-way data, respectively, odd and even sequences of filter output; when M=2, parallel combination is divided into 2-level processing, the first level parallel combination input 9-way data, output 6-way data, the second level parallel combination input 6-way data, output 4-way data; when M=3, parallel combination is divided into 3-level processing, the first level parallel combination input 27-way data, output 18-way data, the second level parallel combination input 18-way data, output 12-way data, the third level parallel combination input 12-way data, output 8-way data; and so on, parallel combination processing of 3 M way sub-filter output data is divided into M-level processing, and the data number of each level processing is reduced by 2 / 3, finally outputting 2 M way polyphase data.
8. A storage medium having stored thereon a computer program, characterized in that The computer program, when executed by a processor, implements the coefficient extension-based digital polyphase filter design method of any one of claims 1 to 7.
9. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the coefficient extension-based digital polyphase filter design method of any one of claims 1 to 7.
10. An electronic device, comprising: comprises: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the coefficient extension-based digital polyphase filter design method of any one of claims 1 to 7 via execution of the executable instructions.