Channel coding method and device

Abstract

The invention discloses a channel coding method and device, and the method comprises the steps that a transmitting device carries out the LDPC coding of an input bit sequence based on a first base graph which corresponds to a first initial transmission code rate and comprises a first core matrix, and obtains a coded bit sequence; wherein the first base graph is one of N base graphs, the N base graphs further comprise a second base graph, the second base graph comprises a second core array and corresponds to the second initial code transmission rate, and N is an integer larger than or equal to 2. The elements in the first base graph are zero elements and non-zero elements, and the elements in the second base graph are zero elements and non-zero elements. The row number of the first base graph is equal to that of the second base graph, and the column number of the first base graph is equal to that of the second base graph. The second initial code transmission rate is smaller than the first initial code transmission rate, and the line number of the second core array is larger than the line number of the first core array. The method can reduce the complexity of channel coding and channel decoding.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a channel coding method and apparatus. Background Technology

[0002] Channel coding is one of the core technologies in the field of wireless communication. To meet the channel coding requirements of communication systems such as 5G communication systems in three major application scenarios, low-density parity-check codes (LDPC) can be used to encode the input bit sequence.

[0003] Among them, LDPC codes can be raptor-like structures, which include a high-rate core matrix and an extended matrix. In scenarios where raptor-like LDPC codes are used for channel coding, how to reduce the complexity of channel coding and decoding remains to be studied. Summary of the Invention

[0004] This application provides a channel coding method and apparatus that can reduce the complexity of channel coding and channel decoding.

[0005] Firstly, embodiments of this application provide a channel coding method. This method can be applied to a transmitting device, such as a transmitting device or a communication module within the transmitting device, or a circuit or chip (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip) responsible for communication functions within the transmitting device. The transmitting device can be a terminal or a network device. Taking the application of this method to a transmitting device as an example, in this method, the transmitting device performs LDPC encoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the encoded bit sequence.

[0006] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0007] As can be seen, by using the above method, different initial transmission code rates do not need to share a core array. Moreover, the smaller the initial transmission code rate, the larger the number of rows in the core array. The base graphs to which different core arrays belong have the same number of rows and columns, which can make the proportion of non-zero elements in the core array with a smaller initial transmission code rate smaller. In other words, the core array with a smaller initial transmission code rate can have a larger sparsity, thereby reducing the sparsity of the base graph and thus reducing the complexity of channel coding and channel decoding.

[0008] In one optional implementation, the number of rows in the second core array is greater than the number of rows in the first core array, which can be replaced by the number of columns in the second core array being greater than the number of columns in the first core array. It is evident that the smaller the initial transmission code rate, the larger the number of columns in the core array, allowing the core array with a smaller initial transmission code rate to have greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0009] In another optional implementation, the number of rows in the second core array is greater than the number of rows in the first core array. This can be replaced by the following: the number of rows in the second core array is greater than the number of rows in the first core array, and the number of columns in the second core array is greater than the number of columns in the first core array. It is evident that the smaller the initial transmission code rate, the larger the number of rows and columns in the core array, allowing the core array with a smaller initial transmission code rate to have greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0010] In one optional implementation, the number of rows in the first core array is associated with a first initial transmission code rate R1, and the number of rows in the second core array is associated with a second initial transmission code rate R2, where R1 and R2 are both positive real numbers. In this approach, the number of rows in the core array is associated with the initial transmission code rate, which helps to ensure that the core array with a smaller initial transmission code rate has greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0011] The number of rows in the first core matrix is ​​related to R1, which can be understood as: there is a correlation between the number of rows in the first core matrix and R1, or the number of rows in the first core matrix is ​​determined based on R1. Similarly, the number of rows in the second core matrix is ​​related to R2, which can be understood as: there is a correlation between the number of rows in the second core matrix and R2, or the number of rows in the second core matrix is ​​determined based on R2.

[0012] In one optional implementation, the first core array has m rows. core1 It is also associated with at least one of the following: the number of columns k in A1 b The number of columns n of the punched columns in A1 prune1 The number of rows m of the second core matrix core2 It is also associated with at least one of the following: the number of columns k in A2 b The number of columns n of the punched columns in A2 prune2 m core1 m core2 k b n prune1 and n prune2 All are integers greater than or equal to 0.

[0013] Where, m core1 It is also associated with at least one of the following: k b n prune1 , can be understood as: m core1 Also with k b n prune1 There is a relationship between them, or it can be understood as: m core1 Also based on k b and n prune1 Confirmed. Similarly, m core2 It is also associated with at least one of the following: k b n prune2 , can be understood as: m core2 Also with k b n prune2 There is a relationship between them, or it can be understood as: m core2 Also based on k b and n prune2 Sure.

[0014] In one optional implementation, the perforated column in A1 can be understood as a perforated column of the first core array, or as a perforated column of the first base map; this application embodiment does not limit this. Similarly, the perforated column in A2 can be understood as a perforated column of the second core array, or as a perforated column of the second base map; this application embodiment does not limit this.

[0015] In one alternative implementation, m core1 satisfy: m core2 satisfy: in, This indicates rounding down. It can be seen that the smaller the initial transmission code rate, the larger the number of rows in the core array. This method allows a smaller initial transmission code rate to correspond to a core array with a larger number of rows, thus enabling the core array with a smaller initial transmission code rate to have greater sparsity, which reduces the complexity of channel coding and channel decoding.

[0016] In one optional implementation, the first core array has m rows. core1 The second core array has p*m rows. core1 Among them, A2's p*m core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched column, and its relationship with m in A1. core1 The non-zero elements in the row and column with punched holes are in the same position. In A1, the non-punched column contains p groups of non-zero elements, and in A2, the q-th m-th non-punched column... core1 The row contains the q-th non-zero element from the p-th non-zero elements, and A2 has p*m core1 The qth m in the row core1 The position of the q-th non-zero element included in the row, and the m of A1 core1 The non-zero elements in the q-th group included in the row are in the same position. Additionally, m... core1 Let p be a positive integer, p be an integer greater than or equal to 2, and q be an integer greater than or equal to 1 and less than or equal to p.

[0017] It is evident that the number of rows in the second core array can be obtained by expanding the number of rows in the first core array by a factor of p. Furthermore, the positions of the non-zero elements in the punched columns of the second core array are associated with the positions of the non-zero elements in the punched columns of the first core array, and the positions of the non-zero elements in the non-punched columns of the second core array are associated with the positions of the non-punched columns of the first core array. This method allows the transmitting device to store a high-bit-rate first core array and a low-bit-rate second core array based on the first core array, reducing the storage overhead of the storage matrix.

[0018] In one optional implementation, the first initial transmission code rate and the second initial transmission code rate belong to different code rate ranges. Therefore, when different initial transmission code rates belong to different code rate ranges, different initial transmission code rates correspond to core matrices with different numbers of rows. Compared with core matrices with different initial transmission code rates corresponding to different numbers of rows within the same code rate range, this method can reduce the storage overhead of the storage matrix.

[0019] Secondly, embodiments of this application also provide a channel decoding method, which can be applied to the receiving device side, such as the receiving device or the communication module in the receiving device, or the circuit or chip responsible for communication functions in the receiving device (such as a modem chip, also known as a baseband chip, or a SoC chip containing a modem core or a system-in-package (SIP) chip). The receiving device can be a network device or a terminal. Taking the application of this method to a receiving device as an example, in this method, the receiving device performs low-density parity-check (LDPC) decoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the decoded bit sequence.

[0020] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0021] As can be seen, by using the above method, different initial transmission code rates do not need to share a core array. Moreover, the smaller the initial transmission code rate, the larger the number of rows in the core array. The base graphs to which different core arrays belong have the same number of rows and columns, which can make the proportion of non-zero elements in the core array with a smaller initial transmission code rate smaller. In other words, the core array with a smaller initial transmission code rate can have a larger sparsity, thereby reducing the sparsity of the base graph and thus reducing the complexity of channel coding and channel decoding.

[0022] In one optional implementation, the number of rows in the second core array is greater than the number of rows in the first core array, which can be replaced by the number of columns in the second core array being greater than the number of columns in the first core array. It is evident that the smaller the initial transmission code rate, the larger the number of columns in the core array, allowing the core array with a smaller initial transmission code rate to have greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0023] In another optional implementation, the number of rows in the second core array is greater than the number of rows in the first core array. This can be replaced by the following: the number of rows in the second core array is greater than the number of rows in the first core array, and the number of columns in the second core array is greater than the number of columns in the first core array. It is evident that the smaller the initial transmission code rate, the larger the number of rows and columns in the core array, allowing the core array with a smaller initial transmission code rate to have greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0024] In one optional implementation, the number of rows in the first core array is associated with a first initial transmission code rate R1, and the number of rows in the second core array is associated with a second initial transmission code rate R2, where R1 and R2 are both positive real numbers. In this approach, the number of rows in the core array is associated with the initial transmission code rate, which helps to ensure that the core array with a smaller initial transmission code rate has greater sparsity, thereby reducing the complexity of channel coding and channel decoding.

[0025] The number of rows in the first core matrix is ​​related to R1, which can be understood as: there is a correlation between the number of rows in the first core matrix and R1, or the number of rows in the first core matrix is ​​determined based on R1. Similarly, the number of rows in the second core matrix is ​​related to R2, which can be understood as: there is a correlation between the number of rows in the second core matrix and R2, or the number of rows in the second core matrix is ​​determined based on R2.

[0026] In one optional implementation, the first core array has m rows. core1 It is also associated with at least one of the following: the number of columns k in A1 b The number of columns n of the punched columns in A1 prune1 The number of rows m of the second core matrix core2 It is also associated with at least one of the following: the number of columns k in A2 b The number of columns n of the punched columns in A2 prune2 m core1 m core2 k b n prune1 and n prune2 All are integers greater than or equal to 0.

[0027] Where, m core1 It is also associated with at least one of the following: k b n prune1 , can be understood as: m core1 Also with k b n prune1 There is a relationship between them, or it can be understood as: m core1 Also based on k b and n prune1 Confirmed. Similarly, m core2 It is also associated with at least one of the following: k b n prune2 , can be understood as: m core2 Also with k b n prune2 There is a relationship between them, or it can be understood as: m core2 Also based on k b and n prune2 Sure.

[0028] In one optional implementation, the perforated column in A1 can be understood as a perforated column of the first core array, or as a perforated column of the first base map; this application embodiment does not limit this. Similarly, the perforated column in A2 can be understood as a perforated column of the second core array, or as a perforated column of the second base map; this application embodiment does not limit this.

[0029] In one alternative implementation, m core1 satisfy: m core2 satisfy: in, This indicates rounding down. It can be seen that the smaller the initial transmission code rate, the larger the number of rows in the core array. This method allows a smaller initial transmission code rate to correspond to a core array with a larger number of rows, thus enabling the core array with a smaller initial transmission code rate to have greater sparsity, which reduces the complexity of channel coding and channel decoding.

[0030] In one optional implementation, the first core array has m rows. core1 The second core array has p*m rows. core1 Among them, A2's p*m core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched column, and its relationship with m in A1. core1 The non-zero elements in the row and column with punched holes are in the same position. In A1, the non-punched column contains p groups of non-zero elements, and in A2, the q-th m-th non-punched column... core1 The row contains the q-th non-zero element from the p-th non-zero elements, and A2 has p*m core1 The qth m in the row core1 The position of the q-th non-zero element included in the row, and the m of A1 core1 The non-zero elements in the q-th group included in the row are in the same position. Additionally, m... core1 Let p be a positive integer, p be an integer greater than or equal to 2, and q be an integer greater than or equal to 1 and less than or equal to p.

[0031] It is evident that the number of rows in the second core array can be obtained by expanding the number of rows in the first core array by a factor of p. Furthermore, the positions of the non-zero elements in the punched columns of the second core array are associated with the positions of the non-zero elements in the punched columns of the first core array, and the positions of the non-zero elements in the non-punched columns of the second core array are associated with the positions of the non-punched columns of the first core array. This method allows the receiving device to store the high-bit-rate first core array and obtain the low-bit-rate second core array based on the first core array, thus reducing the storage overhead of the storage matrix.

[0032] In one optional implementation, the first initial transmission code rate and the second initial transmission code rate belong to different code rate ranges. Therefore, when different initial transmission code rates belong to different code rate ranges, different initial transmission code rates correspond to core matrices with different numbers of rows. Compared with core matrices with different initial transmission code rates corresponding to different numbers of rows within the same code rate range, this method can reduce the storage overhead of the storage matrix.

[0033] Thirdly, embodiments of this application also provide a communication device that has the functions of the first aspect described above. For example, the communication device includes modules, units, or means corresponding to the operations involved in the first aspect. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0034] In one possible design, the communication device may include a processing unit and a communication unit. The processing unit is configured to support the communication device in performing the corresponding functions described in the above method. The communication unit is used to support communication between the communication device and other communication devices. The communication device may also include a storage unit coupled to the processing unit and the communication unit, which stores necessary program instructions and data for the communication device.

[0035] In one embodiment, the communication device includes: a processing unit and a communication unit, wherein the communication unit is used to send and receive signals / signaling.

[0036] The processing unit is used to perform LDPC encoding on the input bit sequence based on a first base map containing a first core array corresponding to the first initial transmission code rate, to obtain the encoded bit sequence.

[0037] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0038] In addition, other alternative implementations of the communication device in this regard can be found in the relevant content of the first aspect above, and will not be described in detail here.

[0039] As an example, the communication unit can be a transceiver or a communication interface, the storage unit can be a memory, and the processing unit can be a processor.

[0040] In one embodiment, the communication device includes: a processor and a transceiver, the transceiver being used for transmitting and receiving signals / signaling;

[0041] The processor is configured to perform LDPC encoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the encoded bit sequence.

[0042] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0043] In addition, other alternative implementations of the communication device in this regard can be found in the relevant content of the first aspect above, and will not be described in detail here.

[0044] Fourthly, embodiments of this application also provide a communication device that has the functions of the second aspect described above. For example, the communication device includes modules, units, or means corresponding to the operations involved in the second aspect described above. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0045] In one possible design, the communication device may include a processing unit and a communication unit. The processing unit is configured to support the communication device in performing the corresponding functions described in the above method. The communication unit is used to support communication between the communication device and other communication devices. The communication device may also include a storage unit coupled to the processing unit and the communication unit, which stores necessary program instructions and data for the communication device.

[0046] In one embodiment, the communication device includes: a processing unit and a communication unit, wherein the communication unit is used to send and receive signals / signaling.

[0047] The processing unit is used to perform LDPC decoding on the input bit sequence based on a first base map containing a first core array corresponding to the first initial transmission code rate, to obtain the decoded bit sequence.

[0048] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0049] In addition, other alternative implementations of the communication device in this regard can be found in the relevant content of the second aspect above, and will not be described in detail here.

[0050] As an example, the communication unit can be a transceiver or a communication interface, the storage unit can be a memory, and the processing unit can be a processor.

[0051] In one embodiment, the communication device includes: a processor and a transceiver, the transceiver being used for transmitting and receiving signals / signaling;

[0052] The processor is configured to perform LDPC decoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the decoded bit sequence.

[0053] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0054] In addition, other alternative implementations of the communication device in this regard can be found in the relevant content of the second aspect above, and will not be described in detail here.

[0055] In another embodiment, the communication device of the third and fourth aspects is a chip or chip system. The processing unit may also be a processing circuit or logic circuit; the communication unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip or chip system.

[0056] In implementation, the processor can be used for, but is not limited to, baseband-related processing, and the transceiver can be used for, but is not limited to, radio frequency transceiver. These devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, the processor can be further divided into analog baseband processors and digital baseband processors. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (e.g., but not limited to graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a System-on-a-Chip (SoC). Whether the devices are disposed independently on different chips or integrated on one or more chips often depends on the needs of the product design. This application does not limit the implementation form of the above-mentioned devices.

[0057] Fifthly, embodiments of this application also provide a communication device, which includes an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions described in the first aspect. The one or more processors can execute the computer program or instructions, and when the computer program or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first aspect. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0058] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0059] In one possible design, the communication device may also include the memory.

[0060] The aforementioned communication device may be a transmitting device, or a communication module in a transmitting device, or a chip in a transmitting device that is responsible for communication functions, such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module.

[0061] Sixthly, embodiments of this application also provide a communication device, which includes an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the computer program or instructions necessary to implement the functions described in the second aspect above. The one or more processors can execute the computer program or instructions, and when the computer program or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the second aspect above. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0062] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0063] In one possible design, the communication device may also include the memory.

[0064] The aforementioned communication device may be a receiving device, or a communication module in a receiving device, or a chip in a receiving device that is responsible for communication functions, such as a modem chip (also known as a baseband chip) or a SoC or SIP chip containing a modem module.

[0065] In a seventh aspect, embodiments of this application also provide a communication system, which includes a transmitting device for performing the method described in any of the first aspects and a receiving device for performing the method described in any of the second aspects. In another possible design, the system may further include other devices / functional network elements that interact with at least one of the transmitting and receiving devices.

[0066] Eighthly, embodiments of this application provide a computer-readable storage medium for storing instructions that, when executed by a computer, implement the method described in either the first or second aspect.

[0067] Ninthly, embodiments of this application also provide a computer program product including instructions that, when run on a computer, implement the method described in either the first or second aspect.

[0068] In a tenth aspect, embodiments of this application provide a chip system including a processor and an interface. The interface is used to acquire programs or instructions, and the processor is used to invoke the programs or instructions to implement or support a transmitting device in implementing the first aspect, or to implement or support a receiving device in implementing the functions involved in the second aspect. For example, determining or processing at least one of the data and information involved in the above methods. In one possible design, the chip system further includes a memory for storing necessary program instructions and data. The chip system may be composed of chips or may include chips and other discrete devices.

[0069] Eleventhly, embodiments of this application provide a communication device including a processor for executing a computer program or executable instructions stored in a memory, wherein when the computer program or executable instructions are executed, the device performs the methods as described in the first aspect or the second aspect and any possible implementation thereof.

[0070] In one possible implementation, the processor and memory are integrated together;

[0071] In another possible implementation, the aforementioned memory is located outside the communication device.

[0072] The beneficial effects of aspects three through eleven can be referenced from the beneficial effects of aspects one or two, and will not be elaborated here. Attached Figure Description

[0073] Figure 1 This is a schematic diagram of a system architecture provided in an embodiment of this application;

[0074] Figure 2 This is a schematic diagram of a Tanner diagram provided in an embodiment of this application;

[0075] Figure 3 and Figure 9 These are schematic diagrams of the base map of the LDPC code provided in the embodiments of this application;

[0076] Figure 4 , Figure 10a and Figure 10b These are schematic diagrams of the base matrix provided in the embodiments of this application;

[0077] Figure 5 This is a schematic diagram of the matrix corresponding to each element in a basis matrix provided in an embodiment of this application;

[0078] Figure 6 , Figures 24 to 27 These are schematic diagrams of the base map provided in the embodiments of this application;

[0079] Figure 7This is a schematic diagram of a submatrix B provided in an embodiment of this application;

[0080] Figure 8 and Figure 15 These are schematic diagrams illustrating the base map selection strategy provided in the embodiments of this application;

[0081] Figure 11 and Figure 12 These are schematic diagrams of base maps at 1 / 3 bit rate and 1 / 2 bit rate provided in the embodiments of this application;

[0082] Figure 13 This is a schematic flowchart of a channel coding method provided in an embodiment of this application;

[0083] Figure 14 This is a schematic diagram illustrating the relationship between the initial transmission rate and the number of rows in the core array, provided in an embodiment of this application.

[0084] Figure 16 , Figure 18 , Figure 19 , Figure 21 and Figure 22 These are schematic diagrams of the core array provided in the embodiments of this application;

[0085] Figure 17 , Figure 20 and Figure 23 These are weight comparison diagrams provided in the embodiments of this application;

[0086] Figure 28 This is a schematic flowchart of a channel decoding method provided in an embodiment of this application;

[0087] Figure 29 and Figure 30 These are schematic diagrams of the base map selection process and the base map reading process provided in the embodiments of this application;

[0088] Figure 31 This is a schematic diagram of a communication system provided in an embodiment of this application;

[0089] Figure 32 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0090] Figure 33 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. Detailed Implementation

[0091] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0092] Figure 1 This is a schematic diagram illustrating one possible, non-limiting system architecture. For example... Figure 1As shown, the communication system 10 includes a radio access network (RAN) 100 and a core network (CN) 200. RAN 100 includes at least one RAN node (e.g., ...). Figure 1 110a and 110b (collectively referred to as 110) and at least one terminal (such as Figure 1 RAN 100, denoted as RAN 120a-120j, is collectively referred to as RAN 120. RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 1 (Not shown in the image). Terminal 120 is connected to RAN node 110 wirelessly. RAN node 110 is connected to core network 200 wirelessly or via wired connection. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0093] RAN100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as a 5th generation (5G) mobile communication system, or a future-oriented evolution system. RAN100 can also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a wireless fidelity (WiFi) system. RAN100 can also be a communication system that integrates two or more of the above systems.

[0094] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. Multiple RAN nodes 110 in communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative, for example... Figure 1 Network element 120i can be a helicopter or a drone, and it can be configured as a mobile base station. For terminals 120j that access RAN 100 through network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes referred to as communication devices, for example... Figure 1 Network elements 110a and 110b can be understood as communication devices with base station functions, while network elements 120a-120j can be understood as communication devices with terminal functions.

[0095] In one possible scenario, a RAN node can be a base station (BS), an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a WiFi system, etc. A RAN node can also be a macro base station (such as...) Figure 1 110a), micro base stations or indoor stations (such as Figure 1 The RAN node can be a relay node or donor node (as described in section 110b), or a wireless controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions and corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software capable of implementing all or part of the RAN node functions.

[0096] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with different RAN nodes each implementing a portion of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be set up separately or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs).

[0097] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules.

[0098] In this application embodiment, the RAN node can also be described in different ways, such as a network device. Unless otherwise specified, the term "network device" will be used throughout this application.

[0099] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), V2X communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. A terminal typically contains a communication module, circuit, or chip that performs the corresponding communication functions. The terminal can also be configured with program instructions for performing the corresponding communication functions.

[0100] The embodiments of this application can be applied to various mobile communication scenarios, including but not limited to point-to-point single-connection communication scenarios, multi-hop single-connection communication scenarios, dual connectivity (DC) communication scenarios, and multi-hop connection communication scenarios. It should be noted that the exemplary communication scenarios of this application do not limit the network architecture applicable to this application; any network-side device in a cellular network that powers other devices is a usable network architecture for this application. Application scenarios of this application include, but are not limited to, scenarios where one or more network-side devices power one or more devices, such as network devices powering terminal devices, network devices powering network devices, network devices powering relays, relay base stations powering terminal devices, multiple network devices powering one terminal device, or multiple network devices powering multiple terminal devices.

[0101] In this embodiment, the transmitting device can be a terminal device, and the receiving device can be a network device. Optionally, the transmitting device can be a network device, and the receiving device can be a terminal device. Optionally, both the transmitting device and the receiving device can be terminal devices. Optionally, both the transmitting device and the receiving device can be network devices. Optionally, the transmitting device and the receiving device can also be processors, modules, chips, chip systems, or software modules that support the implementation of the corresponding methods. This embodiment does not limit the specific form of the transmitting device and the receiving device.

[0102] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes network device functions. This control subsystem, including network device functions, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. Similarly, the functions of the terminal device can be executed by modules (such as chips or modems) within the terminal device, or by a device that includes terminal device functions.

[0103] The embodiments disclosed in this application will be presented to illustrate various aspects, embodiments, or features of this application in relation to systems including multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches may also be used.

[0104] To facilitate understanding of the solutions in the embodiments of this application, the terms that may be involved in the embodiments of this application are explained below.

[0105] 1. Low-density parity-check code (LDPC) code, parity check matrix H, base graph.

[0106] LDPC codes are linear block codes whose parity check matrix exhibits sparse properties, with the proportion of 1s in the matrix being extremely small; hence, they are also known as low-density parity check codes. For an LDPC code with K information bits and N code length, the dimension of its parity check matrix H is (NK) × N, and the codeword c of the corresponding LDPC code can be defined by the parity check matrix H as follows:

[0107] c = {c|Hc} T =0, c∈{0,1} N} (1)

[0108] In the parity check matrix H, each row corresponds to a parity check equation of the LDPC code, and the NK parity check equations correspond to the NK parity check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and the N symbols correspond to the N variable nodes of the LDPC code. Here, K and N are both positive integers. The non-zero elements h in the parity check matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. The number of non-zero elements in each row of the check matrix represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, all variable nodes also have the same degree, and the LDPC code corresponding to this matrix is ​​a regular code; otherwise, it is an irregular code.

[0109] For example, a parity-check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is shown below:

[0110]

[0111] Where V0, V1, ..., V9 represent variable nodes, and C0, C1, ..., C4 represent check nodes.

[0112] Furthermore, LDPC codes can be represented using graphical models, including Tanner graphs, factor graphs, and tree graphs, among which Tanner graphs offer a concise and intuitive description. For example, Figure 2 This is a schematic diagram of a Tanner chart. Specifically, Figure 2 This is a schematic diagram of the Tanner plot of the verification matrix H shown in formula (2) above. Figure 2 As shown, Figure 2 The connecting lines in the parity check matrix H represent the connection relationship between the check nodes and the variable nodes. For example, the check node C0 and the variable node V in the parity check matrix H... . If V1, V2, and V6 are connected, then Figure 2 The verification node C0 is connected to the variable nodes V0, V1, V2 and V6.

[0113] Furthermore, the parity check matrix H of the LDPC code can be obtained through the base graph (BG) and shift values. The base graph typically includes m*n matrix elements (entries), represented as an m x n matrix. Matrix elements are either 0 or 1, where elements representing 0 (sometimes called zero elements) indicate that the element can be replaced by a Z*Z zero matrix, and elements representing 1 (sometimes called non-zero elements) indicate that the element can be replaced by a Z*Z circulant permutation matrix. In other words, each matrix element in the base graph represents either a zero matrix or a circulant permutation matrix. For example, Figure 3 This is a schematic diagram of the base diagram of an LDPC code. Specifically, Figure 3 The diagram shows an exemplary base diagram of an LDPC code with a quasi-cyslic (QC) structure, where m=4 and n=26. It should be noted that in this application, the row and column numbers of the base diagram and matrix start from 0, merely for ease of explanation. For example, column 0 represents the first column of the base diagram and matrix, column 1 represents the second column, row 0 represents the first row, row 1 represents the second row, and so on.

[0114] Understandably, row and column numbers can also start from 1. In this case, the corresponding row and column numbers are based on the row and column numbers shown in the application plus 1. For example, if the row or column numbers start from 1, then the first column represents the first column of the base map and matrix, the second column represents the second column of the base map and matrix, the first row represents the first row of the base map and matrix, the second row represents the second row of the base map and matrix, and so on.

[0115] If the element in the i-th row and j-th column of the base graph is a non-zero element, its offset value is P. i,j P i,j If the integer is greater than or equal to 0, it means that the non-zero element in the i-th row and j-th column can be P. i,j The corresponding Z*Z cyclic permutation matrix replacement, which can be obtained by performing a P-transformation on the Z*Z identity matrix. i,jThe parity check matrix is ​​obtained by cyclically shifting the matrix to the right or left. It can be seen that by replacing each zero element in the base graph with a Z*Z matrix of all zeros, and replacing each non-zero element with a Z*Z cyclic permutation matrix corresponding to its offset value, the parity check matrix of the LDPC code can be obtained. Z is a positive integer, also known as the lifting factor, sometimes referred to as the lifting size, or lifting factor, etc. Z can be determined based on the code block size supported by the system and / or the size of the information data. Therefore, the size of the parity check matrix H is (m*Z)*(n*Z).

[0116] P i,j It can be obtained based on the expansion factor Z. For non-zero elements at the same position, different expansion factors Z may result in different P values. i,j To simplify implementation, the system typically defines an m x n base matrix. Each element in the base matrix corresponds one-to-one with the position of each element in the base graph. Zero elements in the base graph remain in the base matrix and can be represented by -1 or the null value. The non-zero element in the i-th row and j-th column of the base graph remains in the base matrix and can be represented as V. i,j , where P i,j =V i,j mod Z (A mod B means A modulo B). In embodiments of this application, the basis matrix can sometimes be referred to as the offset matrix of the basis graph. For example, Figure 4 This is a schematic diagram of a basis matrix. Figure 4 The basis matrix shown is Figure 3 The base graph shown corresponds to a basis matrix.

[0117] For example, Figure 5 This is a schematic diagram of the matrix corresponding to each element in a basis matrix. Specifically, Figure 5 When the expansion factor Z = 4, the p of the non-zero elements in the base graph i,j The corresponding matrix diagram. For example... Figure 5 As shown, when Z=4, each zero element represented as -1 is replaced by a 4x4 matrix A consisting entirely of zeros. If P 2,3 =2, then the non-zero element in the 2nd row and 3rd column is... Figure 5 Replace the 4x4 cyclic permutation matrix D in the middle, which is composed of Figure 5 The 4x4 identity matrix B is obtained by two right circular shifts. If P 2,4If the value is 0, then the non-zero element in the 2nd row and 4th column is replaced by the identity matrix B. And so on. It should be noted that this is merely an example and not a limitation. Typically, the basis graph or basis matrix of an LDPC code may also include p columns of built-in puncture bits, where p can be an integer from 0 to 2. These columns participate in encoding, but the corresponding systematic bits are not transmitted. Then the code rate of the LDPC code basis matrix satisfies... Based on the above base map Figure 3 For example, if there are two columns of built-in punched bits, the code rate of the base matrix is ​​(26-4) / (26-2) = 11 / 12, which is approximately 0.92.

[0118] The LDPC code used in wireless communication systems is the QC-LDPC code. Its parity bit portion has a double-diagonal structure or a raptor-like structure, which simplifies encoding and supports incremental redundancy hybrid retransmission. QC-LDPC code decoders typically use a QC-LDPC shift network (QSN), a Banyan network, or a Benes network to implement cyclic shifting of information.

[0119] QC-LDPC codes with a raptor-like structure have a base map matrix of size m rows and n columns, which can include 5 submatrices A, B, C, D and I. The weight of the matrix is ​​determined by the number of non-zero elements. The row weight (row weight) refers to the number of non-zero elements in a row, and the column weight (column weight) refers to the number of non-zero elements in a column. Figure 6 This is a schematic diagram of a base diagram structure. For example... Figure 6 As shown, where:

[0120] Submatrix A is m A line n A A matrix of columns, the size of which can be m A ×n A Each column corresponds to Z systematic bits in the LDPC code, which are sometimes also called information bits.

[0121] Submatrix B is m A line m A A square matrix of columns, the size of which can be m A ×m A Each column corresponds to Z parity bits in the LDPC code. Submatrix B consists of a double-diagonal submatrix B′ and a column with a weight of 3 (referred to as a 3-column multiplication column), where the 3-column multiplication column can precede submatrix B′; submatrix B may also include one or more columns with a weight of 1 (referred to as single-column multiplication columns), for example, Figure 7 This is a schematic diagram of a submatrix B. For example...Figure 7 As shown in 7a, the matrix column with a column weight of 3 is placed before the submatrix B′. Additionally, submatrix B may include a matrix column with a column weight of 1, which can be implemented as follows... Figure 7 As shown in 7b or 7c.

[0122] The matrix generated based on submatrix A and submatrix B is usually called the core matrix, which can be used to support high bit rate encoding. Submatrix A is the information bit part of the core matrix, and submatrix B is the parity bit part of the core matrix.

[0123] Submatrix C is a matrix of all zeros and its size is m. A ×m D .

[0124] Submatrix I is the identity matrix with size m. D ×m D And it is the extended check bit portion.

[0125] The size of the submatrix D is m D ×(n A +m A )m D It is typically used to generate low-rate check bits, which are part of the extended information bits.

[0126] It can be seen that [AB] corresponds to the core matrix H in the LDPC code. core [DI] corresponds to the extended matrix H in the LDPC code. ext .

[0127] It is understandable that the above description of the base graph from a mathematical definition perspective, since C is an all-zero matrix and I is the identity matrix, can, in one possible implementation, be simplified to a matrix composed of submatrices A and B, or a matrix composed of submatrices A, B, and D, to represent the base graph of the encoding or decoding matrix. Since the structures of submatrices C and I are relatively fixed, the structures of submatrices A, B, and D are one of the factors affecting the encoding and decoding performance of LDPC codes.

[0128] Furthermore, the base map may include, for example, two types: BG1 and BG2, but this application does not limit the type of base map. Specifically, BG1 has a size of 46×68, and the core array H in BG1... core The size of BG2 is 4×26, and it supports a minimum bitrate of 1 / 3, mainly used in scenarios with high throughput requirements, high bitrate, and long code length. The size of BG2 is 42×52, and the core array H in BG2... core The size is 4×14, mainly used in scenarios with low throughput requirements, low bit rate, and short bit length.

[0129] The transmitting device selects between BG1 and BG2 for channel coding based on the transfer block size (TBS) and the target code rate. See also... Figure 8 , Figure 8 This is a schematic diagram illustrating a basemap selection strategy. For example... Figure 8 As shown, if A≤292, or A≤3824 and R≤0.67, or R≤0.25, BG2 is selected for channel coding; otherwise, BG1 is selected. Here, A is the transport block size, excluding CRC check bits, and R is the target code rate obtained from the modulation and coding scheme (MCS) table during initial transmission.

[0130] 2. LDPC encoding.

[0131] LDPC coding refers to channel coding of an input bit sequence using LDPC codes to obtain the encoded bit sequence. When using a raptor-like LDPC matrix for coding, one possible implementation is to first encode the submatrices A and B (the core matrix) to obtain the parity bits corresponding to submatrix B, and then encode the entire matrix to obtain the parity bits corresponding to submatrix I. Since submatrix B can include a double-diagonal submatrix B′ and a single-column submatrix, the parity bits corresponding to the double-diagonal submatrix can be obtained first during coding, followed by the parity bits corresponding to the single-column submatrix.

[0132] The following is an example of an encoding method. Assume that the core matrix formed by submatrices A and B is H. core H core Removing the last row and last column from the matrix (that is, removing duplicate single columns and rows containing non-zero elements in a given column), the resulting matrix is ​​H. core-dual H core-dual The check digit portion is represented as H. e =[H e1 H e2 ],H e1 For a 3-column stack, H e2 It has a double diagonal structure. According to the definition of the LDPC code matrix, H... core-dual ·[SP e ] T =0, where S is the input sequence, represented by a vector of information bits, and P e The vector consisting of check bits, [SP e ] T This represents the input sequences S and P. e The matrix transpose is formed. Therefore, we can first determine the input sequence S and H.core-dual Calculate H core-dual The corresponding check bits are given in the input sequence S, which includes all information bits; then, based on the obtained H... core-dual The corresponding parity bits and the input sequence S are used to calculate the parity bits corresponding to the single column and the column in submatrix B. At this time, all the parity bits corresponding to submatrix B can be obtained. Then, based on the input sequence S and the parity bits corresponding to submatrix B, the parity bits corresponding to submatrix I are obtained by partially encoding submatrix D. Thus, all the information bits and all the parity bits are obtained. These bits constitute the encoded sequence, which is an LDPC code sequence.

[0133] Optionally, LDPC encoding may also include shortening and puncturing operations. Neither the shortened nor the punctured bits are transmitted.

[0134] Truncation typically starts from the last bit of the information bits and moves forward, and can be done in different ways. For example, to truncate s0 bits, the last s0 bits of the input sequence S can be set to known bits to obtain the input sequence S′, such as 0, null, or other values. Then, the input sequence S′ is encoded using an LDPC matrix. Alternatively, the last (s0 mod Z) bits of the input sequence S can be set to known bits to obtain the input sequence S′, such as 0, null, or other values. The last s0 bits of the submatrix A can then be truncated. Column deletion yields the LDPC matrix H′, which is then used to encode the input sequence S′, or the last column in submatrix A. The column is not involved in encoding the input sequence S′. After encoding is complete, the truncated bits are not sent.

[0135] Punching can be done by punching built-in punch bits in the input sequence or by punching parity bits. When punching parity bits, it's usually done from the last bit, but it can also be done according to a system-preset punching order. One possible implementation is to first encode the input sequence, and then, based on the required number of punched bits p, select the last p bits of the parity bits or select p bits according to the system-preset punching order; these p bits are not sent. Another possible implementation is to determine the p columns of the matrix corresponding to the punched bits and the p rows containing the non-zero elements in these columns; these rows and columns do not participate in encoding and therefore do not generate corresponding parity bits.

[0136] It should be noted that the encoding methods described here are merely examples. Based on the base graph and / or base matrix provided in this application, other encoding methods known to those skilled in the art can also be used, and this application is not limited to these methods. The decoding involved in this application can employ various decoding methods, such as minimum-sum (MS) decoding or belief propagation (BP) decoding. For example, the input sequence is initialized and iteratively processed. After each iteration, a hard-decision check is performed, and the hard-decision result is verified. If the decoding result conforms to the verification equation, the decoding is successful, the iteration terminates, and the decision result is output. If it does not conform to the verification equation, the iteration process is repeated within the maximum number of iterations. If the verification still fails after reaching the maximum number of iterations, the decoding fails. It is understood that those skilled in the art can understand the principle of MS decoding, which will not be detailed here.

[0137] It should be noted that the decoding method is only an example. Other decoding methods known to those skilled in the art can also be used based on the base map and / or base matrix provided in this application. This application does not limit the decoding method.

[0138] LDPC codes are typically derived based on the design of a basis graph and / or basis matrix. For example, optimizing the positions of zero and non-zero elements in the basis graph or basis matrix can determine the upper limit of the LDPC code's performance, and the error level of the LDPC code can be determined based on the offset values ​​in the basis matrix. Improving encoding and decoding performance and reducing the error level are among the goals of determining the basis graph and basis matrix. By designing the basis graph and / or basis matrix, encoding or decoding performance can be improved, and the error level can be reduced. Code lengths in wireless communication systems are flexible and varied, for example, they can be 2560 bits, 38400 bits, etc. Figure 9 This is a schematic diagram of the base graph of an LDPC code. Figure 10a and Figure 10b They are respectively Figure 9 Examples of two basis matrices for the shown basis graph. Figure 10a The set of values ​​for the expansion factor Z corresponding to PCM0 is {2, 4, 8, 16, 32, 64, 128, 256}. Figure 10b The set of values ​​for the expansion factor Z corresponding to PCM1 is {3, 6, 12, 24, 48, 96, 192, 384}. Figure 10a The maximum value of the offset Z corresponding to PCM0 shown is 256. Figure 10b The maximum value of the offset Z corresponding to PCM1 shown is 384. Therefore, Figure 10a and Figure 10b The same base map shown (base) Figure 1 Different base matrices correspond to different maximum values ​​of offset Z, which can meet the performance requirements of different code lengths.

[0139] For ease of explanation and understanding, the attached diagram is shown. Figure 9 as well as Figure 10a and Figure 10b The column number and row number are displayed at the top and leftmost positions, respectively. For example... Figure 9 As shown, Figure 9 The top row (0 to 67) represents the column number, and the leftmost column (0 to 45) represents the row number. In other words, Figure 9 The base diagram shown has a matrix size of 46 rows and 68 columns. Furthermore, for the PCM of BG1, since submatrix C and submatrix I are identical, therefore... Figure 10a and Figure 10b Submatrix C and submatrix I have been omitted.

[0140] In the base graph of a raptor-like LDPC structure, different initial code rates correspond to the same high-rate core matrix, and the expansion matrices for different initial code rates are all obtained by expanding the same core matrix. This results in lower sparsity of the base graph at medium and low code rates, leading to greater complexity in channel coding and decoding. For example, Figure 11 and Figure 12 The diagrams show BG1 at 1 / 3 bitrate and 1 / 2 bitrate, respectively. Figure 11 and Figure 12 In the diagram, bolded positions indicate non-zero elements at corresponding positions in the matrix, while unbolded positions indicate zero elements at corresponding positions. Subsequent base diagrams in this application will also be represented in this manner. For example... Figure 11 and Figure 12 As shown, at 1 / 3 and 1 / 2 code rates, the submatrices A, B, and D in BG1 are relatively dense (or have low sparsity), resulting in a larger weight in the base graph. Consequently, more nodes need to be computed for encoding and decoding, leading to higher encoding and decoding complexity.

[0141] The scheme provided in this application can be applied to channel coding / decoding between communication devices. Channel coding / decoding between communication devices can include: channel coding / decoding between network devices and terminal devices, channel coding / decoding between network devices, and channel coding / decoding between terminal devices. Here, "channel coding / decoding" can also be simply referred to as "coding," and "coding" can also be described as "channel coding / decoding," "network coding," "external code," or "source-channel joint coding / decoding." "Coding structure" can also be simply referred to as "coding," "code type," or "code design," and can also be described as "concatenated code," "layered code," "coupled code," "external code," "sliding window code," "product code," or "ladder code."

[0142] In this application, "sending information" can be understood as one device sending information to another device, or it can also be understood as one logic module within a device sending information to another logic module. For example, "sending information by a sending device" can be understood as a sending device sending information to another device (such as a receiving device), or it can be understood as logic module 1 in the sending device sending information to logic module 2 in the sending device.

[0143] In this application, "receiving information" can be understood as one device receiving information from another device, or it can also be understood as a logic module within a device receiving information from another logic module. For example, "receiving device receiving information" can be understood as the receiving device receiving information from another device (such as a transmitting device), or it can be understood as logic module 1 in the receiving device receiving information from logic module 2 in the receiving device.

[0144] In this application, phrases such as "sending information to... (e.g., a receiving device)" or related illustrations in the accompanying drawings can be understood as the destination of the information being the receiving device. This can include sending information directly or indirectly to the receiving device. Similarly, phrases such as "receiving information from... (e.g., a transmitting device)," "receiving information from... (e.g., a transmitting device)," or "receiving information sent (e.g., by a transmitting device)," or related illustrations in the accompanying drawings, can be understood as the source of the information being the transmitting device. This can include receiving information directly or indirectly from the transmitting device. Information may undergo necessary processing between the source and destination, such as format changes, but the destination can understand the valid information from the source. Similar expressions in this application can be interpreted similarly and will not be elaborated further here.

[0145] The channel coding method, channel decoding method, and apparatus are further described below with reference to the accompanying drawings. It is understood that this application uses a transmitting device and a receiving device as examples to illustrate the interaction, but this application does not limit the execution entities of the interaction. For example, the method executed by the transmitting device in this application can also be implemented by a module in the transmitting device, or a logic node, logic module, or software that can implement all or part of the coding device functions; similarly, the method executed by the receiving device in this application can also be implemented by a module in the receiving device, or a logic node, logic module, or software that can implement all or part of the decoding device functions. Modules in the transmitting and / or receiving devices can be, for example, circuits, chips, or chip systems (such as modem chips, also known as baseband chips, or system-on-a-chip (SOC) chips or SIP chips containing modem cores). The transmitting device can be a terminal or network device, and the receiving device can be a network device or a terminal.

[0146] This application proposes a channel coding method. Figure 13This is a flowchart illustrating the channel coding method. The channel coding method is explained from the perspective of the transmitting device. The channel coding method includes, but is not limited to, the following steps:

[0147] S1301. The transmitting device performs LDPC encoding on the input bit sequence based on a first base map containing a first core array corresponding to the first initial transmission code rate, to obtain the encoded bit sequence.

[0148] In this system, the first base map is one of N base maps, and the N base maps also include a second base map. The second base map contains a second core array and corresponds to a second initial transmission code rate, where N is an integer greater than or equal to 2. The first and second initial transmission code rates are the code rates used when transmitting different input bit sequences for the first time using LDPC, and the first initial transmission code rate is greater than the second initial transmission code rate. Therefore, the transmitting device can also perform LDPC encoding on the input bit sequence based on the second base map containing the second core array, which corresponds to the second initial transmission code rate, to obtain the encoded bit sequence.

[0149] The elements in the first base graph are both zero and non-zero elements, and the elements in the second base graph are both zero and non-zero elements. In one possible approach, the non-zero element is 1, then the elements in the first and / or second base graphs are 0 and 1. In another possible approach, the non-zero element includes 1 and other values, such as 2, 3, 4, etc. For example, if the non-zero element is 1 and 2, then the elements in the first and / or second base graphs are 0, 1, and 2. In yet another possible approach, the non-zero element is any integer value other than 1, such as 2 and 3, then the elements in the first and / or second base graphs are 0, 2, and 3.

[0150] Furthermore, the number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. In other words, the size (dimension) of the first base map and the second base map is equal. Therefore, different base maps corresponding to different initial transmission rates have the same size (dimension).

[0151] In one optional implementation, the first base map and the second base map can be the BG1 or BG2 described above, or a BG defined in a future communication system. This application does not limit the specific implementation of the base map.

[0152] Furthermore, the first core matrix includes submatrix A1 and submatrix B1, and the second core matrix includes submatrix A2 and submatrix B2. The number of columns in A1 and A2 is equal. Specifically, A1 is the information bit portion of the first core matrix, B1 is the parity bit portion of the first core matrix, A2 is the information bit portion of the second core matrix, and B2 is the parity bit portion of the second core matrix.

[0153] B1 consists of columns with a weight of 3 and a submatrix B′1 with a double diagonal structure; B2 consists of columns with a weight of 3 and a submatrix B′2 with a double diagonal structure. Here, "weight" refers to the number of non-zero elements. Both B1 and B2 include columns with a weight of 3, meaning that both B1 and B2 include columns with 3 non-zero elements. B1 including the double diagonal submatrix B′1 can be understood as: B1 includes B′1, and the weight of each column in B′1 is 2, meaning that each column in B′1 has 2 non-zero elements. Similarly, B2 including the double diagonal submatrix B′2 can be understood as: B2 includes B′2, and the weight of each column in B′2 is 2, meaning that each column in B′2 has 2 non-zero elements.

[0154] In this application, the "weight" described in relation to columns can also be called "column weight," which refers to the number of non-zero elements in a column of a matrix. The "weight" described in relation to rows can also be called "row weight," which refers to the number of non-zero elements in a row of a matrix.

[0155] In one possible approach, the number of rows in the second core array is greater than the number of rows in the first core array. In another possible approach, the number of columns in the second core array is greater than the number of columns in the first core array. Yet another possible approach, the number of rows in the second core array is greater than the number of rows in the first core array, and the number of columns in the second core array is also greater than the number of columns in the first core array. It is evident that the lower the initial transmission code rate of the input bit sequence, the larger at least one of the following in the core array: the number of rows or the number of columns. This allows for a smaller proportion of non-zero elements in the core array corresponding to medium-low code rates, meaning that medium-low code rates can correspond to core arrays with higher sparsity, or in other words, they can correspond to core arrays with lower weights. This reduces the number of nodes required for channel coding by the transmitting device and for channel decoding by the receiving device, thus reducing the complexity of channel coding and decoding.

[0156] In this embodiment of the application, low-to-medium bit rate can refer to a bit rate where the initial transmission bit rate is less than a first preset value, and high bit rate can refer to a bit rate where the initial transmission bit rate is greater than or equal to the first preset value, wherein the first preset value can be negotiated or defined in advance by the transmitting device and the receiving device.

[0157] The following describes in detail the implementation methods of the first core array and the second core array through implementation methods a and b:

[0158] Implementation method a: The first core array is associated with the first initial transmission code rate, and the second core array is associated with the second initial transmission code rate.

[0159] Specifically, the number of rows in the first core array is associated with the first initial transmission code rate R1, and the number of rows in the second core array is associated with the second initial transmission code rate R2, where R1 and R2 are both positive real numbers. The association of the number of rows in the first core array with the first initial transmission code rate can be understood as: the number of rows in the first core array can be determined based on the first initial transmission code rate. Similarly, the association of the number of rows in the second core array with the second initial transmission code rate can be understood as: the number of rows in the second core array can be determined based on the second initial transmission code rate. In other words, the transmitting device can determine the number of rows in the first core array based on the first initial transmission code rate, and can determine the number of rows in the second core array based on the second initial transmission code rate.

[0160] In another alternative implementation, the first core array has m rows. core1 It is also associated with at least one of the following: the number of columns k in A1 b The number of columns n of the punched columns in A1 prune1 The number of rows in the second core array is m core2 It is also associated with at least one of the following: the number of columns k in A2 b The number of columns n of the punched columns in A2 prune2 m core1 m core2 k b n prune1 and n prune2 All are positive integers.

[0161] In this system, the number of columns in A1 is equal to the number of columns in A2, and also equal to the number of columns of system bits. The number of punched columns in A1 can also be understood as the number of punched columns in the first core array, or as the number of punched columns in the first base diagram. Similarly, the number of punched columns in A2 can also be understood as the number of punched columns in the second core array, or as the number of punched columns in the second base diagram.

[0162] The number of rows in the first core array is also related to at least one of the following: the number of columns in A1 and the number of punched columns in A1. This can be understood as: the number of rows in the first core array can also be determined based on at least one of the following: the number of columns in A1 and the number of punched columns in A1. Similarly, the number of rows in the second core array is also related to at least one of the following: the number of columns in A2 and the number of punched columns in A2. This can be understood as: the number of rows in the second core array can also be determined based on at least one of the following: the number of columns in A2 and the number of punched columns in A2. Alternatively, the transmitting device can also determine the number of rows in the first core array based on at least one of the following: the number of columns in A1 and the number of punched columns in A1, and can also determine the number of rows in the second core array based on at least one of the following: the number of columns in A2 and the number of punched columns in A2.

[0163] In one alternative implementation, m core1 and m core2 They respectively satisfy:

[0164]

[0165] in, This indicates rounding down to the nearest integer.

[0166] It can be seen that the transmitting device can be based on formula (3), m core1 With R1, k b and n prune1 The relationship between them determines the number of rows m of the first core matrix. core1 The transmitting device can also be based on formula (4), where m core2 With R2, k b and n prune2 The relationship between them determines the number of rows m of the second core matrix. core2 .

[0167] As can be seen from formulas (3) and (4), the number of rows in the core array is related to the initial transmission rate of the input bit sequence, and the larger the initial transmission rate, the smaller the number of rows in the core array; or, the smaller the initial transmission rate, the larger the number of rows in the core array. Therefore, since the second initial transmission rate is less than the first initial transmission rate, the number of rows in the second core array is greater than the number of rows in the first core array.

[0168] In addition, the number of columns n of the first core matrix core1 It equals the number of columns in A1 plus the number of columns in B1, where B1 is a unit of size m. core1 ×m core1 If B1 is a square matrix, then the number of columns in B1 is equal to m. core1 Therefore, the number of columns n of the first core matrix core1 equals k b +m core1 Therefore, the number of columns in the first core matrix is ​​related to the number of columns in A1 and the number of rows in the first core matrix. Similarly, the number of columns n in the second core matrix... core2 It equals the number of columns in A2 plus the number of columns in B2, where B2 is a unit of size m. core2 ×m core2 If B2 is a square matrix, then the number of columns in B2 is equal to m. core2 Therefore, the number of columns n of the second core matrix core2 equals k b +m core2 Therefore, the number of columns in the second core matrix is ​​related to the number of columns in A2 and the number of rows in the second core matrix. Since m core2 Greater than m core1 Then the number of columns n of the second core matrix core2 The number of columns n greater than the first core matrix core1 .

[0169] As can be seen, the transmitting device can determine the number of rows of the first core array based on the first initial transmission code rate, thereby determining the number of columns of the first core array, and further determining the first core array based on the number of rows and columns of the first core array. The transmitting device can determine the number of rows of the second core array based on the second initial transmission code rate, thereby determining the number of columns of the second core array, and further determining the second core array based on the number of rows and columns of the second core array. Specifically, the transmitting device can determine the first core array based on the number of rows and columns of the first core array using density evolution and computer-aided methods. The transmitting device can determine the second core array based on the number of rows and columns of the second core array using density evolution and computer-aided methods.

[0170] As shown above, the number of rows in the first core array is related to the first initial transmission code rate, and the number of columns in the first core array is related to the number of rows in the first core array. Therefore, both the number of rows and columns in the first core array are related to the first initial transmission code rate, and thus the first core array is associated with the first initial transmission code rate. Similarly, the number of rows in the second core array is related to the second initial transmission code rate, and the number of columns in the second core array is related to the number of rows in the first core array. Therefore, both the number of rows and columns in the second core array are related to the second initial transmission code rate, and thus the second core array is associated with the second initial transmission code rate.

[0171] In summary, the smaller the initial transmission rate of the bit sequence, the larger the number of rows in the core array. For example, Figure 14 This is a schematic diagram illustrating the relationship between the initial transmission rate and the number of rows in the core array. For example... Figure 14 As shown, the smaller the initial transmission rate of the bit sequence, the larger the number of rows in the core array; conversely, the larger the initial transmission rate of the bit sequence, the smaller the number of rows in the core array. However, in this method, if the initial transmission rate is divided too finely, there will be too many types of rows in the core array, corresponding to too many BG types, which can easily lead to storage waste. Therefore, the transmitting device can map different rate intervals to different numbers of rows in the core array, so that different rate intervals can correspond to different BG types. This method can save storage resources of the storage matrix. For example, Table 1 is a mapping relationship table between rate intervals and the number of rows in the core array. As shown in Table 1, when the initial transmission rate is in the range of (0.67, 0.95], the core array has 4 rows, and the corresponding BG type is type A (type-A) in BG1; when the initial transmission rate is in the range of (0.5, 0.67], the core array has 13 rows, and the corresponding BG type is type B (type-B) in BG1; when the initial transmission rate is in the range of (0.25, 0.5], the core array has 24 rows, and the corresponding BG type is type C (type-C) in BG1.

[0172] Furthermore, in Table 1, the number of rows in the core array corresponding to each of the three bitrate intervals is equal to the number of rows in the core array corresponding to the highest bitrate value in that bitrate interval. That is, the number of rows in the core array corresponding to the initial bitrate interval (0.67, 0.95] is equal to the number of rows in the core array corresponding to an initial bitrate of 0.95, which is 4; the number of rows in the core array corresponding to the initial bitrate interval (0.5, 0.67] is equal to the number of rows in the core array corresponding to an initial bitrate of 0.67, which is 13; and the number of rows in the core array corresponding to the initial bitrate interval (0.25, 0.5] is equal to the number of rows in the core array corresponding to an initial bitrate of 0.5, which is 24.

[0173] Table 1

[0174] Initial code rate Number of core array rows BG type (0.67,0.95] 4 BG1 type-A (0.5,0.67] 13 BG1 type-B (0.25,0.5] 24 BG1 type-C

[0175] It is evident that when the initial transmission bit rates of the bit sequences belong to the same bit rate range, the number of rows in the core array is equal, and the selected BG type is the same; when the initial transmission bit rates of the bit sequences belong to different bit rate ranges, the number of rows in the core array is unequal, and the selected BG type is different. Compared with the method of having different numbers of core array rows corresponding to different initial transmission bit rates within the same bit rate range, this method can save storage overhead on the storage matrix.

[0176] In one optional implementation, the first initial transmission code rate and the second initial transmission code rate belong to different code rate ranges, so that the number of rows of the second core array corresponding to the second initial transmission code rate is not equal to the number of rows of the first core array corresponding to the first initial transmission code rate.

[0177] In one optional implementation, the transmitting device maps different code rate intervals to different core array rows, so that different code rate intervals can correspond to different BG types. This can also be viewed as the transmitting device dividing BG1 or BG2 into multiple types based on the initial transmission code rate. For example, Figure 15 This is a schematic diagram of a basemap selection strategy. For example... Figure 15 As shown, in the BG1 section, the initial transmission code rates from high to low correspond to BG1Type A / B / C… / N. Therefore, when the transmitting device selects BG1 for channel coding, it can choose different BG1 types based on the code rate range in which the initial transmission code rate falls.

[0178] In this second implementation, when the initial transmission code rates are different, the number of rows of the core array is different, so the core arrays corresponding to different initial transmission code rates are different. Compared with the NR where the core arrays for different initial transmission code rates are all high code rate core arrays, this method is beneficial to make the base map containing the core array have smaller weights, thereby reducing the complexity of channel coding and channel decoding.

[0179] For example, taking a core array with 24 rows as an example, we compare BG1 in 5G new radio (NR) with BG1 type-C in Table 1 above. Figure 16 This is a schematic diagram of a core array, specifically... Figure 16 The above table shows a schematic diagram of the 24-row core matrix in BG1 type-C. For NR, the schematic diagram of the 24-row matrix in BG1 is as described above. Figure 12 As shown. Figure 12 As shown, in NR, the matrix structure of BG1 is a typical Raptor-Like structure, with a relatively dense matrix, resulting in high complexity for channel coding and decoding. Figure 16 As shown, the core array density in BG1Type-C is relatively sparse, resulting in lower complexity for channel coding and decoding. Furthermore, Figure 16 The parity section of the central core matrix has a double-diagonal structure, which can further improve the connectivity of the matrix compared to the single-diagonal structure in Raptor-Like.

[0180] Furthermore, based on the protograph-based extrinsic information transfer (PEXIT) threshold analysis, the thresholds of NR BG1 and BG1 type-C after 50 iterations are 0.57dB and 0.6dB, respectively. Since the thresholds are close, BG1 Type-C and NR BG1 in Table 1 above have similar decoding performance. Figure 17 This is a diagram illustrating a weighted comparison. Specifically, Figure 17 This is a diagram illustrating the weight comparison of matrix columns in NR BG1 and BG1 type-C. (Example:) Figure 17 As shown, the matrices in BG1 Type-C have a lower average column weight compared to those in NR BG1, with the average column weight reduced by 26%. Therefore, the matrices in BG1 Type-C as shown in Table 1 above enable channel coding and channel decoding to have lower complexity.

[0181] Implementation method b: The first core array is associated with the first initial transmission code rate, and the second core array is associated with the second initial transmission code rate and the first core array.

[0182] In one optional implementation, the number of rows of the first core array is associated with the first initial transmission code rate R1, and the implementation method can be found in the above implementation method a, which will not be repeated here.

[0183] In one optional implementation, the first core array has m rows. core1It is also associated with at least one of the following: the number of columns k in A1 b The number of columns n of the punched columns in A1 prune1 The implementation method can be found in the above implementation method a, and will not be repeated here.

[0184] In one optional implementation, the first core array has m rows. core1 The implementation of the relationship shown in formula (3) above can be found in implementation a above, and will not be repeated here.

[0185] In addition, the number of columns of the first core array is equal to the number of columns of A1 plus the number of columns of B1. The implementation method can be found in the above implementation method a, and will not be repeated here.

[0186] It is evident that the implementation method for determining the number of rows and columns of the first core array in implementation method b is the same as the implementation method for determining the number of rows and columns of the first core array in implementation method a. In other words, in implementation method b, the transmitting device can determine the number of rows and columns of the first core array based on the implementation method for determining the number of rows and columns of the first core array in implementation method a.

[0187] In one optional implementation, the second core array is associated with both the second initial transmission code rate and the first core array. This can be understood as follows: when the initial transmission code rate of the bit sequence is the second initial transmission code rate, the second core array corresponding to the second initial transmission code rate is determined based on the first core array. Alternatively, when the initial transmission code rate of the bit sequence is the second initial transmission code rate, the transmitting device determines the second core array corresponding to the second initial transmission code rate based on the first core array corresponding to the first initial transmission code rate.

[0188] In one optional implementation, the second core array has p*m rows. core1 In other words, the number of rows in the second core array is equal to p times the number of rows in the first core array, where p is an integer greater than or equal to 2. Alternatively, when the second initial transmission code rate is less than the first initial transmission code rate, the transmitting device can determine the number of rows in the second core array corresponding to the second initial transmission code rate as p times the number of rows in the first core array corresponding to the first initial transmission code rate. Or, when the second initial transmission code rate is less than the first initial transmission code rate, the transmitting device can expand the number of rows in the first core array corresponding to the first initial transmission code rate by a factor of p to obtain the number of rows in the second core array corresponding to the second initial transmission code rate. Here, the first and second initial transmission code rates belong to different code rate intervals, or they belong to the same code rate interval, which can be pre-divided or determined by the transmitting and receiving devices. When the first and second initial transmission code rates belong to different code rate intervals, the number of rows in the core array corresponding to different code rate intervals is not equal, which saves storage resources. When the first and second initial transmission code rates are in the same code rate range, the number of rows in the core array corresponding to different initial transmission code rates is not equal.

[0189] Additionally, A2's p*m core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched column, and its relationship with m in A1. core1 The non-zero elements in the row and column punched are in the same position, p is an integer greater than or equal to 2, and q is an integer greater than or equal to 1 and less than or equal to p. In other words, the transmitting device can transmit m of A1. core1 Copy the non-zero element positions of the row and column punches to p*m in A2. core1 The qth m in the row core1 Okay, get p*m of A2 core1 The positions of non-zero elements in the punched columns of each row.

[0190] In A1, the non-punched column contains p groups of non-zero elements, and in A2, the q-th m-th element is... core1 The row contains the q-th non-zero element from the p-th non-zero elements, and A2 has p*m core1 The qth m in the row core1 The position of the q-th non-zero element included in the row, and the m of A1 core1 The positions of the qth group of non-zero elements in the row are the same. Alternatively, the transmitting device can divide the non-zero elements in the non-punched column of A1 into p groups of non-zero elements, and can copy the position of the qth group of non-zero elements from these p groups to the qth m-th group of non-punched columns in A2. core1 Okay, so the q-th m-th non-punch column in A2 core1 The position of the non-zero element in the row is the same as the position of the qth group of non-zero elements included in the non-punched column of A1.

[0191] It is evident that the transmitting device can determine the positions of the non-zero elements in the punched columns of the second core array A2 based on the positions of the non-zero elements in the punched columns of the first core array A1, and can also determine the positions of the non-zero elements in the non-punched columns of the second core array A2 based on the positions of the non-punched elements in the non-punched columns of the first core array A1. In other words, when the initial transmission code rate is the second initial transmission code rate, the transmitting device can determine the second core array corresponding to the second initial transmission code rate based on the first core array corresponding to the first initial transmission code rate, thus associating the second core array with the second initial transmission code rate and the first core array.

[0192] Optionally, when the initial transmission code rate is the second code rate, the method by which the transmitting device determines the first core array based on the second core array can also be viewed as performing row splitting on the first core array to obtain the second core array, where the number of rows in the second core array is p times the number of rows in the first core array, and A2 is p*m. core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched column, and its relationship with m in A1. core1 The non-zero elements in the row and column with holes are in the same position. The q-th m-th element in the non-hole column of A2 core1The row contains the q-th non-zero element from the p-th non-zero elements, and A2 has p*m core1 The qth m in the row core1 The position of the q-th non-zero element included in the row, and the m of A1 core1 The non-zero elements in the q-th group included in the row are in the same position.

[0193] When the second initial transmission code rate is less than the first initial transmission code rate, the method of determining the second core array based on the first core array and the second initial transmission code rate is different from the method of directly determining the second core array based on the second initial transmission code rate in the above implementation method a. The transmitting device does not need to store multiple core arrays with different initial transmission code rates. For example, it does not need to store the first core array corresponding to the first initial transmission code rate with a higher initial transmission code rate, nor does it need to store the second core array corresponding to the second initial transmission code rate with a lower initial transmission code rate. The second core array can be obtained by splitting the first core array, thereby reducing the storage overhead of the transmitting device in storing the number of matrices.

[0194] For example, Figure 18 and Figure 19 These are schematic diagrams of a first core array and a second core array, respectively. Figure 18 As shown, the size of the first core array is 4×26. Figure 19 As shown, the size of the second core array is 8×30, meaning that the number of rows in the second core array is doubled from the number of rows in the first core array. Figure 18 and Figure 19 In the diagram, the positions marked with "☆", "▲", "□", and "○" indicate the positions of non-zero elements, while the unmarked positions indicate the positions of zero elements. Figure 18 The positions marked with "☆" are the non-zero element positions in the punched column A1 of the first core array. Figure 19 The position marked with "☆" is the position of the non-zero element in the punched column A2 of the second core array. Figure 18 The positions marked with "▲" and "□" indicate the non-zero element positions in the non-drilled column A1 of the first core array. Figure 19 The positions marked with "▲" and "□" are the non-zero element positions of the non-punch column A2 in the second core array. Figure 18 The position marked with "○" indicates the position of the non-zero element B1 in the first core matrix. Figure 19 The position marked with "○" is the position of the non-zero element B2 in the second core array. Figure 18 The position marked with "▲" can be seen as the position of the first group of non-zero elements in the non-punched column of A1, and the position marked with "□" can be seen as the position of the second group of non-zero elements in the punched column of A1.

[0195] Figure 19 The positions of the non-zero elements in the first 4 rows and the second 4 rows of the second core array, and the punched columns (first and second columns) Figure 18In the first core array, the non-zero elements in the punched columns (first and second columns) of the four rows are in the same position, i.e. Figure 19 The positions of the non-zero elements marked with "☆" in the first four rows and the second four rows of the first two columns are related to... Figure 18 The non-zero elements marked with "☆" in the first two columns are in the same position.

[0196] like Figure 18 and Figure 19 As shown, the position of the first group of non-zero elements in the first 4 rows of the non-punch column in A2 is the same as the position of the first group of non-zero elements in the 4 rows of A1, that is... Figure 19 The position of the non-zero element marked with "▲" in the first 4 rows of the punched column in the China-Africa column, and... Figure 18 The non-zero elements marked with "▲" in the non-punched column are in the same position. The position of the second group of non-zero elements in the second 4 rows of the non-punched column in A2 is the same as the position of the second group of non-zero elements in the 4 rows of A1, that is... Figure 19 The position of the non-zero element marked with "□" in the second 4th row of the punched column in the China-Africa column is the same as... Figure 18 The non-zero elements marked with "□" in the punched column are in the same position.

[0197] in addition, Figure 18 B1 in the matrix includes a column with a weight of 3 and a submatrix with a weight of 2. Figure 19 B2 includes a column with a weight of 3 and a submatrix with a weight of 2.

[0198] Please refer to Table 2, which lists NR BG1 and... Figure 19 A comparison table of thresholds for the core array. As shown in Table 2, NR BG1 and... (The text abruptly ends here, suggesting it's incomplete or a fragment.) Figure 19 The threshold of the core array, and NR BG1 and NR after 20 iterations. Figure 19 The thresholds of the central core array are close to those of the two, therefore Figure 19 The core array in it and NR BG1 have similar decoding performance.

[0199] Table 2

[0200]

[0201] Please see Figure 20 , Figure 20 This is a diagram illustrating another weighting comparison. Specifically, Figure 20 For NR BG1 and Figure 19 A diagram illustrating the weight comparison of the core array. (See diagram below.) Figure 20 As shown, Figure 19 The core array in this model has a lower average column weight compared to NR BG1. Figure 19 Compared to NR BG1, the core array in this model has an average column weight reduction of approximately 10%. Therefore, Figure 19The core array in the middle enables channel coding and channel decoding to have lower complexity.

[0202] For example, Figure 21 and Figure 22 These are schematic diagrams of a first core array and a second core array, respectively. Figure 21 As shown, the size of the first core array is 4×26. Figure 22 As shown, the size of the second core array is 12×34, which means that the number of rows in the second core array is obtained by doubling the number of rows in the first core array. Figure 21 The first core array shown is Figure 18 Compared to the first core matrix shown, the first core matrix has the same size and the positions of the non-zero elements are the same. The difference lies in... Figure 21 The positions of the non-zero elements in the non-punched column of cell A1 are marked as three groups of non-zero element positions, i.e. Figure 21 In A1, the non-punch column includes three groups of non-zero elements. Among them, Figure 21 The position marked with "▲" can be seen as the position of the first group of non-zero elements in the non-punched column of A1, and the position marked with "□" can be seen as the position of the second group of non-zero elements in the non-punched column of A1. The position of the marker can be seen as the position of the third group of non-zero elements in the non-punched column of A1.

[0203] Figure 22 The positions of the non-zero elements in the punched columns (first and second columns) of the first 4 rows, the second 4 rows, and the third 4 rows of the second core array, and... Figure 21 The non-zero elements in the punched columns (first and second columns) of the first core array are in the same position, i.e. Figure 22 The positions of the non-zero elements marked with "☆" in the first four rows, the second four rows, and the third four rows of the first two columns are related to... Figure 21 The non-zero elements marked with "☆" in the first two columns are in the same position.

[0204] like Figure 21 and Figure 22 As shown, the position of the first group of non-zero elements in the first 4 rows of the non-punch column in A2 is the same as the position of the first group of non-zero elements in the 4 rows of A1, that is... Figure 22 The position of the non-zero element marked with "▲" in the first 4 rows of the punched column in the China-Africa column, and... Figure 21 The non-zero elements marked with "▲" in the non-punched column are in the same position. The position of the second group of non-zero elements in the second 4 rows of the non-punched column in A2 is the same as the position of the second group of non-zero elements in the 4 rows of A1, that is... Figure 22 The position of the non-zero element marked with "□" in the second 4th row of the punched column in the China-Africa column is the same as... Figure 21The positions of the non-zero elements marked with "□" in the non-punched column A2 are the same. The position of the third group of non-zero elements in the third row of the non-punched column A2 is the same as the position of the third group of non-zero elements in the fourth row of A1. Figure 22 The third row of the punched column in Central Africa The position of the non-zero element marked, and Figure 21 China-Africa Drilling Series The non-zero elements marked are in the same position.

[0205] in addition, Figure 21 B1 in the matrix includes a column with a weight of 3 and a submatrix with a weight of 2. Figure 22 B2 includes a column with a weight of 3 and a submatrix with a weight of 2.

[0206] Please refer to Table 3, which lists NR BG1 and... Figure 22 A comparison table of thresholds for the core array. As shown in Table 3, NR BG1 and... (The text abruptly ends here, so the translation stops as well.) Figure 26 The threshold of the core array, and NR BG1 and NR after 20 iterations. Figure 22 The thresholds of the central core array are close to those of the two, therefore Figure 22 The matrix and NR BG1 have similar decoding performance.

[0207] Table 3

[0208]

[0209] Please see Figure 23 , Figure 23 This is another illustration of weight comparison. Specifically, Figure 23 For NR BG1 and Figure 22 A diagram illustrating the weight comparison of the core array. (See diagram below.) Figure 23 As shown, Figure 22 The core array in this model has a lower average column weight compared to NR BG1. Figure 22 Compared to NR BG1, the core array in this model has an average column weight reduction of approximately 30%. Therefore, Figure 22 The core array in the middle enables channel coding and channel decoding to have lower complexity.

[0210] It is evident that the first core array and the second core array can be determined through the above implementation methods a and b. Regardless of which implementation method is used to determine the first core array and the second core array, when the second initial transmission code rate is less than the first initial transmission code rate, the number of rows in the second core array is greater than the number of rows in the first core array, and the number of columns in the second core array is greater than the number of columns in the first core array. That is, the size (dimension) of the second core array is greater than the size (dimension) of the first core array. This allows the initial transmission code rate of medium and low code rates to have a core array with greater sparsity, and thus the initial transmission code rate of medium and low code rates to have a base map with greater sparsity, which can reduce the complexity of channel coding and channel decoding.

[0211] Furthermore, if the number of information bits varies in different core matrices corresponding to different code rates, the code block segmentation and the selection of the boost factor become more complex. However, if the number of columns A1 in the first core matrix is ​​equal to the number of columns A2 in the second core matrix, meaning the number of information bits in both matrices remains unchanged, the columns of the parity check matrices corresponding to the first and second core matrices will not change. This simplifies code block segmentation and improves the selection and matching rate process.

[0212] Optionally, the first core array may be determined based on the first initial transmission code rate and other implementation methods, and the second core array may be determined based on the second initial transmission code rate and other implementation methods. This application embodiment does not limit this.

[0213] In addition, the transmitting device can also determine a first base map containing a first core array corresponding to a first initial transmission code rate, and determine a second base map containing a second core array corresponding to a second initial transmission code rate.

[0214] In one optional implementation, the number of columns n1 of the first base map is related to the mother code rate R. m1 The number of columns k in A1 b And the number of columns n of the punched columns in A1 prune1 Correspondingly, the number of columns n2 in the second base map is related to the code rate R of the mother code. m2 The number of columns k in A2 b And the number of columns n of the punched columns in A2 prune2 The number of columns n1 in the first base map is related to the mother code rate R. m1 The number of columns k in A1 b And the number of columns n of the punched columns in A1 prune1 Related, can be understood as: the number of columns n1 in the first base graph can be based on R m1 k b and n prune1 Certainly. Or rather, the transmitting device can be based on R. m1 k b and n prune1 Determine the number of columns n1 of the first base map. The number of columns n2 of the second base map is related to the code rate R of the mother code.m2 The number of columns k in A2 b And the number of columns n of the punched columns in A2 prune2 They are related and have similar understandings, so I will not elaborate further.

[0215] In one optional implementation, the number of columns n1 of the first base graph satisfies: The number of columns n2 in the second base graph satisfies: Or, in other words, the transmitting device can be based on n1 and R m1 k b and n prune1 Based on the aforementioned relationship, the number of columns n1 in the first base graph is determined; the transmitting device can then determine the number of columns n1 based on n2 and R. m2 k b and n prune2 Based on the above relationships, the number of columns n2 in the second base graph is determined.

[0216] Optional, the number of columns n in A1 with punched holes. prune1 The number of columns n of the punched columns in A2 prune2 Equal, mother code rate R m1 With the mother code rate R m2 If they are equal, then the number of columns n1 in the first base graph is equal to the number of columns n2 in the second base graph.

[0217] Optional, the number of columns n in A1 with punched holes. prune1 The number of columns n of the punched columns in A2 prune2 They are not equal, the mother code rate R m1 With the mother code rate R m2 They are not equal, but the number of columns n1 in the first base graph is still equal to the number of columns n2 in the second base graph.

[0218] In one optional implementation, the number of rows m1 of the first base graph satisfies: m1 = n1 - k b The number of rows m1 in the second base graph satisfies: m2 = n2 - k b Or, in other words, the transmitting device can be based on m1 and n1 and k b The above-mentioned relationship between them determines the number of rows m1 in the first base graph, and can be based on m2 and n2 and k. b The above relationship between them determines the number of rows m2 of the second base graph. Since n1 and n2 are equal, the number of rows m1 of the first base graph and the number of rows m2 of the second base graph are equal.

[0219] It is evident that the number of rows m1 in the first base map is equal to the number of rows m2 in the second base map, and the number of columns n1 in the first base map is equal to the number of columns n2 in the second base map. In other words, when the initial transmission code rates are different, the number of rows and columns of the base maps corresponding to different initial transmission code rates are equal. For ease of explanation, the following will use the representation that the number of rows in both the first and second base maps is m, and the number of columns in both the first and second base maps is n.

[0220] Optionally, the transmitting device may also determine a first base map containing a first core array based on the number of rows and columns of the first base map, and may also determine a second base map containing a second core array based on the number of rows and columns of the second base map.

[0221] Optionally, the first base map further includes a submatrix D1, and the second base map further includes a submatrix D2. D1 and D2 are the information bit portions of the first extended array in the first base map. The number of rows in D1 is determined based on the number of rows in the first base map and the number of rows in the first core array; the number of columns in D1 is determined based on the number of columns in the first base map and the number of columns in the first core array; the number of rows in D2 is determined based on the number of rows in the second base map and the number of rows in the second core array; and the number of columns in D2 is determined based on the number of columns in the second base map and the number of columns in the second core array. Alternatively, the transmitting device can also determine the number of rows in D1 based on the number of rows in the first base map and the number of rows in the first core array, and the number of columns in D1 based on the number of columns in the first base map and the number of columns in the first core array; and the number of rows in D2 is determined based on the number of rows in the second base map and the number of rows in the second core array; and the number of columns in D2 is determined based on the number of columns in the second base map and the number of columns in the second core array.

[0222] Specifically, the number of rows in D1 of the first base graph is equal to the number of rows in the first base graph minus the number of rows in the first core matrix, and the number of columns in D1 is equal to the number of columns in the first core matrix. That is to say, the number of rows in D1 is m. ext1 The number of columns n ext1 Each satisfies: m ext1 =mm core1 n ext1 =n core1 .

[0223] Similarly, the number of rows in D2 of the second base graph is equal to the number of rows in the second base graph minus the number of rows in the second core matrix, and the number of columns in D2 is equal to the number of columns in the second core matrix. That is to say, the number of rows in D2 is m. ext2 The number of columns n ext2 Each satisfies: m ext2 =mm core2 n ext2 =n core2 .

[0224] Optionally, the first base map further includes a submatrix C1, and the second base map further includes a submatrix C2, wherein C1 and C2 are all-zero matrices. Specifically, the number of rows in C1 equals the number of rows in the first core matrix, the number of columns in C1 equals the number of columns in the first extended matrix, the number of rows in C2 equals the number of rows in the second core matrix, and the number of columns in C2 equals the number of columns in the second extended matrix.

[0225] Optionally, the first base map further includes a submatrix I1, and the second base map further includes a submatrix I1. Here, I1 and I2 are the parity bit portions of the first extended matrix in the first base map. The number of rows and columns of I1 is equal to the number of rows of D1, and the number of rows and columns of I2 is equal to the number of rows of D2.

[0226] For example, please see Figure 24 , Figure 24 This is a schematic diagram of the structure of the first base map. Figure 24 The first base map includes a first core matrix, which includes submatrix A1 and submatrix B1. The first base map also includes submatrix C1, submatrix D1 and submatrix I1, where C1 is an all-zero matrix, D1 is the information bit part of the first extended matrix, and I1 is the parity bit part of the first extended matrix.

[0227] Therefore, the transmitting device can determine a first base map containing a first core array based on a first initial transmission code rate, so as to retransmit the input bit sequence based on the first base map. Optionally, the transmitting device can also determine a first base map containing a second core array based on a second initial transmission code rate, so as to retransmit the input bit sequence based on the second base map.

[0228] In summary, the second initial transmission code rate is less than the first initial transmission code rate. Regardless of whether the second core array is determined based on the second initial transmission code rate or the first core array, the number of rows in the second core array is greater than the number of rows in the first core array, and the number of columns in the second core array is greater than the number of columns in the first core array. Furthermore, the number of rows in the second base map is equal to the number of rows in the first base map, and the number of columns in the second base map is equal to the number of columns in the first base map. For example, Figure 25 and Figure 26 These are schematic diagrams of a first base map and a second base map, respectively. Figure 25 The number of rows in the first base graph shown is... Figure 26 The second base graph shown has the same number of rows. Figure 25 The number of columns in the first base diagram shown is... Figure 26 The second base graph shown has the same number of columns, and Figure 26 The number of rows in the second core matrix is ​​greater than Figure 25 The row number of the first core array in the middle. Figure 26 The number of columns in the second core matrix is ​​greater than Figure 25 The number of columns in the first core array. Additionally... Figure 25 and Figure 26 In this matrix, the I element represents a non-zero element, such as element 1; the A element represents the cyclic shift matrix of the identity matrix.

[0229] In one optional implementation, the transmitting device performs LDPC encoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate to obtain an encoded bit sequence, including: using the first core array in the first base map to perform LDPC encoding on the input bit sequence to obtain an encoded bit sequence.

[0230] Specifically, when the first initial transmission code rate equals the highest initial transmission code rate value in the initial transmission code rate interval, the transmitting device performs LDPC encoding on the input bit sequence based on the first base map. In practice, it uses the first core array in the first base map, meaning it performs LDPC encoding on the input bit sequence based on the first core array in the first base map. For example, when the first initial transmission code rate equals 0.95 in Table 1 above, the transmitting device performs LDPC encoding on the input bit sequence based on the first base map to obtain the encoded bit sequence, including: performing LDPC encoding on the input bit sequence using the first core array in the first base map to obtain the encoded bit sequence.

[0231] In another optional implementation, the transmitting device performs LDPC encoding on the input bit sequence based on a first base map containing a first core array corresponding to the first initial transmission code rate, to obtain the encoded bit sequence. This includes: using the first core array and an extended portion of the first base map to perform LDPC encoding on the input bit sequence to obtain the encoded bit sequence. The extended portion of the first base map is obtained by extending the first core array by Δm and Δn columns.

[0232] Specifically, when the initial transmission code rate is less than the highest initial transmission code rate value in the initial transmission code rate interval, the transmitting device performs LDPC encoding on the input bit sequence based on the first base map. In practice, it uses the first core array of the first base map and an extended portion that is expanded upon the first core array. For example, Figure 27 This is a schematic diagram of a first-base diagram. Specifically, Figure 27 If the first base map corresponds to an initial transmission code rate range of (0.67, 0.95), then the core array in the first base map is the core array when the initial transmission code rate is 0.95. Therefore, when the first initial transmission code rate is 0.9, the first core array remains as follows: Figure 27 The first core array is shown in the diagram. However, since the first initial transmission code rate falls within the range of (0.67, 0.95) and is less than 0.95, when the transmitting device performs LDPC encoding on the input bit sequence based on the first base map, it actually uses not only the first core array but also... Figure 27 The bold black text within the box represents the expanded portion, which is a... Figure 27 The first core array was obtained by expanding the rows to the lower right corner by Δm, and by... Figure 27The first core matrix is ​​obtained by extending the column to the lower right corner by Δn columns, where Δm = Δn = 4.

[0233] In another optional implementation, the transmitting device performs LDPC encoding on the input bit sequence based on a first base map containing a first core matrix corresponding to the first initial transmission code rate, to obtain the encoded bit sequence. This includes: performing LDPC encoding on the input bits using the entire matrix of the first base map to obtain the encoded bit sequence. In other words, the base map used by the transmitting device to perform LDPC encoding on the input bits based on the first base map is the first base map itself. This implementation is applicable to scenarios where the first initial transmission code rate is equal to the highest code rate in the initial transmission code rate interval, and also applicable to scenarios where the first initial transmission code rate is less than the highest code rate in the initial transmission code rate interval; that is, this implementation is applicable to scenarios where the first initial transmission code rate is any value.

[0234] In one possible approach, when the transmitting device uses the first base map itself as the base map for LDPC encoding of the input bits, the transmitting device can also puncture the encoded bit sequence to obtain a punctured bit sequence. Specifically, when the first initial transmission code rate equals the highest code rate in the initial transmission code rate range, the transmitting device should actually use the first core array in the first base map for LDPC encoding of the input bit sequence. Therefore, if the encoded bit sequence obtained by the transmitting device using the first base map itself for LDPC encoding includes redundant parts, the transmitting device needs to puncture these redundant parts to remove them, ensuring that the output bit sequence is the correctly encoded bit sequence. These redundant parts are the portion obtained by the transmitting device using the remaining parts of the first base map (excluding the first core array) for LDPC encoding of the input bit sequence.

[0235] When the initial transmission rate is less than the highest rate in the rate range, the transmitting device should actually use the first core array plus the extended part of the first base map for LDPC encoding of the input bit sequence. Therefore, the encoded bit sequence obtained by the transmitting device based on the first base map itself for LDPC encoding of the input bit sequence includes the part of the first base map excluding the first core array and the extended part. The redundant part obtained by the transmitting device for LDPC encoding of the input bit sequence needs to be punched out by the transmitting device to ensure that the output bit sequence is the correctly encoded bit sequence.

[0236] Therefore, when the transmitting device performs LDPC encoding on the input bits based on the first base map, it can actually use the first core array in the first base map, or the first core array plus an extended portion obtained by expanding the first core array, or the first base map itself. Whether the transmitting device specifically uses the first core array in the first base map, or the first core array plus the extended portion obtained by expanding the first core array, to perform LDPC encoding on the input bit sequence can be determined based on the first initial transmission code rate. Furthermore, regardless of the value of the first initial transmission code rate, the transmitting device can use the first base map itself to perform LDPC encoding on the input bit sequence and then punch punctures in the encoded bit sequence to obtain the output bit sequence.

[0237] It should be noted that regardless of whether the transmitting device uses the first core array in the first base map to perform LDPC encoding on the input bit sequence, or uses the first core array in the first base map and the extended part obtained based on the expansion of the first core array to perform LDPC encoding on the input bit sequence, or uses the first base map itself to perform LDPC encoding on the input bit sequence, the detailed process of LDPC encoding can be found in the above description of LDPC encoding, and will not be repeated here.

[0238] Optionally, when the transmitting device performs LDPC encoding on the input bit sequence using the first core matrix in the first base map, it determines the corresponding base matrix based on the first core matrix, then determines the parity check matrix H based on the base matrix and the offset value, and then performs LDPC encoding on the input bit sequence based on the parity check matrix H. Optionally, when the transmitting device performs LDPC encoding on the input bit sequence using the first core matrix in the first base map and the extended portion obtained based on the expansion of the first core matrix, it determines the corresponding base matrix based on the first core matrix and the extended portion obtained based on the expansion of the first core matrix, then determines the parity check matrix H based on the base matrix and the offset value, and then performs LDPC encoding on the input bit sequence based on the parity check matrix H. Optionally, when the transmitting device performs LDPC encoding on the input bit sequence using the first base map itself, the transmitting device determines the corresponding base matrix based on the first base map, then determines the parity check matrix H based on the base matrix and the offset value, and then performs LDPC encoding on the input bit sequence based on the parity check matrix H.

[0239] In one optional implementation, after obtaining the encoded bit sequence, the transmitting device may perform the following operations on the encoded bit sequence in sequence to obtain the signal to be transmitted over the air interface: modulation, layer mapping, precoding, framing, inverse fast fourier transform (IFFT), and intermediate and radio frequency (IRF).

[0240] Optionally, the transmitting device may also transmit a first signal, which is the signal after the transmitting device has processed the input bit sequence by LDPC encoding, modulation, layer mapping, precoding, framing, IFFT and IRF.

[0241] As can be seen, in this embodiment, the second initial transmission code rate is less than the first initial transmission code rate. The number of rows in the second core array corresponding to the second initial transmission code rate is equal to the number of rows in the first core array corresponding to the first initial transmission code rate. Furthermore, the size of the second base map, which includes the second core array, corresponding to the second initial transmission code rate is equal to the size of the first base map, which includes the first core array, corresponding to the first initial transmission code rate. Therefore, different initial transmission code rates do not need to share a single core array. The smaller the initial transmission code rate, the larger the number of rows in the core array. Since the base maps to which different core arrays belong have the same number of rows and columns, the proportion of non-zero elements in the core array with the smaller initial transmission code rate is smaller. This means that the core array with the smaller initial transmission code rate can have greater sparsity, thereby reducing the sparsity of the base map and consequently reducing the complexity of channel coding and channel decoding.

[0242] This application also proposes a channel decoding method. Figure 28 This is a flowchart illustrating the channel decoding method. The channel decoding method is explained from the perspective of the receiving device. The channel decoding method includes, but is not limited to, the following steps:

[0243] S2801. The receiving device performs LDPC decoding on the input bit sequence based on a first base map containing a first core array corresponding to the first initial transmission code rate, to obtain the decoded bit sequence.

[0244] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0245] Furthermore, the implementation methods of the first initial transmission code rate, the second initial transmission code rate, the first core array, the third core array, the first base map, and the second base map in this application embodiment can be found in the channel coding method described above, and will not be repeated here.

[0246] In this embodiment, the implementation of LDPC decoding of the input bit sequence by the receiving device based on the first base map containing the first core array corresponding to the first initial transmission code rate can be referred to the implementation of LDPC encoding of the input bit sequence by the transmitting device based on the first base map containing the first core array corresponding to the first initial transmission code rate in the channel coding method described above, and will not be repeated here.

[0247] For example, when the transmitting device uses the first core matrix of the first base map to perform LDPC encoding on the input bit sequence, the receiving device correspondingly uses the first core matrix of the first base map to perform LDPC decoding on the input bit sequence. As another example, when the transmitting device uses the first core matrix and the extended portion of the first base map to perform LDPC encoding on the input bit sequence, the receiving device correspondingly uses the first core matrix and the extended portion of the first base map to perform LDPC decoding on the input bit sequence. As yet another example, when the transmitting device uses the entire matrix of the first base map to perform LDPC encoding on the input bits, the receiving device correspondingly uses the entire matrix of the first base map to perform LDPC decoding on the input bits.

[0248] In one optional implementation, before the receiving device performs LDPC decoding on the input bit sequence based on a first base map containing a first core array corresponding to the first initial transmission code rate, it also receives a first signal from the transmitting device and performs the following operations on the first signal in sequence to obtain the input bit sequence: IRF, fast fourier transform (FFT), deframe, equalization, de-mapping, and demodulation.

[0249] The following example, using implementation method a above, which determines the number of rows of the core array based on the initial transmission code rate, illustrates a selection process for the BG (Browser Group). See also... Figure 29 , Figure 29 This is a schematic diagram of a base map selection process. For example... Figure 29 As shown, the BG selection process includes: determining whether to select BG1 or BG2 based on the transport block size and initial transmission rate; if BG1 is selected, determining the number of rows in the core matrix based on the initial transmission rate, i.e., determining the BG1 type; and reading the matrix corresponding to the BG1 type from the storage unit. Alternatively, if BG2 is selected, the matrix corresponding to BG2 is directly read from the storage unit.

[0250] The following example, using implementation b above as an example, illustrates a BG reading process where a low-bit-rate core array can be obtained by row splitting a high-bit-rate core array. See also Figure 30 , Figure 30 This is a schematic diagram of a base map reading process. For example... Figure 30As shown, the storage unit stores the extended matrices for each code rate of BG1, the core matrix for high code rates of BG1, and the BG2 matrix. The storage unit also includes a row splitting unit and a matrix merging unit. The row splitting unit splits the high code rate core matrix of BG1 to obtain a low code rate core matrix. The matrix merging unit merges the low code rate core matrix and the low code rate extended matrix obtained by the row splitting unit to obtain a merged matrix, which is then output. Therefore, when the BG selection structure is BG2, the output result is the BG2 matrix; when the BG selection result is BG1, the output result is the merged matrix output by the matrix merging unit. In this method, the storage unit stores the high code rate core matrix and the extended matrices corresponding to different code rates in BG1. After reading the high code rate core matrix from the storage unit, the entire matrix can be recovered according to the row splitting method, and the recovered matrix can then be used for LDPC encoding.

[0251] As can be seen, in this embodiment, the second initial transmission code rate is less than the first initial transmission code rate. The number of rows in the second core array corresponding to the second initial transmission code rate is equal to the number of rows in the first core array corresponding to the first initial transmission code rate. Furthermore, the size of the second base map, which includes the second core array, corresponding to the second initial transmission code rate is equal to the size of the first base map, which includes the first core array, corresponding to the first initial transmission code rate. Therefore, different initial transmission code rates do not need to share a single core array. The smaller the initial transmission code rate, the larger the number of rows in the core array. Since the base maps to which different core arrays belong have the same number of rows and columns, the proportion of non-zero elements in the core array with the smaller initial transmission code rate is smaller. This means that the core array with the smaller initial transmission code rate can have greater sparsity, thereby reducing the sparsity of the base map and consequently reducing the complexity of channel decoding.

[0252] also, Figure 31 This is a schematic diagram of a communication system 3100 applicable to embodiments of this application. For example... Figure 31As shown, on the transmitting device 310 side, operations such as cyclic redundancy check (CRC) calculation, code block segmentation, channel coding, rate matching, interleaving, and modulation are performed on the information data, and the processed information data is then transmitted. On the receiving device 320 side, information is received, and operations such as demodulation, deinterleaving, rate matching dematching, channel decoding, code block merging, and CRC are performed on the received information data to obtain the processed information data. The processing on the transmitting device side can be performed by, for example, the transmitting device, modules within the transmitting device (e.g., circuits, chips, or chip systems (e.g., modem chips, or SoC chips or SIP chips containing modem cores), or logic nodes, logic modules, or software that can implement all or part of the encoding device. The processing on the receiving device side can be performed by, for example, the receiving device, modules within the receiving device (e.g., circuits, chips, or chip systems (e.g., modem chips, or SoC chips or SIP chips containing modem cores), or logic nodes, logic modules, or software that can implement all or part of the receiving device.

[0253] The transmitting device can perform corresponding encoding according to the structure of the base map provided in the embodiments of this application, such as LDPC encoding according to the structure of the first base map in this application. The receiving device can perform corresponding decoding according to the structure of the base map provided in the embodiments of this application, such as LDPC decoding according to the structure of the first base map in this application. The encoding and / or decoding in this application can be implemented in hardware, software, or a combination of hardware and software. When the throughput requirement for encoding / decoding is high, a hardware accelerator (HAC) can be used.

[0254] The following section further describes the corresponding device implementation scheme in relation to the technical solution described above.

[0255] To achieve the functions of the methods provided in the embodiments of this application, the terminal-side device and the network-side device may include hardware structures and / or software modules, implementing the above functions in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is executed in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0256] Figure 32 A possible exemplary block diagram of the communication device involved in an embodiment of this application is shown. For example... Figure 32As shown, the communication device 3200 may include modules or units for implementing the methods described in the embodiments above. In one possible design, the communication device 3200 includes a communication unit 3201 and a processing unit 3202. Optionally, the communication device 3200 may further include a storage unit 3203 for storing device program code and / or data.

[0257] The communication device 3200 can be the transmitting device in the above embodiments, for example, the transmitting device or the communication module in the transmitting device, or the circuit or chip in the transmitting device responsible for the communication function.

[0258] For example, in one embodiment, the processing unit 3202 is used to: perform low-density parity-check code (LDPC) encoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the encoded bit sequence.

[0259] Wherein, the first base map is one of N base maps, and the N base maps also include a second base map, the second base map containing a second core matrix and corresponding to a second initial transmission code rate, and N is an integer greater than or equal to 2; the elements in the first base map are zero elements and non-zero elements, and the elements in the second base map are also zero elements and non-zero elements; the number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map; the second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix; the first core matrix includes submatrix A1 and submatrix B1, and the second core matrix includes submatrix A2 and submatrix B2, the number of columns in A1 is equal to the number of columns in A2; B1 includes columns with a weight of 3, and a submatrix B′1 with a double diagonal structure; B2 includes columns with a weight of 3, and a submatrix B′2 with a double diagonal structure.

[0260] In one possible design, the number of rows of the first core array is associated with the first initial transmission rate R1; the number of rows of the second core array is associated with the second initial transmission rate R2; wherein R1 and R2 are both positive real numbers.

[0261] In one possible design, the first core array has m rows. core1 It is also associated with at least one of the following: the number of columns k of A1. b The number of columns n of the punched columns in A1 prune1 The number of rows m of the second core array core2 It is also associated with at least one of the following: the number of columns k of A2. b The number of columns n of the punched columns in A2 prune2 The m core1 The m core2 The kb The n prune1 and the n prune2 All are integers greater than or equal to 0.

[0262] In one possible design, the m core1 satisfy: The m core2 satisfy: in, This indicates rounding down to the nearest integer.

[0263] In another possible design, the first core array has m rows. core1 The second core array has p*m rows. core1 The p*m of A2 core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched hole, and the m of A1. core1 The non-zero elements in the row and column with punched holes are in the same position; the non-punched column in A1 includes p groups of non-zero elements, and the q-th m-th element in the non-punched column in A2... core1 The row includes the q-th non-zero element from the p-th non-zero element group, and the p*m of A2 core1 The qth m in the row core1 The position of the qth non-zero element included in the row, and the m of A1 core1 The positions of the non-zero elements in the q-th group included in the row are the same; the m core1 q is a positive integer, where p is an integer greater than or equal to 2, and q is an integer greater than or equal to 1 and less than or equal to p.

[0264] In one possible design, the first initial transmission bit rate and the second initial transmission bit rate belong to different bit rate ranges.

[0265] In one possible design, when the communication device 3200 is a transmitting device or a communication module within a transmitting device, the function of the processing unit 3202 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) chip or a SIP chip containing a modem core. The function of the communication unit 3201 can be implemented by transceiver circuitry.

[0266] In one possible design, when the communication device 3200 is a circuit or chip responsible for communication functions in a transmitting device, such as a modem chip or a system-on-a-chip (SoC) or SIP chip containing a modem core, the function of the processing unit 3202 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 3201 can be implemented by an interface circuit or data transceiver circuit on the aforementioned chip.

[0267] The communication device 3200 can be the receiving device in the above embodiments, for example, the receiving device or the communication module in the receiving device, or the circuit or chip in the receiving device responsible for the communication function.

[0268] For example, in one embodiment, the processing unit 3202 is used to perform low-density parity-check code (LDPC) decoding on the input bit sequence based on a first base map containing a first core array corresponding to a first initial transmission code rate, to obtain the decoded bit sequence.

[0269] The first base map is one of N base maps, which also include a second base map. The second base map contains a second core matrix and corresponds to the second initial transmission code rate. N is an integer greater than or equal to 2. Elements in the first base map are both zero and non-zero. The number of rows in the first base map is equal to the number of rows in the second base map, and the number of columns in the first base map is equal to the number of columns in the second base map. The second initial transmission code rate is less than the first initial transmission code rate, and the number of rows in the second core matrix is ​​greater than the number of rows in the first core matrix. The first core matrix includes submatrices A1 and B1, and the second core matrix includes submatrices A2 and B2. The number of columns in A1 is equal to the number of columns in A2. B1 includes columns with a weight of 3 and a submatrix B′1 with a double diagonal structure. B2 includes columns with a weight of 3 and a submatrix B′2 with a double diagonal structure.

[0270] It is understandable that the division of units in the above-mentioned device is merely a logical functional division. One function can correspond to one functional unit, or two or more functions can be integrated into one functional unit. In actual implementation, all or some units can be integrated into one physical entity, or they can be distributed across different physical entities. Furthermore, the above-mentioned functional units can be implemented in hardware, software, or a combination of both.

[0271] In one example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as: one or more application-specific integrated circuits (ASICs), or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0272] In one example, storage unit 3203 may include random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory and / or registers, etc.

[0273] See Figure 33 This is a schematic diagram of the structure of a terminal 3300 provided in an embodiment of this application. The terminal 3300 can correspond to... Figure 1 The terminal shown is used to implement the operation of the transmitting or receiving device in the above embodiments. Figure 33 As shown, the terminal includes: one or more antennas 3310, a radio frequency processing system 3320, and a processor system 3330.

[0274] In the downlink or sidelink direction, the RF processing system 3320 receives RF signals through the antenna 3310 and sends the RF-processed signals to the processor system 3330 for further processing. In the uplink or sidelink direction, the processor system 3330 processes the terminal-side information and sends it to the RF processing system 3320, which then processes the signal and transmits it through the antenna 3310.

[0275] In one example, the radio frequency processing system 3320 serves as the communication interface for external communication of the terminal and may include a radio frequency frontend (RFFE) 3321 and a radio frequency transceiver 3322. The RFFE 3321 is primarily used for one or more processing operations, such as shaping, passband selection, or gain adjustment, on the RF signals received by the antenna or those to be transmitted through the antenna. It may include one or more components such as radio frequency switches, duplexers, filters, power amplifiers, antenna tuning, and low-noise amplifiers. The RFFE 3321 can be a circuit system composed of multiple discrete devices or integrated into one or more chips. The radio frequency transceiver 3322 processes the RF signals received by the RFFE into baseband / IF signals for further processing by the processor system 3330, and processes the baseband / IF signals provided by the processor system 3330 into RF signals for transmission to the RFFE 3321. The baseband / IF signals transmitted between the radio frequency transceiver 3322 and the processor system 3330 can be digital or analog signals. The RF transceiver 3322 can be implemented by one or more chips, which are commonly referred to as RF ICs.

[0276] In one example, the processor system 3330 may include one or more processors for processing signals and executing one or more communication protocols. Optionally, the processor system 3330 may also include a memory 3336. In one example, the one or more processors include at least one baseband processor 3331 (also known as a modem processor). The memory 3336 is used to store data and / or computer program instructions. Optionally, the processor system 3330 may also include one or more application processors 3332 for implementing processing of the terminal operating system and application layer. Optionally, the processor system 3330 may also include one or more of a voice subsystem 3333, a multimedia subsystem 3334, or an interface circuit 3335. The voice subsystem 3333 is used to process voice signals, the multimedia subsystem 3334 is used to handle multimedia-related operations, such as video encoding / decoding, image processing, etc., and the interface circuit 3335 is used to implement communication with other terminal components, such as a display 3340, an input device 3350, a memory 3360, etc. The above-mentioned components in the processor system 3330 can communicate with each other via a bus or communication interface circuit.

[0277] In one example, the processor system 3330 can be packaged as a single processor chip, such as a SoC chip or a SIP chip. In another example, the processor system 3330 can be a system composed of multiple chips, for example, the baseband processor 3331 can be packaged as a single chip, or packaged as a chip with some or all of the circuitry of the radio frequency processing system.

[0278] In one example, memory 3336 can be on-chip memory, i.e., located on the processor system 3330 chip. In another example, memory 3360 can be off-chip memory, i.e. located outside the processor system 3330 chip.

[0279] In one example, the baseband processor 3331 may include one or more processor cores 33311 and interface circuitry 33314. The one or more processor cores 33311 are used to process signals and execute one or more communication protocols. Optionally, the baseband processor 3331 may also include a memory 33312 for storing at least a portion of the corresponding computer program instructions and / or data. In one example, the one or more processor cores 33311 execute the computer program instructions stored in the memory 33312 to implement the relevant operations in the above method embodiments (such as executing S1301 or S2801 described above). In this disclosure, memory 33312 is used to store corresponding computer program instructions and / or data. This can mean that memory 33312 stores all corresponding computer program instructions and / or data for execution by processor core 33311; or it can mean that memory 33312 stores a portion of corresponding computer program instructions and / or data, including the computer program instructions and / or data currently required to be executed by processor core 33311. Memory 33312 can store different portions of computer program instructions and / or data multiple times for execution by processor core 33311 to implement the relevant operations in the above method embodiments. Interface circuit 33314 serves as a communication interface for communication with other components, such as transmitting signals with radio frequency processing system 3320, communicating with other subsystems and related components of processor system 3330 via bus, such as transmitting data control signals with application processor 3332, and transmitting data or computer program instructions with memory 3336 or memory 3360. Optionally, in order to reduce the load on the processor core, a baseband signal processing circuit 33313 can be set to perform at least some baseband signal processing, including one or more of signal demodulation, modulation, encoding or decoding.

[0280] In one example, the communication device provided in this application may be a terminal 3300, a communication module including a processor system 3330 and a radio frequency processing system 3320, or a baseband processor 3331.

[0281] The processor, processor system, application processor, baseband processor, processor circuit, or processor core mentioned above can be collectively referred to as a processor. The processor may include one or more of the following: CPU, digital signal processor (DSP), microprocessor unit (MPU), microcontroller unit (MCU), graphics processing unit (GPU), field programmable gate array (FPGA), artificial intelligence processor (AI processor), or neural processing unit (NPU).

[0282] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored on non-volatile memory, such as at least a portion of the aforementioned memory 3360 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). When the terminal is running, the corresponding computer program instructions may be partially or wholly loaded onto a memory with a faster transfer speed than the processor, such as at least a portion of memory 3336 and / or memory 33312 (e.g., one or more of RAM, SRAM, DRAM, PCM, RERAM, MRAM, FRAM, cache, or register), for the processor to execute in order to implement the steps in the above method embodiments.

[0283] In one example, the RF transceiver 3322 and the RF front-end 3321 can also be packaged in a single chip. In another example, the RF transceiver 3322, the RF front-end 3321, and the baseband processor 3331 can also be packaged in a single chip.

[0284] The embodiments of this application and any of the above-described channel coding and channel decoding methods are based on the same concept and have the same technical effects. For the specific principles, please refer to the description of any of the above-described channel coding and channel decoding methods, which will not be repeated here.

[0285] This application also provides a communication system, which includes a transmitting device for implementing any one of the methods described in the above-described method embodiments and a receiving device for implementing any one of the methods described in the above-described method embodiments. In another possible design, the system may further include other devices / functional network elements that interact with at least one of the transmitting and receiving devices.

[0286] This application also provides a chip including a processor that calls a computer program stored in a memory to enable a communication device including the chip to perform the functions of any of the above method embodiments.

[0287] This application also provides a computer-readable storage medium for storing computer software instructions, which, when executed by a communication device, implement the functions of any of the above method embodiments.

[0288] This application also provides a computer program product for storing computer software instructions, which, when executed by a communication device, implement the functions of any of the above method embodiments.

[0289] This application also provides a computer program that, when run on a computer, implements the functions of any of the above method embodiments.

[0290] The terms "system" and "network" in this application embodiment are used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC; "at least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in this application embodiment are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects.

[0291] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0292] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0293] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0294] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. ​ One or more processes and / or boxes ​ The steps of the function specified in one or more boxes.

[0295] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A channel coding method characterized by, The method comprises: performing low-density parity-check code (LDPC) encoding on the input bit sequence based on a first base graph corresponding to a first initial transmission code rate and containing a first core matrix, to obtain an encoded bit sequence; the first base graph is one of N base graphs, the N base graphs further comprising a second base graph containing a second core matrix and corresponding to a second initial transmission code rate, and N is an integer greater than or equal to 2; elements in the first base graph are zero elements and non-zero elements, and elements in the second base graph are zero elements and non-zero elements; the number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph; the second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix; the first core matrix comprises a sub-matrix A1 and a sub-matrix B1, the second core matrix comprises a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2; the B1 comprises columns with a weight of 3, and a sub-matrix B'1 of a double diagonal structure; the B2 comprises columns with a weight of 3, and a sub-matrix B'2 of a double diagonal structure.

2. The method of claim 1, wherein the number of rows of the first core matrix is associated with the first initial transmission code rate R1; the number of rows of the second core matrix is associated with the second initial transmission code rate R2; wherein R1 and R2 are both positive real numbers.

3. The method of claim 2, wherein the number of rows m of the first core array core1 is further associated with at least one of: the number of columns k of the A1 b the number of columns n of punctured columns in the A1 prune1 ; the number of rows m of the second core array core2 is further associated with at least one of: the number of columns k of the A2 b the number of punctured columns n in the A2 prune2 ; The m core1 , the m core2 , the k b , the n prune1 , and the n prune2 are all integers greater than or equal to 0.

4. The method of claim 3, wherein The m core1 Satisfies: The m core2 Satisfies: wherein denotes rounding down.

5. The method of claim 1 or 2, wherein The number of rows of the first core matrix is m core1 The number of rows of the second core matrix is p*m core1 ​ p*m of A2 core1 The qth m in the row core1 The position of the non-zero element in the row and column of the punched hole, and the m of A1. core1 The non-zero elements in rows and columns with punched holes are in the same position; The non-punctured column in the A1 includes a p group of non-zero elements, the qth m core1 column of the non-punctured column in the A2 includes a qth group of non-zero elements in the p group of non-zero elements, and the p*m core1 column of the A2 includes a qth group of non-zero elements core1 The position of the qth group of non-zero elements included in the p*m core1 column of the A1 is the same as the position of the qth group of non-zero elements included in the m The m core1 is a positive integer, the p is an integer greater than or equal to 2, and the q is an integer greater than or equal to 1 and less than or equal to the p.

6. The method of any one of claims 1 to 5, wherein the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals.

7. A communication device, characterized by The device comprises: a processing unit configured to perform low-density parity-check code (LDPC) encoding on the input bit sequence based on a first base graph corresponding to a first initial transmission code rate and containing a first core matrix, to obtain an encoded bit sequence; the first base graph is one of N base graphs, the N base graphs further comprising a second base graph containing a second core matrix and corresponding to a second initial transmission code rate, and N is an integer greater than or equal to 2; elements in the first base graph are zero elements and non-zero elements, and elements in the second base graph are zero elements and non-zero elements; the number of rows of the first base graph is equal to the number of rows of the second base graph, and the number of columns of the first base graph is equal to the number of columns of the second base graph; the second initial transmission code rate is less than the first initial transmission code rate, and the number of rows of the second core matrix is greater than the number of rows of the first core matrix; the first core matrix comprises a sub-matrix A1 and a sub-matrix B1, the second core matrix comprises a sub-matrix A2 and a sub-matrix B2, and the number of columns of A1 is equal to the number of columns of A2; the B1 comprises columns with a weight of 3, and a sub-matrix B'1 of a double diagonal structure; the B2 comprises columns with a weight of 3, and a sub-matrix B'2 of a double diagonal structure.

8. The device of claim 7, wherein a number of rows of the first core matrix is associated with the first initial transmission code rate R1; a number of rows of the second core matrix is associated with the second initial transmission code rate R2; wherein the R1 and the R2 are both positive real numbers.

9. The apparatus of claim 8, wherein a number of rows m of the first core array core1 a number of columns k of the A1 b a number of punctured columns n in the A1 prune1 ; the number of rows m of the second core array core2 is further associated with at least one of: the number of columns k of the A2 b the number of punctured columns n in the A2 prune2 ; The m core1 , the m core2 , the k b , the n prune1 , and the n prune2 are all integers greater than or equal to 0.

10. The apparatus of claim 9, wherein The m core1 Satisfies: The m core2 Satisfies: wherein denotes the floor function.

11. The apparatus of claim 7 or 8, wherein The number of rows of the first core matrix is m core1 The number of rows of the second core matrix is p*m core1 ​ The p*m of the A2 core1 The qth m in the qth row core1 The non-zero element position of the m in the puncturing column of the row is same as the m of the A1 core1 The non-zero element position of the m in the puncturing column of the row is same as the m of the A1 The non-punched column in A1 includes p groups of non-zero elements, and the q-th m-th element in the non-punched column in A2... core1 The row includes the q-th non-zero element from the p-th non-zero element group, and the p*m of A2 core1 The qth m in the row core1 The position of the qth non-zero element included in the row, and the m of A1 core1 The non-zero elements in the q-th group included in the row are in the same position; The m core1 is a positive integer, the p is an integer greater than or equal to 2, and the q is an integer greater than or equal to 1 and less than or equal to the p.

12. The apparatus of any one of claims 7 to 11, wherein the first initial transmission code rate and the second initial transmission code rate belong to different code rate intervals.

13. A computer-readable storage medium, characterized in that, The computer readable storage medium stores instructions which, when executed on a computer, cause the method according to any one of claims 1 to 6 to be performed.

14. A computer program product comprising instructions, characterized in that, The computer readable storage medium stores instructions which, when executed on a computer, cause the method according to any one of claims 1 to 6 to be performed.

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