Autonomous controllable radio station access gateway device

Abstract

The invention belongs to the technical field of wired communication, and particularly discloses an autonomous controllable radio station access gateway device. The system comprises an Ethernet control module, a CPU module, an FPGA module, an audio digital-to-analog conversion module, a serial port interface module and a parallel port acquisition control module, wherein the Ethernet control module is used for realizing network transceiving of data; the CPU module is used for realizing encapsulation and de-encapsulation of audio media streams, serial port data and parallel port data; the FPGA module is used for realizing analysis, coding and decoding of audio, serial port and parallel port signals and network packing transmission work; the audio digital-to-analog conversion module is used for realizing sampling, transmitting and receiving of multiple paths of analog audio signals; the serial port interface module is used for realizing physical layer transmission of serial port signals; the parallel port acquisition control module is used for state acquisition of various input parallel port signals and state control of report and output parallel port signals; therefore, various radio stations and terminal equipment are accessed, differences of different equipment types and communication interfaces are shielded, and a unified network communication platform is established.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of wired communication and relates to a self-controllable radio access gateway device. BACKGROUND

[0002] In a ship communication system, there are various types of devices such as radio equipment, terminal equipment and auxiliary equipment, and the communication interfaces of the devices are complex and diverse. The various communication devices are isolated from each other. In order to shield the differences of the device types and the communication interfaces, establish a unified network communication platform and realize centralized and efficient communication control and management, a radio access gateway device emerges as the times require.

[0003] At present, the radio access gateway device usually uses a special VoIP chip to realize the conversion of analog voice signals and network media stream signals. However, the special VoIP chip is limited by chip design, and the flexibility of its software and hardware is not enough, and the hardware resources are limited. When facing the complex use environment of the ship communication system containing various communication interfaces, the access and integration capability of the radio access gateway device for various types of communication devices in the communication system is insufficient. SUMMARY

[0004] In view of the defects of the prior art, the purpose of the application is to provide a self-controllable radio access device, which aims to solve the technical problems that the software and hardware flexibility of the existing special VoIP chip is insufficient, the hardware resources are limited, and it is difficult to access and integrate various types of communication devices.

[0005] The application relates to a self-controllable radio access gateway device, which comprises: an Ethernet control module, which is used for connecting the Ethernet and the CPU module, converting the audio RTP media stream network signals, serial port network signals and parallel port network signals received from the Ethernet into audio RTP media stream digital signals, serial port digital signals and parallel port digital signals and sending the signals to the CPU module, and converting the audio RTP media stream digital signals, serial port digital signals and parallel port digital signals received from the CPU module into audio RTP media stream network signals, serial port network signals and parallel port network signals and sending the signals to the Ethernet; a CPU module, which is used for connecting the Ethernet control module and the FPGA module, unpacking the audio RTP media stream digital signals, serial port digital signals and parallel port digital signals received from the Ethernet control module into private UDP packets and sending the packets to the FPGA module, packing the private UDP packets received from the FPGA module into audio RTP media stream digital signals, serial port digital signals and parallel port digital signals and sending the signals to the Ethernet control module, and being further used for issuing control instructions to other modules; The FPGA module is connected with the serial port interface module, the parallel port acquisition control module, the CPU module and the audio digital-analog conversion module; the private UDP message received from the CPU module is converted into a serial port signal, a parallel port level state or a digital audio signal; the serial port signal is output to the serial port interface module; the parallel port level state is output to the parallel port acquisition control module; the digital audio signal is output to the audio digital-analog conversion module; the serial port signal, the parallel port level state or the digital audio signal received are packaged into a private UDP message and sent to the CPU module; The audio digital-analog conversion module is connected with the FPGA module and the multi-channel analog audio signal; the digital audio signal is sampled from the multi-channel analog audio signal according to a preset control instruction and sent to the FPGA module; the digital audio signal received from the FPGA module is converted into an analog audio signal and sent out. The serial port interface module is connected with the FPGA module and the serial port peripheral; the voltage of the serial port signal output by the FPGA module is converted into the standard voltage of the serial port signal; the voltage of the serial port signal input to the FPGA module is converted into the I / O pin voltage of the FPGA module. The parallel port acquisition control module is connected with the FPGA module and the parallel port peripheral; the parallel port level state of the parallel port peripheral is read and converted into the I / O pin voltage of the FPGA module and then sent to the FPGA module; the parallel port level state of the FPGA module is read and converted into the standard voltage of the parallel port signal and then output to the parallel port peripheral.

[0006] Preferably, the FPGA module specifically comprises: The packaging unit is used for unpackaging the received private UDP message into serial port data, parallel port data and digital audio data; the serial port data is sent to the universal asynchronous receiving and transmitting unit; the parallel port data is sent to the parallel port signal receiving and transmitting unit; the digital audio data is sent to the audio encoding and decoding unit; the received serial port data, parallel port data or digital audio data is packaged into a private UDP message and sent to the CPU module. The audio encoding and decoding unit is used for decompressing the digital audio data received from the packaging unit into a digital audio signal and then sending out; the received digital audio signal is compressed into digital audio data and then sent to the packaging unit. The universal asynchronous receiving and transmitting unit is used for packaging the serial port data received from the packaging unit into a serial port signal according to the serial port communication protocol and then sending out; the received serial port signal is parsed into serial port data according to the serial port communication protocol and then sent to the packaging unit. Parallel port signal transceiver unit, for converting parallel port data received from the packet assembly unit into the level state of the parallel port output pin and outputting externally, and converting the level state of the parallel port input pin into parallel port data and sending to the packet assembly unit.

[0007] Preferably, the FPGA module further comprises a phase-locked unit, configured to divide the clock source signal into the bit clock frequency, the audio sampling frequency and the working clock frequency of the digital audio signal according to the preset control instruction.

[0008] Preferably, the CPU module specifically comprises: The first network port unit is configured to connect the FPGA module and realize the transmission and reception of private UDP messages. The second network port unit is configured to connect the Ethernet control module and realize the transmission and reception of audio RTP media stream digital signals, serial port digital signals and parallel port digital signals. The media stream processing unit is configured to send the audio RTP media stream digital signals received from the second network port unit to the first network port unit after unpacking the audio RTP media stream digital signals into private UDP messages through the control unit, and send the UDP messages received from the first network port unit to the second network port unit after packing the UDP messages into audio RTP media stream digital signals through the control unit. The control unit is configured to send the serial port digital signals and the parallel port digital signals received from the second network port unit to the first network port unit after unpacking the serial port digital signals and the parallel port digital signals into private UDP messages, and send the private UDP messages received from the first network port unit to the second network port unit after packing the private UDP messages into serial port digital signals and parallel port digital signals.

[0009] Preferably, the CPU module further comprises an interaction unit, configured to convert the interaction control signals received from the outside into interaction control data and send the interaction control data to the control unit, and convert the interaction control data received from the control unit into interaction control signals and send the interaction control signals externally.

[0010] Preferably, the CPU module further comprises a parallel port unit, configured to realize the information interaction with the parallel port peripheral device.

[0011] Preferably, the application further comprises a filtering module connected to the audio digital-analog conversion module and the multi-channel analog audio signals, configured to filter the input analog audio signals according to the preset control instruction.

[0012] Overall, compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects: (1) The application is based on a mixed architecture of FPGA+CPU, wherein the characteristics of hardware parallelism, extremely low and determined response delay and strict synchronization control of multiple signals of FPGA are utilized to realize the collection, analysis, coding and decoding and network packet transmission of various analog audio signals, serial port signals and parallel port signals; the characteristics of flexibility, adaptability to complex logic of CPU are utilized to realize the encapsulation, decapsulation and control functions of media stream signals, thereby integrating various interfaces and device types of various communication devices, shielding the differences of various device types and communication interfaces and establishing a unified network communication platform.

[0013] (2) In the application, the process of converting audio signals into RTP media streams is divided into two parts: private UDP message encapsulation and RTP media stream encapsulation; wherein the private UDP message encapsulation which is more determined is allocated to the FPGA module, which not only conforms to the characteristics of high customization capability of the FPGA module, but also facilitates the transmission of the encapsulated private UDP message between the FPGA module and the CPU module; the RTP media stream encapsulation is more complex, and it is more advantageous to process it by the CPU module. Compared with the traditional VoIP chip which converts specific audio signals and specific RTP media streams, the mixed architecture of FPGA+CPU of the application has more excellent and flexible processing capability.

[0014] (3) In the application, the sampling of digital audio signals is realized through an audio digital-to-analog conversion module, and the sampling frequency, bit clock frequency and working frequency can be flexibly adjusted by the FPGA module, which is more flexible than the current special VoIP chip.

[0015] (4) In the application, the FPGA module is utilized to expand the hardware resources of parallel communication and serial communication of the special VoIP chip, and the CPU module also interacts with the FPGA module through private UDP messages to process corresponding serial port and parallel port data, which not only simplifies the hardware design, but also simplifies the software processing flow. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a specific position schematic diagram of a radio access gateway device in a ship communication system provided by an embodiment of the application.

[0017] Figure 2 is a whole composition schematic diagram of a radio access gateway device provided by an embodiment of the application.

[0018] Figure 3 is a composition schematic diagram of an FPGA module provided by an embodiment of the application.

[0019] Figure 4 is a composition schematic diagram of a CPU module provided by an embodiment of the application.

[0020] Figure 5is a clock frequency implementation block diagram of the audio digital-to-analog conversion module provided in the embodiments of the present application. DETAILED DESCRIPTION

[0021] In order to make the purposes, technical solutions and advantages of the present application clearer, the present application is further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.

[0022] The terms "first" and "second" and the like in the present application are used to distinguish different objects and not used to describe the specific order of the objects. For example, the first audio digital-to-analog conversion module and the second audio digital-to-analog conversion module are used to distinguish different audio digital-to-analog conversion modules and not used to describe the specific order of the audio digital-to-analog conversion modules.

[0023] The term "electrically connected" in the present application can be direct circuit connection or signal transmission through a communication protocol.

[0024] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present concepts in a specific way.

[0025] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more, for example, a plurality of processing units means two or more processing units, and the like; a plurality of elements means two or more elements, and the like.

[0026] First, the technical terms involved in the embodiments of the present application are introduced.

[0027] The embodiments of the present application are described below in combination with the drawings in the embodiments of the present application.

[0028] CPU (Central Processing Unit, central processor), the core of a computer, responsible for executing program instructions and processing data.

[0029] FPGA (Field-Programmable Gate Array, field-programmable gate array), a programmable hardware chip, which can realize a specific hardware circuit through programming.

[0030] UDP (User Datagram Protocol) is a connectionless transport layer protocol. It does not guarantee the order, reliability, or deduplication of data packets, but it has the advantages of low overhead and low latency.

[0031] RTP (Real-time Transport Protocol) is a network protocol used for real-time transmission of audio and video data. It typically runs on top of UDP and provides features such as timestamps and sequence numbers to support real-time playback and synchronization.

[0032] VoIP (Voice over Internet Protocol) is a voice calling technology that uses the Internet Protocol to enable voice calls and multimedia conferencing, that is, to communicate via the Internet.

[0033] The technical solution of this application will now be further explained and illustrated with reference to the accompanying drawings: like Figure 1 The diagram shows the specific location of the radio access gateway device provided in this application embodiment in the ship communication system. The radio access gateway device of this application converts the audio data, serial port data and parallel port data of various radio stations and various terminals into RTP media stream network signals, serial port network signals and parallel port network signals for transmission in the ship integrated communication network, realizing the transformation from traditional voice communication to IP network communication.

[0034] like Figure 2 The figure shows a schematic diagram of the overall composition of the radio access gateway device provided in this application embodiment. As shown in the figure, it mainly includes the following parts: The Ethernet control module is used to connect the Ethernet and CPU modules; it converts the audio RTP media stream network signals, serial port network signals, and parallel port network signals received from the Ethernet into audio RTP media stream digital signals, serial port digital signals, and parallel port digital signals and sends them to the CPU module; it also converts the audio RTP media stream digital signals, serial port digital signals, and parallel port digital signals received from the CPU module into audio RTP media stream network signals, serial port network signals, and parallel port network signals and sends them to the Ethernet.

[0035] The CPU module connects the Ethernet control module and the FPGA module. It decapsulates the audio RTP media stream digital signals, serial port digital signals, and parallel port digital signals received from the Ethernet control module into private UDP packets and sends them to the FPGA module. Conversely, it encapsulates the private UDP packets received from the FPGA module into audio RTP media stream digital signals, serial port digital signals, and parallel port digital signals and sends them to the Ethernet control module. It also issues control commands to other modules. In this embodiment, the minimum system consists of Rockchip's domestically produced RK3399 processor and other domestically produced DDR3 SDRAM chips and eMMC chips (memory chips), with two gigabit Ethernet interfaces externally via a PCIe bus. These interfaces can be implemented using domestically produced gigabit Ethernet control chips such as the WX1860. On the software side, the operating system uses the fully domestically produced Deepin operating system, and the application software is self-developed based on Linux, achieving complete independent control.

[0036] The FPGA module connects the serial interface module, parallel acquisition and control module, CPU module, and audio digital-to-analog converter module. It converts private UDP packets received from the CPU module into serial signals, parallel level status, or digital audio signals. Serial signals are output to the serial interface module, parallel level status to the parallel acquisition and control module, and digital audio signals to the audio digital-to-analog converter module. The FPGA module receives serial signals from the serial interface module, parallel level status from the parallel acquisition and control module, and digital audio signals from the audio digital-to-analog converter module. It encapsulates the received serial signals, parallel level status, or digital audio signals into private UDP packets and sends them to the CPU module. In this embodiment, audio signals, serial data, and input / output parallel port control signals are all processed interactively through the FPGA module and CPU module. The FPGA chip can be a domestically produced chip such as the FMK50T4 from Fudan Microelectronics. The FPGA chip and CPU chip are directly connected via a GMAC interface (Gigabit Media Access Controller), which is simple, convenient, and can achieve gigabit speeds, fully meeting the bandwidth requirements for audio data processing. The FPGA and CPU communicate via private UDP Ethernet packets, which is convenient and flexible. After the CPU obtains the interaction information from the FPGA, it then interacts with the outside world through another Ethernet interface. The audio digital-to-analog converter module is used to connect the FPGA module and multiple analog audio signals. It samples digital audio signals from the multiple analog audio signals according to preset control commands and sends them to the FPGA module. It converts the digital audio signals received from the FPGA module into analog audio signals and sends them out.

[0037] The serial interface module is used to connect the FPGA module and serial peripherals. It converts the voltage of the serial port signal output by the FPGA module into the standard voltage of the serial port signal, and converts the voltage of the serial port signal input to the FPGA module into the I / O pin voltage of the FPGA module.

[0038] The parallel port acquisition and control module is used to connect the FPGA module and the parallel port peripheral. It reads the parallel port level status of the parallel port peripheral and converts the voltage of the parallel port level status of the parallel port peripheral into the I / O pin voltage of the FPGA module and sends it to the FPGA module. It is also used to read the parallel port level status of the FPGA module and convert the voltage of the parallel port level status of the FPGA module into the standard voltage of the parallel port signal and output it to the parallel port peripheral.

[0039] The filtering module connects to the audio digital-to-analog converter module and multiple analog audio signals, and is used to filter the input analog audio signals according to preset control commands.

[0040] If the radio access gateway device receives multiple analog audio signals during operation: After being filtered by the filtering module, the analog audio signal enters the audio digital-to-analog converter module. The audio digital-to-analog converter module samples the audio to obtain a digital audio signal, which is then sent to the FPGA module. The FPGA module encodes the received digital audio signal and performs Ethernet packet assembly, adding MAC / IP / UDP headers to form UDP packets. These packets are then sent to the CPU module for RTP media stream encapsulation. After adding an RTP header to become an RTP media stream digital signal, it is sent to the Ethernet via the Ethernet control module, thus completing the VoIP processing function.

[0041] Conversely, the CPU module receives the RTP media stream digital signal from the network through the Ethernet control module. The CPU decapsulates the RTP media stream digital signal, removes the RTP header information, converts it into a UDP packet, and sends it to the FPGA module. The FPGA module converts the UDP packet into a digital audio signal, decompresses it, and sends it to the audio digital-to-analog converter module. The audio digital-to-analog converter module converts the digital audio signal into an analog audio signal and sends it out through the analog audio interface.

[0042] If the radio access gateway device receives a serial port signal during operation: The serial port signal is level-converted by the serial port interface module on the outside of the device and then sent to the FPGA module. The FPGA module parses the serial port signal according to the UART protocol to obtain the serial port data, packages it into UDP packets and sends them to the CPU module. The CPU module sends the UDP packets to the Ethernet via the Ethernet control module.

[0043] Conversely, the serial digital signal received by the Ethernet control module from the Ethernet is encapsulated into a UDP packet by the CPU module. After the UDP packet is exchanged with the FPGA module, it is decapsulated into a serial signal by the FPGA module. The serial signal is then sent to the serial peripheral after level conversion by the serial interface module.

[0044] If the radio access gateway device receives a parallel port signal during operation: The parallel port peripheral sends a parallel port signal. After the parallel port signal is level-converted by the input parallel port acquisition module, it is acquired and converted by the FPGA module to obtain a UDP packet and sent to the CPU module. The CPU module then sends the UDP packet to the Ethernet via the Ethernet control module.

[0045] like Figure 3 The diagram shown is a schematic representation of the FPGA module provided in an embodiment of this application. Specifically, it includes: The packet assembly unit is used to decapsulate the received private UDP packets into serial port data, parallel port data, and digital audio data. The serial port data is sent to the general asynchronous transceiver unit, the parallel port data is sent to the parallel port signal transceiver unit, and the digital audio data is sent to the audio codec unit. The unit also encapsulates the received serial port data, parallel port data, or digital audio data into private UDP packets and sends them to the CPU module. The audio codec unit is used to decompress the digital audio data received from the packet assembly unit into digital audio signals and then send them out, and to compress the digital audio signals received from the outside into digital audio data and then send them to the packet assembly unit. The general asynchronous transceiver unit is used to encapsulate the serial port data received from the packet assembly unit into serial port signals according to the serial port communication protocol and then send them out to the outside world, and to parse the serial port signals received from the outside world into serial port data according to the serial port communication protocol and then send them to the packet assembly unit. The parallel port signal transceiver unit is used to convert the parallel port data received from the packet assembly unit into the level state of the parallel port output pins for external output, and to read the level state of the parallel port input pins, convert it into parallel port data, and send it to the packet assembly unit.

[0046] like Figure 4 The diagram shown is a schematic representation of the CPU module provided in an embodiment of this application. Specifically, it includes: The first network port unit is used to connect to the FPGA module to realize the sending and receiving of private UDP packets; The second network port unit is used to connect to the Ethernet control module to realize the transmission and reception of digital signals of audio RTP media stream, serial port digital signals and parallel port digital signals; The media stream processing unit is used to decapsulate the audio RTP media stream digital signal received from the second network port unit into a private UDP packet and send it to the first network port unit through the control unit, and to encapsulate the UDP packet received from the first network port unit into an audio RTP media stream digital signal through the control unit and send it to the second network port unit. The control unit is used to decapsulate the serial and parallel digital signals received from the second network port unit into private UDP packets and send them to the first network port unit, and to encapsulate the private UDP packets received from the first network port unit into serial and parallel digital signals and send them to the second network port unit.

[0047] The interaction unit is used to convert interactive control signals received from the outside into interactive control data and send them to the control unit, and to convert interactive control data received from the control unit into interactive control signals and send them to the outside.

[0048] The private UDP communication message format between the FPGA and the CPU is shown in Table 1, without the IP datagram header. The audio data processing format is used as an example.

[0049] Table 1

[0050] In Table 1, the data field represents the audio payload data, the length of which is determined by both the audio sampling frequency and the IP packet transmission interval. Taking G711A as an example (a voice codec), the audio sampling frequency fs is 8kHz, the IP packet transmission interval T is 20ms, and the data length L is... byte.

[0051] Figure 2 In this system, the protocol conversion function of serial port data is implemented by FPGA programming, which simplifies the hardware design. Only an external serial port interface module is needed to realize the level conversion of serial port signals. Domestic chips such as AIP3232TA16 and NSi83086E can be used to implement this.

[0052] Figure 2 In this design, the audio digital-to-analog converter module and peripheral filtering circuitry support not only a narrowband audio sampling rate of 8kHz but also a wideband audio sampling rate of 48kHz. The design utilizes an audio differential operational amplifier chip to achieve a true four-wire analog differential audio interface. The eight audio interfaces are implemented using four audio digital-to-analog converter modules, but all related audio clock signals are provided from the same clock source signal after phase-locked loop (PLL) frequency division by the FPGA module. This simplifies the hardware design and improves clock synchronization between the audio signals. At this time, the FPGA module operates in audio master clock mode, providing the clock signal externally, while the audio digital-to-analog converter modules operate in slave clock mode, receiving the clock signal from an external input.

[0053] like Figure 5 The diagram shows the implementation block diagram of various clock frequencies for the audio digital-to-analog converter module provided in this application embodiment. MCLK1 to MCLK4 are the operating clocks for the four audio digital-to-analog converter modules, typically 12.288MHz; FS1 to FS4 are the audio sampling frequencies, which the CPU can set via commands to the FPGA, thus outputting different sampling frequencies such as 8kHz and 48kHz; SCLK1 to SCLK4 are the bit clock frequencies, determined by the length of the audio PCM data bits, as shown in Table 2.

[0054] Table 2

[0055] Figure 2 In the parallel port signal input section, the FPGA module first acquires the parallel port level status to obtain parallel port data, and then converts it into UDP packets for exchange with the CPU module for processing. Specifically, to meet the needs of certain special application scenarios where changes in the parallel port input status require timely response from the CPU software, the FPGA needs to generate a hardware interrupt signal to the CPU via the GPIO pin of the CPU chip when the external parallel port input status changes. This ensures the timeliness of CPU software processing. Supported parallel port input states are shown in Table 3. Each of the 12 parallel port input interfaces can be configured via software to support one of the following three input types, offering flexibility.

[0056] Table 3

[0057] In the 12 parallel output interfaces, each channel can be configured via software to support one of the four types listed in Table 4, making it widely applicable.

[0058] Table 4

[0059] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0060] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the components can rotate relative to each other after connection. "Sliding connection" refers to a connection where the components can slide relative to each other after connection. The directional terms mentioned in the embodiments of this application, such as "top," "bottom," "inner," "outer," "left," and "right," are only for reference to the directions in the accompanying drawings. Therefore, the directional terms used are for better and clearer explanation and understanding of the embodiments of this application, and are not intended to indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0061] Furthermore, the mathematical concepts mentioned in the embodiments of this application, such as symmetry, equality, parallelism, and perpendicularity, are limitations specific to the current technological level, rather than absolute and strict mathematical definitions. Slight deviations are permissible; approximations of symmetry, equality, parallelism, and perpendicularity are all acceptable. For example, "A and B are parallel" means that A and B are parallel or approximately parallel, and the angle between A and B can be between 0 and 10 degrees. "A and B are perpendicular" means that A and B are perpendicular or approximately perpendicular, and the angle between A and B can be between 80 and 100 degrees.

[0062] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An autonomously controllable radio access gateway apparatus, characterized by The application relates to a multi-channel audio signal transmission system, which comprises the following modules: an Ethernet control module, which is used for connecting the Ethernet and the CPU module, converting audio RTP media stream network signals, serial port network signals and parallel port network signals received from the Ethernet into audio RTP media stream digital signals, serial port digital signals and parallel port digital signals and sending the signals to the CPU module, converting audio RTP media stream digital signals, serial port digital signals and parallel port digital signals received from the CPU module into audio RTP media stream network signals, serial port network signals and parallel port network signals and sending the signals to the Ethernet, and issuing control instructions to other modules; a CPU module, which is used for connecting the Ethernet control module and the FPGA module, unpacking audio RTP media stream digital signals, serial port digital signals and parallel port digital signals received from the Ethernet control module into private UDP packets and sending the packets to the FPGA module, packing private UDP packets received from the FPGA module into audio RTP media stream digital signals, serial port digital signals and parallel port digital signals and sending the signals to the Ethernet control module, and issuing control instructions to other modules; an FPGA module, which is used for connecting a serial port interface module, a parallel port acquisition control module, the CPU module and an audio digital-analog conversion module, converting private UDP packets received from the CPU module into serial port signals, parallel port level states or digital audio signals, outputting the serial port signals to the serial port interface module, outputting the parallel port level states to the parallel port acquisition control module, and outputting the digital audio signals to the audio digital-analog conversion module; receiving serial port signals from the serial port interface module, receiving parallel port level states from the parallel port acquisition control module, receiving digital audio signals from the audio digital-analog conversion module, and packing the received serial port signals, parallel port level states and digital audio signals into private UDP packets and sending the packets to the CPU module; an audio digital-analog conversion module, which is used for connecting the FPGA module and multi-channel analog audio signals, sampling digital audio signals from the multi-channel analog audio signals according to preset control instructions and sending the signals to the FPGA module, and converting the digital audio signals received from the FPGA module into analog audio signals and sending the analog audio signals to the outside; a serial port interface module, which is used for connecting the FPGA module and a serial port peripheral, converting the voltage of the serial port signals output by the FPGA module into the standard voltage of the serial port signals, and converting the voltage of the serial port signals input to the FPGA module into the I / O pin voltage of the FPGA module; a parallel port acquisition control module, which is used for connecting the FPGA module and a parallel port peripheral, reading the parallel port level state of the parallel port peripheral, converting the voltage of the parallel port level state of the parallel port peripheral into the I / O pin voltage of the FPGA module, and sending the I / O pin voltage to the FPGA module; and reading the parallel port level state of the FPGA module, converting the voltage of the parallel port level state of the FPGA module into the standard voltage of the parallel port signals, and outputting the standard voltage to the parallel port peripheral.

2. The radio access gateway apparatus of claim 1, wherein, The FPGA module specifically comprises: The group packaging unit is used for unpacking the received private UDP message into serial port data, parallel port data and digital audio data, sending the serial port data to the universal asynchronous receiving / transmitting unit, sending the parallel port data to the parallel port signal receiving / transmitting unit, and sending the digital audio data to the audio codec unit; and is used for packaging the received serial port data, parallel port data or digital audio data into a private UDP message and sending the private UDP message to the CPU module. The audio codec unit is used for decompressing the digital audio data received from the group packaging unit into a digital audio signal and sending the digital audio signal to the outside, and compressing the digital audio signal received from the outside into digital audio data and sending the digital audio data to the group packaging unit. The universal asynchronous receiving / transmitting unit is used for packaging the serial port data received from the group packaging unit into a serial port signal according to a serial port communication protocol and sending the serial port signal to the outside, and analyzing the serial port signal received from the outside according to the serial port communication protocol into serial port data and sending the serial port data to the group packaging unit. The parallel port signal receiving / transmitting unit is used for converting the parallel port data received from the group packaging unit into the level state of the parallel port output pin and outputting the level state to the outside, and reading the level state of the parallel port input pin and converting the level state into parallel port data and sending the parallel port data to the group packaging unit.

3. The radio access gateway apparatus of claim 2, wherein, The FPGA module further comprises a phase-locked loop unit, which is used for dividing the clock source signal into a bit clock frequency, an audio sampling frequency and a working clock frequency of the digital audio signal according to a preset control instruction.

4. The radio access gateway apparatus of claim 1, wherein, The CPU module specifically comprises: The first network port unit is used for connecting the FPGA module and realizing the receiving and sending of the private UDP message. The second network port unit is used for connecting the Ethernet control module and realizing the receiving and sending of the audio RTP media stream digital signal, the serial port digital signal and the parallel port digital signal. The media stream processing unit is used for unpacking the audio RTP media stream digital signal received from the second network port unit into a private UDP message, sending the private UDP message to the first network port unit through the control unit, and packing the UDP message received from the first network port unit into an audio RTP media stream digital signal and sending the audio RTP media stream digital signal to the second network port unit through the control unit. The control unit is used for unpacking the serial port digital signal and the parallel port digital signal received from the second network port unit into a private UDP message and sending the private UDP message to the first network port unit, and packing the private UDP message received from the first network port unit into a serial port digital signal and a parallel port digital signal and sending the serial port digital signal and the parallel port digital signal to the second network port unit.

5. The radio access gateway apparatus of claim 4, wherein, The CPU module further comprises an interaction unit, which is used for converting the interaction control signal received from the outside into interaction control data and sending the interaction control data to the control unit, and converting the interaction control data received from the control unit into an interaction control signal and sending the interaction control signal to the outside.

6. The radio access gateway apparatus of claim 4, wherein, The CPU module further comprises a parallel port unit, which is used for realizing the information interaction with a parallel port peripheral device.

7. The radio access gateway apparatus of claim 1, wherein, Further comprising: The filtering module is connected with the audio digital-to-analog conversion module and the multi-channel analog audio signal, and is used for filtering the input analog audio signal according to a preset control instruction.

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