Jitter compensation calibration

Abstract

The embodiment of the invention relates to jitter compensation calibration. According to one embodiment, a method for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter is presented. The method includes: receiving a digital signal corresponding to a voltage or a current of a transmitter coil in a wireless power system implemented with frequency jitter; iteratively adjusting a counter value associated with a jitter table of the local oscillator; wherein for each iteration, the method comprises generating an in-phase (I) component and a quadrature (Q) component using a local oscillator, calculating a metric based on the I component and the Q component, and storing a counter value if the calculated metric exceeds a previously stored optimal metric; and configuring the local oscillator with the stored counter value associated with the optimal metric.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to electronic devices, and in particular embodiments, to calibrating a dither-compensated down conversion mixer for amplitude shift keying (ASK) demodulators in a wireless power transmitter. BACKGROUND

[0002] In wireless power transfer, inductive charging has emerged as a useful technique for transmitting energy from a transmitter to a receiver. Inductive charging utilizes the principle of inductive coupling (also known as mutual inductance) between two coils (one in each terminal) to facilitate power transfer and communication between the transmitter and the receiver. The transmitter can be a battery charger, while the receiver can be a device such as a smartphone or a sensor. To enable bidirectional communication, the receiver can employ backscatter modulation, which involves imposing amplitude shift keying (ASK) modulation on the current or voltage in the primary coil by changing the load impedance. To operate effectively, the integrated driver within the transmitter can include circuitry that can demodulate and recognize incoming messages. SUMMARY

[0003] Technical advantages are generally achieved by embodiments of the present disclosure, which describe calibrating a dither-compensated down conversion mixer for amplitude shift keying (ASK) demodulators in a wireless power transmitter.

[0004] A first aspect relates to a method for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter. The method comprises receiving a digital signal corresponding to a voltage or current of a transmitter coil in a wireless power system implemented with frequency dithering; iteratively adjusting a counter value associated with a dither table of the local oscillator; wherein for each iteration, the method comprises generating an in-phase (I) component and a quadrature (Q) component using the local oscillator, calculating a metric based on the I component and the Q component, and storing the counter value if the calculated metric exceeds a previously stored best metric; and configuring the local oscillator with the stored counter value associated with the best metric.

[0005] The second aspect relates to a circuit for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter. The circuit includes: an analog-to-digital converter (ADC) configured to receive a signal corresponding to the voltage or current of a transmitter coil in a wireless power system implemented using frequency jitter; a local oscillator configured to generate in-phase (I) and quadrature (Q) components based on a counter value associated with a jitter table; and processing circuitry configured to iteratively adjust the counter value, calculate a metric based on the I and Q components for each iteration, and store the counter value if the calculated metric exceeds a previously stored optimal metric, wherein the local oscillator is further configured to use the stored counter value associated with the optimal metric for subsequent operations.

[0006] The third aspect relates to a wireless power system. This wireless power system includes: a transmitter coil; and an amplitude shift keying (ASK) demodulator circuit coupled to the transmitter coil and configured to demodulate a backscattered modulated signal. The ASK demodulator circuit includes: a local oscillator implemented using frequency jitter; and a calibration circuit configured to: receive a digital signal corresponding to a voltage of the transmitter coil; iteratively adjust a counter value associated with a jitter table of the local oscillator; and configure the local oscillator using a stored counter value associated with an optimal metric. For each iteration, the calibration circuit is configured to: generate in-phase (I) and quadrature (Q) components using the local oscillator; calculate a metric based on the I and Q components; and store the counter value if the calculated metric exceeds the previously stored optimal metric.

[0007] The embodiments can be implemented in hardware, software, or any combination thereof. Attached Figure Description

[0008] To gain a more complete understanding of this disclosure and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This is an example of a wireless power system;

[0010] Figure 2 This is the receiving device in the embodiment;

[0011] Figure 3 This is the transmitting device in the embodiment;

[0012] Figure 4 This is a schematic diagram of the sensing circuit in an embodiment;

[0013] Figure 5 This is a block diagram of the PWM jitter timer circuit in the embodiment;

[0014] Figure 6This is a block diagram of the signal processing chain in an embodiment;

[0015] Figure 7 It is used for targeting Figure 6 A flowchart illustrating an embodiment of the initialization routine for the signal processing chain;

[0016] Figure 8 This is a flowchart of an embodiment method that can be implemented to calibrate a local oscillator;

[0017] Figure 9 This is a block diagram of the signal processing chain in an embodiment;

[0018] Figure 10 This is a flowchart of a method for implementing a local oscillator calibration embodiment;

[0019] Figure 11 This is a block diagram of the signal processing chain in an embodiment;

[0020] Figure 12 A flowchart of an embodiment method for calibrating a local oscillator; and

[0021] Figure 13 This is a block diagram of the signal processing chain in an embodiment. Detailed Implementation

[0022] This disclosure provides numerous applicable inventive concepts that can be embodied in a variety of specific contexts. Specific embodiments are provided only to illustrate particular configurations and do not limit the scope of the claimed embodiments. Unless otherwise stated, features from different embodiments may be combined to form other embodiments. Various embodiments are illustrated in the accompanying drawings, wherein identical components and elements are identified by the same reference numerals, and repeated descriptions are omitted for brevity.

[0023] Variations or modifications described in one embodiment may also be applicable to other embodiments. Furthermore, various changes, substitutions, and alterations are possible without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0024] While the inventive aspects are primarily described in the context of Qi-compliant wireless power systems and amplitude shift keying (ASK) modulation, it should be understood that these inventive aspects are also applicable to any other type of amplitude modulation (AM) scheme or similar coding scheme. Furthermore, embodiments of the invention can operate without conforming to the Qi standard.

[0025] In wireless power transmission systems, a power receiver can communicate with a power transmitter using backscatter modulation (e.g., ASK modulation). The transmitter can employ a square wave generated by a PWM (Pulse Width Modulation) which is filtered to produce a sinusoidal signal in the power transmitter coil. This sinusoidal signal induces a sinusoidal signal in the power receiver coil and serves as the carrier for backscatter modulation-based communication. The carrier can be subjected to frequency jitter to amplify signal energy and reduce peak transmission. However, jitter introduces interference during demodulation.

[0026] Embodiments of this disclosure present a method for calibrating a local oscillator with frequency jitter, designed for use in the mixer of an amplitude shift keying (ASK) demodulator. The proposed calibration method integrates hardware demodulation components with firmware-controlled processes to optimize demodulator performance.

[0027] In this embodiment, the firmware is responsible for controlling the activation and deactivation of the analog-to-digital converter (ADC), selecting initial configuration parameters for the local oscillator, and calculating calibration metrics to evaluate the quality of each setup. The iterative approach allows the wireless power system to systematically explore various oscillator configurations.

[0028] This disclosure advantageously provides a calibration process for a local oscillator that accurately simulates the jitter pattern of an input external signal on a sample-by-sample basis. By closely aligning the behavior of the local oscillator with the jitter pattern of the external signal, the proposed method significantly reduces interference caused by frequency jitter in the demodulated signal. Reduced jitter-related interference enhances the overall quality and reliability of the ASK demodulation process, particularly in applications where accurate signal interpretation is advantageous, such as communication interfaces in wireless power delivery systems.

[0029] This disclosure addresses this problem by implementing a calibration routine that identifies the optimal initial settings for the local oscillator counter. This calibration routine ensures proper alignment between the sine wave sampled by the ADC of the power transmitter and the sine wave generated in the ASK demodulator circuitry of the power transmitter. The calibration process maps the delay between the PWM-generated signal and the ADC-sampled signal onto the address difference of the jitter table pointer used by the ASK demodulator circuitry and the PWM timer circuitry.

[0030] In this embodiment, the calibration algorithm operates during the quiet period between ASK communications. It iteratively tests different initial settings for the local oscillator, calculates metrics based on spectral analysis of the down-converted signal, and selects the setting that maximizes the DC component while minimizing jitter interference. This setting selection is achieved by analyzing the energy distribution between the DC component and the jitter fundamental frequency in the demodulated signal spectrum.

[0031] In the embodiments, existing hardware in the ASK demodulator circuitry (such as numerically controlled local oscillators and cascaded integrator comb (CIC) filters) and firmware processing are used to calculate calibration metrics. Various implementations have been proposed, including full-spectrum analysis and simplified DC-only solutions. Calibration can be performed using samples from different stages of the demodulation chain, allowing for flexibility across different hardware architectures.

[0032] Advantageously, embodiments of this disclosure are able to map external delays onto variations in the counter of the jitter-compensated local oscillator. This mapping ensures proper alignment between the external signal and the local oscillator for efficient demodulation. Furthermore, the calibration process is advantageously independent of the ASK modulation depth, making it more versatile and robust under different signal conditions. Additionally, the calibration of the local oscillator significantly reduces interference associated with the jitter fundamental frequency.

[0033] By optimizing the alignment between the local oscillator and the received signal, embodiments of this disclosure improve the signal-to-noise ratio (SNR) of the demodulated signal and enhance the overall performance of ASK demodulation in wireless power delivery systems. The proposed method eliminates the need for additional hardware filters and provides a more efficient solution than a fixed averaging frequency for the local oscillator. These and additional details will be further elaborated below.

[0034] Figure 1 An embodiment of a wireless power system 100 is illustrated, which may also be referred to as a wireless charging system. The system includes a transmitting device 110 and a receiving device 120, which may (or may not) be arranged as shown. The transmitting device 110 generates wireless energy 130 and transmits the wireless energy 130 to the receiving device 120.

[0035] The transmitting device 110 may be a base station, such as a charging pad, which provides inductive power to the receiving device 120. The receiving device 120 may be, for example, a mobile device, tablet computer, mobile phone, wearable communication device (e.g., smartwatch), digital pen, wireless headphones, toothbrush, sensor, Internet of Things (IoT) device, etc. The receiving device 120 is the consumer of inductive power.

[0036] Transmitting device 110 includes transmitter coil 112 (L TX The receiving device 120 includes a receiver coil 122 (L). RX Each coil or winding can be a loop antenna or a magnetic antenna. The coil can have a physical magnetic core (e.g., a ferrite core) or an air core. The coil can be implemented as an antenna bar or using Litz wire. The resonant frequency of each coil is based on the shape and size of the loop or coil. In some embodiments, additional capacitance and inductance can be added to each coil to create a resonant structure at the desired resonant operating frequency.

[0037] In this embodiment, wireless power 130 is transmitted from transmitting device 110 to receiving device 120 via resonant inductive coupling between transmitter coil 112 and receiver coil 122. Receiving device 120 can use the power to charge a rechargeable battery or directly power its internal components.

[0038] Figure 2 An embodiment of a receiving device 120 is shown. The receiving device 120 includes a receiver coil 122, a power charging circuit 200, and a load 128. The power charging circuit 200 includes a rectifier 124 and a regulator 126. The receiving device 120 may include... Figure 2 Additional components not described herein include long-term storage devices (e.g., non-volatile memory), non-transitory computer-readable media, one or more antenna elements, drivers, demodulators, modulators, filter circuits, and impedance matching circuits.

[0039] Rectifier 124 converts the alternating current (AC) voltage at receiver coil 122 into a direct current (DC) voltage. It can be any type of rectifier, such as a low-impedance synchronous rectifier with full-wave or half-wave rectification, or an active rectifier. In this embodiment, rectifier 124 can be a bridge rectifier; however, other types of rectifiers are also considered.

[0040] Regulator 126 receives voltage (V) from rectifier 124 RECT Then adjust the voltage to maintain a constant output voltage (V) at the load 128. OUT ). Regulator 126 can be any type of voltage regulator, such as a linear regulator (e.g., a low dropout (LDO) linear regulator). In some embodiments, rectifier 124 and regulator 126 can be part of a switch-mode power supply (SMPS) circuit.

[0041] As shown in the figure, load 128 is the primary beneficiary of the transmitted wireless energy 130. Load 128 can be a charge storage device, such as a battery. For example, load 128 can be a mobile phone battery or a smartwatch. For example, transmitting device 110 can be a charging pad, and the smartwatch can be placed on the charging pad. The charging pad transmits wireless power to the smartwatch's battery without requiring a cable connection between the two devices.

[0042] Several interface standards have been developed to standardize wireless power delivery and related functions. One such interface standard is Qi, which is promoted by the Wireless Power Consortium (WPC). Qi and similar standardized protocols can be used to define the communication interface used to control power delivery in wireless power system 100. For example, receiving device 120 can request changes (e.g., increase, decrease, pause, etc.) related to the transmitted wireless energy 130 from transmitting device 110.

[0043] Inductive power transfer mechanisms can also be used for communication between transmitting device 110 and receiving device 120. For example, receiving device 120 can notify transmitting device 110 when the charging process is complete. This communication can be facilitated by a technique known as backscatter modulation, as specified in the Qi standard for inductive wireless power transfer.

[0044] In practice, receiving device 120 can change its load impedance, for example, by changing the impedance of load 128. The change in impedance causes an observable change in the amplitude of the current or voltage in transmitter coil 112, allowing information to be transmitted from receiving device 120 to transmitting device 110.

[0045] Figure 3 An embodiment of a transmitting device 110 is illustrated. The transmitting device 110 includes a microcontroller 302, additional circuitry 306, and a transmitter coil 112, which may (or may not) be arranged as shown. The transmitting device 110 may include a memory for storage. In one embodiment, the microcontroller 302 includes embedded memory. In another embodiment, a PWM timer circuit 304 is embedded within the microcontroller 302.

[0046] Typically, digital modulation schemes use a finite number of different signals to represent digital data. ASK modulation refers to a modulation scheme in which digital data is represented as variations in the amplitude of a carrier wave.

[0047] In ASK-based communication, transmitting device 110 generates a carrier signal. This carrier signal is typically a sine wave generated by filtering a square wave produced by PWM. The digital information to be transmitted modulates the amplitude of the carrier signal.

[0048] In one embodiment, a PWM timer circuit 304 embedded in the microcontroller 302 generates a PWM square wave based on programmed parameters. The microcontroller 302 can precisely control the frequency, duty cycle, and timing of the square wave. In a system employing jitter, the microcontroller 302 can also manage the periodic changes in the PWM frequency according to preset jitter patterns stored in its memory.

[0049] At transmitting device 110, the PWM signal may be subject to controlled, periodic disturbances in its period / frequency, known as jitter. Jitter causes similar periodic variations in the sinusoidal current and voltage at transmitter coil 112 (i.e., periodic variations in the ASK carrier frequency). Jitter spreads the spectrum of the PWM signal across multiple frequencies, thereby effectively reducing the peak values ​​associated with the main harmonics of the square wave.

[0050] Jitter distributes signal energy over a wider frequency range, thus extending the energy over a wider harmonic range. It particularly affects frequencies with non-zero contributions in the spectrum of non-jitter signals, such as odd harmonics of square waves, whose spectral contribution is reduced by jitter. This distribution minimizes overall electromagnetic interference, making power transfer more compliant with EMC standards and reducing peak emissions. Therefore, jitter can reduce electromagnetic interference emissions in power transfer mechanisms.

[0051] The PWM timer circuit 304 employs frequency jitter by slightly altering the signal frequency according to a predetermined pattern stored in a jitter table. The modulated and jittered signal is sent to the transmitter coil, generating an electromagnetic field for power transfer and data communication. This method allows for simultaneous power transfer and data transmission, with the data largely dependent on the power transfer signal.

[0052] After the PWM timer circuit 304 generates a digital square wave, this square wave passes through an additional circuit system 306 (such as a power inverter and a filter) to generate a sine wave for the induced power transfer process. The receiving device 120 rectifies the induced signal at the receiver coil 122, and the induced signal charges the receiving device 120. In this embodiment, resonant filtering is performed by a capacitor and the transmitter coil 112.

[0053] Figure 4 A schematic diagram of an embodiment of sensing circuit 400 is shown, which may be located in transmitting device 110 for backscatter modulation detection. Sensing circuit 400 is coupled to terminals of transmitter coil 112. Sensing circuit 400 includes sensing resistor (R) 402, amplifier 404, analog-to-digital converter (ADC) 406, ASK demodulator circuitry 408, and interface 414, which may (or may not) be arranged as shown. Sensing circuit 400 may also include additional components not shown in the figure.

[0054] When the receiving device 120 modulates its load 128 (e.g., by changing its impedance), this causes a detectable change in the current or voltage of the transmitter coil 112. These changes are typically small variations in the current or voltage at the transmitter coil 112. The sensing circuit 400 continuously monitors the characteristics of the transmitter coil 112, such as the current or voltage.

[0055] The sensing resistor 402 is arranged in series with the transmitter coil 112 to detect these changes. The voltage across the sensing resistor 402 is proportional to the coil current. The amplifier 404 amplifies the voltage across the sensing resistor 402 and feeds it into the ADC 406.

[0056] In this embodiment, a dedicated timer circuit within the microcontroller 302 sends an ADC trigger (ADC_TRIG) signal to the ADC 406. This signal has two main functions. First, when the trigger mode is selected and enabled, the enable edge (rising or falling) of the ADC trigger signal initiates a hardware-based transition. Second, regardless of the mode, the enable edge of the ADC trigger signal marks subsequent ADC groups using the START flag. A synchronization mechanism ensures that ADC sampling always begins from a consistent point in the jitter mode, regardless of the ADC's operating state.

[0057] Synchronization is advantageous when ADC 406 is temporarily disabled, such as during FSK communication from transmitting device 110 to receiving device 120 or before metric calculations. When ADC 406 is reactivated, the ADC trigger signal ensures that sampling is recovered from the same relative point in the jitter mode. This consistency allows the integrity of the jitter compensation demodulation process to be maintained.

[0058] Furthermore, by generating ADC trigger signals with time periods that match the jitter pattern, each iteration of the calibration or demodulation process is guaranteed to work using the same sample set. Repeatability facilitates accurate comparisons between different calibration attempts and ensures that the optimization process is based on consistent data across multiple iterations.

[0059] ADC 406 converts the amplified analog voltage across sense resistor 402 into a digital signal. In one embodiment, ADC 406 is coupled to ASK demodulator circuitry 408 via interface 414. In another embodiment, interface 414 relates to both a serial data interface and a pre-conditioned digital signal processing unit responsible for removing residual DC components, bandpass filtering near the ASK carrier frequency, or windowing the input signal. In another embodiment, interface 414 is a four-channel Serial Peripheral Interface (SPI4L) followed by offset removal and a resonant-like digital filter. In another embodiment, in response to ADC 406 being enabled, the rising edge of the ADC trigger signal data indicates continuous communication of ADC packets containing a digital signal corresponding to the amplified analog voltage sensed at sense resistor 402.

[0060] ASK demodulator circuit 408 includes a mixer 410 and a local oscillator 412. In an embodiment, ASK demodulator circuit 408 includes additional components not shown, such as a low-pass filter, a decimator, and other signal processing components for ASK demodulation. In an embodiment, ASK demodulator circuit 408 is embedded within microcontroller 302.

[0061] In this embodiment, the local oscillator 412 is a numerically controlled oscillator circuit. In this embodiment, the local oscillator 412 is implemented using a coordinate rotating digital computer (CORDIC). CORDIC is an iterative algorithm for calculating fixed-point trigonometric functions, utilizing algebraic sums, shifts, sign checks, and most multiplications. It should be understood that the functionality of the mixer 410 and the local oscillator 412 can be implemented using other signal processing components, not limited to the CORDIC / Q generator circuit.

[0062] The digital signal from ADC 406 is demodulated by ASK demodulator circuit 408. ASK demodulator circuit 408 analyzes the amplitude variations of the digital signal to extract the digital information transmitted by receiving device 120. ASK demodulator circuit 408 can down-convert the information signal to baseband using mixer 410. This process typically involves an input modulated signal containing both in-phase (I) and quadrature (Q) components. Mixer 410 multiplies the digital signal from ADC 406 with a local oscillator signal generated by local oscillator 412. The local oscillator signal from local oscillator 412 is typically generated to match the carrier frequency of the received signal.

[0063] Mixer 410 effectively shifts the frequency of the information signal down to baseband, where the original data is easier to process and extract. The resulting baseband signal retains its I and Q components, which represent the real and imaginary parts of the complex signal, respectively. The baseband I and Q signals contain amplitude variations that are encoded in ASK modulation to represent the transmitted information. ASK demodulator circuit 408 is capable of processing the baseband I and Q signals to recover the original digital data, for example, by examining the amplitude variations of the complex signal formed by the I and Q components.

[0064] In ASK demodulation, frequency jitter introduces additional interference that can affect the demodulation process. In systems employing jitter, the ASK demodulator circuit 408 considers jitter patterns when interpreting the received signal. It uses knowledge of jitter patterns to correctly interpret amplitude variations caused by load modulation of the receiver, distinguishing these amplitude variations from those caused by jitter from the transmitting device 110 during signal transmission.

[0065] In this embodiment, the local oscillator 412 includes an I / Q generator circuit. The I / Q generator circuit is configured to efficiently generate the in-phase (I) and quadrature (Q) components of a sinusoidal signal. The I and Q components represent a reference signal that should be matched to the carrier wave (including its jitter pattern) of the input ASK signal. The I / Q generator circuit produces the sine and cosine waveforms required for demodulation. In this embodiment, the I / Q generator circuit is a CORDIC I / Q generator circuit.

[0066] The local oscillator 412 may include additional components such as a phase accumulator for tracking the current phase (including jitter adjustment); a jitter control circuitry system for managing jitter modes based on a jitter table and counter; or control logic for managing the overall operation and synchronization of the local oscillator components.

[0067] Mixer 410 is positioned after local oscillator 412 in the signal processing chain. It performs the multiplication of the input ASK signal with the I and Q signals generated locally from the I / Q generator circuit. The multiplication process effectively shifts the frequency of the input ASK signal down to baseband, thereby separating the modulation information from the carrier.

[0068] By following the jitter pattern, the local oscillator 412 improves ASK demodulation and removes jitter interference. This method is feasible because the PWM timer circuit 304 and the ASK demodulator circuit 408 are components embedded within the transmitting device 110, and the local oscillator 412 is capable of following the jitter pattern.

[0069] Figure 5 A block diagram of an embodiment of the PWM jitter timer circuit 500 is shown. The PWM jitter timer circuit 500 is used by the PWM timer circuit 304 to implement frequency jitter. In addition, the local oscillator 412 of the ASK demodulator circuit 408 replicates the jitter pattern generated by the PWM jitter timer circuit 500, which is used during ASK demodulation.

[0070] The PWM jitter timer circuit 500 includes timer logic circuit 502, automatic reload register (ARR) 504, jitter table 506, PWM index counter 508, first adder 514, and second adder 516, which may (or may not) be arranged as shown in the figure. The PWM jitter timer circuit 500 may include additional components not shown in the figure. The PWM jitter timer circuit 500 may be implemented within microcontroller 302 or PWM timer circuit 304.

[0071] Dynamic frequency jitter can be implemented using a jitter table 506 to introduce minute variations in the carrier frequency. The jitter table 506 can be implemented as a register or embedded memory within the microcontroller 302. In an embodiment, each entry in the jitter table 506 includes an offset field 522 and a slot repetition field 524. For example, if each entry is 8 bits, the first two bits can be assigned to the slot repetition field 524, and the next six bits can be assigned to the offset field 522. In an embodiment, the offset field 522 contains signed entries.

[0072] The offset field 522 is added to the ARR 504 via either the first adder 514 or the second adder 516 to obtain the jittered ARR value. The slot repetition field 526 determines how many switching cycles (e.g., 1, 2, or 4) the offset field 522 should use.

[0073] In an embodiment, the mode length register (P) LENGTH This can be used to set the effective length of the jitter table 506. For example, if the length of the jitter table 506 is 32 bits, the pattern length register is set to 5 bits (i.e., 32 equals 2). 5 ).

[0074] In this embodiment, the PWM timer circuit 304 uses a counter (e.g., a register) to manage the jitter mode. For example, the PWM timer circuit 304 utilizes a PWM index counter 508 to track the current position in the jitter table, a PWM repetition counter 510 to track how many times the current table entry has been used (i.e., how many times the current offset has been applied within its allocated time slot), and a PWM period counter 512 (i.e., a standard PWM count) that increments with each clock cycle and is compared with the ARR to determine the end of the switching cycle.

[0075] In this embodiment, the value of PWM index counter 508 is PWM_IDX, the value of PWM repetition counter 510 is PWM_REP, and the value of PWM period counter 512 is PWM_CNT.

[0076] In one embodiment, the local oscillator 412 replicates the jitter pattern at the PWM timer circuit 304. In another embodiment, the counters of the PWM timer circuit 304 (e.g., PWM index counter 508, PWM repetition counter 510, and PWM period counter 512) are replicated for the local oscillator 412.

[0077] The value of ARR 504 is modified during each switching cycle. As mentioned above, the jitter table 506 includes an offset field containing a signed offset that is added to the base ARR value. For increased flexibility, each offset can be applied to up to four consecutive switching cycles, controlled by a repeating field within each table entry.

[0078] The timer logic circuit 502 applies the current offset from the jitter table 506 to the ARR 504, thereby modifying the PWM frequency.

[0079] The sinusoidal signal sampled by sensing circuit 400 is delayed relative to the square wave generated by PWM timer circuit 304. For example, the sampled signal may be delayed by the analog circuitry of the wireless power transmitter and by the filter in interface 414. Therefore, during demodulation, ASK demodulator circuit 408 must account for this delay to correctly interpret frequency jitter.

[0080] In this embodiment, the PWM timer circuit 304 and the local oscillator 412 use a jitter table 506, but with separate pointers. Due to the aforementioned delay, the pointer for the PWM timer circuit 304 and the pointer for the local oscillator 412 point to different table entries. Therefore, the pointer for the PWM timer circuit 304 is offset relative to the pointer for the local oscillator 412 by a time constant address difference. For example, at any given moment, the pointer for the PWM timer circuit 304 can be several entries ahead of the pointer for the local oscillator 412.

[0081] Embodiments of this disclosure provide a method for identifying and initializing the operation of a local oscillator 412 to ensure proper alignment of a sine wave sampled by sensing circuitry 400. In an embodiment, the signal that begins to be sampled by ADC 406 (e.g., an ADC trigger signal) has the same time period as the signal associated with the jitter mode. In an embodiment, the time constant address difference between the pointers for PWM timer circuitry 304 and local oscillator 412 is associated with the address difference between the pointers for PWM timer circuitry 304 and local oscillator 412.

[0082] Werner's formula (i.e., the trigonometric product to sum formula) describes how the product of two sine waves can be expressed as the sum of other sine functions. Specifically, Werner's formula states that the product of two sine waves with frequencies f1 and f2 can be expressed as... Where A1 and A2 are the amplitudes of two sine waves, f1 and f2 are their frequencies, φ1 and φ2 are their phase shifts, and t is time.

[0083] Therefore, multiplying two sine waves will produce two new sine waves: (1) the beat frequency component at |f1-f2| and (2) the mirror frequency component at f1+f2.

[0084] In the context of signals with frequency jitter, Werner's formula exhibits a dynamic aspect. When two sine waves being multiplied are subjected to frequency jitter, their instantaneous frequencies f1(t) and f2(t) are not constant, but vary with time according to a predetermined pattern. As a result, the beat frequency, which is the difference between these two frequencies, also changes with time. The time-varying beat frequency means that the output of mixer 410 (which multiplies the two sine wave signals) is not a simple DC component or a single-frequency sine wave, but a more complex signal with dynamically changing frequency content.

[0085] When the frequency of the local oscillator 412 is perfectly aligned with the frequency of the digital signal from the ADC 406, the beat frequency becomes 0Hz, thereby generating the DC component (the desired baseband signal) and eliminating jitter interference. Subsequent low-pass filtering typically removes the image frequency component.

[0086] Therefore, the degree of alignment between the local oscillator 412 and the digital signal from the ADC 406 affects the quality of the demodulated output. When the jitter patterns of these two signals are well aligned, the mixer 410 produces an output with unique characteristics. Specifically, a higher degree of alignment causes the beat component (representing the difference between the two input frequencies) in the mixer output to be more tightly concentrated near the DC (0Hz) frequency. This concentration at DC is desirable because it indicates that the baseband signal of interest is preserved. At the same time, improved alignment leads to a reduction in jitter interference, which manifests as unwanted frequency components in the mixer output. These unwanted components, when present, can interfere with the accurate recovery of the transmitted information. Therefore, achieving better alignment not only enhances the desired signal by concentrating energy at DC but also minimizes the interference effects of jitter, ultimately resulting in more reliable and efficient ASK demodulation in the wireless power system 100.

[0087] Traditionally, local oscillators operating at a fixed "average" frequency without jitter have been utilized. Conventional methods rely on additional band-stop or notch filters to remove harmonics associated with jitter interference from the received signal. While these methods mitigate some problems caused by frequency jitter, they have significant drawbacks. If a dedicated notch filter is integrated into the ASK demodulator architecture, it requires additional chip area, increasing the overall device size and potentially cost. Alternatively, if a programmable filter, such as an infinite impulse response (IIR) filter, is used to implement the notch filter, this reduces the available degrees of freedom for low-pass filtering. These limitations can impair the overall filtering performance of the demodulator, potentially leading to suboptimal signal processing.

[0088] This disclosure describes a calibration technique for a local oscillator 412. The proposed calibration process aims to optimize the settings of the local oscillator 412 by focusing on two key aspects of the down-converted signal (especially in the absence of amplitude modulation). First, it attempts to maximize the DC component of the down-converted signal, which represents the desired baseband information. Second, it strives to minimize the jitter component, which manifests as unwanted distortion in the down-converted signal. By adjusting the parameters of the local oscillator 412 (such as its initial phase and jitter mode), the calibration algorithm iteratively searches for the configuration that best achieves these two objectives.

[0089] The proposed method advantageously ensures that the ASK demodulator circuit 408 is optimally prepared to extract transmitted information with minimal distortion from the jitter process when the actual amplitude-modulated signal is received. In the embodiment, calibration is performed during periods of no communication, allowing the wireless power system 100 to adapt to the specific characteristics of the wireless power transmission channel without interfering with data transmission.

[0090] In this embodiment, the calibration process for the local oscillator 412 involves analyzing the I and Q components of the down-converted signal. The firmware processes samples to calculate their Discrete Fourier Transform (DFT) spectra at specific target frequencies (i.e., DC and jitter harmonics). For each frequency of interest, with element I... f and upper limit Q f Complex vectors are generated.

[0091] The energy at each frequency can be estimated by calculating the norm square of the vector, and is expressed as... The recommended calibration uses a universal metric (C), which is calculated as in It is the energy contribution at DC, and It is the energy contribution of the k-th dithering harmonic, where the sum is This includes contributions from M jitter harmonics within the target bandwidth of the ASK signal, typically up to five times the bit rate.

[0092] For simplicity, only the fundamental frequency jitter can be considered. In this case, the metric simplifies to Furthermore, when focusing only on the DC component, this metric can be further simplified to

[0093] Therefore, the goal of the calibration process is to maximize the difference between the lengths of two vectors: one representing the DC component and the other representing the jitter fundamental frequency. Maximization aims to achieve the best possible alignment between the local oscillator 412 and the input signal from the ADC 406, thereby optimizing demodulation performance. The process iteratively adjusts the local oscillator parameters to find the configuration that produces the highest metric, indicating the most effective suppression of jitter interference and enhancement of the desired signal component.

[0094] Figure 6 A block diagram of an embodiment signal processing chain 600 is shown. The signal processing chain 600 includes an I / Q generator circuit 602, a filtering and first-in-first-out (FIFO) buffer circuit 604, and a firmware processing circuit 622, which may (or may not) be arranged as shown. The signal processing chain 600 may also include additional components not shown in the figure, such as bandpass filters, IIR filters, scalars, input adapters, counters, amplifiers, edge detection circuitry, and bit decoders.

[0095] In this embodiment, the I / Q generator circuit 602 is implemented within the local oscillator 412. It receives ASK samples from the ADC 406 or interface 414 and generates the in-phase (I) and quadrature (Q) components of the input sine wave signal. The I and Q components represent a reference signal that should be matched to the carrier wave of the input ASK signal (including its jitter pattern). The I / Q generator circuit 602 produces the sine and cosine waveforms required for demodulation.

[0096] The output of the I / Q generator circuit 602 is coupled to a filter and FIFO buffer circuit 604, which receives both the I and Q components. In an embodiment, the filter and FIFO buffer circuit 604 interfaces with the hardware demodulation chain and the firmware processing circuit 622. The filter and FIFO buffer circuit 604 enables the calibration algorithm to access the necessary signals from various points in the hardware demodulation chain, thereby facilitating an iterative process to find the optimal settings for the local oscillator 412 for improved ASK demodulation.

[0097] In an embodiment, the filtering and FIFO buffer circuit 604 includes an optional first filter 610, an optional second filter 612, a first ACC & W:1 (ACC & W:1) circuit 614, a second ACC & W:1 circuit 616, a first FIFO buffer 618, and a second FIFO buffer 620.

[0098] In an embodiment, a first filter 610 and a second filter 612 filter the input signal. The first filter 610 and the second filter 612 can be implemented as infinite impulse response (IIR) filters. In an embodiment, the first filter 610 and the second filter 612 are low-pass filters that attenuate high-frequency components of the input signal to remove noise and unwanted harmonics. The filtering action helps to shape the frequency response of the demodulated signal, optimizing it for subsequent processing stages. The first filter 610 and the second filter 612 also provide bandwidth limiting, focusing on the frequency range containing the desired information, while improving the overall signal-to-noise ratio by removing out-of-band noise. Furthermore, the first filter 610 and the second filter 612 can provide anti-aliasing functionality by limiting the signal bandwidth.

[0099] Each ACC&W:1 circuit is a processing unit capable of performing accumulation and decimation functions. "ACC" stands for accumulator, and "W:1" indicates the decimation rate, where W samples are combined to produce one output sample. Each ACC&W:1 circuit operates by adding W consecutive input samples and outputting the result, effectively reducing the data rate by a factor of W. The primary function of each ACC&W:1 circuit is to perform low-pass filtering and data rate reduction, which helps isolate the desired baseband signal and reduces the computational load on subsequent processing stages. By accumulating samples, it attenuates high-frequency components and noise, while the decimation aspect allows for more efficient signal processing at lower sampling rates. Each ACC&W:1 circuit can be implemented in hardware to ensure real-time processing capabilities. The specific value of W can be adjusted based on system requirements, balancing noise reduction, signal preservation, and the desired output data rate.

[0100] The first FIFO buffer 618 and the second FIFO buffer 620 are coupled to the outputs of the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616, respectively. Each FIFO buffer provides a data storage queue based on a first-in, first-out (FIFO) principle. It temporarily stores samples selected by the multiplexer coupled to it, thereby allowing asynchronous data transfer between the high-speed hardware demodulation chain and the potentially slower firmware processing circuit 622. Each FIFO buffer has a defined depth, determining how many samples it can store before overflowing.

[0101] During calibration, the first multiplexer 606 and the second multiplexer 608 are configured by the firmware processing circuitry 622 to select appropriate signals from the hardware demodulation chain. As samples are generated at the selected points in the hardware demodulation chain, these samples are sequentially written to the first FIFO buffer 618 and the second FIFO buffer 620. When executed by the firmware processing circuitry 622, the firmware is then able to read samples from the first FIFO buffer 618 and the second FIFO buffer 620 at its own pace, thereby ensuring that no data is lost due to timing mismatches between hardware and software components.

[0102] In an embodiment, the filtering and FIFO buffer circuit 604 may include control signals and status flags. For example, the filtering and FIFO buffer circuit 604 may include a FIFO full flag, a FIFO empty flag, and an interrupt signal that can be triggered when the FIFO buffer contains data or reaches a specific fill level. These signals allow the firmware to efficiently manage the data transfer process, read available samples, and process them without constantly polling the hardware.

[0103] The proposed calibration technique ensures optimal alignment of the local oscillator 412 with the digital signal from the ADC 406 or interface 414—the digital signal from the ADC corresponding to the voltage of the transmitter coil 112 in the wireless power system 100, which utilizes frequency jitter. This alignment of the local oscillator 412 with the digital signal from the ADC 406 or interface 414 improves the overall demodulation performance in the wireless power system 100.

[0104] Furthermore, the calibration process for the local oscillator 412 aims to ensure accurate and consistent results under various operating conditions. Since the output of mixer 410 is directly affected by the amplitude of the input sine wave (i.e., the output of the local oscillator 412 and the digital signal from ADC 406), the calibration metric is calculated in the absence of amplitude modulation. This method ensures that the metric results are not biased by variations in carrier amplitude, thus providing a more reliable basis for comparison. Therefore, in this embodiment, the calibration routine is performed during the quiet period between ASK communications. According to the Qi standard for wireless power delivery, this quiet period has a minimum duration of 6 milliseconds and a target duration of 7 milliseconds, providing ample time for the calibration process.

[0105] In this embodiment, the calibration process employs the same low-pass filter settings used in conventional ASK demodulation to maintain consistency with real-world operating conditions. This ensures that the effects of unwanted harmonics are accurately represented during calibration, reflecting the situation present in the actual demodulation scenario. However, the system allows for flexible selection of the low-pass filter if it meets two key criteria: preserving DC and jitter harmonics while adequately attenuating potential aliasing noise harmonics in the baseband. This flexibility allows for filter design optimization based on specific system requirements or constraints.

[0106] In this embodiment, the firmware uses the square of the norm (amplitude) of the complex spectral components to calculate the calibration metric. Advantageously, this approach avoids the computationally intensive square root operations required when using the actual amplitude. By using the square of the norm, the firmware can perform the necessary calculations more efficiently, reducing processing time and potentially lowering power consumption. This optimization is particularly advantageous given the limited time available for calibration during the quiet period and the potential resource constraints of the embedded system.

[0107] Figure 7 A flowchart of an embodiment of method 700 for the initialization routine of signal processing chain 600 is shown. The calibration routine initializes ADC 406, ASK demodulator circuit 408, and filter and FIFO buffer circuit 604. It should be noted that all steps listed in the flowchart of method 700 are not necessarily required and can be optional. Furthermore, changes to the arrangement of steps, the removal of one or more steps and path connections, and the addition of steps and path connections are similarly considered.

[0108] At step 702, if ADC 406 is ON, then it is OFF.

[0109] At step 704, the ASK demodulator circuit 408 is reset, setting an initial value for the counter associated with the jitter meter 506. In this embodiment, the ASK demodulator circuit 408 is reset via a software-generated reset signal. In this embodiment, the initial value of the counter is controlled by firmware.

[0110] In this embodiment, the counters of the ASK demodulator circuit 408 include: an ASKD index counter for tracking the current position in the jitter table 506; an ASKD repetition counter for tracking how many times the current table entry has been used; and an ASKD period counter for counting up to the ARR value for each carrier cycle. In this embodiment, the value of the ASKD index counter is reset to HW_INIT_IDX, the value of the ASKD repetition counter is reset to HW_INIT_REP, and the value of the ASKD period counter is reset to HW_INIT_CNT.

[0111] At step 706, the filtering and FIFO buffer circuit 604 is enabled in debug mode.

[0112] At step 708, the reset signal at ASK demodulator circuit 408 is de-asserted—but ADC406 is not activated.

[0113] At step 710, the microcontroller 302 asserts the ADC trigger signal to start the ADC 406 at the beginning of the PWM jitter mode and demodulate it using the ASK demodulator circuit 408. At the beginning of the PWM jitter mode, the PWM index counter has a value of 0 (i.e., PWM_IDX equals 0), the PWM repeat counter has a value of 0 (i.e., PWM_REP equals 0), and the PWM period counter has a value of 0 (i.e., PWM_CNT equals 0).

[0114] Figure 8 A flowchart of embodiment method 800 is shown, which can be implemented to calibrate local oscillator 412. It should be noted that all steps listed in the flowchart of method 800 are not necessarily required and can be optional. Furthermore, changes to the arrangement of steps, the removal of one or more steps and path connections, and the addition of steps and path connections are similarly considered.

[0115] In an embodiment, method 800 utilizes I-samples and Q-samples output by the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616 to calculate various metrics. In another embodiment, the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616 perform additional low-pass filtering to supplement the initial filtering performed by the first filter 610 and the second filter 612. Furthermore, the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616 combine sample decimation, thereby effectively reducing the data rate of the signal. This data rate reduction converts all subsequent signals into a so-called low-speed domain.

[0116] The first FIFO buffer 618 and the second FIFO buffer 620 facilitate the observation and capture of low-speed I-downconverted and Q-downconverted signals. The FIFO buffers act as an interface between the hardware processing components and the firmware processing circuitry 622. Depending on system requirements, the firmware processing circuitry 622 can be implemented using various processor options such as general-purpose microprocessors or dedicated digital signal processors.

[0117] The advantage of this architecture is that the reduced data rate in the low-speed domain is manageable, ensuring a seamless interface with the firmware processing circuitry 622. This design feature prevents data loss during transmission from hardware components to the firmware processing level, which is crucial for accurate calibration and overall system performance. The combination of hardware filtering, decimation, and buffering, followed by firmware processing, allows for efficient and accurate calibration of the ASK demodulator system.

[0118] At step 802, the first filter 610 and the second filter 612 of the signal processing chain 600 are initialized by setting their coefficients, for example, in preparation for signal processing. In embodiments, any additional filters that may be included in the signal chain... Figure 6 (Not shown in the image) are all initialized.

[0119] At step 804, the filter and FIFO buffer circuit 604 is configured to capture the output from the I and Q components via the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616, thereby enabling the firmware to acquire the demodulator results.

[0120] At step 806, the number of Discrete Fourier Transform (DFT) samples and the corresponding target frequency are selected, for example, by firmware processing circuitry 622. Computational complexity and spectral accuracy can be balanced by selecting an appropriate number of samples and target frequency. A larger number of DFT sample values ​​provides more detailed spectral information, but requires more processing time and resources. The target frequency is typically chosen to capture the necessary signal characteristics, including DC components and associated jitter harmonics, while avoiding aliasing. In an embodiment, the number of DFT samples can be between 20 and 100. In an embodiment, the number of DFT samples is equal to 50.

[0121] The number of DFT samples and the corresponding target frequency help determine the accuracy and resolution of the spectral analysis performed during calibration. Generally, a larger number of DFT samples results in better frequency resolution in the DFT output, allowing for more accurate identification of spectral components. Increased resolution helps distinguish closely spaced frequency components, such as DC components and jitter fundamental frequencies. The choice of target frequency determines which spectral components are analyzed, typically focusing on DC components and jitter harmonics related to the bandwidth of the ASK signal.

[0122] At step 808, the metric associated with the optimal counter setting of the local oscillator 412 is initialized, for example, by firmware processing circuitry 622 to a minimum negative value, thereby establishing a baseline for comparison in the search for the optimal configuration.

[0123] At step 810, method 800 enters a loop that explores various combinations of counter values. In an embodiment, the counter values ​​set by the firmware include an FW index counter value associated with an index value of jitter table 506, an FW repeat counter value associated with a repeat value of jitter table 506, and an FW period counter value associated with a period value of jitter table 506.

[0124] During the exploration sequence, various combined values ​​are provided by, for example, firmware processing circuitry 622 to the FW index counter value, the FW repeat counter value, and the FW period value. At each loop, the value of the ASKD index counter is set to equal the current FW index counter value, the value of the ASKD repeat counter is set to equal the current FW repeat counter value, and the value of the ASKD period counter is set to equal the current FW period counter value.

[0125] Furthermore, an initialization routine is executed in each loop to initialize the ADC 406, the ASK demodulator circuit 408, and the filter and FIFO buffer circuit 604. In an embodiment, the initialization routine may follow method 700.

[0126] Within each loop, samples from both the I and Q channels are processed, with a counter incremented for each channel (i.e., the counter associated with the processed I and Q channels) until the required number of DFT samples is reached. In this embodiment, the I and Q channels are processed in parallel. Once enough samples have been collected, the ADC 406 is stopped, and a DFT-based spectral analysis is performed for the current metric of the loop.

[0127] If the calculated current metric exceeds the best metric found so far (i.e., the metric associated with the best counter setting of the local oscillator 412), the metric associated with the best counter setting of the local oscillator 412 is used when the metric is updated, and the corresponding values ​​for the FW index counter value, FW repeat counter value, and FW period counter value are stored as the best configuration.

[0128] After each iteration, the variables associated with the spectrum calculation are reset, and the process proceeds to the next combination of the FW index counter value, the FW repeat counter value, and the FW period counter value.

[0129] At step 812, after exploring all combinations of FW index counter value, FW repeat counter value, and FW period counter value, the values ​​of ASKD index counter, ASKD repeat counter, and ASKD period counter are set to the FW index counter value, FW repeat counter value, and FW period counter value as determined by the optimal configuration found at step 810, respectively.

[0130] At step 814, the signal processing chain 600 and associated components (e.g., filters, comparators, distance counters, etc.) are configured. In an embodiment, step 814 is performed at step 802.

[0131] At step 816, a final initialization routine is executed to initialize the ADC 406, the ASK demodulator circuit 408, and the filter and FIFO buffer circuit 604. In an embodiment, the initialization routine may follow method 700.

[0132] In this embodiment, the firmware manages various variables, including jitter table indexes, repetition values, and counters, through firmware processing circuitry 622 to explore and track optimal configurations. Method 800 effectively balances hardware operation with firmware control to achieve optimal ASK demodulation performance in the presence of frequency jitter.

[0133] Figure 9 A block diagram of an embodiment signal processing chain 900 is shown. In this embodiment, the signal processing chain 900 introduces a DC-only solution for ASK demodulation and calibration. By leveraging the fact that the DFT for the DC components is simply a sum of samples, the DC components of the I and Q channels are computed using, for example, a cascaded integrator comb (CIC) filter (which inherently performs sample accumulation). This method bypasses the need for complex DFT calculations across multiple frequencies, focusing only on the DC components.

[0134] The signal processing chain 900 includes an I / Q generator circuit 602, a filter and FIFO buffer circuit 604, a firmware processing circuit 622, a Cartesian-to-polarity converter 902, a third filter 904, and a fourth filter 906. These circuits may (or may not) be arranged as shown in the figure. The signal processing chain 900 may also include additional components not shown in the figure, such as bandpass filters, IIR filters, scalars, input adapters, counters, amplifiers, and edge detection circuitry.

[0135] For the sake of brevity, the functional and structural descriptions of components with the same element numbers that have been previously discussed regarding the signal processing chain 600 will not be repeated.

[0136] The I and Q channels at the outputs of the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616 are provided as inputs to the Cartesian-to-pole information converter 902 (a dedicated digital signal processing component). In this embodiment, the Cartesian-to-pole information converter 902 is configured in bypass mode by the firmware processing circuit 622 to ensure that the extracted I and Q signals can be accumulated.

[0137] In this embodiment, the Cartesian-to-polar information converter 902 acquires decimated I and Q samples from the first ACC&W:1 circuit 614 and the second ACC&W:1 circuit 616, and performs vector rotation to convert the Cartesian coordinates (I and Q) to polar coordinates (amplitude and phase). This conversion is very useful in ASK demodulation because it allows the extraction of magnitude information from the complex signal for decoding ASK modulated data. The phase information can be used for various purposes, such as frequency offset estimation or phase error correction. It should be understood that the functionality of the Cartesian-to-polar information converter 902 can be implemented using other signal processing components, and is not limited to CORDIC amplitude / phase generator circuitry.

[0138] The in-phase amplitude component (I / M) at the output of the Cartesian-to-polar information converter 902 is fed to the third filter 904. The quadrature phase component (Q / P) at the output of the Cartesian-to-polar information converter 902 is fed to the fourth filter 906. The third filter 904 and the fourth filter 906 further reduce the data rate and accumulate samples, thereby achieving a low-pass filtering operation. This accumulation is equivalent to calculating the DC component of the signal. The outputs of the third filter 904 and the fourth filter 906 are fed to the firmware processing circuit 622. The third filter 904 and the fourth filter 906 can be implemented as CIC filters. In an embodiment, the third filter 904 and the fourth filter 906 are implemented as first-order CIC filters.

[0139] Figure 10 A flowchart of embodiment method 1000 is shown, which can be implemented to calibrate local oscillator 412. It should be noted that all steps listed in the flowchart of method 1000 are not necessarily required and can be optional. Furthermore, changes to the arrangement of steps, the removal of one or more steps and path connections, and the addition of steps and path connections are similarly considered.

[0140] Method 1000 outlines a streamlined approach for calibrating a local oscillator 412, focusing on a DC-only solution. In an embodiment, Method 1000 utilizes the outputs of a third filter 904 and a fourth filter 906 to calculate various metrics. For example, DC-only metrics... The outputs of the third filter 904 and the fourth filter 906 can be used for calculation. The firmware processing circuit 622 receives the accumulated I from the third filter 904 and the fourth filter 906. DC and Q DC Value, and through calculation This simplification reduces the computational load on the firmware processing circuitry 622 and advantageously speeds up the calibration process.

[0141] At step 1002, the first filter 610 and the second filter 612 of the signal processing chain 900 are initialized by setting their coefficients, for example, in preparation for signal processing. In embodiments, any other filters that may be included in the signal chain ( Figure 9 (Not shown in the image) will also be initialized.

[0142] At step 1004, the third filter 904 and the fourth filter 906 associated with the I channel and Q channel are configured to have a decimation factor equal to the number of DFT samples used for spectral analysis.

[0143] At step 1006, the filtering and FIFO buffer circuit 604 and the Cartesian-to-pole information converter 902 are configured to capture the output from the I component and the output from the Q component through the I-chain filter and Q-chain filter (i.e., the third filter 904 and the fourth filter 906) at the firmware processing circuit 622, so that the firmware can access the processed signal.

[0144] At step 1008, the metric associated with the optimal counter setting of the local oscillator 412 is initialized, for example, by firmware processing circuitry 622 to a minimum negative value, thereby establishing a baseline for comparisons in the search for the optimal configuration.

[0145] At step 1010, method 1000 enters a loop that explores various combinations of counter values. In an embodiment, the counter values ​​set by the firmware include an FW index counter value associated with an index value of jitter table 506, an FW repeat counter value associated with a repeat value of jitter table 506, and an FW period counter value associated with a period value of jitter table 506.

[0146] During the exploration sequence, various combined values ​​are provided to the FW index counter value, the FW repeat counter value, and the FW period value. In each loop, the ASKD index counter value is set to equal the current FW index counter value, the ASKD repeat counter value is set to equal the current FW repeat counter value, and the ASKD period counter value is set to equal the current FW period counter value.

[0147] Furthermore, an initialization routine is executed in each loop to initialize the ADC 406, the ASK demodulator circuit 408, and the filter and FIFO buffer circuit 604. In an embodiment, the initialization routine may follow method 700.

[0148] Within each cycle, a new pair of samples from the I and Q channels is received, which causes the ADC 406 to stop. The current metric for the cycle is calculated using the outputs of the third filter 904 and the fourth filter 906, which effectively provide the DC component of the signal.

[0149] If the calculated current metric exceeds the best metric found so far (i.e., the metric associated with the best counter setting of the local oscillator 412), the metric associated with the best counter setting of the local oscillator 412 is updated with the current metric, and the corresponding values ​​for the FW index counter value, the corresponding values ​​for the FW repeat counter value, and the corresponding values ​​for the FW period counter value are stored as the best configuration.

[0150] After each iteration, the process proceeds to the next combination of the FW index counter value, the FW repeat counter value, and the FW period counter value.

[0151] At step 1012, after exploring all combinations of FW index counter value, FW repeat counter value, and FW period counter value, the values ​​of ASKD index counter, ASKD repeat counter, and ASKD period counter are respectively set to the FW index counter value, FW repeat counter value, and FW period counter value as determined by the optimal configuration found at step 1010.

[0152] At step 1014, the signal processing chain 900 and associated components (e.g., filters, comparators, distance counters, etc.) are configured. In an embodiment, step 1014 can be performed at step 1002.

[0153] At step 1016, a final initialization routine is executed to initialize the ADC 406, the ASK demodulator circuit 408, and the filter and FIFO buffer circuit 604. In an embodiment, the initialization routine may follow method 700.

[0154] In this embodiment, the firmware manages various variables, including jitter table indexes, repetition values, and counters, via firmware processing circuitry 622 for exploring and tracking optimal configurations. Method 1000 utilizes filters 904 and 906 to efficiently calculate DC-only metrics. Firmware processing circuitry 622 receives accumulated I_DC and Q_DC values ​​and calculates DC-only metrics, thereby simplifying calculations and accelerating the calibration process.

[0155] Figure 11 A block diagram of an embodiment of the signal processing chain 1100 is shown. In this embodiment, the signal processing chain 1100 introduces a DC-only solution for ASK demodulation and calibration.

[0156] In the absence of amplitude modulation, even with only DC measurement Not equal to Accumulation of amplitude signals It can also be used as a simplified DC-only metric, since higher magnitudes are expected to be associated with higher calibration.

[0157] Signal processing chain 1100 includes an I / Q generator circuit 602, a filter and FIFO buffer circuit 604, a firmware processing circuit 622, a Cartesian-to-polarity converter 902, processing circuit 1102, and a third filter 1104. These circuits may (or may not) be arranged as shown in the figure. Signal processing chain 1100 may also include additional components not shown in the figure, such as bandpass filters, IIR filters, scalars, input adapters, counters, amplifiers, and edge detector circuits. For the sake of brevity, the functional and structural descriptions of the components with the same element numbers previously discussed in signal processing chains 600 and 900 will not be repeated.

[0158] The in-phase (I) and quadrature (Q) components are fed into a Cartesian-to-pole information converter 902. The Cartesian-to-pole information converter 902 calculates the amplitude for the current I / Q sample pair.

[0159] The calculated value at the output of processing circuit 1102 is fed to third filter 1104. Third filter 1104 further reduces the data rate and accumulates samples, thereby achieving low-pass filtering. The output of third filter 1104 is an amplitude value that can already be used as a metric, which is fed to firmware processing circuit 622. Third filter 1104 can be implemented as a CIC filter. In an embodiment, third filter 1104 is implemented as a first-order CIC filter. In an embodiment, firmware processing circuit 622 optionally calculates the square of the amplitude to enhance the difference in the metric value.

[0160] Figure 12 A flowchart of embodiment method 1200 is shown, which can be implemented to calibrate local oscillator 412. It should be noted that all steps listed in the flowchart of method 1200 are not necessarily required and can be optional. Furthermore, changes to the arrangement of steps, the removal of one or more steps and path connections, and the addition of steps and path connections are similarly considered. Method 1200 outlines another approach for calibrating local oscillator 412, focusing on a DC-only solution. In this embodiment, method 1200 utilizes the output of a third filter 1104, which already includes feasible measurements for firmware processing circuitry 622.

[0161] At step 1202, the first filter 610 and the second filter 612 of the signal processing chain 1100 are initialized by setting their coefficients, for example, in preparation for signal processing. In embodiments, any additional filters that may be included in the signal chain ( Figure 11 (Not shown in the image) have all been initialized.

[0162] At step 1204, the third filter 1104 is configured with a decimation factor equal to the number of DFT samples used for spectral analysis.

[0163] At step 1206, the filtering and FIFO buffer circuit 604 and the Cartesian-to-pole information converter 902 are configured such that the firmware processing circuit 622 receives a sample from the third filter 1104, the sample having an amplitude signal. The cumulative value.

[0164] At step 1208, the metric associated with the optimal counter setting of the local oscillator 412 is initialized, for example, to a minimum negative value by firmware processing circuitry 622, establishing a baseline for comparison in the search for the optimal configuration.

[0165] At step 1210, method 1200 enters a loop that explores various combinations of counter values. In an embodiment, the counter values ​​set by the firmware include an FW index counter value associated with an index value of jitter table 506, an FW repeat counter value associated with a repeat value of jitter table 506, and an FW period counter value associated with a period value of jitter table 506.

[0166] During the exploration sequence, various combined values ​​are provided, for example, by firmware processing circuitry 622 to the FW index counter value, the FW repeat counter value, and the FW period value. In each cycle, the value of the ASKD index counter is set to equal the current FW index counter value, the value of the ASKD repeat counter is set to equal the current FW repeat counter value, and the value of the ASKD period counter is set to equal the current FW period counter value.

[0167] Furthermore, an initialization routine is executed in each loop to initialize the ADC 406, the ASK demodulator circuit 408, and the filter and FIFO buffer circuit 604. In an embodiment, the initialization routine may follow method 700.

[0168] Within each loop, samples are received from the third filter 1104, which stops the ADC 406. Amplitude signal The accumulation of values ​​is associated with a metric for the current sample. In an embodiment, firmware processing circuitry 622 calculates the square of the calculated values ​​(i.e., ), as a metric for the current sample.

[0169] If the current metric exceeds the best metric found so far (i.e., the metric associated with the best counter setting of the local oscillator 412), the metric associated with the best counter setting of the local oscillator 412 is updated with the current metric, and the corresponding values ​​for the FW index counter value, the corresponding values ​​for the FW repeat counter value, and the corresponding values ​​for the FW period counter value are stored as the best configuration.

[0170] After each iteration, the process proceeds to the next combination of the FW index counter value, the FW repeat counter value, and the FW period counter value.

[0171] At step 1212, after exploring all combinations of FW index counter value, FW repeat counter value, and FW period counter value, the values ​​of ASKD index counter, ASKD repeat counter, and ASKD period counter are respectively set to the FW index counter value, FW repeat counter value, and FW period counter value as determined by the optimal configuration found at step 1210.

[0172] At step 1214, the signal processing chain 1100 and associated components (e.g., filters, comparators, distance counters, etc.) are configured. In an embodiment, step 1214 is performed at step 1202.

[0173] At step 1216, a final initialization routine is executed to initialize the ADC 406, the ASK demodulator circuit 408, and the filter and FIFO buffer circuit 604. In an embodiment, the initialization routine may follow method 700.

[0174] In this embodiment, the firmware manages various variables, including jitter table indexes, repetition values, and counters, via firmware processing circuitry 622 for exploring and tracking optimal configurations. Method 1200 utilizes a Cartesian-to-pole information converter 902, processing circuitry 1102, and a third filter 1104 to calculate a current metric for samples from the ADC 406. This metric can be readily used by the firmware processing circuitry 622 without requiring any further calculations, thus simplifying the computation and accelerating the calibration process.

[0175] In various embodiments, the firmware processing circuitry 622 can be implemented as a digital signal processor. The firmware processing circuitry 622 can communicate with the ADC 406 to activate and deactivate the ADC. In some embodiments, the firmware processing circuitry 622 is coupled to the ADC 406, for example, when the ADC 406 and the firmware processing circuitry 622 are on the same chip.

[0176] In some embodiments, the firmware processing circuitry 622 is coupled to the ADC 406 via a serial interface (such as an internal integrated circuit (I2C)), for example, when the ADC 406 and the firmware processing circuitry 622 are not on the same chip. In some embodiments, the firmware processing circuitry 622 is coupled to the ASK demodulator circuitry 408 to assert and deassert reset signals.

[0177] Figure 13 A block diagram of an embodiment of signal processing chain 1300 is shown. Signal processing chain 1300 illustrates an implementation for ASK demodulation and calibration, wherein the signal chain is divided into high-speed domain circuitry and low-speed domain circuitry. Signal processing chain 1300 includes high-speed domain circuitry 1302 and low-speed domain circuitry 1312, which may (or may not) be arranged as shown. Signal processing chain 1300 may include additional components not shown in the figure.

[0178] High-speed domain circuit 1302 receives ASK samples from interface 414 and converts the high-speed domain signal to low-speed domain circuit 1312. High-speed domain circuit 1302 includes a mixer 1304 with a jitter-compensated local oscillator, a filter 1306, and a decimator 1308. The mixer 1304 with the jitter-compensated local oscillator processes the ADC samples, generating I and Q components to account for frequency jitter. The I and Q components are passed through filter 1306 (typically a low-pass filter) and decimator 1308, respectively, to reduce noise and data rate. The outputs of filter 1306 and decimator 1308 are fed to a processor via multiplexer 1310, enabling DFT processing for calibration.

[0179] Low-speed domain circuit 1312 receives and processes the down-converted signal to generate I-bit and Q-bit streams. Low-speed domain circuit 1312 includes parallel paths for the I and Q components. A first path includes a first DC removal circuit 1314, a first slicer circuit 1318, and a first symbol decoder circuit 1322. A second path includes a second DC removal circuit 1316, a second slicer circuit 1320, and a second symbol decoder circuit 1324 in the Q-chain component path. In an embodiment, the first DC removal circuit 1314 and the second DC removal circuit 1316 are implemented as high-pass frequency filters to remove DC offset. The first slicer circuit 1318 and the second slicer circuit 1320 provide signal quantization. The first symbol decoder circuit 1322 and the second symbol decoder circuit 1324 generate the final bitstream.

[0180] This embodiment advantageously provides flexibility in applying calibration metrics. While the metric is typically applied to the down-converted signal after low-pass filtering, samples can be taken from various points in the link (including the high-speed domain circuitry 1302) depending on the data rate and system requirements. This flexibility allows for optimization of processing load and power consumption.

[0181] The calibration results can be applied to various types of jitter-compensated local oscillators, not limited to those based on indexed, repetitive, and time-counter triplets, because the metric is independent of the specific phase encoding used for frequency jitter. Furthermore, the proposed circuitry allows for hardware-based DFT processing, with simple accumulators sufficient for DC component analysis.

[0182] This architecture also facilitates the easy implementation of ADC control features, such as on / off switching and periodic start-of-conversion commands, thereby enhancing adaptability to different operational requirements.

[0183] In some embodiments, in an ASK demodulation system utilizing frequency jitter, the demodulation process is performed under a synchronous demodulation mechanism. This method ensures that the jitter period (calculated as the product of the PWM period (TPWM) and the sum of all adjusted automatic reload register (ARR) values ​​plus 1 divided by the entire jitter mode) is an integer multiple of the sampling period. Synchronization helps maintain the consistency of the sampling process throughout the jitter mode. Under ideal conditions, i.e., without amplitude modulation and without external noise, synchronous sampling techniques cause significant periodicity in the acquired samples.

[0184] The first aspect relates to a method for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter. The method includes: receiving a digital signal corresponding to a voltage or current of a transmitter coil in a wireless power system implemented using frequency jitter; iteratively adjusting a counter value associated with a jitter table of the local oscillator; wherein for each iteration, the method includes generating an in-phase (I) component and a quadrature (Q) component using the local oscillator, calculating a metric based on the I and Q components, and storing a counter value if the calculated metric exceeds a previously stored optimal metric; and configuring the local oscillator using the stored counter value associated with the optimal metric.

[0185] In a first implementation of the method, according to the first aspect itself, the counter values ​​include an index counter value associated with an index of the jitter table; a repeat counter value associated with a repeat value of the jitter table; and a time period counter value associated with a time period of the jitter table.

[0186] In a second implementation of the method, the metric calculation, according to the first aspect itself or any of the aforementioned implementations of the first aspect, includes performing a discrete Fourier transform (DFT) on the I and Q components; calculating the energy contribution at DC and the energy contribution at at least one jitter harmonic frequency; and determining the difference between the DC energy contribution and the jitter harmonic energy contribution.

[0187] In a third implementation of the method, the metric calculation, according to the first aspect itself or any of the aforementioned implementations of the first aspect, includes: accumulating I samples and Q samples to calculate the DC component; and calculating the sum of squares of the DC component.

[0188] In a fourth implementation of the method, the calculation of the metric, according to the first aspect itself or any of the foregoing implementations of the first aspect, includes: calculating the magnitude of each I-sample and Q-sample pair; and accumulating the calculated magnitude.

[0189] In a fifth implementation of the method, depending on the first aspect itself or any of the foregoing implementations of the first aspect, the method further includes: configuring filtering and first-in-first-out (FIFO) buffer circuitry to capture the outputs from the I-component processing chain and the Q-component processing chain.

[0190] In a sixth implementation of the method, generating the I and Q components, according to the first aspect itself or any of the foregoing implementations of the first aspect, includes using a numerically controlled oscillator.

[0191] In a seventh implementation of the method, depending on the first aspect itself or any of the foregoing implementations of the first aspect, the method further includes: filtering the I and Q components using a cascaded integrator comb (CIC) filter before calculating the metric.

[0192] The second aspect relates to a circuit for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter. The circuit includes: an analog-to-digital converter (ADC) configured to receive a signal corresponding to the voltage or current of a transmitter coil in a wireless power system implemented using frequency jitter; a local oscillator configured to generate in-phase (I) and quadrature (Q) components based on a counter value associated with a jitter table; and processing circuitry configured to iteratively adjust the counter value, calculate a metric based on the I and Q components for each iteration, and store the counter value if the calculated metric exceeds a previously stored optimal metric, wherein the local oscillator is further configured to use the stored counter value associated with the optimal metric for subsequent operations.

[0193] In a first implementation of the circuit, according to the second aspect itself, the local oscillator includes an I / Q generator circuit configured to generate I and Q components.

[0194] In a second implementation of the circuit, depending on the second aspect itself or any of the foregoing implementations of the second aspect, the circuit further includes a filtering and first-in-first-out (FIFO) buffer circuit configured to capture the outputs from the I-component processing chain and the Q-component processing chain, and to provide the outputs to the processing circuit.

[0195] In a third implementation of the circuit, according to the second aspect itself or any of the aforementioned implementations of the second aspect, the circuit further includes a Cartesian-to-pole information converter configured to calculate amplitude and phase values ​​based on the I and Q components.

[0196] In a fourth implementation of the circuit, according to the second aspect itself or any of the foregoing implementations of the second aspect, the circuit further includes a filter that is coupled to the output of the Cartesian-to-polar information converter and configured to accumulate amplitude values.

[0197] In a fifth implementation of the circuit, according to the second aspect itself or any of the foregoing implementations of the second aspect, the processing circuit is further configured to perform a discrete Fourier transform (DFT) on the I and Q components; calculate the energy contribution at DC and the energy contribution at at least one jitter harmonic frequency; and determine the metric as the difference between the DC energy contribution and the jitter harmonic energy contribution.

[0198] In a sixth implementation of the circuit, according to the second aspect itself or any of the foregoing embodiments of the second aspect, the circuit further includes a cascaded integrator comb (CIC) filter, which is coupled to the I-component processing chain and the Q-component processing chain and configured to compute the DC components of the I-component and the Q-component.

[0199] The third aspect relates to a wireless power system. This wireless power system includes a transmitter coil and an amplitude shift keying (ASK) demodulator circuit coupled to the transmitter coil and configured to demodulate a backscattered modulated signal. The ASK demodulator circuit includes a local oscillator implemented using frequency jitter, a calibration circuit configured to receive a digital signal corresponding to the voltage of the transmitter coil; iteratively adjust a counter value associated with the jitter table of the local oscillator; and configure the local oscillator using a stored counter value associated with an optimal metric. For each iteration, the calibration circuit is configured to generate in-phase (I) and quadrature (Q) components using the local oscillator; calculate a metric based on the I and Q components; and store the counter value if the calculated metric exceeds the previously stored optimal metric.

[0200] In a first implementation of the wireless power system according to the third aspect, the local oscillator includes an I / Q generator circuit configured to generate I and Q components.

[0201] In a second implementation of the wireless power system according to the third aspect itself or any of the foregoing embodiments of the third aspect, the calibration circuit includes a filtering and first-in-first-out (FIFO) buffer circuit configured to capture the outputs from the I component processing chain and the Q component processing chain.

[0202] In a third implementation of the wireless power system according to the third aspect itself or any of the foregoing implementations of the third aspect, the wireless power system further includes a Cartesian-to-pole information converter configured to calculate amplitude and phase values ​​based on I and Q components; and a filter coupled to the output of the Cartesian-to-pole information converter and configured to accumulate amplitude values.

[0203] In a fourth implementation of the wireless power system according to the third aspect itself or any of the foregoing implementations of the third aspect, the calibration circuit is configured to calculate the metric by: accumulating I samples and Q samples to calculate the DC component; and calculating the sum of squares of the DC component.

[0204] Although this specification has been described in detail, it should be understood that various changes, substitutions, and modifications may be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various figures, the same elements are designated using the same reference numerals. Furthermore, the scope of this disclosure is not limited to the specific embodiments described herein, as those skilled in the art will readily understand from this disclosure that existing or later-developed processes, machines, manufactures, material compositions, components, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, components, methods, or steps within their scope.

[0205] Therefore, the specification and drawings should be regarded only as a description of this disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of this disclosure.

Claims

1. A method for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter, the method comprising: receiving a digital signal corresponding to a voltage or a current of a transmitter coil in a wireless power system implemented with frequency dithering; iteratively adjusting a counter value associated with a dither table of the local oscillator; wherein for each iteration, the method comprises: generating in-phase (I) and quadrature (Q) components using the local oscillator, calculating a metric based on the I and Q components, and storing the counter value if the calculated metric exceeds a previously stored best metric; and configuring the local oscillator with the stored counter value associated with the best metric.

2. The method of claim 1, wherein the counter value comprises: an index counter value associated with an index of the dither table; a repetition counter value associated with a repetition value of the dither table; and a period counter value associated with a period of the dither table.

3. The method of claim 1, wherein calculating the metric comprises: performing a discrete Fourier transform (DFT) on the I and Q components; calculating an energy contribution at DC and an energy contribution at at least one dithered harmonic frequency; and determining a difference between the DC energy contribution and the dithered harmonic energy contribution.

4. The method of claim 1, wherein calculating the metric comprises: accumulating I and Q samples to calculate a DC component; and calculating a sum of squares of the DC component.

5. The method of claim 1, wherein calculating the metric comprises: calculating an amplitude of each I and Q sample pair; and accumulating the calculated amplitudes. configuring a filter and a first-in-first-out (FIFO) buffer circuit to capture outputs from an I component processing chain and a Q component processing chain.

6. The method of claim 1, further comprising: using a digitally controlled oscillator.

7. The method of claim 1, wherein generating the I component and the Q component comprises: filtering the I and Q components using a cascaded integrator comb (CIC) filter prior to calculating the metric.

8. The method of claim 1, further comprising:

9. A circuit for calibrating a local oscillator in an amplitude shift keying (ASK) demodulator of a wireless power transmitter, the circuit comprising: an analog-to-digital converter (ADC) configured to receive a signal corresponding to a voltage or a current of a transmitter coil in a wireless power system implemented with frequency dithering; a local oscillator configured to generate in-phase (I) and quadrature (Q) components based on a counter value associated with a dither table; and a processing circuit configured to: iteratively adjust the counter value, calculate a metric based on the I and Q components for each iteration, and store the counter value if the calculated metric exceeds a previously stored best metric, wherein the local oscillator is further configured to use the stored counter value associated with the best metric for subsequent operations.

10. The circuit of claim 9, wherein the local oscillator comprises an I / Q generator circuit configured to generate the I and Q components. ​ 11. The circuit of claim 9, further comprising a filter and first-in-first-out (FIFO) buffer circuit configured to capture outputs from an I-component processing chain and a Q-component processing chain and provide the outputs from the I-component processing chain and the Q-component processing chain to the processing circuit.

12. The circuit of claim 9, further comprising a Cartesian-to-polar information converter configured to compute a magnitude value and a phase value from the I-component and the Q-component.

13. The circuit of claim 12, further comprising a filter coupled to an output of the Cartesian-to-polar information converter and configured to accumulate magnitude values.

14. The circuit of claim 9, wherein the processing circuit is further configured to: perform a discrete Fourier transform (DFT) on the I-component and the Q-component; compute an energy contribution at DC and an energy contribution at at least one dithered harmonic frequency; and determine the metric as a difference between the DC energy contribution and the dithered harmonic energy contribution.

15. The circuit of claim 9, further comprising a cascaded integrator comb (CIC) filter coupled to an I-component processing chain and a Q-component processing chain and configured to compute a DC component of the I-component and a DC component of the Q-component.

16. A wireless power system, comprising: a transmitter coil; an amplitude shift keying (ASK) demodulator circuit coupled to the transmitter coil and configured to demodulate a backscatter modulated signal, the ASK demodulator circuit comprising: a local oscillator implemented with frequency dithering; a calibration circuit configured to: receive a digital signal corresponding to a voltage of the transmitter coil; iteratively adjust a counter value associated with a dither table of the local oscillator; wherein for each iteration, the calibration circuit is configured to: generate an in-phase (I) component and a quadrature (Q) component using the local oscillator; compute a metric based on the I-component and the Q-component; and if the computed metric exceeds a previously stored best metric, store the counter value; configure the local oscillator with the stored counter value associated with the best metric.

17. The wireless power system of claim 16, wherein the local oscillator comprises an I / Q generator circuit configured to generate the I-component and the Q-component.

18. The wireless power system of claim 16, wherein the calibration circuit comprises a filter and first-in-first-out (FIFO) buffer circuit configured to capture outputs from an I-component processing chain and a Q-component processing chain.

19. The wireless power system of claim 16, wherein the wireless power system further comprises: a Cartesian-to-polar information converter configured to compute a magnitude value and a phase value from the I-component and the Q-component; and a filter coupled to an output of the Cartesian-to-polar information converter and configured to accumulate magnitude values. a filter coupled to an output of the Cartesian-to-polar information converter and configured to accumulate amplitude values.

20. The wireless power system of claim 16, wherein the calibration circuit is configured to compute the metric by: accumulating I and Q samples to compute a DC component; and computing a sum of squares of the DC component.

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