Data processing device and data processing method
By incorporating multiple chips within the data processing device and directly connecting them to ports, the bandwidth limitation problem of data exchange equipment is solved, enabling linear bandwidth increments and non-blocking switching to meet business requirements.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-05
- Publication Date
- 2026-03-10
AI Technical Summary
The bandwidth of existing data switching equipment is limited by the maximum bandwidth of a single switching chip, making it difficult to meet business needs.
Multiple chips are installed in the data processing device, and each chip is connected to multiple ports through physical links. Data can be forwarded directly from the chip at the port without needing to be forwarded between chips, ensuring that the bandwidth is the sum of the bandwidths of multiple chips.
Effectively improve the bandwidth of the data processing device, ensure that the data processing device can meet business needs, achieve non-blocking switching, and maximize the utilization of chip bandwidth.
Smart Images
Figure CN121644491A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication technology, and in particular to a data processing apparatus and a data processing method. Background Technology
[0002] In a data center, all types of business data are transmitted through data exchange equipment (such as switches) within the data center. Therefore, the performance of the data exchange equipment in the data center affects the transmission performance of various business data.
[0003] With the large-scale application of artificial intelligence technology, the amount of business data that needs to be exchanged between network devices in data centers is increasing, thus placing higher demands on the bandwidth of data switching equipment within data centers. Generally, data switching equipment includes a switching chip, and the bandwidth of the data switching equipment is usually determined by the bandwidth supported by the switching chip within the equipment.
[0004] Due to technological and cost limitations, the maximum bandwidth of a single switching chip is often limited; for example, the current maximum bandwidth of a single switching chip is 51.2 terabits per second (Tbps). Therefore, with a fixed bandwidth for the switching chip, the bandwidth of the data switching equipment is also often fixed, making it difficult for current data switching equipment to meet business demands. Summary of the Invention
[0005] This application provides a data processing apparatus and a data processing method, which can effectively improve the bandwidth of the data processing apparatus and ensure that the data processing apparatus can meet the needs of business operations.
[0006] A first aspect provides a data processing apparatus, comprising: a first chip, a second chip, a first port, and a second port. The first chip is connected to both the first port and the second port via a first physical link; the second chip is connected to both the first port and the second port via a second physical link.
[0007] Since the first chip and the second chip are connected to the first port and the second port respectively, data entering from either the first port or the second port can be directly forwarded out from the other port through either the first chip or the second chip, without needing to be forwarded between the first chip and the second chip.
[0008] In this solution, by incorporating multiple chips within the data processing device, with each chip connected to each of the device's multiple ports via physical links, data entering from any port can be forwarded by a chip from another port, ensuring the data processing device can perform data exchange normally. Furthermore, since multiple chips are integrated into a single data processing device, the actual bandwidth of the device is the sum of the bandwidths of all the chips. This effectively increases the bandwidth of the data processing device while maintaining a fixed chip bandwidth, ensuring that the device can meet business requirements.
[0009] In one possible implementation, there is no physical link connection between the first chip and the second chip. For example, all physical links connecting the first chip and the second chip are connected to the first port and the second port. That is, the first chip and the second chip do not exchange data, and the first chip and the second chip do not need to reserve additional bandwidth for the inter-chip link, thereby ensuring that the bandwidth of the first chip and the second chip can be provided to the outside world as much as possible through the ports.
[0010] In one possible implementation, the first physical link includes at least two physical sub-links. The first chip is connected to a first port via at least one of the at least two physical sub-links, and also connected to a second port via at least one of the at least two physical sub-links. That is, the number of physical sub-links connecting the first chip to the first port is one or more, and the number of physical sub-links connecting the first chip to the second port is also one or more.
[0011] In one possible implementation, to ensure non-blocking data exchange, the number of physical sub-links connected to the first port by the first chip is the same as the number of physical sub-links connected to the second port by the first chip.
[0012] In this solution, since the bandwidth of different physical sub-links connected to a chip is often the same, by setting the number of physical sub-links connected to different ports to be the same, it can be ensured that the chip provides the same bandwidth to each port, thereby ensuring non-blocking data exchange and guaranteeing data forwarding efficiency.
[0013] In one possible implementation, the first physical link and the second physical link include the same number of physical sub-links. That is, the bandwidth of the first chip is the same as the bandwidth of the second chip, and both the first chip and the second chip are connected to the port via the same number of physical sub-links. The number of physical sub-links connected to the first port and the second port is a first value, and the number of physical sub-links connecting the first chip and the second chip to a port is half of the first value.
[0014] In this scheme, when the chips in the data processing device have the same bandwidth and each port provides the same bandwidth to the outside world, the connection between the chip and the port can be achieved by connecting the physical sub-links that each port can connect to each chip on an even basis, and the data can be exchanged without blocking between any two ports.
[0015] In one possible implementation, both the first port and the second port are physical ports. That is, the first port and the second port are independent, pluggable physical ports.
[0016] Alternatively, both the first port and the second port can be logical ports derived from physical ports, and both ports are used to connect different devices outside the data processing device. That is, the first port and the second port are not independent physical ports, but rather logical ports derived from a single physical port. In this case, other devices within the data processing device are connected to the physical port to which the first port or the second port belongs via connected optical fibers or cables. Although the first port and the second port are not independent physical ports, they still function as independent logical ports, connecting to different devices outside the data processing device to ensure data forwarding isolation between different devices.
[0017] In one possible implementation, in addition to the first chip, the second chip, the first port, and the second port, the data processing device further includes a third chip; wherein the third chip is connected to the first port and the second port respectively via a third physical link.
[0018] In other words, a data processing device may include two or more chips. Furthermore, each chip in the data processing device is physically connected to each port of the data processing device, thereby ensuring that data between any two ports can be forwarded using the same chip.
[0019] In one possible implementation, there are no physical links between the first, second, and third chips; that is, there are no physical links between any of the chips in the data processing device. Each chip in the data processing device receives data through one connected port and then forwards the data directly through another connected port, without forwarding the data to another chip. In this way, none of the chips in the data processing device need to reserve additional bandwidth for inter-chip links, ensuring that the bandwidth of the data processing device is the sum of the bandwidths of all the chips within it, thus maximizing the utilization of the chip bandwidth.
[0020] In one possible implementation, the third physical link includes at least two physical sub-links, and the third chip is connected to the first port through at least one of the at least two physical sub-links.
[0021] In one possible implementation, the first physical link, the second physical link, and the third physical link include the same number of physical sub-links, the number of physical sub-links connected to the first port and the second port are both the second value, and the number of physical sub-links connected to a port by the first chip, the second chip, and the third chip are all one-third of the second value.
[0022] In simple terms, when a data processing device includes multiple chips, all physical sub-links connected to each port in the data processing device are evenly connected to each chip in the data processing device, so that the number of physical sub-links connected to the same port by each chip is the same.
[0023] In one possible implementation, the first chip and the second chip are programmable logic device (PLD) chips, application-specific integrated circuit (ASIC) chips, network processing processors (NP), central processing units (CPU), graphics processing units (GPUs), neural network processing units (NPUs), or tensor processing units (TPUs).
[0024] In one possible implementation, the data processing device is a switch, router, server, line card, optical branch board, or optical circuit board.
[0025] Secondly, a data processing method is provided, applied to a data processing device. The data processing device includes a first chip, a second chip, a first port, and a second port. The first chip is connected to both the first port and the second port via a first physical link, and the second chip is connected to both the first port and the second port via a second physical link. The data processing method includes: the first chip receiving first data from the first port via the first physical link; the first chip forwarding the first data from the second port via the first physical link; the second chip receiving second data from the first port via the second physical link; and the second chip forwarding the second data from the second port via the second physical link.
[0026] In one possible implementation, there is no physical link between the first chip and the second chip.
[0027] In one possible implementation, the first physical link includes at least two physical sub-links, and the first chip is connected to the first port through at least one of the at least two physical sub-links, and receives first data from the first port through at least one physical sub-link.
[0028] In one possible implementation, the number of physical sub-links connected to the first port by the first chip is the same as the number of physical sub-links connected to the second port by the first chip.
[0029] In one possible implementation, the first physical link and the second physical link include the same number of physical sub-links, the number of physical sub-links connected to the first port and the second port are both a first value, and the number of physical sub-links connected to the first chip and the second chip to a port are both half of the first value.
[0030] In one possible implementation, both the first port and the second port are physical ports; or, both the first port and the second port are logical ports derived from the division of physical ports, and the first port and the second port are used to connect different devices other than the data processing device.
[0031] In one possible implementation, the data processing device further includes: a third chip; the third chip is connected to the first port and the second port respectively via a third physical link; the third chip receives third data from the first port via the third physical link; and the third chip forwards the third data from the second port via the third physical link.
[0032] In one possible implementation, there is no physical link between the first chip, the second chip, and the third chip.
[0033] In one possible implementation, the third physical link includes at least two physical sub-links, and the third chip is connected to the first port through at least one of the at least two physical sub-links.
[0034] In one possible implementation, the first physical link, the second physical link, and the third physical link include the same number of physical sub-links, the number of physical sub-links connected to the first port and the second port are both the second value, and the number of physical sub-links connected to a port by the first chip, the second chip, and the third chip are all one-third of the second value.
[0035] In one possible implementation, the first chip and the second chip are PLD chips, ASIC chips, NP, CPU, GPU, NPU or TPU.
[0036] In one possible implementation, the data processing device is a switch, router, server, line card, optical branch board, or optical circuit board. Attached Figure Description
[0037] Figure 1 A schematic diagram of the structure of a data exchange device provided in this application;
[0038] Figure 2 A schematic diagram of the structure of a data processing device provided in this application;
[0039] Figure 3 A schematic diagram showing that the first port and the second port are physical ports, as provided in this application;
[0040] Figure 4 A schematic diagram showing that the first port and the second port are logical ports, as provided in this application;
[0041] Figure 5 A schematic diagram of another data processing apparatus provided in this application;
[0042] Figure 6 A schematic diagram showing the connection between multiple chips and multiple physical ports in a data processing device provided in this application;
[0043] Figure 7 A schematic diagram showing the connection of multiple chips and multiple logic ports in a data processing device provided in this application;
[0044] Figure 8 A network topology diagram of a switch provided in this application;
[0045] Figure 9 A network diagram of another type of switch provided in this application. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application are described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.
[0047] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. For example, "first chip" and "second chip" are used to distinguish different chips, not to describe a specific order of the chips, and should not be construed as implying that the first chip is more important than the second chip. In this application, unless otherwise stated, "at least one" means one or more, and "multiple" means two or more.
[0048] Currently, data switching equipment typically includes a switching chip, and the bandwidth of the data switching equipment is determined by the bandwidth supported by this switching chip. However, the maximum bandwidth of a single switching chip is often limited; for example, the current maximum bandwidth of a single switching chip is 51.2 Tbps. Therefore, with a fixed bandwidth for the switching chip, the bandwidth of the data switching equipment is often also fixed, making it difficult for current data switching equipment to meet business demands.
[0049] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a data exchange device provided in this application. Figure 1 As shown, in one possible implementation, the data switching device deploys chip 1 and chip 2, and a link connects chip 1 and chip 2 to facilitate data forwarding between them. Additionally, chip 1 is connected to port 1, and chip 2 is connected to port 2, and the data switching device connects to external network devices through ports 1 and 2. In other words, chip 1 and chip 2 jointly provide bandwidth, and the total bandwidth of the data switching device is the sum of the bandwidths provided by chip 1 and chip 2. Although... Figure 1 The implementation shown can slightly increase the bandwidth of the data exchange device. However, since additional interconnection links are required between the chips, a portion of the bandwidth of chip 1 and chip 2 itself will be provided to the interconnection links between the chips, resulting in the actual bandwidth provided by chip 1 and chip 2 to the outside world not being high.
[0050] In view of this, this application provides a data processing apparatus. By incorporating multiple chips within the data processing apparatus, with each chip connected to each of the multiple ports of the data processing apparatus via a physical link, data entering from any port within the data processing apparatus can be directly forwarded out by a chip from another port, thereby ensuring that the data processing apparatus can perform data exchange normally. Furthermore, since multiple chips are incorporated within a single data processing apparatus, the bandwidth of the data processing apparatus is actually the sum of the bandwidths of the multiple chips. This effectively increases the bandwidth of the data processing apparatus while maintaining a fixed chip bandwidth, ensuring that the data processing apparatus can meet the needs of business operations.
[0051] For example, please refer to Figure 2 , Figure 2 This is a schematic diagram of the structure of a data processing device provided in this application. Figure 2 As shown, the data processing apparatus provided in this application includes: a first chip, a second chip, a first port, and a second port. The first chip is connected to both the first port and the second port via a first physical link. The second chip is connected to both the first port and the second port via a second physical link.
[0052] It should be noted that the first physical link between the first chip and the first port and the second port is actually a bidirectional connection, meaning that the first chip can send data to and / or receive data from the first port and / or the second port through the first physical link. Similarly, the second physical link between the second chip and the first port and the second port is also a bidirectional connection, meaning that the second chip can send data to and / or receive data from the first port and / or the second port through the second physical link.
[0053] Furthermore, both the first and second chips are equipped with serializers / deserializers (SerDes). The first physical link connected to the first chip is actually connected to the SerDes of the first chip, and the second physical link connected to the second chip is actually connected to the SerDes of the second chip. SerDes are interface devices used to implement medium- to long-distance high-speed communication. They are commonly used as the physical layer implementation scheme for communication protocols such as the high-speed serial computer interconnect express (PCI-Express), Gigabit Ethernet, and fiber optic communication, and are widely used for high-speed interconnection between chips, boards, and devices.
[0054] Since the first chip and the second chip are connected to the first port and the second port respectively, data entering from either the first port or the second port can be directly forwarded out from the other port through either the first chip or the second chip, without needing to be forwarded between the first chip and the second chip.
[0055] For example, in a data processing device, a first chip receives first data from a first port via a first physical link, and forwards the first data from a second port via the same first physical link. A second chip receives second data from the first port via a second physical link, and forwards the second data from the second port via the same second physical link. Alternatively, either the first or second chip could receive data from the second port and forward the received data from the second port back out through the first port.
[0056] In this way, by connecting both the first and second chips in the data processing device to every port on the device, data entering from any port can be directly forwarded out by any chip from another port, ensuring that the data processing device can perform data exchange normally. Furthermore, since the first and second chips do not need to perform data forwarding between themselves, all the bandwidth of both chips can be provided externally through the ports, making the actual bandwidth of the data processing device the sum of the bandwidths of the first and second chips. For example, if the bandwidth of both the first and second chips is 50Tbps, the actual bandwidth of the data processing device is 100Tbps.
[0057] Therefore, when the chips and ports in the data processing device adopt the connection method provided in this application, the bandwidth of the data processing device can increase linearly with the increase of the number of chips, effectively improving the bandwidth of the data processing device and ensuring that the data processing device can meet the needs of the business.
[0058] Optionally, there is no physical link connection between the first chip and the second chip. That is, the first chip and the second chip do not exchange data, and there is no need to reserve additional bandwidth for the link between the two chips. This ensures that the bandwidth of the first chip and the second chip can be provided to the outside through the port as much as possible, thus maximizing the utilization of the bandwidth of the first chip and the second chip.
[0059] Of course, the first chip and the second chip can be connected by a physical link. However, this physical link is not used to forward user service data, but rather to synchronize control or configuration information between the two chips. Therefore, even if there is a physical link between the first and second chips, it will not consume too much bandwidth, ensuring that the first and second chips can provide as much bandwidth as possible to the outside world through their ports.
[0060] In a specific implementation, the aforementioned first physical link includes multiple physical sub-links, and the first chip connects to the first port and the second port through different physical sub-links. The second physical link also includes multiple physical sub-links, and the second chip connects to the first port and the second port through different physical sub-links.
[0061] For example, the first physical link includes at least two physical sub-links. The first chip is connected to a first port via at least one of the at least two physical sub-links, and also connected to a second port via at least one of the at least two physical sub-links. Furthermore, the physical sub-links connected to the first port and the physical sub-links connected to the second port are different on the first chip. That is, the first chip is connected to the first port and the second port respectively via different physical sub-links. For example, suppose the first physical link includes physical sub-link 1 and physical sub-link 2, the first chip is connected to the first port via physical sub-link 1, and connected to the second port via physical sub-link 2. Or, suppose the first physical link includes physical sub-link 1, physical sub-link 2, physical sub-link 3, and physical sub-link 4, the first chip is connected to the first port via physical sub-link 1 and physical sub-link 2, and connected to the second port via physical sub-link 3 and physical sub-link 4.
[0062] Similarly, the second physical link also includes two or more physical sub-links. The second chip is connected to the first port through at least one of the physical sub-links included in the second physical link, and to the second port through at least one other physical sub-link. Furthermore, the physical sub-links connected to the first port and the physical sub-links connected to the second port are different on the second chip. That is, the second chip is connected to the first port and the second port respectively through different physical sub-links. For example, suppose the second physical link includes physical sub-link 1 and physical sub-link 2; the second chip is connected to the first port through physical sub-link 1 and to the second port through physical sub-link 2. Or, suppose the second physical link includes physical sub-link 1, physical sub-link 2, physical sub-link 3, and physical sub-link 4; the second chip is connected to the first port through physical sub-link 1 and physical sub-link 2, and to the second port through physical sub-link 3 and physical sub-link 4.
[0063] Furthermore, the first and second physical links can be implemented using printed circuit boards (PCBs), flexible printed circuit boards (FPCs), or cables. The first and second physical links only need to ensure data transmission between the chip and the port; this application does not specify the particular implementation method of the first and second physical links.
[0064] Optionally, to ensure non-blocking data exchange, the number of physical sub-links connected to the first port by the first chip is the same as the number of physical sub-links connected to the second port by the first chip. Similarly, the number of physical sub-links connected to the first port by the second chip is also the same as the number of physical sub-links connected to the second port by the second chip.
[0065] Generally, the bandwidth of a single physical sub-link connected to a port by a chip is fixed, and the bandwidth of different physical sub-links connected to a chip is often the same. However, if the number of physical sub-links a chip connects to different ports varies, the bandwidth provided by the chip to those ports will also differ. For example, if a chip connects to five physical sub-links on a first port and three on a second port, then if the chip simultaneously receives data from the five physical sub-links connected to the first port, it will often only be able to forward the data through the three physical sub-links connected to the second port, potentially leading to data congestion.
[0066] Therefore, by setting the number of physical sub-links connected to different ports to be the same in this solution, it can be ensured that the bandwidth provided by the chip to each port is the same, thereby ensuring non-blocking data exchange and guaranteeing data forwarding efficiency.
[0067] Optionally, the first physical link connected to the first chip and the second physical link connected to the second chip include the same number of physical sub-links. That is, the bandwidth of the first chip and the bandwidth of the second chip are the same, and both the first chip and the second chip are connected to the port through the same number of physical sub-links.
[0068] Furthermore, the number of physical sub-links connected to the first port and the second port are both the first value, and the number of physical sub-links connected to the first chip and the second chip to a port are both half of the first value.
[0069] In other words, for each port in the data processing device, all physical sub-links connected to that port are evenly connected to each chip in the data processing device, ensuring that the number of physical sub-links connected to the same port is the same for each chip. For example, in Figure 2 In this configuration, the first physical link connected to the first chip includes two physical sub-links, and the second physical link connected to the second chip also includes two physical sub-links. Furthermore, the first chip is connected to the first port via one physical sub-link and to the second port via one physical sub-link. Similarly, the second chip is connected to the first port via one physical sub-link and to the second port via one physical sub-link.
[0070] Of course, in other embodiments, the number of physical sub-links connecting the first chip and the second chip to each port may also be other values. For example, the first chip may be connected to the first port via two physical sub-links and to the second port via two physical sub-links. The second chip may also be connected to the first port via two physical sub-links and to the second port via two physical sub-links.
[0071] In summary, when the chips within a data processing device have the same bandwidth and each port provides the same bandwidth to the outside world, by evenly connecting the physical sub-links that each chip can connect to each port, it is possible to achieve the connection between the chip and the port, and ensure that data can be exchanged without blocking between any two ports.
[0072] Furthermore, in some possible embodiments, the number of physical sub-links connected to the first chip and the second chip may be different. For example, the bandwidth of the first chip may be half that of the second chip, the first chip may connect to 4 physical sub-links, while the second chip may connect to 8 physical sub-links. In this case, the first chip may connect to the first port via 2 physical sub-links and to the second port via 2 physical sub-links; while the second chip may connect to the first port via 4 physical sub-links and to the second port via 4 physical sub-links.
[0073] Optionally, in the above-mentioned data processing device, there are two ways to implement the first port and the second port.
[0074] In one possible implementation, both the first port and the second port are physical ports. That is, the first port and the second port are independent physical ports for pluggable optical fibers or cables. Other devices besides the data processing device can connect to the first port or the second port by inserting the connected physical lines such as optical fibers or cables into the first port or the second port.
[0075] For example, please refer to Figure 3 , Figure 3 This application provides a schematic diagram showing that the first and second ports are physical ports. For example... Figure 3 As shown, both the first and second ports are physical ports with a bandwidth of 400 (gigabits per second, Gbps) (referred to as 400G physical ports). Furthermore, within the data processing device, both the first and second ports can connect to four lanes, each with a bandwidth of 100Gbps. Therefore, in... Figure 3In this configuration, the first chip is connected to the first port via two physical sub-links and to the second port via another two physical sub-links. The second chip is also connected to the first port via two physical sub-links and to the second port via another two physical sub-links.
[0076] In another possible implementation, both the first port and the second port are logical ports derived from physical ports, and are used to connect different devices outside the data processing device. That is, the first port and the second port are not independent physical ports, but rather logical ports derived from a single physical port, and a physical port is typically composed of multiple logical ports. In this case, other devices of the data processing device are connected to the physical port to which the first port or the second port belongs via connected optical fibers or cables. Furthermore, although the first port and the second port are not independent physical ports, they still act as independent logical ports and are connected to different devices outside the data processing device to ensure data forwarding isolation between different devices.
[0077] For example, please refer to Figure 4 , Figure 4 This application provides a schematic diagram showing that the first and second ports are logical ports. For example... Figure 4 As shown, the first port and the second port are logical ports derived from the same 800G physical port; that is, the first port is 400G logical port 0, and the second port is 400G logical port 1. Furthermore, both the first and second ports can connect four links. Therefore, in Figure 4 In this configuration, the first chip is connected to the first port via two physical sub-links and to the second port via another two physical sub-links. The second chip is also connected to the first port via two physical sub-links and to the second port via another two physical sub-links. Thus, for the 800G physical port formed by the first and second ports, the first chip is actually connected to the 800G physical port via four physical sub-links, and the second chip is actually connected to the 800G physical port via eight physical sub-links.
[0078] Furthermore, taking an 800G physical port connected to an external fiber optic cable as an example, to enable different logical ports to connect to different devices outside the data processing device, a multi-channel optical module can be used to connect to the 800G physical port of the data processing device. One end of the optical module is a pluggable interface that inserts into the 800G physical port of the data processing device; the other end of the optical module connects to two pairs of optical fibers, which can connect to two different devices (e.g., two switches with a bandwidth of 400Gbps). Alternatively, when using fiber optic connectors (also known as fiber optic patch cords) to connect to the data processing device, one end of the fiber optic connector is inserted into the 800G physical port of the data processing device; the other end of the fiber optic connector connects to two pairs of optical fibers, which can connect to different devices.
[0079] It should be noted that the above example uses a port bandwidth of 400Gbps and each link connected to the port has a bandwidth of 100Gbps. In practical applications, the bandwidth of each link connected to the port can be, for example, 10Gbps, 25Gbps, 56Gbps, 224Gbps, 336Gbps, or 448Gbps, and the port bandwidth can be, for example, 400Gbps, 1.6Tbps, or 3.2Tbps. This application does not specifically limit the bandwidth of the port or the bandwidth of the links connected to the port. Furthermore, the above example uses an 800G physical port divided into two 400G logical ports. In practical applications, a physical port can be divided into two, four, or eight logical ports, and this application does not limit the number of logical ports that can be obtained from a single physical port.
[0080] The above embodiments describe a data processing device including a first chip and a second chip. In some scenarios, the data processing device can include more than two chips.
[0081] For example, please refer to Figure 5 , Figure 5 A schematic diagram of another data processing apparatus provided in this application. Figure 5 As shown, the data processing device includes a first chip, a second chip, and a third chip, as well as a first port and a second port. The first chip is connected to both the first and second ports via a first physical link, the second chip is connected to both the first and second ports via a second physical link, and the third chip is connected to both the first and second ports via a third physical link.
[0082] The third physical link includes at least two physical sub-links. The third chip is connected to the first port through at least one of the at least two physical sub-links and is also connected to the first port through at least one physical sub-link.
[0083] In other words, a data processing device may include two or more chips. Furthermore, each chip in the data processing device is physically connected to each port of the data processing device, thereby ensuring that data between any two ports can be forwarded using the same chip.
[0084] Optionally, there is no physical link connection between the first, second, and third chips. In other words, there is no physical link connection between any of the chips in the data processing device. Each chip in the data processing device receives data through one connected port and then directly forwards the data through another connected port, without forwarding the data to another chip. In this way, no additional bandwidth needs to be reserved for inter-chip links, ensuring that the bandwidth of the data processing device is the sum of the bandwidths of all the chips within it, thus maximizing the utilization of the chip bandwidth.
[0085] Optionally, in the data processing device, the first physical link, the second physical link, and the third physical link include the same number of physical sub-links. The number of physical sub-links connected to the first port and the second port are both the second value, and the number of physical sub-links connected to one port by the first chip, the second chip, and the third chip are all one-third of the second value.
[0086] In simple terms, when a data processing device comprises multiple chips, all physical sub-links connected to each chip in the data processing device are evenly connected to each port in the data processing device, ensuring that the number of physical sub-links connected to the same port by each chip is the same. For example, in Figure 5 In this configuration, the first physical link connected to the first chip, the second physical link connected to the second chip, and the third physical link connected to the third chip each include two physical sub-links. Furthermore, the first chip, the second chip, and the third chip are all connected to the first port via one physical sub-link and to the second port via another physical sub-link.
[0087] The above embodiments describe a data processing device that includes 3 chips and 2 ports. In practical applications, a data processing device may include two or more chips and two or more ports. This application does not specifically limit the number of chips and ports in a data processing device.
[0088] It should be noted that regardless of the number of chips and ports included in the data processing device, each chip must be physically connected to each port. Furthermore, to ensure non-blocking data exchange between ports, the chips in the data processing device need to be connected to the ports in a specific manner to ensure that each port provides the same bandwidth.
[0089] For example, please refer to Figure 6 , Figure 6 This is a schematic diagram illustrating the connection between multiple chips and multiple physical ports in a data processing device provided in this application. (See diagram for example.) Figure 6 As shown, the data processing device includes n chips (i.e., chip 1 to chip n) and y physical ports (i.e., physical port 1 to physical port y). Each physical port from physical port 1 to physical port y can connect to m links. In the case of chips 1 to chip n, assuming the number of links connecting each chip to a physical port is x, then x is the number of links a physical port can connect to divided by the number of chips, i.e., x = m / n. Here, x, m, and n are all positive integers.
[0090] In other words, when each chip connects to the same number of links, the multiple links connected to each chip are evenly distributed to each port, so that the number of links connected between different chips and the same physical port is the same (i.e., m / n).
[0091] Please see Figure 7 , Figure 7 This is a schematic diagram illustrating the connection between multiple chips and multiple logic ports in a data processing device provided in this application. Figure 7 As shown, the data processing device includes n chips (i.e., chip 1 to chip n) and y physical ports (i.e., port 1 to port y). Each physical port (port 1 to port y) includes z logical ports (i.e., port 1 to port z), and each physical port can connect to m links. Furthermore, the number of links connected to each logical port within a physical port is the same. In the case of chips 1 to chip n, assuming the number of links connected to a physical port for each chip is x, then x is the number of links that a physical port can connect to divided by the number of logical ports and the number of chips, i.e., x = m / z / n. Here, x, m, z, and n are all positive integers.
[0092] In simple terms, when each chip connects to the same number of links and a physical port is divided into multiple logical ports, all links connected to a physical port (such as...) Figure 7The m links in the physical port are evenly distributed to each logical port included in the physical port, and the multiple links connected to each chip are evenly distributed to each logical port, so that the number of links connected between different chips and the same logical port is the same (i.e., m / z / n).
[0093] The above describes the specific structure of the data processing device provided in this application. The following will describe the specific application scenarios of the data processing device.
[0094] For example, in the data processing device, the first chip and the second chip are programmable logic device (PLD) chips, application-specific integrated circuit (ASIC) chips, network processors (NP), central processing units (CPUs), graphics processing units (GPUs), neural-network processing units (NPUs), or tensor processing units (TPUs). The programmable logic device includes, for example, any one or more of the following devices: complex programmable logic device (CPLD), field-programmable gate array (FPGA), and generic array logic (GAL).
[0095] Of course, when the data processing device also includes other chips besides the first chip and the second chip, the other chips can specifically be the devices described above.
[0096] Specifically, taking the first chip as an example, when the first chip is a PLD chip, ASIC chip, or NP, it is essentially a data forwarding chip, responsible for forwarding data received from one port to another. When the first chip is a CPU, GPU, NPU, or TPU, it is essentially a computing chip, responsible for performing calculations on the data received from one port and sending the calculated data out from another port.
[0097] Optionally, the aforementioned data processing device may specifically be a switch, router, server, line card, optical tributary board, or optical line board. When the data processing device is a switch, router, or server, and the chip within the data processing device is a data forwarding chip, the ports in the data processing device are ports that provide data forwarding functionality to the outside world. Therefore, all links connected to the chip in the data processing device are connected to these ports to provide external bandwidth.
[0098] When the data processing device is a line card, optical tributary board, or optical line board in a network device, and the chip in the data processing device is a data forwarding chip, the ports in the data processing device are also ports that provide data forwarding functions to the outside world. However, the network device may also have other line cards, optical tributary boards, or optical line boards. Therefore, some links connected to the chip in the data processing device are connected to the ports that provide bandwidth to the outside world, while other links are connected to other line cards, optical tributary boards, or optical line boards in the network device.
[0099] When the data processing device is a server and the chip within it is a computing chip, the ports in the data processing device can be externally accessible ports, allowing other devices besides the server to connect via fiber optic cables or other cables. In this case, the chip in the data processing device receives data from one port, performs calculations on the data, and then forwards the calculated data out through another port.
[0100] When the data processing device is a server and the chip within it is a computing chip, the ports in the data processing device can also be internally provided ports. For example, a port in the data processing device could be a port connected to an internal data forwarding chip. In this case, the chip in the data processing device receives data from one of the connected ports, performs calculations on the data, and then forwards the calculated data out through any port. This allows the chip in the data processing device to process the data sent by the data forwarding chip inside the server.
[0101] In summary, the data processing device provided in this application can be applied to any data interaction scenario and can achieve large-capacity, non-blocking data interaction, which is beneficial for using the data processing device to meet networking requirements in various scenarios in practical applications.
[0102] For example, please refer to Figure 8 , Figure 8 This is a network topology diagram of a switch provided in this application. Figure 8 As shown, taking the spine-leaf network architecture as an example, the spine-leaf network architecture consists of spine switches and leaf switches.
[0103] The spine layer comprises 32 spine switches with a bandwidth of 100Tbps. The data processing device provided in this application specifically represents one spine switch. Furthermore, each spine switch includes two chips (e.g., Figure 8 The system consists of a first chip and a second chip, and 128 800G physical ports. At this time, both the first chip and the second chip are connected to each of the 128 800G physical ports through 4 physical sub-links, meaning that the bandwidth of each physical sub-link is 100Gbps.
[0104] In addition, the leaf layer provides 128 leaf switches (e.g.) Figure 8 The network consists of leaf switches 1 through 128. Each leaf switch has 64 800G physical ports, with 32 uplink 800G physical ports connected to the corresponding 800G physical ports of the spine switch, and the 32 downlink 800G physical ports connected to network interface cards (NICs). Therefore, since each leaf switch can connect to 32 NICs, the 128 leaf switches can connect to 4096 800Gbps bandwidth NICs, achieving a network scale of 4096 NICs.
[0105] For example, please refer to Figure 9 , Figure 9 A network diagram of another type of switch provided in this application. (See diagram below.) Figure 9 As shown, Figure 9 The network architecture also includes a spine layer and a leaf layer.
[0106] The spine layer comprises 64 spine switches with a bandwidth of 100Tbps. The data processing device provided in this application is specifically represented as one spine switch. Each spine switch includes a first chip, a second chip, and 128 800G physical ports, each of which can be divided into two 400G logical ports. In this case, both the first chip and the second chip are connected to each of the 256 400G logical ports via two physical sub-links.
[0107] In addition, the leaf layer provides 256 leaf switches (e.g.) Figure 8The network consists of leaf switches 1 through 256. Each leaf switch has 128 400G physical ports, with 64 uplink 400G physical ports connected to the corresponding 400G logical ports of the spine switches, and the other 64 downlink 400G physical ports connected to 400Gbps network interface cards (NICs). Therefore, since each leaf switch can connect 64 NICs, the 256 leaf switches can connect to 16,384 NICs, enabling a network with 16,384 NICs.
[0108] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A data processing apparatus, characterized by, Comprising: a first chip, a second chip, a first port and a second port; the first chip is connected to the first port and the second port through a first physical link respectively; the second chip is connected to the first port and the second port through a second physical link respectively.
2. The apparatus of claim 1, wherein, There is no physical link connection between the first chip and the second chip.
3. The apparatus of claim 1 or 2, wherein, The first physical link comprises at least two physical sublinks, and the first chip is connected to the first port through at least one of the at least two physical sublinks.
4. The apparatus according to claim 3, wherein: The number of physical sublinks connected by the first chip to the first port is the same as the number of physical sublinks connected by the first chip to the second port.
5. The apparatus according to any one of claims 1-4, wherein: The first physical link and the second physical link comprise the same number of physical sublinks, the number of physical sublinks connected to the first port and the second port is a first value, and the number of physical sublinks connected by the first chip and the second chip to one port is half of the first value.
6. The apparatus of any one of claims 1-5, wherein, The first port and the second port are physical ports; Or, the first port and the second port are logical ports divided based on physical ports, and the first port and the second port are used to connect different apparatuses other than the data processing apparatus.
7. The apparatus of claim 1, wherein, The apparatus further comprises a third chip; The third chip is connected to the first port and the second port through a third physical link respectively.
8. The apparatus of claim 7, wherein, There is no physical link connection between the first chip, the second chip and the third chip.
9. The apparatus of claim 7 or 8, wherein, The third physical link comprises at least two physical sublinks, and the third chip is connected to the first port through at least one of the at least two physical sublinks.
10. The apparatus of any of claims 7-9, wherein, The first physical link, the second physical link and the third physical link comprise the same number of physical sublinks, the number of physical sublinks connected to the first port and the second port is a second value, and the number of physical sublinks connected by the first chip, the second chip and the third chip to one port is one third of the second value.
11. The apparatus of any one of claims 1-10, wherein, The first chip and the second chip are programmable logic device (PLD) chips, application specific integrated circuit (ASIC) chips, network processors (NP), central processing units (CPU), graphics processing units (GPU), neural processing units (NPU) or tensor processing units (TPU).
12. The apparatus of any one of claims 1-11, wherein, The apparatus is a switch, a router, a server, a line card, an optical tributary board or an optical line board.
13. A data processing method applied to a data processing apparatus, the data processing apparatus comprising a first chip, a second chip, a first port and a second port, the first chip being connected to the first port and the second port through a first physical link respectively, and the second chip being connected to the first port and the second port through a second physical link respectively; The method comprises: The first chip receives first data from the first port through the first physical link; The first chip forwards the first data from the second port through the first physical link; The second chip receives second data from the first port through the second physical link; The second chip forwards the second data from the second port through the second physical link.
14. The method of claim 13, wherein, There is no physical link connection between the first chip and the second chip.
15. The method according to claim 13 or 14, characterized in that, The first physical link includes at least two physical sublinks, and the first chip is connected to the first port through at least one of the at least two physical sublinks.
16. The method of claim 15, wherein, The number of physical sublinks that the first chip is connected to on the first port is the same as the number of physical sublinks that the first chip is connected to on the second port.
17. The method of any one of claims 13-16, wherein, The first physical link and the second physical link include the same number of physical sublinks, the number of physical sublinks connected on the first port and the second port is a first value, and the number of physical sublinks that the first chip and the second chip are connected to on a port is half of the first value.
18. The method according to any one of claims 13-17, characterized by, The first port and the second port are both physical ports; Or, the first port and the second port are both logical ports divided based on physical ports, and the first port and the second port are used to connect different devices other than the data processing device.
19. The method of claim 13, wherein, The device further includes a third chip; the third chip is connected to the first port and the second port through a third physical link respectively; The method further includes: The third chip receives third data from the first port through a third physical link; The third chip forwards the third data from the second port through the third physical link.
20. The method of claim 19, wherein, There is no physical link connection between the first chip, the second chip and the third chip.
21. The method of claim 19 or 20, wherein, The third physical link includes at least two physical sublinks, and the third chip is connected to the first port through at least one of the at least two physical sublinks.
22. The method of any one of claims 19-21, wherein, The first physical link, the second physical link and the third physical link include the same number of physical sublinks, the number of physical sublinks connected on the first port and the second port is a second value, and the number of physical sublinks that the first chip, the second chip and the third chip are connected to on a port is one third of the second value.
23. The method of any one of claims 13-22, wherein, The first chip and the second chip are PLD chips, ASIC chips, NPs, CPUs, GPUs, NPUs or TPUs.
24. The method of any of claims 13-23, wherein, The device is a switch, a router, a server, a line card, an optical branch board or an optical line board.