Input transistor with built-in high frequency cut-off ring and method for manufacturing the same
By integrating capacitor dielectric and doped region inside the transistor, the problems of high cost and chip area waste caused by external high-frequency cutoff ring are solved, realizing a highly integrated input transistor with strong anti-interference capability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HANGZHOU ZHISHAN MICROELECTRONICS TECH CO LTD
- Filing Date
- 2026-02-05
- Publication Date
- 2026-05-12
AI Technical Summary
In existing technologies, high-frequency cutoff loops typically require external filter circuits or external resistors, resulting in high costs, low reliability, and wasted chip area.
Design an input transistor with a built-in high-frequency cutoff ring. By integrating a capacitor, dielectric, and doped region inside the transistor, high-frequency cutoff is achieved using concentrically arranged doped regions and metal lead-out layers, reducing external components and improving integration density.
It achieves input transistors with strong high-frequency cutoff capability, strong anti-interference capability, small chip area, and low cost.
Smart Images
Figure CN121645977B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to input transistors, and more particularly to an input transistor with a built-in high-frequency cutoff ring and its fabrication method. Background Technology
[0002] To achieve high-frequency cutoff, existing technologies typically use external filter circuits, which adds discrete components, increases costs, reduces reliability, and provides unsatisfactory anti-interference performance. Other technologies incorporate built-in high-frequency cutoff loops, but the matching resistors still need to be externally placed or appear as separate components in an independent layout, wasting chip area, reducing integration density, and increasing costs. Summary of the Invention
[0003] To address the above problems, this invention provides an input transistor with a built-in high-frequency cutoff ring and its fabrication method.
[0004] This invention provides the following technical solution: an input transistor with a built-in high-frequency cutoff ring, comprising a substrate, an epitaxial layer, and an insulating layer arranged sequentially from bottom to top, with a buried layer between the substrate and the epitaxial layer, a cylindrical first doped region within the epitaxial layer, an emitter region at the upper part of the first doped region, a capacitor dielectric disposed at the upper part of the emitter region, the first doped region and the capacitor dielectric being led out through a first metal as a base; the emitter region being led out through a second metal as an emitter.
[0005] The upper part of the epitaxial layer also has a second doped region disposed outside the first doped region, and a third doped region is disposed between the first doped region and the second doped region; the second doped region is led out through a third metal.
[0006] The epitaxial layer also has a diffusion region on the right side, which connects the buried layer and the insulating layer. The upper part of the diffusion region has a fourth doped region, which is led out through a fourth metal.
[0007] Furthermore, the first doped region is cylindrical, the emitter region is cylindrical, the capacitor dielectric is cylindrical, the second doped region is cylindrical, and the third doped region is cylindrical. The first doped region, the emitter region, the capacitor dielectric, the second doped region, and the third doped region are arranged concentrically.
[0008] Furthermore, the substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer, the buried layer is an N-type buried layer, the first doped region is a P-type doped region, the emitter region is an N+ emitter region, the second doped region is a P-type doped region, the diffusion region is an N+ diffusion region, and the fourth doped region is a P- doped region.
[0009] Furthermore, the substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, the buried layer is a P-type buried layer, the first doped region is an N-type doped region, the emitter region is a P+ emitter region, the second doped region is an N-type doped region, the diffusion region is a P+ diffusion region, and the fourth doped region is an N- doped region.
[0010] Furthermore, the capacitor dielectric is silicon dioxide, silicon nitride, or a composite material of silicon dioxide and silicon nitride.
[0011] A method for fabricating an input transistor with a built-in high-frequency cutoff ring includes the following steps:
[0012] (1) An N-type buried layer is fabricated on a P-type substrate by patterning a photomask and implanting As with ions;
[0013] (2) Grow an N-type epitaxial layer with a thickness of 2-10 μm and a doping concentration of 1e14 cm⁻¹. -3 ~1e16cm -3 ;
[0014] (3) An N+ diffusion region is created on the N-type epitaxial layer by using a patterned photomask and ion implantation of phosphorus.
[0015] (4) A first P-type region (5) and a second P-type region are fabricated on the N-type epitaxial layer by patterning a photomask and implanting BF2 or B11 with ions.
[0016] (5) On the N-type epitaxial layer, a patterned photomask is used to create an emitter region, a third doped region and a fourth doped region by ion implantation of phosphorus or arsenic, and boron is implanted to create a P-body region.
[0017] (6) Thermal oxidation of the silicon surface, followed by deposition of SiO2 or Si3N4, to create an insulating layer;
[0018] (7) The capacitor dielectric is fabricated by patterning a photomask and etching;
[0019] (8) The lead hole layer is fabricated by patterning a photomask and etching;
[0020] (9) Fabricate metal lead-out layers: first metal, second metal, third metal and fourth metal.
[0021] Cutoff frequency f T Follow formula f T =1 / (2πRC), where R is the resistance and C is the capacitance. Designers can set different resistance and capacitance values according to different product application fields to achieve different cutoff frequency requirements.
[0022] The beneficial effects of this invention are as follows:
[0023] The input transistors of this invention have high integration density, strong anti-interference ability, small chip area, and low cost. Attached Figure Description
[0024] Figure 1 This is a schematic diagram of the input transistor with a built-in high-frequency cutoff loop in this invention.
[0025] Figure 2 This is the equivalent circuit diagram of the input transistor with a built-in high-frequency cutoff ring in this invention.
[0026] Among them, substrate 1, epitaxial layer 2, insulating layer 3, buried layer 4, first doped region 5, emitter region 6, capacitor dielectric 7, first metal 8, second metal 9, second doped region 10, third doped region 11, third metal 12, diffusion region 13, fourth doped region 14, and fourth metal 15. Detailed Implementation
[0027] To further illustrate the technical means and effects of the present invention in achieving its intended purpose, the following detailed description of the specific implementation methods, structures, features, and effects of the present invention, in conjunction with the accompanying drawings and preferred embodiments, is provided below.
[0028] The input transistors of this invention have high integration density, strong anti-interference ability, small chip area, and low cost.
[0029] The embodiments of the present invention will be further described below with reference to several examples.
[0030] Example 1
[0031] like Figure 1 The input transistor with a built-in high-frequency cutoff ring includes a substrate 1, an epitaxial layer 2, and an insulating layer 3 arranged sequentially from bottom to top. A buried layer 4 is provided between the substrate 1 and the epitaxial layer 2. A first doped region 5 is provided in the epitaxial layer 2. An emitter region 6 is provided in the upper part of the first doped region 5. A capacitor dielectric 7 is provided in the upper part of the emitter region 6. The first doped region 5 and the capacitor dielectric 7 are led out through a first metal 8 as the base. The emitter region 6 is led out through a second metal 9 as the emitter.
[0032] The upper part of the epitaxial layer 2 also has a second doped region 10 disposed outside the first doped region 5, and a third doped region 11 is disposed between the first doped region 5 and the second doped region 10; the second doped region 10 is led out through the third metal 12.
[0033] The epitaxial layer 2 also has a diffusion region 13 on the right side, which connects the buried layer 4 and the insulating layer 3. The upper part of the diffusion region 13 has a fourth doped region 14, which is led out through a fourth metal 15.
[0034] Specifically, it includes a P-type substrate 1, an N-type epitaxial layer 2, and an insulating layer 3 arranged sequentially from bottom to top. An N-type buried layer 4 is located between the P-type substrate 1 and the N-type epitaxial layer 2. A first P-type region 5 is located within the N-type epitaxial layer 2. An N+ emitter region 6 is located above the first P-type region 5. A capacitor dielectric 7 is located above the N+ emitter region 6. The first P-type region 5 and the capacitor dielectric 7 are led out through a first metal 8 to serve as the base. The N+ emitter region 6 is led out through a second metal 9 to serve as the emitter.
[0035] The N-type epitaxial layer 2 also has a second P-type region 10 disposed outside the first P-type region 5, and a first P-region 11 is disposed between the first P-type region 5 and the second P-type region 10; the second P-type region 10 is led out through the third metal 12;
[0036] The right side of the N-type epitaxial layer 2 also has an N+ diffusion region 13, which connects the N-type buried layer 4 and the insulating layer 3. The upper part of the N+ diffusion region 13 has a third P-type region 14, which is led out through a fourth metal 15.
[0037] The capacitor dielectric 7 is silicon dioxide, and in some embodiments it may also be silicon nitride or a composite material of silicon dioxide and silicon nitride.
[0038] Figure 2 This is the equivalent circuit of the input transistor with a built-in high-frequency cutoff loop.
[0039] Example 2
[0040] like Figure 1 The input transistor with a built-in high-frequency cutoff ring includes a substrate 1, an epitaxial layer 2, and an insulating layer 3 arranged sequentially from bottom to top. A buried layer 4 is provided between the substrate 1 and the epitaxial layer 2. The epitaxial layer 2 has a cylindrical first doped region 5. The upper part of the first doped region 5 has a cylindrical emitter region 6. A cylindrical capacitor dielectric 7 is provided on the upper part of the emitter region 6. The first doped region 5 and the capacitor dielectric 7 are led out through a first metal 8 as the base. The emitter region 6 is led out through a second metal 9 as the emitter.
[0041] The upper part of the epitaxial layer 2 also has a cylindrical second doped region 10 disposed outside the first doped region 5, and a cylindrical third doped region 11 is disposed between the first doped region 5 and the second doped region 10; the second doped region 10 is led out through the third metal 12.
[0042] The epitaxial layer 2 also has a diffusion region 13 on the right side, which connects the buried layer 4 and the insulating layer 3. The upper part of the diffusion region 13 has a fourth doped region 14, which is led out through a fourth metal 15.
[0043] The first doped region, emitter region, capacitor dielectric, second doped region, and third doped region are arranged concentrically.
[0044] Specifically, it includes an N-type substrate 1, a P-type epitaxial layer 2, and an insulating layer 3 arranged sequentially from bottom to top. A P-type buried layer 4 is located between the N-type substrate 1 and the P-type epitaxial layer 2. A cylindrical first N-type region 5 is located within the P-type epitaxial layer 2. A cylindrical P+ emitter region 6 is located at the upper part of the first N-type region 5. A cylindrical capacitor dielectric 7 is located at the upper part of the P+ emitter region 6. The first N-type region 5 and the capacitor dielectric 7 are led out through a first metal 8 as the base. The P+ emitter region 6 is led out through a second metal 9 as the emitter.
[0045] The P-type epitaxial layer 2 also has a cylindrical second N-type region 10 disposed outside the first N-type region 5, and a cylindrical first N-region 11 is disposed between the first N-type region 5 and the second N-type region 10; the second N-type region 10 is led out through the third metal 12.
[0046] The right side of the P-type epitaxial layer 2 also has a P+ diffusion region 13, which connects the P-type buried layer 4 and the insulating layer 3. The upper part of the P+ diffusion region 13 has a third N-type region 14, which is led out through the fourth metal 15.
[0047] The first N-type region 5, the P+ emitter region 6, the capacitor dielectric 7, the first N- region 11, and the second N-type region 10 are arranged concentrically.
[0048] The capacitor dielectric 7 is silicon nitride, and in some embodiments it may also be silicon dioxide or a composite material of silicon dioxide and silicon nitride.
[0049] Figure 2 This is the equivalent circuit of the input transistor with a built-in high-frequency cutoff loop.
[0050] Example 3
[0051] The fabrication method of the input transistor with a built-in high-frequency cutoff loop in Example 1 includes the following steps:
[0052] (1) An N-type buried layer 4 was fabricated on a P-type substrate 1 by patterning a photomask and implanting As with ions;
[0053] (2) An N-type epitaxial layer 2 with a thickness of 2-10 μm and a doping concentration of 1e14 cm⁻¹ is grown. -3 ~1e16cm -3 ;
[0054] (3) An N+ diffusion region 13 was created on the N-type epitaxial layer 2 by patterning a photomask and ion implanting phosphorus.
[0055] (4) A first P-type region 5 and a second P-type region 10 are fabricated on the N-type epitaxial layer 2 by patterning a photomask and ion implanting BF2 or B11.
[0056] (5) On the N-type epitaxial layer 2, a patterned photomask is used to create an emission region 6, a third doped region 11 and a fourth doped region 14 by ion implantation of phosphorus or arsenic. Boron is then implanted to create a P-body region 11.
[0057] (6) Thermal oxidation of the silicon surface, followed by deposition of SiO2 or Si3N4, to create insulating layer 3;
[0058] (7) The capacitor dielectric 7 is fabricated by patterning a photomask and etching;
[0059] (8) The lead hole layer is fabricated by patterning a photomask and etching;
[0060] (9) Fabricate metal lead-out layers: first metal 8, second metal 9, third metal 12 and fourth metal 15.
[0061] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. An input transistor with a built-in high-frequency cutoff loop, characterized in that, The device comprises a substrate, an epitaxial layer, and an insulating layer arranged sequentially from bottom to top. A buried layer is located between the substrate and the epitaxial layer. The epitaxial layer has a cylindrical first doped region. An emitter region is located at the top of the first doped region. A capacitor dielectric is disposed at the top of the emitter region. The first doped region and the capacitor dielectric are led out through a first metal to serve as the base. The emitter region is led out through a second metal to serve as the emitter. The upper part of the epitaxial layer also has a second doped region disposed outside the first doped region, and a third doped region is disposed between the first doped region and the second doped region; the second doped region is led out through a third metal. The epitaxial layer also has a diffusion region on the right side, which connects the buried layer and the insulating layer. The upper part of the diffusion region has a fourth doped region, which is led out through a fourth metal.
2. The input transistor with a built-in high-frequency cutoff loop according to claim 1, characterized in that, The first doped region is cylindrical, the emitter region is cylindrical, the capacitor dielectric is cylindrical, the second doped region is cylindrical, and the third doped region is cylindrical. The first doped region, emitter region, capacitor dielectric, second doped region, and third doped region are arranged concentrically.
3. The input transistor with a built-in high-frequency cutoff loop according to claim 1, characterized in that, The substrate is a P-type substrate, the epitaxial layer is an N-type epitaxial layer, the buried layer is an N-type buried layer, the first doped region is a P-type doped region, the emitter region is an N+ emitter region, the second doped region is a P-type doped region, the diffusion region is an N+ diffusion region, and the fourth doped region is a P- doped region.
4. The input transistor with a built-in high-frequency cutoff loop according to claim 1, characterized in that, The substrate is an N-type substrate, the epitaxial layer is a P-type epitaxial layer, the buried layer is a P-type buried layer, the first doped region is an N-type doped region, the emitter region is a P+ emitter region, the second doped region is an N-type doped region, the diffusion region is a P+ diffusion region, and the fourth doped region is an N- doped region.
5. The input transistor with a built-in high-frequency cutoff loop according to any one of claims 1-4, characterized in that, The capacitor dielectric is silicon dioxide, silicon nitride, or a composite material of silicon dioxide and silicon nitride.
6. A method for fabricating an input transistor with a built-in high-frequency cutoff loop as described in claim 1, characterized in that, Includes the following steps: (1) An N-type buried layer is fabricated on a P-type substrate by patterning a photomask and implanting As with ions; (2) Grow an N-type epitaxial layer with a thickness of 2-10 μm and a doping concentration of 1e14 cm⁻¹. -3 ~1e16cm -3 ; (3) An N+ diffusion region is created on the N-type epitaxial layer by using a patterned photomask and ion implantation of phosphorus; (4) A patterned photomask is applied to the N-type epitaxial layer, and BF2+ or ion implantation is performed. 11 B, create the first P-type region (5) and the second P-type region; (5) On the N-type epitaxial layer, a patterned photomask is used to create an emitter region, a third doped region, and a fourth doped region by ion implantation of phosphorus or arsenic. Boron is then implanted to create a P-body region. (6) Thermal oxidation of the silicon surface, followed by deposition of SiO2 or Si3N4, to create an insulating layer; (7) The capacitor dielectric is fabricated by patterning a photomask and etching; (8) The lead hole layer is fabricated by patterning a photomask and etching; (9) Fabricate metal lead-out layers: first metal, second metal, third metal and fourth metal.