Chip mass production test method and device, chip and electronic equipment
By automatically generating target test programs for chips, the problem of low efficiency in traditional manual coding is solved, and efficient and accurate chip mass production testing is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-22
- Publication Date
- 2026-03-13
AI Technical Summary
Traditional chip mass production test program development relies on manual coding, which is inefficient and prone to errors.
By acquiring configuration files and chip information, the target test program for the chip is automatically generated, including the connection relationship between pins and the power supply channel of the test machine. The parameters are automatically updated using the ATE test program template to generate high-quality test code.
It improves the development efficiency of chip mass production test programs, reduces human error, and ensures the accuracy of test objects and hardware circuits as well as the comprehensiveness of test plans.
Smart Images
Figure CN121656799A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chips, specifically to a chip mass production testing method, apparatus, chip, and electronic equipment. Background Technology
[0002] In the mass production of integrated circuits (ICs), automated test equipment (ATE) is a critical component in ensuring that chip performance, functionality, and quality meet design specifications. ATE performs comprehensive parameter measurements, functional verification, and defect screening on the chip by executing pre-developed test programs.
[0003] Currently, the traditional ATE test program development process in the industry usually requires test development engineers to read and understand the test plan (for example, the test plan defines test items, test parameters, etc.), and then the test development engineers need to manually develop programming language code that the ATE equipment can recognize based on the test plan.
[0004] However, this traditional development model, which relies heavily on manual coding, is inefficient and prone to human error. Summary of the Invention
[0005] To address the aforementioned issues, this application provides a chip mass production testing method, apparatus, chip, and electronic device, which can improve the efficiency of chip mass production testing program development.
[0006] In a first aspect, this application provides a chip mass production testing method, the method comprising: obtaining a configuration file, the configuration file including test scheme data and information for each chip among multiple chips; generating a corresponding chip model based on the information for each chip; generating a target test model for each chip based on the chip model for each chip; obtaining a test program template corresponding to each chip, the test program template corresponding to each chip corresponding to the target model of the test machine corresponding to each chip; updating the parameters in the test program template corresponding to each chip; obtaining the target test program for each chip and importing it into the test machine to test each chip.
[0007] In this embodiment of the application, for mass production chip testing scenarios, a target test program (such as a target ATE test program) for each chip can be automatically generated based on the configuration of a batch of chips (such as multiple different chips). This can avoid the problems of low efficiency and high error rate caused by manual development and improve the development efficiency of chip mass production test programs.
[0008] In one implementation of the first aspect, the target test model for each chip includes the target connection relationship between the pins of each chip and the power supply channel of the test machine.
[0009] In one implementation of the first aspect, updating the parameters in the test program template corresponding to each chip includes: updating the parameters in the test program template corresponding to each chip based on the test scheme data of each chip, the chip model of each chip, and the target test model of each chip.
[0010] In one implementation of the first aspect, the information for each chip includes the target model of the test machine corresponding to each chip. Based on the information for each chip, a corresponding chip model is generated, including: generating an initial test model that matches the target model, the initial test model including the initial connection relationship between the pins of each chip and the power channel of the test machine; updating the initial connection relationship between the pins of each chip and the power channel of the test machine in the initial test model to the target connection relationship between the pins of each chip and the power channel of the test machine, thereby obtaining the chip model corresponding to each chip.
[0011] In one implementation of the first aspect, the configuration file also includes a save path and obtaining the test program template corresponding to each chip, including: determining the template folder corresponding to the target model; and storing the project files in the template folder to the save path, wherein the project files include the test program template.
[0012] In one implementation of the first aspect, the information for each chip includes the chip type, and the test plan data for each chip includes test parameters. Based on the test plan data for each chip, the chip model for each chip, and the target test model for each chip, the parameters in the test program template corresponding to each chip are updated, including: adding test code blocks to the test program template corresponding to each chip based on the test plan data for each chip and the chip model for each chip, wherein the test code blocks match the chip type and target model, and the number of test code blocks is consistent with the number of test parameters; and updating the parameters in the test code blocks based on the test plan data for each chip and the target test model for each chip.
[0013] In one implementation of the first aspect, the test scheme data also includes test parameters, test conditions, upper limit of test value, and lower limit of test value. Based on the test scheme data for each chip and the target test model for each chip, the parameters in the test code block are updated, including: replacing the pins and power channels in the test code block with the pins and power channels of each chip in the target test model, respectively, according to the target test model for each chip; and replacing the test parameters, test conditions, upper limit of test value, and lower limit of test value in the ATE test program template corresponding to each chip with the test parameters, test conditions, upper limit of test value, and lower limit of test value in the test scheme data for each chip, respectively, according to the test scheme data.
[0014] In one implementation of the first aspect, the method further includes: uploading a target test program for each chip to a server, wherein the target test program for each chip is used to download from the server to at least two test machines of the target model, and the at least two test machines are used to test each chip based on the target test program for each chip.
[0015] In one implementation of the first aspect, the method further includes: obtaining historical test report data of a second chip, wherein the second chip is a historical version of the first chip; generating test plan data of the first chip based on the historical test report data of the second chip, wherein the test plan data of the first chip includes a first test parameter, wherein the first test parameter is an abnormal parameter in the historical test report data of the second chip.
[0016] In one implementation of the first aspect, after generating the corresponding chip model, the method further includes: displaying a preview image of the chip model of each chip; if the preview image of the chip model of the third chip does not match the third chip, updating the chip information of the third chip, and regenerating the chip model of the third chip based on the updated chip information of the third chip.
[0017] In one implementation of the first aspect, the test plan data includes at least one of the following: test items, test parameters, test conditions, upper limit of test value, lower limit of test value, category number, and storage path.
[0018] In one implementation of the first aspect, the chip information includes at least one of the following: chip type, chip package type, number of chip pins, name and order of chip pins, and target model.
[0019] In a second aspect, this application provides an electronic device, comprising: a memory for storing one or more programs; and a processor for executing one or more programs to cause the electronic device to implement the method of the first aspect.
[0020] Thirdly, this application provides a computer-readable storage medium storing one or more programs, which, when executed on an electronic device, cause the electronic device to implement the method of the first aspect. Attached Figure Description
[0021] Figure 1 A schematic flowchart of a chip mass production testing method is shown according to an embodiment of this application;
[0022] Figure 2 A schematic diagram of a configuration file is shown according to an embodiment of this application;
[0023] Figure 3 A schematic diagram of a test model is shown according to an embodiment of this application;
[0024] Figure 4 A schematic diagram of a chip mass production testing system is shown according to an embodiment of this application;
[0025] Figure 5 A schematic diagram of an interactive interface is shown according to an embodiment of this application;
[0026] Figure 6 A structural block diagram of a server is shown according to an embodiment of this application. Detailed Implementation
[0027] The illustrative embodiments of this application include, but are not limited to, a chip mass production testing method, apparatus, chip, and electronic device.
[0028] The specific implementation process of the technical solution provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0029] As mentioned before, the traditional method of manually developing ATE code is inefficient and prone to human error.
[0030] This application provides a program generation method. By acquiring user-imported test plan data (such as test plan documents), user-configured chip models and test models, and obtaining an ATE test program template, specific parameters can be modified based on the test plan data, chip models, and test models to automatically generate a target ATE test program. This avoids the inefficiency and high error rate problems caused by manually developing ATE programs.
[0031] The following describes an exemplary flow of a chip mass production testing method provided in an embodiment of this application. It is understood that the method is applied to electronic devices, and references are made to... Figure 1 An exemplary process of the method includes the following steps.
[0032] S101: Obtain the configuration file, which includes test scheme data and information for each chip in the multiple chips.
[0033] According to some embodiments, each of the multiple chips is based on a different chip model. It can be understood that the chip mass production testing method provided in this application can automatically generate target ATE mass production test code for each chip (i.e., each chip model).
[0034] According to some embodiments, the test plan data includes one or more of the following information: test items, test parameters, test conditions, upper limit of test value, lower limit of test value, category number, and storage path.
[0035] See Figure 2 According to one embodiment, the configuration file includes, for example: Figure 2 The three test items shown are: open / short (OS), I-shutdown (ISD), and performance test at 1575MHz (SP_1575), along with multiple test parameters for each item. Each parameter includes the test conditions, test description, upper and lower limits of the test value, and hardware BIN (as an example of a classification number). OS is used to verify the good connection between the chip pins and the test machine and to check for chip defects. ISD measures the static power consumption of the chip in its non-operating state. SP_1575 verifies the RF characteristics of the chip at 1575MHz.
[0036] Test parameters represent the specific object or signal to be measured in a test item. For example, under the OS test item, the test parameters include the names of each pin (such as VCC, EN, RFIN, RFOUT), indicating that these pins are tested for open / short circuits one by one. Under the ISO test item, the test parameters include the current under different conditions; for example, VCC_3P1 can represent the VCC current at 3.1V. Under the SP_1575 item, the test parameters are RF specifications (such as S11, S12).
[0037] Test conditions indicate the electrical environment that the tester needs to provide to the chip during test execution. For example, "Set: =-1mA, Others Set: = 0V" means applying a current of -1mA to the pin under test, and setting all other pins to 0V. For example, "VCC = 3.1V, EN = 0V" means providing 3.1V to the VCC pin and 0V to the EN pin.
[0038] The test description is an instruction on the test operation, indicating the excitation sequence in the target ATE test program corresponding to the test plan. For example, "VCC = 1.8V, EN = 1.8V, RFIN=0V, RFOUT=0V, Shz=1575, Sdb=-30" means that first, a 1.8V voltage is applied to the VCC pin to establish power, then a 1.8V voltage is provided to the EN pin to enable the chip, then the DC bias of the RFIN and RFOUT pins is set to 0V, and finally the signal parameters are configured, that is, the frequency of the RF signal input to the chip is controlled to be 1575MHz and the power of the RF signal is -30dBm.
[0039] The upper limit, lower limit, and unit of the test value define the acceptable range of the test parameter. In other words, if the test result is less than or equal to the upper limit and greater than or equal to the lower limit, the chip is considered to have passed the test parameter.
[0040] The hardware BIN is a classification identifier. For example, if the BIN is 1, it means the chip has passed all the test items, that is, all the test items are qualified. If the test result of the OS test item is unqualified, the hardware BIN of the chip is 5. If the test result of the ISD test item is unqualified, the hardware BIN of the chip is 6. If the test result of the SP_1575 test item is unqualified, the hardware BIN of the chip is 7.
[0041] It can be understood that Figure 2 The configuration file shown is only an example, and the present application does not limit the specific data in the configuration file.
[0042] According to some embodiments, the information of each chip includes one or more of the following information: chip type, chip package type, number of chip pins, names and arrangement order of chip pins, target model.
[0043] S102: Based on the information of each chip, generate the corresponding chip model.
[0044] According to some embodiments, after generating the chip model of each chip, a preview image of the chip model of each chip can be displayed. And, in the case where the preview image of the chip model of the chip does not match the chip itself, update the chip information of the chip, and regenerate the chip model of the chip based on the updated chip information.
[0045] For example, the preview image of the chip model can be matched with a reference image, and it is determined that they do not match when the matching degree is lower than the threshold.
[0046] For another example, the preview image can be displayed to the user. In the case where the user views the preview image and determines that the preview image does not conform to the actual structure of the chip, the user can manually update the chip information in the configuration file and re-import the configuration file, so that the chip model configuration module can update the chip information and regenerate the chip model of the chip based on the updated chip information.
[0047] S103: Generate the target test model of each chip based on the chip model of each chip.
[0048] According to some embodiments, the target test model of each chip includes the target connection relationship between the pins of each chip and the power channels of the testing machine.
[0049] It can be understood that the target test model is used to define the connection relationship between the pins of the chip and the power channels of the testing machine. For example, referring to Figure 3 , a target test model can define the connection relationship between 6 pins of the chip and 6 power channels respectively.
[0050] According to some embodiments, an initial test model matching the target model can be generated based on the target model. The initial test model includes the initial connection relationship between the pins of each chip and the power channel of the test machine. Then, the initial connection relationship between the pins of each chip and the power channel of the test machine in the initial test model is updated to the target connection relationship between the pins of each chip and the power channel of the test machine, so as to obtain the target test model for each chip.
[0051] S104: Obtain the test program template corresponding to each chip. The test program template corresponding to each chip corresponds to the target model of the test machine corresponding to each chip.
[0052] According to some embodiments, the test program template may be an ATE test program template.
[0053] According to some embodiments, the template folder corresponding to the target model can be determined; the project files in the template folder are stored in the save path, wherein the project files include ATE test program templates.
[0054] S105: Generate a target test model for each chip based on the chip model of each chip; obtain the test program template corresponding to each chip, which corresponds to the target model of the test machine corresponding to each chip; update the parameters in the test program template corresponding to each chip; obtain the target test program for each chip and import it into the test machine to test each chip.
[0055] For example, the target test program is, for instance, the target ATE test program.
[0056] According to some embodiments, the parameters in the test program template corresponding to each chip are updated, including: based on the test scheme data of each chip, the chip model of each chip, and the target test model of each chip, the parameters in the test program template corresponding to each chip are updated.
[0057] According to some embodiments, test code blocks can be added to the test program template corresponding to each chip based on the test plan data and chip model of each chip. The test code blocks match the chip type and target model, and the number of test code blocks matches the number of test parameters. Based on the test plan data and target test model of each chip, the parameters in the test code blocks are updated to obtain the target test program for each chip. For example, test code blocks matching the chip type, target model, and test items can be obtained from a standardized code library first. Then, according to the number of test parameters in the test items, the test code blocks are copied to obtain the code block corresponding to each test parameter. For example, for n test parameters, the test code library is copied n-1 times to obtain n test code blocks.
[0058] According to some embodiments, updating the parameters in the test code block may include: replacing the pins and power channels in the test code block with the pins and power channels of each chip in the target test model, respectively, according to the target test model of each chip; and replacing the test parameters, test conditions, upper limit of test value, and lower limit of test value in the test program template corresponding to each chip with the test parameters, test conditions, upper limit of test value, and lower limit of test value in the test plan data of each chip, respectively, according to the test plan data.
[0059] It is understood that in the embodiments of this application, the generated target test program can be used to test chips on target test platforms of multiple target models. Specifically, the target test program for each chip is used to test chips of the same model. For example, the target test program for each chip can be uploaded to a server. The target test program for each chip is then downloaded from the server to at least two test machines of the target model, and these at least two test machines test each chip based on the target test program for each chip. Thus, the target test program for each of multiple chips is uploaded to the server.
[0060] According to some embodiments, for chips of the same series, before testing a new version of the chip, historical test report data of the old version chip can be automatically analyzed to automatically generate recommended test items or test parameters for testing the new version chip. For example, test parameters with a high failure rate in the historical test report data can be used as test parameters in the configuration file of the new version chip, or the number of tests for that test parameter can be increased. For instance, historical test report data of the old version chip can be obtained; based on the historical test report data of the old version chip, test plan data for the new version chip can be generated, wherein the test plan data for the new version chip includes a first test parameter, which may be, for example, an abnormal parameter in the historical test report data of the old version chip.
[0061] In this embodiment, the process of writing test code is transformed into a series of intuitive configuration operations. Engineers only need to import the test plan, configure the chip model, and verify the test model to generate high-quality, error-free initial code in a very short time. Furthermore, code can be generated for each chip in a batch, allowing for the generation of mass production test code for the entire batch at once. This not only ensures the accuracy of the test object and the test hardware circuit but also guarantees the comprehensive coverage of the test plan through standardized templates. The generated code can be directly imported into equipment (such as ATE equipment) for on-site debugging, greatly shortening the development cycle of mass production chip test programs and significantly improving engineers' development efficiency.
[0062] The following is combined Figure 4 This application introduces a chip mass production testing system provided in an embodiment.
[0063] See Figure 4 According to one embodiment, the chip mass production testing system includes a test plan import module, a chip model configuration module, a test model configuration module, and a code generation module.
[0064] The test plan import module is used to import structured configuration files. These configuration files can be, for example, tabular files or structured text files, such as xlsx, xls, csv, json, or xml formats. This application does not impose any restrictions on the format of the configuration files.
[0065] For example, the configuration file can define a chip test plan, such as defining the test item name, test function items, test parameters corresponding to each item, test conditions, and upper and lower limits for parameter pass / fail. Furthermore, the configuration file can also include the chip type of the chip under test configured by the user, and the save path of the target test program specified by the user.
[0066] It is understandable that other aspects of the test plan import module's functionality can be found in the previous description of S101, and will not be repeated here.
[0067] The chip model configuration module is used to create a chip model of the chip under test. In this module, users configure the chip's physical characteristics, such as chip model, chip package, number of pins, pin names and their order, as well as the hardware test platform, i.e., the target model of the test machine. This module provides the chip's hardware context for subsequent processes.
[0068] For example, the configuration file can include configurable information from the aforementioned chip model, such as the chip model, chip package, number of chip pins, pin names and their order, and the target model of the test machine. Thus, the chip model configuration module can read the relevant information from the configuration file and automatically build the chip test model.
[0069] It is understandable that other functions of the chip model configuration module can be found in the previous description of S102, and will not be repeated here.
[0070] The test model configuration module is used to automatically generate standardized test models based on the aforementioned chip model and hardware test platform. The test model defines the signal allocation during chip testing. For example, the test model uses default rules to assign a power channel from the test machine to each pin; or, for example, the configuration file can include pin power configuration information, which may specify which power channel from the test machine is assigned to each chip, i.e., the connection relationship between the chip pins and the test machine's power channels. Therefore, the test model configuration module can automatically configure the power channels for each chip pin in the test model based on the pin power configuration information in the configuration file.
[0071] In some embodiments, users can flexibly modify the power supply corresponding to any pin of the chip based on all power options supported by the test platform, i.e. all power channels of the test machine, according to the actual hardware connection of the test board, thus ensuring the consistency between the test model and the real test environment.
[0072] It is understandable that other aspects of the test model configuration module's functionality can be found in the previous description of S103, and will not be repeated here.
[0073] The code generation module is the execution engine of the entire device, and its workflow is as follows.
[0074] First, the code generation module locates the corresponding project template for the target model of the test machine (i.e., the hardware test platform) from the pre-stored template folder, and copies all files (including the main test file) from the project template to the target project folder. For example, the path of the target project folder is the save path configured by the user in the configuration file.
[0075] Subsequently, the code generation module automatically updates information related to the current test project in the project files within the target project folder based on the configuration file. For example, it might rename the project file to the test project name (or project name) specified in the configuration file. It might also update chip version information, such as including the chip model number. For instance, the same chip signal may have multiple versions, each corresponding to a version number. For example, it might update the test platform information, such as updating the test machine model to the target model in the configuration file. Furthermore, it might update the parallel test quantity information, which indicates the number of chips tested simultaneously during the testing of the same model or version of a chip; for example, a quantity of 8 indicates that 8 chips of the same model and version can be tested simultaneously. It's understood that the updated information can be configured by the user in the configuration file, allowing the code generation module to automatically update the information in the project files.
[0076] Next, the code generation module opens the main test file in the project file and, starting from the beginning of the test function, writes the test code for each test item in the configuration file. For example, for each test item, the code generation module searches for standard code blocks corresponding to the chip type and hardware test platform in the standardized code library and copies the standard code block corresponding to the test item to the main test file. Then, for each test sub-item under that test item (i.e., each test parameter under the test item), the code generation module copies the standard code block to generate the corresponding test sub-code block for each test sub-item. After this, the code generation module iterates through all the generated code, and based on the connection relationship of the chip pins and power channels defined in the configuration file in the test model configuration module, automatically replaces the pin and power variables in the code with the actual configuration values, and fills in the various parameters specified in the test plan, such as test conditions, upper limit of measurement value, lower limit of measurement value, and unit of measurement value. This process is executed cyclically until all test items and test sub-items in the chip test plan have been processed, thereby generating ATE program code that can be directly used for testing.
[0077] It is understandable that other aspects of the code generation module's functionality can be found in the descriptions of S104 and S105 above, and will not be repeated here.
[0078] The following is combined Figure 5 This application introduces an interactive interface provided by an embodiment. For example... Figure 5 As shown, the interactive interface includes a chip model preview area, a test model preview area, a test scheme preview area, and a target ATE mass production test code preview area. The chip model and test model preview areas are used to preview the chip images generated by the chip model configuration module, as well as the connection relationships between the chip pins and the test machine power supply channels. For example, the preview image is as follows: Figure 3 As shown. The test plan preview area is used to preview the test plan for the chip, including various test items, test parameters, test conditions, etc. For example, the preview image is as follows. Figure 2 As shown. The target ATE mass production test code area is used to preview the generated target ATE mass production test code.
[0079] like Figure 5 As shown, the interactive interface also includes interactive controls. These include controls for importing configuration files, generating chip models, generating test models, generating code, enabling repair, generating test projects, and sending projects.
[0080] For example, an import configuration file control is used to import configuration files. For instance, in response to a user's touch on the import configuration file control, a file explorer can be displayed, and in response to a user's touch on a configuration file in the file explorer, the configuration file can be retrieved.
[0081] For example, a chip model generation control is used to generate a chip model. For instance, in response to a user's touch operation on the chip model generation control, a chip model can be generated based on a configuration file. For instance, after generating the chip model, an image of the chip model can be previewed in the chip model and test model preview areas for user confirmation.
[0082] For example, a test model generation control is used to generate a test model. For instance, in response to a user's touch operation on the test model generation control, a test model can be generated based on a configuration file. For instance, after generating the test model, the connection relationships between the chip pins and the power supply channels of the test machine can be previewed in the chip model and test model preview areas.
[0083] For example, the generated code is used to generate mass production test code for the target ATE. For instance, after generating the mass production test code for the target ATE, the generated code can be previewed in the target ATE mass production test code preview area.
[0084] For example, the repair enable control is used for chips with repair resources. When a stage requiring repair is encountered during testing, the test program executes a repair algorithm in response to a touch operation on the repair enable control, enabling the chip's repair function. It can be understood that when a chip is found to have small-scale defects during production testing, these redundant units can be used to replace the defective units through methods such as laser fusing, electronic fusing, or software configuration, thereby "repairing" the chip and improving yield.
[0085] For example, the Generate Test Project control is used to generate a test project after confirming that the target ATE mass production test code is error-free. For instance, in response to a touch operation on the Generate Test Project control, a test project is generated based on the target ATE mass production test code. It can be understood that the test project is a set of files containing the main test program (such as the target ATE mass production test code), control files, and other project-related files.
[0086] For example, the Send Project control is used to send a test project to a server or a test machine. For instance, a test project is sent to a server or test machine in response to a touch operation on the Send Project control.
[0087] Figure 6 According to some embodiments of this application, a structural block diagram of a server 100 applicable to the chip mass production testing method provided in this application is shown. Specifically, as Figure 6 As shown, server 100 includes one or more processors 104, system control logic 108 connected to at least one of the processors 104, system memory 112 connected to system control logic 108, non-volatile memory (NVM) 116 connected to system control logic 108, and network interface 120 connected to system control logic 108.
[0088] In some embodiments, processor 104 may include one or more single-core or multi-core processors. In some embodiments, processor 104 may include one or any combination of general-purpose processors and special-purpose processors (e.g., graphics processors, application processors, baseband processors, etc.). For example, the processor may be any one of a graphics processor (GPU), a neural network processor (NPU), a tensor processor (TPU), a central processing unit (CPU), a digital signal processor (DSP), or a field-programmable gate array (FPGA), and this application is not limited thereto. For example, in embodiments where server 100 employs an Evolved Node B (ENB) or a Radio Access Network (RAN) controller, processor 104 may be configured to perform various corresponding embodiments.
[0089] In some embodiments, system control logic 108 may include any suitable interface controller to provide any suitable interface to at least one of the processors 104 and / or any suitable device or component communicating with system control logic 108.
[0090] In some embodiments, system control logic 108 may include one or more memory controllers to provide an interface to system memory 112. System memory 112 may be used to load and store data and / or instructions. In some embodiments, system memory 112 of server 100 may include any suitable volatile memory, such as suitable dynamic random access memory (DRAM). In some embodiments, system memory 112 may be used to load or store instructions for implementing chip mass production testing methods, or system memory 112 may be used to load or store instructions for implementing chip mass production testing methods.
[0091] NVM / memory 116 may include one or more tangible, non-transitory computer-readable media for storing data and / or instructions. In some embodiments, NVM / memory 116 may include any suitable non-volatile memory such as flash memory and / or any suitable non-volatile storage device, such as at least one of a hard disk drive (HDD), a compact disc (CD) drive, and a digital versatile disc (DVD) drive. NVM / memory 116 may also be used to store parameters of the ROPE module.
[0092] NVM / Storage 116 may include a portion of the storage resources on the device on which Server 100 is installed, or it may be accessible by the device, but is not necessarily part of the device. For example, NVM / Storage 116 may be accessed over a network via Network Interface 120.
[0093] Specifically, system memory 112 and NVM / memory 116 may each include a temporary copy and a permanent copy of instruction 124. Instruction 124 may include, when executed by at least one of processors 104, causing server 100 to perform actions such as... Figure 1 The instructions for the method shown. In some embodiments, instructions 124, hardware, firmware and / or their software components may additionally / alternatively be located in system control logic 108, network interface 120 and / or processor 104.
[0094] Network interface 120 may include a transceiver for providing a radio interface to server 100, thereby enabling communication with any other suitable device (such as a front-end module, antenna, etc.) via one or more networks. In some embodiments, network interface 120 may be integrated into other components of server 100. For example, network interface 120 may be integrated into at least one of processor 104, system memory 112, NVM / memory 116, and firmware device (not shown) with instructions that, when at least one of processor 104 executes instructions, server 100 implements, as Figure 1 The method shown.
[0095] The network interface 120 may further include any suitable hardware and / or firmware to provide a multiple-input multiple-output radio interface. For example, the network interface 120 may be a network adapter, a wireless network adapter, a telephone modem, and / or a wireless modem.
[0096] In some embodiments, at least one of the processors 104 may be packaged together with the logic of one or more controllers for system control logic 108 to form a system-in-package (SIP). In some embodiments, at least one of the processors 104 may be integrated on the same die with the logic of one or more controllers for system control logic 108 to form a system-on-a-chip (SOC).
[0097] Server 100 may further include: input / output (I / O) device 132. I / O device 132 may include a user interface that enables a user to interact with server 100; the design of the peripheral component interface enables peripheral components to also interact with server 100.
[0098] Accordingly, embodiments of this application provide an electronic device, including: a memory for storing instructions executed by one or more processors of the electronic device, and a processor for executing instructions of the above-described chip mass production testing method.
[0099] Accordingly, this application provides a storage medium storing instructions, which, when executed on an electronic device, cause the electronic device to perform the aforementioned chip mass production testing method.
[0100] Accordingly, this application provides a computer program product, which includes instructions that, when executed, enable the aforementioned chip mass production testing method to be implemented.
[0101] Accordingly, this application provides a chip, which includes a memory for storing instructions executed by one or more processors of an electronic device, and one or more processors for executing the chip mass production testing method described above.
[0102] This specification provides the methods or processes shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one of many execution orders and does not represent the only execution order. In actual execution, the methods or processes shown in the embodiments or drawings can be executed in sequence or in parallel (e.g., in a parallel controller or multi-threaded processing environment).
[0103] The embodiments disclosed in this application can be implemented in hardware, software, firmware, or a combination of these implementation methods. Embodiments of this application can be implemented as computer programs or program code executable on a programmable system, the programmable system including at least one processor, a storage system (including volatile and non-volatile memory and / or storage elements), at least one input device, and at least one output device.
[0104] Program code can be applied to input instructions to execute the functions described in this application and generate output information. The output information can be applied to one or more output devices in a known manner. For the purposes of this application, the processing system includes any system having a processor such as, for example, a digital signal processor (DSP), a microcontroller, an application-specific integrated circuit (ASIC), or a microprocessor.
[0105] The program code can be implemented using a high-level procedural language or an object-oriented programming language to communicate with the processing system. Assembly language or machine language can also be used when needed. In fact, the mechanisms described in this application are not limited to any particular programming language. In either case, the language can be a compiled language or an interpreted language.
[0106] In some cases, the disclosed embodiments may be implemented in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried or stored thereon on one or more temporary or non-temporary machine-readable (e.g., computer-readable) storage media, which may be read and executed by one or more processors. For example, the instructions may be distributed via a network or through other computer-readable media. Therefore, machine-readable media may include any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form, including but not limited to floppy disks, optical disks, CD-ROMs, magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic cards or optical cards, flash memory, or tangible machine-readable storage for transmitting information (e.g., carrier waves, infrared signals, digital signals, etc.) using the Internet in the form of electrical, optical, acoustic, or other propagation signals. Therefore, machine-readable media include any type of machine-readable medium suitable for storing or transmitting electronic instructions or information in a machine-readable (e.g., computer-readable) form.
[0107] As used herein, the term "module" may refer to, as part of, or include: a memory (shared, dedicated, or grouped) for running one or more software or firmware programs, an application-specific integrated circuit (ASIC), electronic circuitry and / or a processor (shared, dedicated, or grouped), combinational logic circuitry, and / or other suitable components that provide the said functionality.
[0108] In the accompanying drawings, some structural or methodological features may be shown in a specific arrangement and / or order. However, it should be understood that such a specific arrangement and / or order is not necessary. Rather, in some embodiments, these features may be illustrated in a manner and / or order different from that shown in the illustrative drawings. Furthermore, the inclusion of structural or methodological features in a particular drawing does not mean that all embodiments need to include such features; in some embodiments, these features may be omitted, or they may be combined with other features.
[0109] The embodiments of this application have been described in detail above with reference to the accompanying drawings. However, the use of the technical solutions of this application is not limited to the various applications mentioned in the embodiments of this patent. Various structures and modifications can be easily implemented with reference to the technical solutions of this application to achieve the various beneficial effects mentioned herein. Within the scope of knowledge possessed by those skilled in the art, all changes made without departing from the spirit of this application should be considered within the scope of this patent application.
Claims
1. A chip mass production testing method, characterized in that, The method includes: Obtain the configuration file, which includes test scheme data for each of the multiple chips and information about each chip; Based on the information of each chip, a corresponding chip model is generated; A target test model for each chip is generated based on the chip model of each chip. Obtain the test program template corresponding to each chip, wherein the test program template corresponding to each chip corresponds to the target model of the test machine corresponding to each chip; Update the parameters in the test program template corresponding to each chip, obtain the target test program for each chip, and import it into the test machine to test each chip.
2. The method according to claim 1, characterized in that, The target test model for each chip includes the target connection relationship between the pins of each chip and the power supply channel of the test machine.
3. The method according to claim 1, characterized in that, Updating the parameters in the test program template corresponding to each chip includes: Based on the test scheme data, chip model, and target test model of each chip, the parameters in the test program template corresponding to each chip are updated.
4. The method according to any one of claims 1-3, characterized in that, The information for each chip includes the target model of the test machine corresponding to each chip. The step of generating a corresponding chip model based on the information of each chip includes: Based on the target model, an initial test model matching the target model is generated. The initial test model includes the initial connection relationship between the pins of each chip and the power channel of the test machine. The initial connection relationship between the pins of each chip in the initial test model and the power channel of the test machine is updated to the target connection relationship between the pins of each chip and the power channel of the test machine, thus obtaining the chip model corresponding to each chip.
5. The method according to claim 4, characterized in that, The configuration file also includes a save path. The step of obtaining the test program template corresponding to each chip includes: Determine the template folder corresponding to the target model; Store the project files in the template folder to the save path, wherein the project files include the test program template.
6. The method according to claim 4 or 5, characterized in that, The information for each chip includes the chip type, and the test plan data for each chip includes test parameters. The step of updating the parameters in the test program template corresponding to each chip based on the test plan data, chip model, and target test model of each chip includes: Based on the test scheme data and chip model of each chip, test code blocks are added to the test program template corresponding to each chip. The test code blocks are matched with the chip type and the target model, and the number of test code blocks is consistent with the number of test parameters. Based on the test scheme data and the target test model for each chip, the parameters in the test code block are updated.
7. The method according to claim 6, characterized in that, The test plan data also includes test parameters, test conditions, upper limit of test values, and lower limit of test values. The step of updating the parameters in the test code block based on the test scheme data and the target test model for each chip includes: Based on the target test model for each chip, the pins and power channels in the test code block are replaced with the pins and power channels of each chip in the target test model, respectively. Based on the test scheme data, the test parameters, test conditions, upper limit of test value, and lower limit of test value in the ATE test program template corresponding to each chip are replaced with the test parameters, test conditions, upper limit of test value, and lower limit of test value in the test scheme data of each chip.
8. The method according to claim 1, characterized in that, Also includes: The target test program for each chip is uploaded to the server. The target test program for each chip is used to download from the server to at least two test machines of the target model. The at least two test machines are used to test each chip based on the target test program for each chip.
9. The method according to claim 1, characterized in that, The plurality of chips includes a first chip, and the method further includes: Obtain historical test report data for the second chip, which is a historical version of the first chip; Based on the historical test report data of the second chip, test plan data for the first chip is generated. The test plan data for the first chip includes a first test parameter, which is an abnormal parameter in the historical test report data of the second chip.
10. The method according to claim 1, characterized in that, After generating the corresponding chip model, the method further includes: Display a preview image of the chip model corresponding to each chip; If the preview image of the chip model of the third chip does not match the third chip, the chip information of the third chip is updated, and the chip model corresponding to the third chip is regenerated based on the updated chip information of the third chip.
11. The method according to any one of claims 1-10, characterized in that, The test plan data includes at least one of the following: Test items, test parameters, test conditions, upper limit of test value, lower limit of test value, category number, and save path.
12. The method according to any one of claims 1-11, characterized in that, The information for each chip includes at least one of the following: Chip type, chip package type, number of chip pins, name and order of chip pins, target model.
13. An electronic device, characterized in that, include: Memory, used to store one or more programs; A processor for executing the one or more programs to cause the electronic device to perform the method of any one of claims 1-12.
14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which, when executed on an electronic device, cause the electronic device to perform the method described in any one of 1 to 12.