Hardware control platform and method for generating high-precision standard signal

Abstract

The invention relates to the technical field of oscilloscope calibration, in particular to a hardware control platform and method for generating high-precision standard signals. The invention relates to a localization hardware control platform for an oscilloscope calibrator. The localization hardware control platform comprises a control module, a clock module, a communication peripheral interface design, a signal generation module, a digital-to-analog conversion self-calibration module and a power supply module. Through periodic self-calibration, the time-varying errors can be measured and compensated in real time, so that the system can maintain factory precision for a long time, and the dependence on external high-end calibration equipment and the maintenance cost are reduced. The system can eliminate signal drift caused by environment temperature change through self-calibration, and the reliability and the consistency of equipment in different working environments are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of oscilloscope calibration technology, and in particular to a hardware control platform and method for generating high-precision standard signals. Background Technology

[0002] As a fundamental test instrument in the field of electronic measurement, the oscilloscope is widely used in electronic measurement, communications, and computer industries. With the increasing complexity and diversity of testing environments for modern electronic equipment, the demand for oscilloscopes is constantly growing, and the importance of their calibration is becoming increasingly prominent. An oscilloscope calibrator, as a test instrument capable of generating high-precision standard signals to calibrate oscilloscopes, plays a crucial role in ensuring the accuracy and reliability of oscilloscopes.

[0003] Currently, the development of oscilloscope calibrators abroad is very mature, while the development of oscilloscope calibrators in China is still in its initial stage. The technical level of domestic oscilloscope calibrators lags behind international advanced levels, which to some extent limits the development and application of domestic oscilloscopes. Therefore, developing and researching the design of a domestic platform for oscilloscope calibrators is of great significance for improving the technical level of domestic oscilloscope calibrators and promoting the self-reliance of oscilloscope calibration technology. Summary of the Invention

[0004] The purpose of this invention is to optimize the performance of oscilloscope calibrators, improve their accuracy and stability, achieve independent and controllable design of oscilloscope calibrators, promote the widespread application of domestically produced oscilloscope calibrators, and enhance the market competitiveness of domestic oscilloscope calibration through the design and research of oscilloscope calibrator control platform.

[0005] To achieve the above-mentioned objectives, this invention provides a domestically produced hardware control platform for oscilloscope calibrators, comprising: a control module, a clock module, a communication peripheral interface design, a signal generation module, a digital-to-analog conversion self-calibration module, and a power supply module. Wherein: The control module primarily employs a dual-MCU + FPGA architecture to achieve task separation and efficient processing. MCU1 serves as the communication management unit, responsible for command interaction with the host computer; MCU2 acts as the system control and scheduling unit, responsible for parsing commands and managing the FPGA; the FPGA, as the high-speed signal processing and execution unit, is responsible for generating precise waveform control timing. MCU1 and MCU2 communicate via an asynchronous serial port, while MCU2 and the FPGA transmit control commands via a high-speed SPI synchronous serial interface. This architecture modularizes complex control tasks according to function, effectively improving the system's real-time performance, reliability, and scalability.

[0006] The clock module is responsible for generating a stable, low-jitter clock required by the FPGA to meet the stable timing requirements of the FPGA during operation. The FPGA configures the clock chip online via the SPI protocol, enabling it to output clock signals of different frequencies, thereby flexibly adapting to the timing requirements of various calibration scenarios and ensuring accurate synchronization between signal generation and sampling.

[0007] The communication peripheral interface design is mainly responsible for the communication requirements with peripheral devices. Among them, the GPIB interface is responsible for the communication between MCU1 and the host computer, the serial port is responsible for the MCU code programming, and the JTAG interface is responsible for the FPGA code programming.

[0008] The signal generation module is mainly implemented by an FPGA controlling a DAC to generate the required high-precision calibration signal. The DAC uses the 3PD9708 chip from Silergy Microelectronics Technology Co., Ltd. In this invention, the FPGA and DAC are directly connected in parallel, eliminating the need for intermediate logic conversion chips. This design simplifies the hardware structure, reduces signal transmission delay, and improves system integration and reliability, thereby ensuring the real-time performance and accuracy of calibration signal data acquisition.

[0009] This invention integrates a digital-to-analog self-calibration module. This module achieves real-time self-monitoring and correction of the output signal accuracy by constructing a closed calibration loop between the digital-to-analog converter and the analog-to-digital converter. The FPGA calculates error correction parameters by comparing the data from the ADC sampling feedback with the expected ideal data, and applies them in real time to subsequent signal generation, thereby ensuring the long-term high accuracy and stability of the output calibration signal.

[0010] The power module described in this invention adopts a hierarchical power architecture. The externally input 12V DC power is first converted to 5V by a low-dropout linear regulator; this 5V power then serves as the input to a switching regulator, generating various low-voltage operating power supplies required by the system to power the MCU, FPGA, and other chips. This architecture balances power efficiency and noise performance, ensuring the stability and reliability of the entire system.

[0011] The host computer provides instructions to MCU1, which then sends the instructions to MCU2 via serial port. MCU1 sends the instructions to FPGA via SPI protocol. The instructions include the type, phase, and frequency of the generated waveform. The FPGA and the FLASH memory that stores the waveform data send the binary waveform data to the digital-to-analog converter (DAC). With the cooperation of the DAC, the analog-to-digital converter (ADC), and the FPGA, the oscilloscope calibrator performs self-calibration. After the above steps are completed, the calibrated waveform data is sent to the ADC. After filtering and squaring by the peripheral circuit, a high-precision, low-noise standard calibration signal is generated and output. Attached Figure Description

[0012] Figure 1 This is a system block diagram of the hardware control platform for an oscilloscope calibrator; Figure 2 It is the hardware control platform architecture and communication method of the oscilloscope calibrator; Figure 3 It is a power module schematic design; Figure 4 It is a schematic design of a phase-locked loop chip; Figure 5 It is a schematic design of an external flash memory for an FPGA. Detailed Implementation

[0013] The following is in conjunction with the appendix Figures 1-5 Specific embodiments of the present invention will be described to enable those skilled in the art to better understand the invention.

[0014] like Figure 1 As shown, the hardware control platform of the oscilloscope calibrator mainly includes the following core modules: control module, signal generation module, digital-analog self-calibration module, clock module, and power supply module.

[0015] The core workflow is as follows: the host computer sends calibration commands to the control module via a communication interface. After the control module parses the commands, the control signal generation module generates the corresponding initial analog signal. The digital-analog self-calibration module samples and calibrates the initial signal to improve accuracy. Finally, the conditioned high-precision standard calibration signal is output to the oscilloscope. The timing of the entire system is uniformly controlled by a high-precision clock module, and a clean and stable power supply is provided by the power supply module.

[0016] Detailed implementation of the control module 1. Hardware configuration and connection relationships: The core of the control module consists of two microcontrollers (MCU1, MCU2) and a field-programmable gate array (FPGA).

[0017] The preferred models for MCU1 and MCU2 are STC8H series chips from Hongjing Technology.

[0018] The preferred FPGA model is the PANGO series PGL25G chip from Ziguang Tongchuang.

[0019] like Figure 5 As shown, the FPGA is externally connected to a domestically produced GD25Q128 series FLASH chip, which is used to store the FPGA's configuration file and preset waveform data.

[0020] 2. Communication Interface and Data Flow: like Figure 2As shown, the communication between MCU1 and the host computer is as follows: MCU1 connects to the host computer software through the GPIB transceiver chip and receives comprehensive calibration instructions including waveform type, frequency, amplitude, and phase.

[0021] Communication between MCU1 and MCU2: After receiving instructions from the host computer, MCU1 sends the instruction data to the UART_RX pin of MCU2 via its UART_TX pin. The baud rate of this asynchronous serial communication interface can be configured to 115200bps or higher to ensure real-time instruction transmission.

[0022] Communication between MCU2 and FPGA: After parsing and verifying the instructions from MCU1, MCU2 communicates with the FPGA through its SPI master interface. Specifically, the MOSI pin of MCU2 is connected to the FPGA's SPI slave data input pin, used to write waveform parameters and control words to the FPGA. The SPI clock pin of MCU2 provides a synchronization clock for the entire communication process.

[0023] Detailed implementation of the clock module like Figure 4 As shown, the core of the clock module is the phase-locked loop chip U9 (model HMC830). The high-frequency, high-precision, low-phase-noise clock signal generated by its RF output terminal is directly connected to the global clock input pin of the FPGA, serving as the main clock reference for the FPGA's operation.

[0024] The FPGA configures the HMC830 chip via the SPI interface. Specifically, the FPGA's three general-purpose I / O pins are configured as the MOSI (data output), SCK (clock), and SEN (chip select) signals for the SPI master device, and directly connected to the corresponding SDATA, CLK, and SEN pins of the HMC830 chip.

[0025] During power-on initialization, the FPGA's internal logic first writes a set of predefined configuration parameters to the HMC830 chip's internal control register via the SPI interface. These parameters determine the phase-locked loop's feedback division ratio, reference frequency, and output frequency, thereby locking the HMC830 to the target frequency. By modifying these configuration parameters, the FPGA can dynamically control the HMC830 to output different clock frequencies to adapt to different operating modes.

[0026] In terms of PCB layout, the VCO inductor and loop filter components of the HMC830 should be placed strictly in accordance with the values ​​and layout requirements recommended in the chip datasheet, and as close as possible to the chip pins to optimize phase noise and lock-in performance.

[0027] Detailed implementation of the signal generation module Referring to the diagram, the specific connection method between the FPGA and the ADC is as follows: Each pin of the ADC's 8-bit wide parallel data output bus is directly connected to one of the 8 general-purpose pins of the FPGA.

[0028] The ADC's data clock output pin is directly connected to a dedicated clock input pin of the FPGA.

[0029] In PCB layout, the above set of signal lines should be treated as a bus with equal length to ensure timing consistency.

[0030] Detailed Implementation of the Digital Analog Self-calibration Module The analog-to-digital self-calibration module mainly consists of a domestically produced ADC and DAC, along with their peripheral circuitry. It is primarily responsible for calibrating the signals generated by the oscilloscope calibrator itself, ensuring high accuracy and stability. The DAC chip is the 3PD9708 from Silergy Microelectronics Technology Co., Ltd., and the ADC is the 3PA9280 from the same company. The analog signal transmission pins between the DAC and ADC are connected via pluggable connector leads (e.g., DuPont wires). This design makes the analog-to-digital self-calibration module a physically configurable independent unit. When system self-calibration is required, the ADC and DAC are connected via leads to form a calibration loop. After calibration, or when the ADC needs to be used for other measurement tasks, the leads can be directly disconnected without altering the PCB layout. This design greatly improves the flexibility and maintainability of the hardware platform, facilitating debugging, repair, and functional reconfiguration.

[0031] Detailed implementation of the power module like Figure 3As shown, the power module is mainly responsible for supplying power to the entire system, firstly directly receiving an external 12V DC power supply. The first-stage conversion chip is implemented by the RY9125. The RY9125 is configured as a low-dropout linear regulator, with its input VIN connected to the 12V power supply and its output VOUT generating a stable 5V power supply. To ensure stability, capacitors C41 (22uF) and C42 (0.1uF) are connected in parallel at its input, and capacitors C50 (22uF) and C51 (220uF) are connected in parallel at its output. The second-stage conversion chip is implemented by the EA3059. The EA3059 is a switching regulator, with its input VIN connected to the 5V power supply obtained from the first stage conversion. By configuring the resistance ratio of its external feedback resistor, its output VOUT is controlled to 3.3V. The converted voltage can power the MCU and FPGA. The 1.1V voltage required by the FPGA core is also obtained by the EA3059 through 5V conversion and directly connected to the FPGA's VCCINT pin. In PCB layout, the inductors, input and output capacitors of the EA3059 switching regulator should be placed as close as possible to the chip pins to form a compact current loop and reduce electromagnetic radiation.

[0032] System Workflow Overview In summary, the typical workflow control of the hardware control platform of this invention is as follows: Power-on and initialization: The power module supplies power to each chip; the FPGA loads its configuration from the FLASH; the main control MCU initializes the peripherals; the FPGA configures the clock chip HMC830 to output the required frequency via SPI.

[0033] Command reception and parsing: The host computer sends a calibration command, which is parsed by MCU1 and MCU2, and the waveform parameters are sent to the FPGA via SPI.

[0034] Self-calibration process: If self-calibration is required, the FPGA control signal generation and the self-calibration module form a closed loop, execute the calibration algorithm, and store the error parameters.

[0035] Signal generation and output: The FPGA uses calibrated parameters to control the DAC to generate high-precision analog signals, which are then output after conditioning circuitry.

[0036] Real-time control: Throughout the process, the FPGA and MCU2 work together to adjust the parameters of the output signal in real time as needed.

[0037] The advantages of this invention using a dual MCU + FPGA control architecture are as follows: Task separation improves real-time performance and reliability: The time-consuming and protocol-complex machine communication task is separated from the high-precision waveform generation task, which is handled by MCU1 and FPGA respectively. This avoids response delay or timing jitter caused by resource contention of a single processor, and significantly improves the real-time control capability and overall stability of the system.

[0038] By leveraging their respective strengths, the system performance is optimized: MCUs excel at complex logic scheduling and protocol processing, while FPGAs excel at high-speed, parallel digital logic and precise timing control. This architecture allows the two to complement each other's advantages, with the MCU handling 'decision-making' and the FPGA responsible for 'execution,' ensuring high precision and flexibility in waveform generation.

[0039] Enhanced scalability: The architecture is modular, so if the communication interface needs to be upgraded in the future (such as adding Gigabit Ethernet), only the program of MCU1 needs to be updated; if new waveform algorithms or control logic need to be added, the logic of FPGA needs to be modified. Upgrades of each unit do not interfere with each other, which greatly improves the maintainability and scalability of the platform.

[0040] Achieving complete domestic production: The core control chips (STC8H, PGL25G) are all domestically produced, breaking the foreign technology monopoly and ensuring supply chain security.

[0041] The beneficial effects of introducing a digital-analog self-calibration module in this invention are as follows: Compensating for hardware defects and achieving long-term high precision: The output accuracy of traditional calibrators decreases with the aging and temperature drift of components such as DACs. This invention, through periodic self-calibration, can measure and compensate for these time-varying errors in real time, enabling the system to maintain factory accuracy over a long period, reducing dependence on external high-end calibration equipment and maintenance costs.

[0042] Improved temperature stability: The system can eliminate signal drift caused by changes in ambient temperature through self-calibration, which significantly improves the reliability and consistency of the equipment under different working environments.

[0043] The leap from "fixed precision" to "adaptive precision": This design transforms the calibrator from a device that outputs fixed precision signals into an intelligent system capable of self-sensing and self-correction. This is a significant innovation in the intelligent aspect of the hardware platform.

[0044] Enhanced reliability: This self-test function can be used as a self-test process during system startup to quickly determine whether the signal chain is working properly, thereby improving the maintainability and reliability of the product.

Claims

1. A hardware control platform for generating high-precision standard signals, characterized in that, include: Control module, clock module, communication peripheral interface design, signal generation module, digital-to-analog conversion self-calibration module, power supply module; among which: The control module includes a dual MCU + FPGA architecture, where MCU1 is responsible for communicating with the host computer, MCU2 is responsible for communicating with MCU1, and FPGA is responsible for receiving control signals generated by MCU2 to drive other external chips to work. The clock module is responsible for generating the high-frequency, high-precision clock required by the FPGA to meet the stable timing requirements of the FPGA during operation. The communication peripheral interface design is responsible for the communication requirements with peripheral devices. Among them, the GPIB interface is responsible for the communication between MCU1 and the host computer, the serial port is responsible for the MCU code programming, and the JTAG interface is responsible for the FPGA code programming. The signal generation module is implemented by FPGA-controlled DAC to generate the required high-precision calibration signal; The analog-to-digital self-calibration module includes the ADC and DAC and their peripheral circuits, which are responsible for calibrating the signals generated by the oscilloscope calibrator itself to ensure the high accuracy and stability of the generated signals. The power module is responsible for supplying power to the entire system. It provides power of different sizes to the MCU and FPGA through a DC chip to ensure their normal operation.

2. The hardware control platform for generating high-precision standard signals according to claim 1, characterized in that, MCU1 and MCU2 communicate via an asynchronous serial port, while MCU2 and FPGA transmit control commands via a high-speed SPI synchronous serial interface.

3. The hardware control platform for generating high-precision standard signals according to claim 1, characterized in that, The FPGA and DAC are connected in direct parallel.

4. The hardware control platform for generating high-precision standard signals according to claim 1, characterized in that, The digital-to-analog self-calibration module achieves real-time self-monitoring and correction of the output signal accuracy by constructing a closed calibration loop between the digital-to-analog converter and the analog-to-digital converter.

5. The hardware control platform for generating high-precision standard signals according to claim 1, characterized in that, The FPGA calculates error correction parameters by comparing the data sampled and fed back by the ADC with the expected ideal data, and applies them in real time to the subsequent signal generation, thereby ensuring the long-term high accuracy and stability of the output calibration signal.

6. The hardware control platform for generating high-precision standard signals according to claim 1, characterized in that, The power module adopts a hierarchical power architecture. The externally input 12V DC power is first converted into 5V power by a low-dropout linear regulator. This 5V power is then used as the input of a switching regulator to generate various low-voltage operating power supplies required by the system.

7. The hardware control platform for generating high-precision standard signals according to claim 1, characterized in that, MCU1 connects to the host computer software via a GPIB transceiver chip to receive comprehensive calibration commands, including waveform type, frequency, amplitude, and phase.

8. A hardware control method for generating high-precision standard signals, characterized in that, Includes the following steps: In the hardware control platform for generating high-precision standard signals as described in claim 1, the host computer provides instructions to MCU1, MCU1 sends the instructions to MCU2 via a serial port, and MCU1 sends the instructions to FPGA via the SPI protocol. The instructions include the type, phase, and frequency of the generated waveform. The FPGA and the FLASH memory that stores the waveform data send the binary waveform data to the digital-to-analog converter. With the cooperation of the digital-to-analog converter, the analog-to-digital converter, and the FPGA, the oscilloscope calibrator performs self-calibration. The calibrated waveform data is sent to the digital-to-analog converter, and after filtering and squaring by the peripheral circuit, a high-precision, low-noise standard calibration signal is generated and output.

9. The hardware control platform for generating high-precision standard signals according to claim 8, characterized in that, After receiving the instruction from the host computer, MCU1 sends the instruction data to the UART_RX pin of MCU2 through its UART_TX pin.

10. The hardware control platform for generating high-precision standard signals according to claim 8, characterized in that, The FPGA configures the HMC830 chip through the SPI interface. The three general-purpose I / O pins of the FPGA are configured as the data output, clock, and chip select signals of the SPI master device, respectively, and directly connected to the corresponding SDATA, CLK, and chip select pins of the HMC830 chip.

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