Field programmable gate array (FPGA)-based post-pulse-compression environment self-adaptive dynamic bit cutting method

Abstract

The invention relates to the technical field of electronic countermeasures, in particular to an FPGA (Field Programmable Gate Array)-based post-pulse-compression environment self-adaptive dynamic bit cutting method. The method comprises the steps of data storage, symbol detection, exception processing, position calculation, adaptive bit interception and the like. When a radar system is powered on or calibration is executed, the surrounding environment is actively scanned, pulse compression output data in each beam direction are collected, and the maximum echo amplitude in each beam direction is extracted; and based on the maximum value, dynamically calculating an optimal truncation start bit of the corresponding beam. Real-time calculation or feedback adjustment is not needed, the whole process only relates to simple bit operation, the time sequence allowance is sufficient, and resource consumption is extremely low.

Description

Technical Field

[0001] This invention relates to the field of electronic countermeasures technology, and in particular to an FPGA-based post-pulse compression environment adaptive dynamic truncation method. Background Technology

[0002] Modern radar systems commonly employ pulse compression technology to balance long-range detection capabilities and high range resolution with limited peak transmit power, effectively improving signal-to-noise ratio (SNR) and ranging accuracy. In engineering implementation, leveraging the advantages of FPGAs such as parallel processing, high real-time performance, low power consumption, and reconfigurability, pulse compression algorithms are typically deployed on FPGAs. However, implementing this algorithm on FPGAs can lead to severe bit-width expansion problems. For example, 16-bit fixed-point data can expand to 40 bits or even larger after undergoing a 4096-point FFT / iFFT. Excessively high output bit width significantly increases the complexity of subsequent data transmission and the resource consumption of subsequent processing modules (such as MTD and CFAR).

[0003] Current engineering commonly employs a fixed truncation strategy to compress the output data bit width (e.g., retaining only the high 16 bits). This strategy sets the truncation position during design based on the "worst-case" scenario (such as strong clutter or strong reflectors at close range) to prevent signal saturation. While this static method perfectly avoids signal saturation overflow, it still has the following shortcomings in practical engineering:

[0004] (1) Low dynamic range utilization: The fixed high-bit truncation strategy still forces the retention of high bits in non-extreme scenarios, resulting in a large amount of high-bit redundancy and the discarding of effective low-bit information, which wastes bit width resources and significantly reduces the system's dynamic range utilization efficiency. (2) Weak targets are easy to miss: When the target echo amplitude is much lower than that of strong clutter, its signal energy is often located in the low bit region of the data; the fixed truncation will directly cut off this part, causing weak targets to be set to zero or suffer severe quantization distortion, thus causing missed detection. (3) Poor environmental adaptability: The system adopts a fixed truncation strategy, which cannot adaptively adjust the truncation position according to changes in the deployment environment (such as urban strong clutter areas, and weak echo areas in the wild), resulting in severe dynamic range loss in non-design scenarios. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides an FPGA-based post-pulse compression environment-adaptive dynamic truncation method. When the radar system powers on or performs calibration, this invention actively scans the surrounding environment, collects pulse compression output data for each beam direction, and extracts the maximum echo amplitude for each beam direction. Based on this maximum value, the optimal truncation start position for the corresponding beam is dynamically calculated. During subsequent normal operation, all pulse compression output data is truncated at the high end according to the start position determined in this calibration phase. This method belongs to the dynamic range optimization method and can be directly applied to ground surveillance radar systems.

[0006] The technical solution of this invention is: an FPGA-based pulse compression post-environment adaptive dynamic truncation method, characterized by the following steps:

[0007] Step 1: Data storage. When the system powers on and initializes or receives an external calibration command, the command receiving and execution unit triggers an environmental scan calibration process.

[0008] Step 2: Sign Detection. For each wave bit data stored in Step 1, perform consecutive sign bit detection on both the real and imaginary parts. For each signed integer, count the number of consecutive identical sign bits starting from the most significant bit and moving towards the least significant bit. Take the minimum value among all real parts and the minimum value among all imaginary parts, and select the smaller of these two values ​​as the "minimum number of sign bits" for that wave bit, denoted as . , Each value corresponds to a dynamic range characteristic of a wave position, with i ranging from 1 to B. Preset wave number;

[0009] Step 3: Exception handling, for each Apply an upper limit constraint; if a certain If, then it is forced to be restricted to Z; if If the original data remains unchanged, Z is the maximum safe right shift number;

[0010] Step 4: Position calculation, independently calculate the truncation interval for each wave position; the truncation strategy adopts high-bit alignment and downward truncation: based on the smallest detected symbol bit length. As a right shift offset, from the original Extracting the consecutive data immediately following the symbol redundancy region from the bit data. Valid data bits This refers to the data bit width after bit width compression. This represents the original data bit width.

[0011] Step 5: Adaptive truncation. After the radar system completes calibration, it enters normal working mode.

[0012] According to the FPGA-based post-pulse compression environment adaptive dynamic truncation method described above, the characteristic is that: in step 1, the antenna sequentially traverses all... Each preset wave position sends a pulse and receives an echo. After pulse compression processing, the complex data of the transmission and reception cycle is extracted.

[0013] According to the above-described FPGA-based pulse compression post-environment adaptive dynamic truncation method, the feature is that the preset number of pulses is 8.

[0014] According to the FPGA-based post-pulse compression environment adaptive dynamic truncation method described above, the method is characterized by: .

[0015] According to the FPGA-based post-pulse compression environment adaptive dynamic truncation method described above, the method is characterized by: .

[0016] According to the FPGA-based pulse compression post-environment adaptive dynamic truncation method described above, the characteristic is that: in step 5, the pulse compression module continuously outputs... For a complex data stream, the truncation control unit reads the corresponding truncation start position from a pre-stored register based on the current wave index and performs bit selection operations on the real and imaginary parts simultaneously, outputting complex data with a fixed bit width.

[0017] This invention maximizes the quantization accuracy and dynamic range utilization of the effective signal while maintaining a constant output bit width (e.g., 16 bits); it reduces truncation distortion, effectively improves the ability to retain weak targets, and enhances the system's environmental adaptability. This method requires only one calibration, eliminates the need for real-time calculations, has low computational complexity and low hardware overhead, and is easily implemented in real-time on resource-constrained FPGA platforms. It is particularly suitable for applications with high requirements for weak target detection performance and large clutter dynamic range, such as ground surveillance radar. The method of this invention belongs to the dynamic range optimization method and can be directly applied to ground surveillance radar systems. Attached Figure Description

[0018] Figure 1 It is a logic function module deployed in an FPGA.

[0019] Figure 2 This is the output simulation effect of a traditional fixed-cutoff position.

[0020] Figure 3 This is the simulation result after applying the method of this invention.

[0021] Definition: FPGA is an abbreviation for "Field-Programmable Gate Array", which is a type of programmable logic device. Specific Implementation

[0022] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings.

[0023] This section uses a ground surveillance radar system as an example for detailed explanation. The pulse compression (PPC) output data of this system is represented as complex numbers. The real part With the imaginary part All Bit signed fixed-point integer This is the original data bit width; each transmit / receive cycle contains The system supports a total of [number] data points per distance unit. Each pulse has an independent pulse position (the method of this invention can support any number of pulse positions), and subsequent processing links (such as FFT, constant false alarm rate detection, etc.) require the pulse compression output to be compressed to a fixed value. The bit width, N, B, and W can be changed according to actual needs.

[0024] like Figure 1 As shown, the logical function modules of this invention include instruction receiving, data storage, symbol detection, exception handling, position calculation, adaptive truncation, etc.

[0025] The present invention provides an FPGA-based post-pulse compression environment adaptive dynamic truncation method, comprising the following steps:

[0026] Step 1: Data Storage. Upon system power-on initialization or upon receiving an external calibration command, the command receiving and execution unit triggers an environmental scan calibration process, which includes steps 1 through 4. During this process, the antenna sequentially traverses all... Each preset wave position sends a pulse and receives an echo. After pulse compression processing, the entire pulse signal from the first complete transmit / receive cycle is extracted. Multiple complex data points are collected and stored. To reduce calibration overhead and reflect typical environmental characteristics, only the data from the first cycle is acquired (which typically already contains sufficient clutter information for that beam direction), and this data is stored in its raw form. Bit precision is stored in on-chip ROM or a dedicated calibration cache. This embodiment stores a total of [number missing] bits. There are a complex number of samples, each consisting of two... The system consists of signed integers (real and imaginary parts) and serves as the basis for subsequent calculations of truncation parameters.

[0027] Step 2: Symbol Detection. For each bit data stored in Step 1, perform continuous symbol detection on both the real and imaginary parts. Specifically, for each... For a signed integer, starting from the most significant bit (MSB) and moving towards the least significant bit, the number of consecutive identical sign bits is counted. This value reflects the maximum number of bits that can be safely shifted right within the current dynamic range without loss of useful information. For each bit... For each complex point, the number of consecutive sign bits in its 1024 real parts and 1024 imaginary parts is counted. The minimum value among all real parts and the minimum value among all imaginary parts are then selected, with the smaller value being taken as the "minimum number of sign bits" for that wave position. Thanks to the powerful parallel processing capabilities of the FPGA, the data from 8 waves can be processed in parallel and synchronously, ultimately outputting 8 integer values, denoted as follows: , Each value corresponds to a dynamic range feature of a wave position, with i ranging from 1 to B.

[0028] Step 3: Anomaly Handling. To ensure that the truncation operation is always performed within the valid data range and to avoid exceeding the truncation limit due to excessively large sign bit detection values ​​caused by environmental anomalies (such as no echo or noise dominance), each bit obtained in Step 2 needs to be processed. Apply an upper limit constraint. Theoretically, if truncation is taken... The actual maximum safe right shift bit Z is (bits). Therefore, if a certain If, then it is forced to be restricted to Z; if If the original data remains unchanged, then the clipping remains the same. This clipping mechanism ensures that regardless of environmental changes, the captured data remains consistent. The position is always completely in the original position. Within the valid representation range of bit data, prevent all-zero output or invalid data due to excessive right shift.

[0029] Step 4: Position Calculation. Based on the amplitude limiting result from Step 3. Calculate its independent value for each wavelength. Bit truncation interval. The truncation strategy uses high-bit alignment and downward truncation: based on the smallest detected sign bit length. As a right shift offset, from the original Extracting the consecutive data immediately following the symbol redundancy region from the bit data. Valid data. Specifically, the bit segment is truncated from the high-order index. To the low-order index In this embodiment, if Then the high-order index: Low-order index The calculated start and end bits (or start bit + width) for each truncation group are stored in two registers (reg type variables) for subsequent truncation logic calls. Eight waveforms correspond to eight independent configurations, achieving waveform-level adaptive control.

[0030] Step 5: Adaptive Truncation. After the radar system completes calibration, it enters normal operating mode. During this stage, the pulse compression module continuously outputs... The truncation control unit reads the corresponding truncation start position from a pre-stored register based on the current wave index and performs bit selection operations on the real and imaginary parts simultaneously, outputting a fixed 16-bit wide complex data. Since the truncation parameters are determined during calibration, no real-time calculation or feedback adjustment is required. The entire process involves only simple bit operations, with ample timing margin and extremely low resource consumption.

[0031] The advantage of this step is that the mechanism allows each wave position to be allocated bit width resources "tailor-made" according to the actual echo intensity of its environment: high bit widths are reserved in strong cluttered wave positions to prevent saturation, and the cutoff point is lowered in weak echoed wave positions to preserve faint target details. Ultimately, this leads to a unified... With the bit output interface, the overall dynamic range utilization and weak target detection capability of the system are significantly improved. Processing the same echo signal, as shown in the attached diagram... Figure 2 The image shows the pulse compression result of the traditional method with truncation output, as shown in the attached figure. Figure 3 The image shows the truncation result output after applying this method. Figure 3 This improves the ability to identify weak target signals.

[0032] The beneficial effects of this invention are:

[0033] (1) Dynamic range optimization and quantization accuracy improvement. The truncation start point is dynamically determined based on the maximum echo amplitude of the actual pulse compression output, so that the fixed 16-bit output bit width is always aligned with the effective signal range of the current scene, making the maximum use of the available dynamic range, significantly improving quantization accuracy, and avoiding the resource waste problem of high bit redundancy and low bit truncation coexisting.

[0034] (2) Strong environmental adaptability. This method can automatically adapt to the optimal cutoff strategy according to the radar deployment environment (such as urban areas with strong clutter or open fields with weak echoes), without the need for manual intervention or preset conservative parameters. It effectively balances strong clutter suppression and weak signal preservation, and adapts to complex and ever-changing combat scenarios.

[0035] (3) Enhanced detection performance of weak targets. In unsaturated scenarios, the echo of weak targets is often located in the low bit region of the data. This method retains more effective low bit information by lowering the truncation starting point, avoiding signal clipping or severe distortion caused by traditional fixed high bit truncation, and significantly improving the detectability and signal-to-noise ratio of weak targets.

[0036] (4) Fully compatible with existing system architecture. The output data still maintains a fixed bit width (e.g., 16 bits), without the need to modify the interface or data path of subsequent signal processing links (e.g., FFT, CFAR, tracking modules), and can be seamlessly integrated into existing radar systems to achieve "zero-intrusion" performance upgrades.

Claims

1. A post-pulse compression environment adaptive dynamic truncation method based on FPGA, characterized in that: Includes the following steps: Step 1: Data storage. When the system powers on and initializes or receives an external calibration command, the command receiving unit triggers an environmental scan calibration process. Step 2: Sign Detection. For each wave bit data stored in Step 1, perform consecutive sign bit detection on both the real and imaginary parts. For each signed integer, count the number of consecutive identical sign bits starting from the most significant bit and moving towards the least significant bit. Take the minimum value among all real parts and the minimum value among all imaginary parts, and select the smaller of these two values ​​as the "minimum number of sign bits" for that wave bit, denoted as . , Each value corresponds to a dynamic range characteristic of a wave position, with i ranging from 1 to B. Preset wave number; Step 3: Exception handling, for each Apply upper limit constraints; If a certain If, then it is forced to be restricted to Z; if If the original data remains unchanged, Z is the maximum safe right shift number; Step 4: Position calculation, independently calculate the truncation interval for each wave position; the truncation strategy adopts high-bit alignment and downward truncation: based on the smallest detected symbol bit length. As a right shift offset, from the original Extracting the consecutive data immediately following the symbol redundancy region from the bit data. Valid data, This refers to the data bit width after bit width compression. This represents the original data bit width. Step 5: Adaptive truncation. After the radar system completes calibration, it enters normal working mode.

2. The FPGA-based pulse compression post-environment adaptive dynamic truncation method according to claim 1, characterized in that: In step 1, the antennas are traversed sequentially. Each preset wave position sends a pulse and receives an echo. After pulse compression processing, the complex data of the transmission and reception cycle is extracted.

3. The FPGA-based pulse compression post-environment adaptive dynamic truncation method according to claim 1, characterized in that: The preset number of wavelets is 8.

4. The FPGA-based pulse compression post-environment adaptive dynamic truncation method according to claim 1, characterized in that: The formula for calculating the maximum safe right shift bits is: .

5. The FPGA-based pulse compression post-environment adaptive dynamic truncation method according to claim 1, characterized in that: 。 6. The FPGA-based post-pulse compression environment adaptive dynamic truncation method according to any one of claims 1 to 5, characterized in that: In step 5, the pulse compression module continuously outputs... For a complex data stream, the truncation control unit reads the corresponding truncation start position from a pre-stored register based on the current wave index and performs bit selection operations on the real and imaginary parts simultaneously, outputting complex data with a fixed bit width.

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