Pulse signal generating device

Abstract

The utility model relates to a pulse signal generating device. The circuit comprises an ECL to TTL circuit module which is used for receiving a first clock signal input from the outside and converting the first clock signal of an ECL level into a second clock signal of a TTL level; the first driving module is used for generating a second selection control signal; the input end of the FPGA module is connected with the output end of the ECL-TTL conversion circuit module and the output end of the first driving module, and the FPGA module generates a timing pulse signal based on a second selection control signal and a second clock signal; the second driving module is connected with the output end of the FPGA and is used for performing driving processing on the timing pulse signal; the single-ended to differential module is connected with the output end of the second driving module and is used for converting the timing pulse signal subjected to driving processing into a differential signal and outputting the differential signal; and the power supply conversion module is used for converting an external input power supply into a preset voltage and providing a required working power supply for the FPGA module. And the pulse signal of the radar system can be generated more efficiently and conveniently.

Description

TECHNICAL FIELD

[0001] The utility model relates to pulse signal generation technical field especially is to point to a kind of pulse signal generation device. BACKGROUND

[0002] Pulse signal has crucial effect in radar system, especially the selection of pulse repetition frequency (PRF, Pulse Repetition Frequency) signal is particularly remarkable to the influence of radar performance.PRF not only determines the ranging accuracy and speed measurement ability of radar, but also directly affects the effect of clutter suppression.Through adjusting PRF, the overall performance of radar system can be effectively optimized, so that the best detection effect is realized in different application scenarios.Therefore, PRF signal has been widely applied in modern radar system.In addition to PRF signal, radar system also needs to generate a variety of other types of pulse signals to support its normal operation.These signals include but are not limited to frame synchronization signal, blocking signal, pre-modulation signal, frequency hopping trigger signal, frequency modulation trigger signal and CAL modulation signal, etc.These different types of pulse signals work together to ensure that the radar system can stably and efficiently run in various working modes.

[0003] The existing pulse signal generation technology usually relies on high-frequency clock signal, and various pulse signals required are generated through complex circuit design and multi-stage frequency division.These traditional methods often need multiple independent signal generation modules, resulting in large system size, high power consumption and lack of flexibility.In addition, the demand for pulse width and frequency is diverse under different working modes, and the existing technology often needs to manually replace hardware components when adjusting these parameters, which is tedious and difficult to achieve dynamic adjustment. SUMMARY

[0004] Therefore, the utility model provides a kind of pulse signal generation device, solves the problem of low integration, insufficient flexibility, complex power supply and higher cost in prior art, so that the pulse signal generation of radar system is more efficient and convenient.

[0005] To solve the above technical problems, the utility model provides a kind of pulse signal generation device, comprising:

[0006] ECL to TTL circuit module is used to receive the first clock signal inputted from outside, and the first clock signal of ECL level is converted into the second clock signal of TTL level;

[0007] First drive module is used to receive the first selection control signal inputted from outside and generate the second selection control signal after driving processing, and the first selection control signal includes PRF reference signal pulse width selection, working mode selection and frame / inter-pulse selection signal;

[0008] An FPGA module, input ends of which are connected with output ends of the ECL-to-TTL circuit module and the first driving module respectively, the FPGA module generates a timing pulse signal based on the second selection control signal and the second clock signal;

[0009] A second driving module, connected with an output end of the FPGA module, for driving processing of the timing pulse signal;

[0010] A single-ended-to-differential module, connected with an output end of the second driving module, for converting the driving-processed timing pulse signal into a differential signal and then outputting;

[0011] A power conversion module for converting an externally input power into a predetermined voltage to provide a required working power supply for the FPGA module.

[0012] In an embodiment of the utility model, the first clock signal is a 100MHz clock signal.

[0013] In an embodiment of the utility model, the first driving module and the second driving module are both SN74ALVC164245DL chips.

[0014] In an embodiment of the utility model, the single-ended-to-differential module is a 26LS31 chip.

[0015] In an embodiment of the utility model, the FPGA module comprises a phase-locked loop circuit.

[0016] In an embodiment of the utility model, the ECL-to-TTL circuit module is an MC100ELT25 chip.

[0017] In an embodiment of the utility model, the power conversion module adopts a DC-DC converter.

[0018] The above technical solution of the utility model has the following advantages compared with the prior art:

[0019] The utility model discloses a pulse signal generating device can through the clock signal of specific frequency (such as 100MHz) drive produces the device required in various different working conditions under the pulse signal. The device passes through the integration design, realized generating multiple pulse signals on single signal generating board, simplified the system structure, reduced the equipment volume. Meanwhile, adopt adjustable PRF reference signal pulse width selection switch and working mode selection switch, improved the flexibility and configurable of system, can under different working mode fast adjustment pulse width and frequency, satisfy the diversification demand of radar system. In addition, the device can adopt +5V power supply, simplified power management, improved the compatibility and stability of system. Through above improvement, solved the low integration, the flexibility is insufficient, the power supply complex and higher cost etc. of prior art, made radar system's pulse signal generation more efficient, convenient. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the content of the utility model more easily be clearly understood, below according to the specific embodiment of the utility model and combining with the attached drawing, the utility model is further detailed.

[0021] Figure 1 It is the structure schematic diagram of the utility model pulse signal generating device.

[0022] Explanation of the drawing mark of the specification:

[0023] 100, ECL turns TTL circuit module;200, first drive module;300, FPGA module;400, second drive module;500, single-ended conversion difference module;600, power conversion module. Specific implementation

[0024] The utility model is further explained in combination with the attached drawing and specific embodiment, so that the person skilled in the art can better understand the utility model and can be implemented, but the embodiment is not as the limitation of the utility model.

[0025] In the utility model, if there is description to direction (up, down, left, right, front and back), it is only for the convenience of describing the technical scheme of the utility model, and is not instructing or suggesting that the indicated technical feature must have a particular orientation, with a particular orientation structure and operation, therefore can not be understood as the limitation of the utility model.

[0026] In the utility model, the meaning of "several" is one or more, the meaning of "multiple" is two or more, and "greater than", "less than", "exceed" and the like are understood as not including the number; "above", "below", "within" and the like are understood as including the number. In the description of the utility model, if "first" and "second" are described, they are only used for distinguishing technical features for the purpose, and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of indicated technical features or implicitly indicating the sequence of indicated technical features.

[0027] In the utility model, unless otherwise explicitly limited, the words such as "arrangement", "installation", "connection" should be understood in a broad sense, for example, can be directly connected, can also be indirectly connected through an intermediate medium, can be fixedly connected, can also be detachably connected, can also be integrally formed, can be mechanically connected, can also be electrically connected or capable of intercommunication, can be the communication or interaction relationship between two elements. The person skilled in the art can reasonably determine the specific meaning of the above words in the utility model in combination with the specific content of the technical scheme.

[0028] Referring to Figure 1 The utility model discloses a pulse signal generating device, including:

[0029] ECL turns TTL circuit module 100 for receiving the first clock signal of external input, and the first clock signal of ECL level is converted into the second clock signal of TTL level, and ECL (emitter coupled logic) has higher working speed and better anti-interference ability, but the level range is incompatible with TTL (transistor-transistor logic), so this ECL turns TTL circuit module 100 is needed;

[0030] First drive module 200 for receiving the first selection control signal of external input and generating the second selection control signal after driving processing, and the first selection control signal includes PRF reference signal pulse width selection, working mode selection and frame / inter-pulse selection signal, and various selection control signals of external input are shaped and driven to make it meet the input requirement (level, driving capacity etc.) of the rear stage FPGA;

[0031] FPGA module 300, its input end is connected with the output end of ECL turns TTL circuit module 100 and the output end of first drive module 200 respectively, and the FPGA module 300 generates timing pulse signal based on the second selection control signal and the second clock signal, and generates multiple sets of timing pulse signal through the logic control (counting, frequency division, logic operation) of FPGA itself interior;

[0032] The second driving module 400 is connected with the output end of the FPGA module 300, and is used for driving (shaping) the timing pulse signal to meet the level of subsequent differential conversion and longer distance transmission;

[0033] The single-ended-to-differential module 500 is connected with the output end of the second driving module 400, and is used for converting the driving-processed timing pulse signal into a differential signal and then outputting the differential signal; better anti-interference performance and signal integrity are obtained through the differential output mode, and obvious advantages are obtained especially in high-speed or long-distance transmission;

[0034] The power conversion module 600 is used for converting an external input power into a predetermined voltage to provide a required working power for the FPGA module 300, and ensure the stable working of the FPGA and the peripheral circuit.

[0035] In an embodiment, the first clock signal is a 100 MHz clock signal. The FPGA module 300 generates six groups of timing pulse signals through frequency division, counting and logical operation of the externally input second selection control signal based on the 100 MHz clock. The six groups of timing pulse signals include one or more of a PRF pulse signal, a frame synchronization signal, a blocking signal, a pre-modulation signal, a frequency hopping trigger signal, a frequency modulation trigger signal, a CAL modulation signal and the like.

[0036] In an embodiment, the first driving module 200 and the second driving module 400 are both SN74ALVC164245DL chips. The externally input pulse width selection, working mode selection and interframe / inter-pulse selection signals are input to the FPGA after being shaped or driven by the SN74ALVC164245DL chip, so as to realize optional control of the pulse signal generation process in different working states.

[0037] The SN74ALVC164245DL is a bidirectional level conversion and driving bus transceiver, which can perform data transmission and level conversion between different voltage domains and has good driving capability. Shaping the externally input selection control signal by the chip helps to remove glitches, ringing and ensure that the FPGA input level threshold requirement is met, thereby improving signal integrity and reliability.

[0038] In an embodiment, the single-ended-to-differential module 500 is a 26LS31 chip. The 26LS31 is a common single-ended input-to-differential output driver, which can convert TTL and other single-ended signals into differential signals (such as RS422 standard). In high-speed or long-distance transmission occasions, the differential signal can more effectively suppress electromagnetic interference (EMI) and enhance signal integrity.

[0039] In one embodiment, the FPGA module 300 includes a Phase-Locked Loop (PLL). The input 100MHz clock is multiplied or divided by the PLL function integrated in the FPGA, so as to adapt to the output requirements of different pulse repetition frequencies and different frame intervals and pulse intervals.

[0040] It should be noted that the PRF pulse width selection comes from the host computer or other control panel, and is generated by means of a key, a dial switch or a GPIO, for selecting different pulse repetition frequencies (Pulse Repetition Frequency) or pulse widths; the working mode selection signal is used to set the running state of the pulse generation system, such as continuous mode, single trigger mode, test / calibration mode, etc.; and the frame / pulse interval selection signal is used to determine whether the generated pulses need to be switched or synchronized at the frame level or the pulse level (such as radar frame synchronization, pulse interval switching, etc.).

[0041] The PRF reference signal pulse width selection, the working mode selection and the frame / pulse interval selection signal come from the external hardware input, are shaped and driven by the SN74ALVC164245DL, and then enter the FPGA; the clock management control is mainly realized by the Phase-Locked Loop (PLL) in the FPGA, and then the logic circuits such as the counter, the frequency divider, the comparator and the state machine are used to finally output the pulse waveforms in multiple ways according to the pulse width, the frequency and the frame / pulse interval set by the external selection signals; the internal processing process of the FPGA is the prior art, and will not be described here.

[0042] In one embodiment, the ECL-to-TTL circuit module 100 is an MC100ELT25 chip when converting the ECL (emitter coupled logic) signal into the TTL (transistor-transistor logic) level. The MC100ELT25 is an ECL-to-TTL level converter chip, which can convert the PECL or ECL signal into a standard TTL level. Such a device generally has a built-in high-speed comparison circuit and a bias circuit, so as to ensure a small propagation delay and a good conversion speed in the conversion process.

[0043] In one embodiment, the power conversion module 600 adopts a DC-DC converter, such as a PW2052 or a PL5900; the power conversion module 600 is used to convert the externally input +5V, 2A power supply into +3.3V, +2.5V and +1.2V voltages, so as to provide a working power supply for the FPGA module 300. The DC-DC converter converts the input 5V voltage into multiple different voltage outputs in a switching regulator (Switching Regulator) mode, so as to meet the requirements of different voltage domains (core voltage, I / O voltage, etc.) of the FPGA.

[0044] In operation, the +5V power supply is first processed by the power conversion module 600 to obtain +3.3V, +2.5V and +1.2V three voltages to meet the working voltage requirements of the FPGA and peripheral circuits; the 100MHz clock signal input from outside is usually output in ECL level, in order to enable the FPGA to normally receive the clock signal, the ECL-TTL circuit (SY100ELT21LZ) is required to be used to perform level conversion, and the TTL level clock meeting the input requirements of the FPGA is output.

[0045] The FPGA internally utilizes the phase-locked loop (PLL) function and high-precision counting logic to divide, multiply or shift the 100MHz clock signal to generate the reference clock required by different pulse widths, different pulse repetition frequencies (PRF) and different interframe / interpulse intervals;

[0046] The ten PRF pulse width selection signals, three working mode selection signals and interframe / interpulse selection signals input from outside are shaped by the SN74ALVC164245DL chip and then input to the FPGA as selection control flags;

[0047] The FPGA module 300 outputs multiple groups of pulse signals (the specific number can be six groups or more) according to the external selection signals and internal clock logic.

[0048] The multiple groups of timing pulse signals output by the FPGA are further driven and level-converted by the SN74ALVC164245DL chip, and finally the output signals are differentially converted by the 26LS31 single-ended to differential chip to improve the anti-interference ability in high-speed and long-distance transmission.

[0049] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the examples, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application, and all should be covered in the scope of the claims of the present application.

Claims

1. A pulse signal generating device, characterized by comprising: The application relates to a circuit module for generating a timing pulse signal. The circuit module comprises: an ECL-to-TTL circuit module (100) for receiving an externally input first clock signal and converting the ECL-level first clock signal into a TTL-level second clock signal; a first driving module (200) for receiving an externally input first selection control signal and generating a second selection control signal after driving processing, wherein the first selection control signal comprises a PRF reference signal pulse width selection, a working mode selection and an interframe / interpulse selection signal; an FPGA module (300) having input ends connected with output ends of the ECL-to-TTL circuit module (100) and output ends of the first driving module (200), wherein the FPGA module (300) generates the timing pulse signal based on the second selection control signal and the second clock signal; a second driving module (400) connected with an output end of the FPGA module (300) and used for driving processing of the timing pulse signal; a single-end-to-differential module (500) connected with an output end of the second driving module (400) and used for converting the driving-processed timing pulse signal into a differential signal and then outputting the differential signal; 2. A pulse signal generating device according to claim 1, characterized in that a power conversion module (600) for converting an externally input power into a predetermined voltage to provide a required working power for the FPGA module (300).

3. A pulse signal generating device according to claim 1, wherein The first clock signal is a 100MHz clock signal.

4. A pulse signal generating device according to claim 1, wherein The first driving module (200) and the second driving module (400) are both SN74ALVC164245DL chips.

5. The pulse signal generating device according to claim 1, wherein The single-end-to-differential module (500) is a 26LS31 chip.

6. A pulse signal generating device according to claim 1, wherein The FPGA module (300) comprises a phase-locked loop circuit.

7. A pulse signal generating device according to claim 1, wherein The ECL-to-TTL circuit module (100) is an MC100ELT25 chip. The power conversion module (600) adopts a DC-DC converter.

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