Booth encoding and decoding circuit and multiplier
By designing Booth encoding and decoding circuits with first and second operation signals that are not simultaneously 1, the problems of high flip frequency and asymmetric path in traditional Booth multipliers are solved, achieving higher operation speed and lower dynamic power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2026-03-13
AI Technical Summary
Traditional Booth multipliers suffer from high dynamic power consumption and slow operation speed due to high flip-flop frequency and asymmetric paths in their encoding and decoding circuits.
Design a Booth codec circuit to reduce signal path delay and glitches, and lower dynamic power consumption by generating a first operation signal and a second operation signal that are not simultaneously 1, and by performing a symmetrical design of the decoding circuit.
It reduces the area of the encoding circuit, decreases the signal switching frequency, improves the operation speed, and reduces dynamic power consumption, especially in the 8*9 signed bit multiplier circuit where power consumption is reduced by 20%.
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Figure CN121657962A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of this disclosure relate to the field of data processing technology, and more specifically, to a Booth codec circuit and a multiplier. Background Technology
[0002] Multipliers are widely used in digital signal processing and artificial intelligence chips. Over 90% of convolutional neural network calculations are multiply-accumulate operations, making multiplier performance and power consumption particularly important in these chips. Traditional multipliers mainly consist of two parts: multiplying the multiplier and multiplicand to produce partial products (PPs), and performing addition tree operations on these partial products. Addition tree operations, in particular, dominate overall computational speed and dynamic power consumption. Therefore, reducing the number of partial products can significantly simplify the circuitry, thereby improving computational speed and reducing chip power consumption. Summary of the Invention
[0003] At least one embodiment of this disclosure provides a Booth encoding / decoding circuit including an encoding circuit and a decoding circuit. The encoding circuit is configured to generate a first operational signal and a second operational signal based on the coefficients of the multiplicand, wherein the first operational signal and the second operational signal are not simultaneously 1; the decoding circuit is configured to obtain a partial product of the multiplier and the multiplicand based on the first operational signal, the second operational signal, the coefficients of the multiplier, and the coefficients of the multiplicand.
[0004] At least one embodiment of this disclosure also provides a multiplier, including the Booth encoding / decoding circuit provided in any of the above embodiments of this disclosure. Attached Figure Description
[0005] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0006] Figure 1 A schematic diagram of a radix-4 booth multiplication encoding circuit is shown.
[0007] Figure 2 A schematic diagram of a radix-4 booth multiplication decoding circuit is shown.
[0008] Figure 3 A schematic block diagram of a Booth codec circuit provided in at least one embodiment of the present disclosure is shown.
[0009] Figure 4 This is a schematic diagram of a decoding circuit provided for at least one embodiment of the present disclosure.
[0010] Figure 5This is a schematic diagram of an encoding circuit provided for at least one embodiment of the present disclosure.
[0011] Figure 6 A schematic diagram of a multiplier provided in at least one embodiment of the present disclosure is shown.
[0012] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure. Detailed Implementation
[0013] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.
[0014] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.
[0015] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.
[0016] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.
[0017] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".
[0018] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.
[0019] In related technologies, the Booth multiplication algorithm was invented by Andrew Donald Booth in 1950. Because the radix-4 Booth algorithm can reduce the number of rows in the partial product by half, it greatly improves the computation speed and reduces chip power consumption. The derivation of the Booth multiplication code is as follows:
[0020] X = x 2n-1 x 2n-2 ...x1 x0,
[0021] Y = (y 2n+1 y 2n )y 2n-1 y 2n-2 ...y1 y0(y -1 ).
[0022] Where X is the multiplier, Y is the multiplicand, and x 2n-1 x 2n-2 ...x1 x0 represents the coefficients of the multiplier, y 2n-1 y 2n-2 ...y1 y0 represents the coefficient of the multiplicand, y -1 To add zeros at the end, y 2n+1 y 2n For extended sign bit.
[0023] Multiplying the multiplier X and the multiplicand Y yields the following:
[0024]
[0025] By expanding the odd-numbered digits of the multiplicand and merging them into the even-numbered digits, the partial product is reduced to half its original value. The coefficients at the beginning of the partial product depend on y. 2k-1 +y 2k -2y 2k+1 The value of is the value of the three adjacent bits of the multiplicand Y. Therefore, by encoding the three adjacent bits of the multiplicand Y, the operation corresponding to the partial product can be obtained.
[0026] The derived formulas provide the radix-4 booth multiplication encoding table shown in Table 1 below:
[0027] Table 1
[0028] <![CDATA[Y i+1 ]]> <![CDATA[Y i ]]> <![CDATA[Y i-1 ]]> Operation 0 0 0 +0X 0 0 1 +1X 0 1 0 +1X 0 1 1 +2X 1 0 0 -2X 1 0 1 -1X 1 1 0 -1X 1 1 1 -0X
[0029] The improved radix-4-booth multiplication encoding table, which is widely used, is shown in Table 2 below:
[0030] Table 2
[0031]
[0032]
[0033] This 4-booth multiplication encoding table can be used... Figure 1 The encoding circuit shown and Figure 2 The decoding circuit shown is implemented.
[0034] The inventors noted that, on the one hand, the encoding circuit generates three signals X2, X1, and Z through XNOR or XOR gates. This logic has the highest toggle rate, with a random toggle frequency of 0.5, and the high toggle rate leads to high dynamic power consumption. On the other hand, the decoding circuit has an asymmetrical structure, for example... Figure 2 As shown, the NOR gate in the upper path has three inputs, while the NOR gate in the lower path has two inputs. This is because different operations will use different paths to obtain the partial product signal (PP). ij Therefore, structural asymmetry can lead to varying path delays, which in turn can cause signal misalignment and glitch, thereby increasing dynamic power consumption.
[0035] At least one embodiment of this disclosure provides a Booth encoding / decoding circuit, including: an encoding circuit and a decoding circuit, wherein the encoding circuit is configured to generate a first operation signal and a second operation signal based on the coefficients of the multiplicand, wherein the first operation signal and the second operation signal are not simultaneously 1; and the decoding circuit is configured to obtain a partial product of the multiplier and the multiplicand based on the first operation signal, the second operation signal, the coefficients of the multiplier and the coefficients of the multiplicand.
[0036] The Booth encoding / decoding circuit provided in at least one embodiment of this disclosure can reduce the area of the encoding circuit, lower the random flip frequency, and avoid glitches by symmetrically designing different paths of the decoding circuit, thereby improving the operation speed and reducing dynamic power consumption.
[0037] The embodiments and some examples of this disclosure will now be described in detail with reference to the accompanying drawings.
[0038] Figure 3 A schematic block diagram of a Booth codec circuit provided in at least one embodiment of the present disclosure is shown. For example, this Booth codec circuit is used to calculate a partial product in a multiplier.
[0039] For example, such as Figure 3 As shown, the Booth encoding / decoding circuit 100 includes an encoding circuit 110 and a decoding circuit 120. For example, the encoding circuit 110 is configured to generate a first operational signal X1 and a second operational signal X2 based on the coefficients of the multiplicand. For example, the first operational signal X1 and the second operational signal X2 are not both 1. For example, the specific values of the first operational signal X1 and the second operational signal X2 can be found in Table 3 below.
[0040] For example, the decoding circuit 120 is configured to obtain a partial product of the multiplier and the multiplicand based on the first operation signal, the second operation signal, the coefficient of the multiplier, and the coefficient of the multiplicand.
[0041] The radix-4-booth multiplication encoding table and corresponding encoding / decoding circuit provided in this embodiment will Figure 1 and Figure 2 The logic of the Z signal is incorporated into the first operation signal X1 and the second operation signal X2, reducing one signal and making the structure of different paths symmetrical. This avoids glitches caused by signal delay and is more conducive to reducing dynamic power consumption. At the same time, it makes the circuit simpler, thereby reducing power consumption by reducing the circuit area.
[0042] For example, the Booth multiplication encoding table corresponding to the Booth encoding / decoding circuit 100 provided in this embodiment is shown in Table 3 below:
[0043] Table 3
[0044] <![CDATA[Y i+1 ]]> <![CDATA[Y i ]]> <![CDATA[Y i-1 ]]> <![CDATA[PP ij ]]> X1 X2 0 0 0 +0X 0 0 0 0 1 +1X 1 0 0 1 0 +1X 1 0 0 1 1 +2X 0 1 1 0 0 -2X 0 1 1 0 1 -1X 1 0 1 1 0 -1X 1 0 1 1 1 -0X 0 0
[0045] For example, through Figure 3 The Booth encoding / decoding circuit 100 shown can implement the Booth multiplication encoding table.
[0046] Figure 4 This is a schematic diagram of a decoding circuit provided for at least one embodiment of the present disclosure. For example, such as Figure 4 As shown, the decoding circuit 120 includes an inverting sub-circuit 121, a selecting sub-circuit 122, and an output sub-circuit 123.
[0047] For example, the inverting sub-circuit 121 is configured to invert the coefficients Xj-1 of the (j-1)th multiplier and Xj of the jth multiplier based on the coefficient Yi+1 of the (i+1)th multiplicand.
[0048] For example, in some examples, such as Figure 4 As shown, the inverting circuit 121 includes a first XOR gate A1 and a second XOR gate A2. For example, the first input of the first XOR gate A1 is the coefficient Yi+1 of the (i+1)th multiplicand, and the second input of the first XOR gate A1 is the coefficient Xj-1 of the (j-1)th multiplier; the first input of the second XOR gate A2 is the coefficient Yi+1 of the (i+1)th multiplicand, and the second input of the second XOR gate A2 is the coefficient Xj of the jth multiplier.
[0049] For example, the selector circuit 122 is configured to determine whether to shift the coefficients of the multiplier after the inversion operation based on the first operation signal and the second operation signal to obtain the first intermediate signal and the second intermediate signal.
[0050] For example, in some examples, such as Figure 4 As shown, the selector circuit 122 includes a first NAND gate A3 and a second NAND gate A4.
[0051] For example, the first input of the first NAND gate A3 is the second operation signal X2, and the second input of the first NAND gate A3 is connected to the output of the first XOR gate A1; the first input of the second NAND gate A4 is the first operation signal X1, and the second input of the second NAND gate A4 is connected to the output of the second XOR gate A2.
[0052] For example, the output sub-circuit 123 is configured to output a partial product based on the first intermediate signal and the second intermediate signal. For example, the output sub-circuit 123 is configured to determine which path to use for output based on the first intermediate signal and the second intermediate signal, that is, to determine whether the result of the path where output X2 is located or the result of the path where X1 is located is used as the partial product.
[0053] For example, such as Figure 4 As shown, the output sub-circuit 123 includes a third NAND gate A5; for example, the first input of the third NAND gate A5 is connected to the output of the first NAND gate A3, the second input of the third NAND gate A5 is connected to the output of the second NAND gate A4, and the output of the third NAND gate A5 is connected to the first output terminal OUT1 to output the partial product PPij.
[0054] See Figure 4 In the embodiments of this disclosure, the upper and lower paths of the Booth decoding circuit are completely symmetrical, which can make different operation paths consistent and avoid glitches caused by path delay due to inconsistency in the upper and lower path structures, thereby improving the operation speed and reducing dynamic power consumption.
[0055] Figure 5 This is a schematic diagram of an encoding circuit provided for at least one embodiment of the present disclosure. Figure 5 As shown, the encoding circuit 110 includes: a first operational signal generation circuit 111 and a second operational signal generation circuit 112.
[0056] For example, the first operation signal generation circuit 111 is configured to obtain a first operation signal X1 based on the coefficient Yi-1 of the (i-1)th multiplicand and the coefficient Yi of the ith multiplicand; the second operation signal generation circuit 112 is configured to obtain a second operation signal X2 based on the coefficient Yi-1 of the (i-1)th multiplicand, the coefficient Yi of the ith multiplicand, and the coefficient Yi+1 of the (i+1)th multiplicand.
[0057] For example, in some examples, such as Figure 5 As shown, the first operational signal generation circuit 111 includes a first NOR gate A6, a second NOR gate A7, and a first AND gate A8.
[0058] For example, the first input of the first NOR gate A6 is the coefficient Yi-1 of the (i-1)th multiplicand, and the second input of the first NOR gate A6 is the coefficient Yi of the ith multiplicand. The first input of the second NOR gate A7 is connected to the output of the first AND gate A8, the second input of the second NOR gate A7 is connected to the output of the first NOR gate A6, and the output of the second NOR gate A7 is connected to the second output terminal OUT2 to output the first operational signal X1. The first input of the first AND gate A8 is the coefficient Yi-1 of the (i-1)th multiplicand, and the second input of the first AND gate A8 is the coefficient Yi of the ith multiplicand.
[0059] For example, such as Figure 5 As shown, the second operational signal generation circuit 112 includes a first transistor T1, a second transistor T2, a third transistor T3 and a fourth transistor T4, a fourth NAND gate A9, and a first inverter A10.
[0060] For example, the gate of the first transistor T1 receives the first inverted signal A2B, and the gate of the second transistor T2 receives the second inverted signal A2. The second inverted signal A2 is the inverted signal of the first inverted signal A2B, and the first inverted signal A2B is the inverted signal of the coefficient Yi+1 of the (i+1)th multiplicand.
[0061] like Figure 5 As shown, the second operational signal generation circuit further includes a second inverter A11 and a third inverter A12; the input of the second inverter A11 receives the coefficient Yi+1 of the (i+1)th bit of the multiplicand, and the output of the second inverter A11 is the first inverted signal A2B, thereby obtaining the first inverted signal A2B; the input of the third inverter A12 receives the first inverted signal A2B, and the output of the third inverter A12 is the second inverted signal A2, thereby obtaining the second inverted signal A2.
[0062] For example, such as Figure 5 As shown, the first terminal of the first transistor T1 is connected to the output of the first NOR gate A6, and the second terminal of the first transistor T1 is connected to the third output terminal OUT3; the first terminal of the second transistor T2 is connected to the output of the first NOR gate A6, and the second terminal of the second transistor T2 is connected to the third output terminal OUT3; the gate of the third transistor T3 receives the second inverted signal A2, and the first terminal of the third transistor T3 is connected to the first voltage terminal VDD to receive the first voltage; the second terminal of the third transistor T3 is connected to the first input of the first inverter A10; the gate of the fourth transistor T4 receives the first inverted signal A2B, and the first terminal of the fourth transistor T4 is connected to the second voltage terminal VSS to receive the second voltage; the second terminal of the fourth transistor is connected to the second input of the first inverter A10, thereby determining whether to output the output of the first NOR gate A6 as the second operational signal X2 or output the output of the fourth NAND gate A9 as the second operational signal X2 based on whether Yi+1 equals 0 or equals 1.
[0063] For example, the first input of the fourth NAND gate A9 is the coefficient Yi-1 of the (i-1)th multiplicand, and the second input of the fourth NAND gate A9 is the coefficient Yi of the ith multiplicand; the third input of the first inverter A10 is connected to the output of the fourth NAND gate A9, and the output of the first inverter A10 is connected to the third output terminal OUT3.
[0064] For example, such as Figure 5 As shown, the first transistor T1 and the third transistor T3 are P-type, and the second transistor T2 and the fourth transistor T4 are N-type. For example, in the embodiments of this disclosure, the first terminal of the N-type transistor is the drain and the second terminal is the source; the first terminal of the P-type transistor is the source and the second terminal is the drain.
[0065] For example, the specific implementations of the various logic gate circuits in the above embodiments of this disclosure can be achieved through structures in the art, and will not be described in detail here.
[0066] It should be noted that the transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure all use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal.
[0067] For example, the first voltage terminal VDD is configured to provide a DC high-level signal (e.g., higher than or equal to the high-level portion of a clock signal). This DC high-level signal is referred to as the first voltage. For example, the first voltage is greater than the second voltage. The following embodiments are the same and will not be described again.
[0068] For example, the second voltage terminal VSS is configured to provide a DC low-level signal (e.g., lower than or equal to the low-level portion of the clock signal), such as ground. This DC low-level signal is referred to here as the second voltage. The following embodiments are the same and will not be described again.
[0069] See Figure 5 In the embodiments of this disclosure, referring to Table 2 above, the existing Booth encoding circuit generates three signals X1, X2 and Z with a flip frequency of 0.5. However, referring to Table 3, the Booth encoding circuit in the embodiments of this disclosure only has two signals, X1 and X2. The flip frequency of the first operational signal X1 is 0.5, and the flip frequency of the second operational signal X2 is 0.25. Therefore, the signal flip frequency of the Booth encoding circuit provided in the embodiments of this disclosure is half that of the existing ones.
[0070] Furthermore, existing Booth encoding circuits require 14 transistors to implement a single XOR gate or a single XOR gate, thus requiring 42 transistors in total. In contrast, the Booth encoding circuit disclosed herein can be implemented with only 24 transistors, thereby reducing the area of the encoding circuit section by 40%.
[0071] At least one embodiment of this disclosure also provides a multiplier, including the Booth encoding / decoding circuit provided in any of the above embodiments of this disclosure.
[0072] Figure 6 A schematic diagram of a multiplier provided in at least one embodiment of the present disclosure is shown. For example, such as Figure 6 As shown, the multiplier 200 includes a Booth codec circuit 100. For example, the Booth codec circuit 100 can employ... Figures 3-5 The circuit structure in the multiplier 200 is implemented to obtain a partial product. The multiplier 200 can perform subsequent addition tree operations based on the partial product obtained by the Booth encoding / decoding circuit 100. For example, the multiplier can be used in an 8*9 multiplier circuit with a signed bit, and it can also be applied to other multiplier circuits. The embodiments disclosed herein do not limit this.
[0073] When the Booth codec circuit of this disclosure is applied to an 8*9 signed multiplier circuit, the total power consumption of the 8*9 signed multiplier is reduced by 20% compared to using existing Booth codec circuits.
[0074] It should be noted that, for clarity and brevity, this disclosure does not show all the constituent units of the multiplier 200. To achieve the necessary functions of the multiplier 200, those skilled in the art can provide or set other constituent units (not shown) according to specific needs, and this disclosure does not limit this.
[0075] The following is for reference. Figure 7 It illustrates an electronic device suitable for implementing embodiments of the present disclosure (e.g., Figure 1 The diagram below shows the structure of the terminal device or server 600. The terminal device in this embodiment may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and vehicle terminals (e.g., vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 7 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.
[0076] like Figure 7As shown, electronic device 600 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 601, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 602 or a program loaded from storage device 606 into random access memory (RAM) 603. RAM 603 also stores various programs and data required for the operation of electronic device 600. Processing device 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604. For example, the processing device may include the multiplier provided in the above embodiments of this disclosure.
[0077] Typically, the following devices can be connected to I / O interface 605: input devices 606 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 607 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 606 including, for example, magnetic tapes, hard disks, etc.; and communication devices 609. Communication device 609 allows electronic device 600 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 6 An electronic device 600 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.
[0078] For example, some methods and procedures performed by electronic device 600 can be implemented as computer software programs. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing methods. In such embodiments, the computer program can be downloaded and installed from a network via communication device 609, or installed from storage device 606, or installed from ROM 602. When the computer program is executed by processing device 601, it performs defined specific functions.
[0079] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.
[0080] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.
[0081] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.
[0082] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: acquire at least two Internet Protocol (IP) addresses; send a node evaluation request including the at least two IP addresses to a node evaluation device, wherein the node evaluation device selects an IP address from the at least two IP addresses and returns it; and receive the IP address returned by the node evaluation device; wherein the acquired IP address indicates an edge node in a content delivery network.
[0083] Alternatively, the aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receive a node evaluation request including at least two Internet Protocol (IP) addresses; select an IP address from the at least two IP addresses; and return the selected IP address; wherein the received IP address indicates an edge node in the content delivery network.
[0084] Computer program code for performing method operations can be written in one or more programming languages or a combination thereof. These programming languages include, but are not limited to, object-oriented programming languages—such as Java, Smalltalk, and C++—as well as conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0085] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The name of a unit does not necessarily limit the unit itself; for example, the first acquisition unit can also be described as "a unit that acquires at least two Internet Protocol addresses".
[0086] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.
[0087] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0088] According to one or more embodiments of this disclosure, Example 1 provides a Booth encoding / decoding circuit, including: an encoding circuit and a decoding circuit, wherein,
[0089] The encoding circuit is configured to generate a first operational signal and a second operational signal based on the coefficients of the multiplicand, wherein the first operational signal and the second operational signal are not both 1 at the same time;
[0090] The decoding circuit is configured to obtain a partial product of the multiplier and the multiplicand based on the first operational signal, the second operational signal, the coefficient of the multiplier, and the coefficient of the multiplicand.
[0091] According to one or more embodiments of this disclosure, Example 2 provides that the decoding circuit in Example 1 includes an inverting sub-circuit, a selecting sub-circuit, and an output sub-circuit;
[0092] The inverting sub-circuit is configured to invert the coefficients Xj-1 of the (j-1)th multiplier and Xj of the jth multiplier based on the coefficient Yi+1 of the (i+1)th multiplicand.
[0093] The selection sub-circuit is configured to determine, based on the first operational signal and the second operational signal, whether to shift the coefficients of the multiplier after the inversion operation and obtain the first intermediate signal and the second intermediate signal;
[0094] The output sub-circuit is configured to output the partial product based on the first intermediate signal and the second intermediate signal, where i is an integer greater than 0 and j is an integer greater than 0.
[0095] According to one or more embodiments of this disclosure, Example 3 provides that the encoding circuit in Example 1 includes: a first operational signal generation circuit and a second operational signal generation circuit;
[0096] The first operational signal generation circuit is configured to obtain the first operational signal based on the coefficient Yi-1 of the (i-1)th multiplicand and the coefficient Yi of the ith multiplicand.
[0097] The second operation signal generation circuit is configured to obtain the second operation signal based on the coefficient Yi-1 of the (i-1)th multiplicand, the coefficient Yi of the ith multiplicand, and the coefficient Yi+1 of the (i+1)th multiplicand, where i is an integer greater than 0.
[0098] According to one or more embodiments of this disclosure, Example 4 provides the inverting sub-circuit of Example 2, which includes a first XOR gate A1 and a second XOR gate A2, wherein the first input of the first XOR gate is the coefficient Yi+1 of the (i+1)th multiplicand, and the second input of the first XOR gate is the coefficient Xj-1 of the (j-1)th multiplier; the first input of the second XOR gate is the coefficient Yi+1 of the (i+1)th multiplicand, and the second input of the second XOR gate is the coefficient Xj of the jth multiplier.
[0099] According to one or more embodiments of this disclosure, Example 5 provides that the selection sub-circuit in Example 2 includes a first NAND gate A3 and a second NAND gate A4;
[0100] Wherein, the first input of the first NAND gate is the second operation signal, and the second input of the first NAND gate is connected to the output of the first XOR gate;
[0101] The first input of the second NAND gate is the first operation signal, and the second input of the second NAND gate is connected to the output of the second XOR gate.
[0102] According to one or more embodiments of this disclosure, Example 6 provides that the output sub-circuit of Example 2 includes a third NAND gate A5;
[0103] Wherein, the first input of the third NAND gate is connected to the output of the first NAND gate, the second input of the third NAND gate is connected to the output of the second NAND gate, and the output of the third NAND gate is connected to the first output terminal to output the partial product.
[0104] According to one or more embodiments of this disclosure, Example 7 provides the first operational signal generation circuit in Example 3, which includes a first NOR gate A6, a second NOR gate A7, and a first AND gate A8;
[0105] Wherein, the first input of the first NOR gate is the coefficient Yi-1 of the (i-1)th multiplicand, and the second input of the first NOR gate is the coefficient Yi of the i-th multiplicand;
[0106] The first input of the second NOR gate is connected to the output of the first AND gate, the second input of the second NOR gate is connected to the output of the first NOR gate, and the output of the second NOR gate is connected to the second output terminal to output the first arithmetic signal.
[0107] The first input of the first AND gate is the coefficient Yi-1 of the (i-1)th multiplicand, and the second input of the first AND gate is the coefficient Yi of the ith multiplicand.
[0108] According to one or more embodiments of this disclosure, Example 8 provides the second operational signal generation circuit in Example 7, which includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fourth NAND gate A9, and a first inverter A10;
[0109] Wherein, the gate of the first transistor receives the first inverted signal A2B, and the gate of the second transistor receives the second inverted signal A2, wherein the second inverted signal A2 is the inverted signal of the first inverted signal A2B, and the first inverted signal A2B is the inverted signal of the coefficient Yi+1 of the (i+1)th multiplicand.
[0110] The first terminal of the first transistor is connected to the output of the first NOR gate A6, and the second terminal of the first transistor is connected to the third output terminal.
[0111] The first terminal of the second transistor is connected to the output of the first NOR gate A6, and the second terminal of the second transistor is connected to the third output terminal;
[0112] The gate of the third transistor receives the second inverted signal A2; the first terminal of the third transistor is connected to the first voltage terminal VDD to receive the first voltage; the second terminal of the third transistor is connected to the first input of the first inverter A10.
[0113] The gate of the fourth transistor receives the first inverted signal A2B, the first terminal of the fourth transistor is connected to the second voltage terminal VSS to receive the second voltage, and the second terminal of the fourth transistor is connected to the second input of the first inverter A10.
[0114] The first input of the fourth NAND gate A9 is the coefficient Yi-1 of the (i-1)th multiplicand, and the second input of the fourth NAND gate A9 is the coefficient Yi of the i-th multiplicand;
[0115] The third input of the first inverter A10 is connected to the output of the fourth NAND gate A9, and the output of the first inverter A10 is connected to the third output terminal.
[0116] According to one or more embodiments of this disclosure, Example 9 provides that the first transistor and the third transistor in Example 8 are P-type, and the second transistor and the fourth transistor are N-type.
[0117] According to one or more embodiments of this disclosure, Example 10 provides that the second operational signal generation circuit in Example 8 further includes a second inverter A11 and a third inverter A12;
[0118] Wherein, the input of the second inverter A11 receives the coefficient Yi+1 of the (i+1)th multiplicand, and the output of the second inverter A11 is the first inverted signal;
[0119] The input of the third inverter A12 receives the first inverted signal A2B, and the output of the third inverter A12 is the second inverted signal A2.
[0120] According to one or more embodiments of this disclosure, Example 11 provides a multiplier including the Booth codec circuitry provided in Examples 1-10.
[0121] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.
[0122] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.
[0123] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.
Claims
1. A Booth encoding / decoding circuit, comprising: Encoding circuit and decoding circuit, among which, The encoding circuit is configured to generate a first operation signal and a second operation signal based on the coefficients of the multiplicand, wherein the first operation signal and the second operation signal are not both 1 at the same time; The decoding circuit is configured to obtain a partial product of the multiplier and the multiplicand based on the first operational signal, the second operational signal, the coefficient of the multiplier, and the coefficient of the multiplicand.
2. The circuit according to claim 1, wherein, The decoding circuit includes an inverting sub-circuit, a selecting sub-circuit, and an output sub-circuit; The inverting sub-circuit is configured to invert the coefficients of the (j-1)th multiplier and the jth multiplier based on the coefficient of the (i+1)th multiplicand. The selection sub-circuit is configured to determine, based on the first operational signal and the second operational signal, whether to shift the coefficients of the multiplier after the inversion operation and obtain the first intermediate signal and the second intermediate signal; The output sub-circuit is configured to output the partial product based on the first intermediate signal and the second intermediate signal, where i is an integer greater than 0 and j is an integer greater than 0.
3. The circuit according to claim 1, wherein, The encoding circuit includes: a first operational signal generation circuit and a second operational signal generation circuit; The first operational signal generation circuit is configured to obtain the first operational signal based on the coefficient of the (i-1)th multiplicand and the coefficient of the ith multiplicand. The second operation signal generation circuit is configured to obtain the second operation signal based on the coefficient of the (i-1)th multiplicand, the coefficient of the ith multiplicand, and the coefficient of the (i+1)th multiplicand, where i is an integer greater than 0.
4. The circuit according to claim 2, wherein, The inverting sub-circuit includes a first XOR gate and a second XOR gate, wherein the first input of the first XOR gate is the coefficient of the (i+1)th bit multiplicand, and the second input of the first XOR gate is the coefficient of the (j-1)th bit multiplier; the first input of the second XOR gate is the coefficient of the (i+1)th bit multiplicand, and the second input of the second XOR gate is the coefficient of the jth bit multiplier.
5. The circuit according to claim 4, wherein, The selection sub-circuit includes a first NAND gate and a second NAND gate; Wherein, the first input of the first NAND gate is the second operation signal, and the second input of the first NAND gate is connected to the output of the first XOR gate; The first input of the second NAND gate is the first operation signal, and the second input of the second NAND gate is connected to the output of the second XOR gate.
6. The circuit according to claim 5, wherein, The output sub-circuit includes a third NAND gate; Wherein, the first input of the third NAND gate is connected to the output of the first NAND gate, the second input of the third NAND gate is connected to the output of the second NAND gate, and the output of the third NAND gate is connected to the first output terminal to output the partial product.
7. The circuit according to claim 3, wherein, The first operational signal generation circuit includes a first NOR gate, a second NOR gate, and a first AND gate; Wherein, the first input of the first NOR gate is the coefficient of the (i-1)th multiplicand, and the second input of the first NOR gate is the coefficient of the i-th multiplicand; The first input of the second NOR gate is connected to the output of the first AND gate, the second input of the second NOR gate is connected to the output of the first NOR gate, and the output of the second NOR gate is connected to the second output terminal to output the first arithmetic signal. The first input of the first AND gate is the coefficient of the (i-1)th multiplicand, and the second input of the first AND gate is the coefficient of the ith multiplicand.
8. The circuit according to claim 7, wherein, The second operational signal generation circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fourth NAND gate, and a first inverter; Wherein, the gate of the first transistor receives a first inverted signal, and the gate of the second transistor receives a second inverted signal, wherein the second inverted signal is the inverted signal of the first inverted signal, and the first inverted signal is the inverted signal corresponding to the coefficient of the (i+1)th multiplicand. The first terminal of the first transistor is connected to the output of the first NOR gate, and the second terminal of the first transistor is connected to the third output terminal. The first terminal of the second transistor is connected to the output of the first NOR gate, and the second terminal of the second transistor is connected to the third output terminal; The gate of the third transistor receives the second inverted signal; the first terminal of the third transistor is connected to the first voltage terminal to receive the first voltage; the second terminal of the third transistor is connected to the first input of the first inverter. The gate of the fourth transistor receives the first inverted signal; the first terminal of the fourth transistor is connected to the second voltage terminal to receive the second voltage; the second terminal of the fourth transistor is connected to the second input of the first inverter. The first input of the fourth NAND gate is the coefficient of the (i-1)th multiplicand, and the second input of the fourth NAND gate is the coefficient of the i-th multiplicand. The third input of the first inverter is connected to the output of the fourth NAND gate, and the output of the first inverter is connected to the third output terminal.
9. The circuit according to claim 8, wherein, The first transistor and the third transistor are P-type, and the second transistor and the fourth transistor are N-type.
10. The circuit according to claim 8, wherein, The second operational signal generation circuit further includes a second inverter and a third inverter; The input of the second inverter receives the coefficient of the (i+1)th bit multiplicand, and the output of the second inverter is the first inverted signal. The input of the third inverter receives the first inverted signal, and the output of the third inverter is the second inverted signal.
11. A multiplier comprising the Booth encoding / decoding circuitry as described in any one of claims 1-10.