Multi-chip series IAP upgrading method and device, program product and storage medium

Abstract

The invention discloses a multi-chip series IAP upgrading method and device, a program product and a storage medium, and relates to the technical field of chip upgrading. A communication network between the chips is obtained and constructed, and the connection relation of all the chips in the equipment is comprehensively mastered; calculating an optimal transmission path from the main control chip to each chip to be upgraded based on the communication network, and establishing a dynamic routing table to provide reliable path guidance for subsequent data transmission; the method comprises the following steps: analyzing a target chip list and firmware version information in an IAP upgrading instruction, and accurately identifying a target chip needing to be upgraded; the firmware data is divided into a plurality of data packets, and the data packets are transmitted in series according to the optimal transmission path in the dynamic routing table, so that the firmware data transmission of the chip without the direct communication interface is realized; and finally, through firmware verification and updating operation, the reliability of firmware upgrading is ensured. The limitation that only the master control MCU directly connected with the external communication interface can be upgraded in a traditional IAP upgrading scheme is broken through, and the coverage range of firmware upgrading is widened.

Description

Technical Field

[0001] This application relates to the field of chip upgrade technology, specifically to a multi-chip cascade IAP upgrade method, device, program product, and storage medium. Background Technology

[0002] As electronic devices become increasingly feature-rich, single MCUs are no longer sufficient to meet the demands of complex functions. More and more electronic devices are adopting multi-chip architectures to implement different functional modules. In practical applications, these chips require periodic firmware upgrades to fix vulnerabilities, optimize performance, or add new features. Currently, the most common firmware upgrade method is In-Application Programming (IAP) upgrade, which involves receiving firmware data through an external communication interface and directly modifying the MCU's internal firmware storage area to achieve the firmware upgrade.

[0003] However, in practical applications, electronic devices typically provide only one communication interface to the outside world, while internally they often house multiple MCUs. Existing IAP upgrade solutions primarily target the main control MCU directly connected to the external communication interface, failing to upgrade the firmware of other MCUs within the device. This is because other onboard MCUs usually lack direct external communication interfaces and can only interact with the main control MCU via an internal bus. When it's necessary to update the firmware of multiple MCUs within the device, or to specify an upgrade for a particular MCU, existing solutions cannot update the firmware of these MCUs without direct communication interfaces. This results in incomplete firmware upgrade coverage and limited upgrade scope, thus affecting the normal operation of the entire device. Summary of the Invention

[0004] In view of this, this application provides a multi-chip cascaded IAP upgrade method, device, program product and storage medium.

[0005] Firstly, this application provides a multi-chip cascaded IAP upgrade method, the method comprising: Obtain the connection topology information of each chip in a multi-chip device, and construct an inter-chip communication network based on the topology information; Calculate the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network, and establish a dynamic routing table; Receive the IAP upgrade command sent by the host computer, parse the target chip list and firmware version information in the IAP upgrade command, and send the control command to enter IAP mode to each target chip to be upgraded in the target chip list; The firmware data corresponding to the firmware version information is divided into multiple data packets, and the data packets are transmitted in series to each of the target chips to be upgraded according to the optimal transmission path in the dynamic routing table. After each target chip to be upgraded receives the firmware, firmware verification is performed. The new firmware that passes the verification is written into the program storage area of ​​each target chip to be upgraded and the firmware update operation is executed.

[0006] By adopting the above technical solution, and by acquiring the connection topology information of each chip in a multi-chip device and constructing an inter-chip communication network, the connection relationships of all chips within the device can be fully understood. Based on this communication network, the optimal transmission path from the main control chip to each chip to be upgraded is calculated, and a dynamic routing table is established to provide reliable path guidance for subsequent data transmission. By parsing the target chip list and firmware version information in the IAP upgrade command, the target chip that needs to be upgraded can be accurately identified. The firmware data is divided into multiple data packets and transmitted in series according to the optimal transmission path in the dynamic routing table, realizing firmware data transmission for chips without direct communication interfaces. Finally, firmware verification and update operations ensure the reliability of the firmware upgrade. This solution breaks through the limitation of traditional IAP upgrade solutions that can only upgrade the main control MCU directly connected to the external communication interface, realizing firmware upgrades for any chip within the device, improving the coverage of firmware upgrades, and ensuring the normal operation of each functional module of the multi-chip device.

[0007] Optionally, constructing an inter-chip communication network based on the topology information includes: Based on the number and quality of connections of each chip node in the topology information, calculate the importance weight of each chip node in the topology; Based on the length of the connection path and the number of relay nodes in the topology information, the transmission efficiency of each connection path is evaluated. Based on the importance weights and the transmission efficiency, key chips are determined from the topology information; Based on the key chips and topological connections, an inter-chip communication network with trunk paths and branch paths is constructed.

[0008] Optionally, the step of calculating the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network and establishing a dynamic routing table includes: The system detects all candidate main control chips with external communication interfaces in a multi-chip device and obtains the processing performance parameters and storage capacity parameters of the candidate main control chips. Based on the processing performance parameters and storage capacity parameters, a weighted calculation is performed, and the candidate main control chip with the highest weighted value and which has established a communication connection with the host computer is selected as the main control chip. Obtain the communication bandwidth parameters and response delay parameters of each chip node in the inter-chip communication network; Calculate the data transmission time between adjacent chip nodes based on the communication bandwidth parameters and response delay parameters; Based on the data transmission time and the historical communication failure records of all chip nodes, calculate the reliability weight of all transmission paths between the main control chip and each chip to be upgraded. Using the shortest path algorithm, the reliability weight is used as the path cost to calculate the optimal transmission path from the main control chip to each chip to be upgraded, and the optimal transmission path, the communication bandwidth parameter, and the response delay parameter are recorded in the dynamic routing table.

[0009] Optionally, the step of dividing the firmware data corresponding to the firmware version information into multiple data packets includes: Obtain the minimum communication buffer capacity and the maximum number of bytes transmitted in a single operation in the inter-chip communication network; The data packet size is determined based on the minimum communication buffer capacity and the maximum number of bytes transmitted in a single transmission. The firmware data corresponding to the firmware version information is divided sequentially according to the size of the data packet, and an incremental sequence number is assigned to each data packet. Add a data packet header to each data packet containing the incrementing sequence number, the target chip identifier to be upgraded, and the data packet checksum; A packet forwarding flag is set based on the target chip identifier to be upgraded in the packet header, and the packet forwarding flag is used to indicate the number of packet forwardings; The data packets are prioritized according to the data packet forwarding flag, with higher priority given a greater number of forwarding attempts.

[0010] Optionally, the step of transmitting the data packets in series to each of the target chips to be upgraded according to the optimal transmission path in the dynamic routing table includes: Based on the optimal transmission path in the dynamic routing table, the multiple target cores to be upgraded are divided into multiple serial transmission branches; Obtain the historical fluctuation range of the communication bandwidth parameters and response delay parameters of the first target chip to be upgraded within each of the serial transmission branches; Based on the historical fluctuation range, calculate the upper limit of the transmission capacity and the fluctuation coefficient of the first target chip to be upgraded in each of the serial transmission branches; Based on the transmission capacity limit and the fluctuation coefficient, the data packets will be divided into a base data packet group and a compensation data packet group according to the increasing sequence number of the data packets; The reference data packet group is sent to the first target chip to be upgraded in each of the serial transmission branches. The first target chip to be upgraded receives and forwards the reference data packet group to the next target chip to be upgraded in the branch. At the same time as the reference data packet group is transmitted, the compensation data packet group is sent to the first target chip to be upgraded in the serial transmission branch to supplement the data packets lost by each target chip to be upgraded during the reception of the reference data packet group.

[0011] Optionally, the step of transmitting the data packets in series to each of the target chips to be upgraded according to the optimal transmission path in the dynamic routing table further includes: Monitor the data packet reception status of each target chip to be upgraded in each of the aforementioned serial transmission branches; When an abnormal chip awaiting upgrade is detected with an abnormal data packet reception status, the data packet loss rate of the abnormal chip awaiting upgrade is calculated. Based on the packet loss rate, adjust the ratio of the baseline packet group and the compensation packet group in the corresponding serial transmission branch; Based on the response delay parameters of the abnormal chip to be upgraded, set the data packet retransmission waiting time; If no confirmation of receipt is received from the abnormal chip to be upgraded during the data packet retransmission waiting time, the baseline data packet group and the compensation data packet group will be retransmitted according to the adjusted ratio.

[0012] Optionally, the firmware verification after each of the target chips to be upgraded has received the firmware includes: All data packets received by each of the target chips to be upgraded are reassembled into complete firmware according to their incrementing sequence numbers; Calculate the checksum of the complete firmware and compare it with the firmware checksum carried in the IAP upgrade instruction; If the checksum matches the firmware check value, a firmware check pass flag is generated; If the checksum is inconsistent with the firmware checksum, a checksum failure message is sent to the main control chip and a request is made to retransmit the firmware data.

[0013] A second aspect of this application provides a multi-chip cascaded IAP upgrade electronic device, the electronic device comprising: one or more processors and a memory; the memory being coupled to the one or more processors, the memory being used to store computer program code including computer instructions, the one or more processors calling the computer instructions to cause the multi-chip cascaded IAP upgrade electronic device to perform the method described in the first aspect and any possible implementation thereof.

[0014] A third aspect of this application provides a computer program product containing instructions that, when run on a multi-chip cascaded IAP-upgraded electronic device, causes the electronic device to perform the method described in the first aspect and any possible implementation thereof.

[0015] A fourth aspect of this application provides a computer-readable storage medium including instructions that, when run on a multi-chip cascaded IAP-upgraded electronic device, cause the electronic device to perform the methods described in the first aspect and any possible implementation thereof.

[0016] In summary, one or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages: This application acquires the connection topology information of each chip in a multi-chip device and constructs an inter-chip communication network, enabling a comprehensive understanding of the connection relationships of all chips within the device. Based on this communication network, it calculates the optimal transmission path from the main control chip to each chip to be upgraded and establishes a dynamic routing table, providing reliable path guidance for subsequent data transmission. By parsing the target chip list and firmware version information in the IAP upgrade command, it can accurately identify the target chip that needs to be upgraded. Firmware data is segmented into multiple data packets and transmitted in series according to the optimal transmission path in the dynamic routing table, enabling firmware data transmission for chips without direct communication interfaces. Finally, firmware verification and update operations ensure the reliability of the firmware upgrade. This solution overcomes the limitation of traditional IAP upgrade schemes, which can only upgrade the main control MCU directly connected to an external communication interface, realizing firmware upgrades for any chip within the device, improving the coverage of firmware upgrades, and ensuring the normal operation of each functional module of the multi-chip device. Attached Figure Description

[0017] Figure 1 This is a flowchart illustrating a multi-chip cascaded IAP upgrade method provided in an embodiment of this application; Figure 2 This is a flowchart of the data packet transmission process for multi-chip cascaded IAP upgrade provided in an embodiment of this application; Figure 3 This is a flowchart of an IAP upgrade process for a single target chip to be upgraded, provided in an embodiment of this application. Figure 4 This is a schematic diagram of an exemplary hardware structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0019] In the description of the embodiments of this application, the words "for example" or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design that is described as "for example" or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design options. Rather, the use of the words "for example" or "for instance" is intended to present the relevant concepts in a specific manner.

[0020] In the description of the embodiments of this application, the term "multiple" means two or more. For example, multiple systems means two or more systems, and multiple screen terminals means two or more screen terminals. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0021] Please refer to Figure 1 A flowchart illustrating a multi-chip cascaded IAP upgrade method is presented. This method can be implemented using a computer program, a microcontroller, or run on a multi-chip cascaded IAP upgrade device. The computer program can be integrated into the computer device or run as a standalone application. Specifically, the method includes steps 10 to 40, as follows: Step 10: Obtain the connection topology information of each chip in the multi-chip device, and construct an inter-chip communication network based on the topology information.

[0022] Among them, connection topology information refers to the connection relationships, connection quality, and connection paths of each chip node in a multi-chip device, which is used to reflect the physical connection structure and communication status of the chips inside the device.

[0023] Inter-chip communication networks refer to chip communication architectures with backbone and branch paths built based on topology information, used to realize data transmission and information exchange between different chips within a device. This communication network identifies key chips and establishes an efficient communication structure by evaluating the importance weights of chip nodes and the transmission efficiency of connection paths, providing a network foundation for the subsequent serial transmission of firmware data.

[0024] Specifically, in the IAP upgrade process of multi-chip devices, the internal chips are connected through different communication buses and interfaces, forming a complex network structure. Traditional upgrade solutions can only upgrade chips directly connected to external communication interfaces, failing to reach other internal chips. Therefore, it is necessary to obtain the connection topology information of each chip in the multi-chip device and construct an inter-chip communication network. In the specific implementation of obtaining connection topology information, the main control chip first sends topology discovery messages to adjacent chips through various communication interfaces. These messages contain the source chip identifier and a hop count counter. After receiving the discovery message, each chip node encapsulates its own chip identifier, communication interface type, connection status, and other information into a response message and returns it. Simultaneously, it forwards the discovery message to other adjacent nodes and increments the hop count counter. The main control chip analyzes the collected response messages to obtain the complete chip connection relationships, communication interface parameters, and network topology. When constructing the inter-chip communication network based on the acquired topology information, the system first calculates the importance weight of each chip node based on the number and quality of connections, with nodes having more connections and higher communication quality receiving greater weight. Then, it evaluates transmission efficiency based on the length of the connection path and the number of relay nodes, with shorter paths and fewer relays resulting in higher efficiency. The system identifies key chips based on importance weights and transmission efficiency; these key chips are typically located at the intersection of multiple high-efficiency paths. Finally, based on the key chips and topology connections, an inter-chip communication network with backbone and branch paths is constructed. The backbone connects key chips to form a high-speed transmission backbone, while the branch paths ensure full network coverage. This inter-chip communication network provides a reliable foundation for subsequent path calculation and data transmission, enabling firmware data to reach any target chip via serial transmission. It achieves IAP upgrade capabilities even for devices without direct external interface chips, addressing the complex chip interconnection structure within the device and providing reliable network support for subsequent firmware upgrade transmission.

[0025] As an optional embodiment, the step of constructing an inter-chip communication network based on topology information may further include the following steps: Step 101: Based on the number and quality of connections of each chip node in the topology information, calculate the importance weight of each chip node in the topology.

[0026] Specifically, in the process of building an inter-chip communication network, due to the different status and role of different chip nodes in the network, some nodes have complex connection relationships and high communication quality, playing a key hub role in data transmission, while some nodes are relatively isolated or have limited communication capabilities. Therefore, it is necessary to calculate the importance weight of each chip node in the topology based on the number and quality of connections of each chip node in the topology information, so as to prioritize the selection of important nodes to build a stable communication network.

[0027] The system first counts the number of connections for each chip node, i.e., the number of adjacent chip nodes directly connected to that node. The number of connections reflects the node's connectivity; a node with more connections has a greater influence in the network. Next, the system evaluates the connection quality of each chip node. Connection quality is comprehensively evaluated using multiple parameters, including the communication bandwidth, signal strength, historical communication success rate, and response latency of each connection interface. The system obtains the maximum transmission rate of each connection interface as the bandwidth parameter, measures signal strength and response latency by sending test messages, and simultaneously calculates the data packet success rate during historical communication as the communication success rate. For each chip node, the system calculates a weighted average of the quality parameters of all its connection interfaces to obtain the overall connection quality score for that node. After obtaining the number of connections and connection quality parameters, the system uses a weighted calculation method to calculate the importance weight. The specific formula is: importance weight equals the number of connections multiplied by the connection number weight coefficient plus the connection quality score multiplied by the connection quality weight coefficient. The connection number weight coefficient and connection quality weight coefficient are set according to the actual application scenario; typically, the connection number weight coefficient is set to 0.6, and the connection quality weight coefficient is set to 0.4, reflecting that the importance of connection quantity is slightly higher than connection quality.

[0028] Step 102: Evaluate the transmission efficiency of each connection path based on the length of the connection path and the number of relay nodes in the topology information.

[0029] Specifically, in inter-chip communication networks, different connection paths have different transmission characteristics. Path length and the number of relay nodes directly affect the efficiency and reliability of data transmission. Therefore, it is necessary to evaluate the transmission efficiency of each connection path based on the length of the connection path and the number of relay nodes in the topology information. First, the length of each connection path is calculated. The length of a connection path is calculated by accumulating the transmission delays of each segment of the path. The transmission delay of each segment is equal to the data packet size divided by the transmission bandwidth of that segment. For a complete connection path, the system traverses all connection segments on the path, accumulates the transmission delays of each segment, and obtains the total transmission delay of the entire path as the path length indicator. At the same time, the system counts the number of relay nodes on each connection path, that is, the number of all intermediate nodes on the path excluding the source node and the destination node. The number of relay nodes reflects the complexity of data transmission. Each additional relay node adds one data processing and forwarding operation, introducing additional processing delays and transmission risks. After obtaining the path length and the number of relay nodes, the system calculates a transmission efficiency score. The transmission efficiency score uses a comprehensive evaluation method, specifically the formula: Transmission efficiency score equals baseline efficiency score minus path length penalty score minus relay node penalty score. The baseline efficiency score is set to 100 points, the path length penalty score equals the total path transmission delay multiplied by a delay penalty coefficient, and the relay node penalty score equals the number of relay nodes multiplied by a node penalty coefficient. The delay penalty coefficient is typically set to 10, and the node penalty coefficient is typically set to 5. This setting reasonably balances the impact of path length and relay complexity on transmission efficiency.

[0030] Step 103: Determine the key chips from the topology information based on importance weight and transmission efficiency.

[0031] Specifically, the system first establishes a candidate list of key chips, including chip nodes whose importance weight exceeds a preset threshold. The preset threshold is determined based on network scale and performance requirements, typically set to 1.2 times the average importance weight of all nodes, thus filtering out nodes with significantly higher-than-average importance. Next, the system analyzes the distribution of candidate chip nodes in efficient transmission paths, counting the frequency with which each candidate node appears as a relay node in the top 20% of transmission efficiency paths. Nodes with high frequency of appearance indicate that they play a crucial role in multiple efficient paths, exhibiting stronger network hub characteristics. Next, the system calculates the comprehensive score of the candidate chips, which equals the importance weight multiplied by the importance weight coefficient plus the path frequency multiplied by the path frequency coefficient. The importance weight coefficient is typically set to 0.7, and the path frequency coefficient is typically set to 0.3; this weighting distribution considers both the node's own importance and its actual role in network transmission. The system sorts the candidate chips according to their comprehensive scores and selects the chips with the highest comprehensive scores as key chips. The number of critical chips is determined based on the network size, typically ranging from 10% to 20% of the total number of nodes. This balances ensuring the stability of the network backbone with avoiding excessive complexity. After determining the critical chips, the system also needs to verify the connectivity between them to ensure they can form connected subnetworks. If connectivity issues are found between critical chips, the system will adjust the selection of critical chips accordingly, adding necessary bridging nodes.

[0032] Step 104: Based on the key chips and topology connections, construct an inter-chip communication network with trunk paths and branch paths.

[0033] Specifically, the system first constructs a backbone path network. The backbone path construction uses key chips as core nodes, and the system identifies the connection path with the highest transmission efficiency among the key chips as the backbone path. The system employs a shortest path algorithm, using the reciprocal of the transmission efficiency score as the path weight, to calculate the optimal connection path between any two key chips. For each candidate path, the system calculates the sum of the weights of all connection segments on the path and selects the path with the smallest total weight as the backbone path between the two key chips. In this way, the system establishes backbone path connections among all key chips, forming a backbone path network. The backbone path network features high bandwidth and low latency, capable of handling most firmware data transmission tasks. Next, the system constructs a branch path network. The role of branch paths is to extend the backbone paths to various ordinary chip nodes, ensuring comprehensive network coverage. For each non-key chip node, the system finds the nearest key chip as the access point, and then calculates the optimal connection path from that key chip to the non-key chip as the branch path. The calculation of branch paths also uses the shortest path algorithm, using the reciprocal of the transmission efficiency score as the path weight. When constructing branch paths, the system also considers load balancing to prevent excessive load on any single critical chip due to too many branch paths. Specifically, the system counts the number of branch paths connected to each critical chip. When the number of branch paths for a critical chip exceeds a preset limit, the system allocates new non-critical chip nodes to other critical chips with lighter loads. The upper limit for the number of branch paths is typically set to 1.5 times the total number of nodes divided by the number of critical chips, thus ensuring a relatively even distribution of network load.

[0034] Step 20: Calculate the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network, and establish a dynamic routing table.

[0035] Specifically, in the process of multi-chip cascaded IAP upgrade, there are multiple optional paths from the main control chip to each chip to be upgraded in the inter-chip communication network. The transmission efficiency and reliability of different paths vary significantly. If the transmission path is selected arbitrarily, the upgrade data transmission may be slow or fail. Therefore, it is necessary to calculate the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network and establish a dynamic routing table to manage and maintain these path information.

[0036] The system first identifies all chips requiring IAP upgrades and obtains their node identifiers and location information in the inter-chip communication network. Then, using an improved Dijkstra's shortest path algorithm with transmission efficiency scores as path weights, the system calculates the optimal transmission path from the main control chip to each chip to be upgraded. During path calculation, the algorithm traverses all reachable paths in the inter-chip communication network, comprehensively considering factors such as path length, number of relay nodes, node importance weights, and connection quality, selecting the path with the best overall performance as the optimal transmission path. For each optimal transmission path, the system records the complete path node sequence, total transmission delay, transmission efficiency score, and path reliability index. Based on the calculated optimal transmission path information, the system establishes a dynamic routing table. The dynamic routing table includes fields such as source chip identifier, destination chip identifier, path node sequence, path transmission efficiency score, path status identifier, and path update timestamp, enabling rapid lookup of the optimal path between any pair of chips. The system also establishes a real-time update mechanism for the dynamic routing table; when network topology changes or path performance degradation are detected, the affected paths are automatically recalculated and routing table entries are updated.

[0037] As an optional embodiment, the step of calculating the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network and establishing a dynamic routing table may further include the following steps: Step 201: Detect all candidate main control chips with external communication interfaces in the multi-chip device, and obtain the processing performance parameters and storage capacity parameters of the candidate main control chips.

[0038] Specifically, in the IAP upgrade system of multi-chip devices, the main control chip undertakes the core tasks of receiving upgrade instructions from the host computer, coordinating the entire upgrade process, and managing data transmission. If the selected main control chip has insufficient processing power or limited storage capacity, it will lead to a slow upgrade process or even failure. Therefore, it is necessary to test all candidate main control chips with external communication interfaces in the multi-chip device.

[0039] The system first scans all chip nodes in the multi-chip device, identifying chips with external communication interfaces by querying their hardware configuration information and interface status. These external communication interfaces include USB, Ethernet, serial ports, CAN bus interfaces, and other types capable of direct communication with a host computer. The system checks the interface configuration registers and driver status of each chip to confirm interface availability and communication capabilities. For each detected candidate controller chip, the system obtains its processing performance parameters, including key indicators such as CPU frequency, instruction execution speed, memory bandwidth, and floating-point arithmetic capability. The system obtains the CPU frequency by reading the chip's performance counters and configuration registers, measures instruction execution speed by executing standard test programs, and evaluates memory bandwidth through memory read / write tests. Simultaneously, the system obtains the storage capacity parameters of the candidate controller chips, including RAM capacity, Flash capacity, cache size, and available storage space. The system obtains total capacity information by querying the memory management unit and storage controller, and queries available storage space through the file system interface.

[0040] Step 202: Perform a weighted calculation based on processing performance parameters and storage capacity parameters, and select the candidate main control chip with the highest weighted value and which has established a communication connection with the host computer as the main control chip.

[0041] Specifically, after obtaining the performance parameters of each candidate master control chip, due to differences in processing power and storage resources among the chips, and the need to ensure that the selected chip has established a stable communication connection with the host computer, a weighted calculation based on processing performance parameters and storage capacity parameters is required. The candidate master control chip with the highest weighted value and already established a communication connection with the host computer is selected as the master control chip. In the specific implementation of the master control chip selection process, the system first standardizes the processing performance parameters and storage capacity parameters of the candidate master control chips, dividing each chip's CPU frequency, memory bandwidth, RAM capacity, etc., by the maximum value of the same type of parameter. Then, the system performs a weighted calculation, with the comprehensive score equal to the processing performance score multiplied by 0.6 plus the storage capacity score multiplied by 0.4. The system verifies the communication connection status of each candidate master control chip by sending heartbeat messages to the host computer, and selects the chip with the highest comprehensive score from the candidate master control chips with established communication connections as the master control chip.

[0042] Step 203: Obtain the communication bandwidth parameters and response latency parameters of each chip node in the inter-chip communication network.

[0043] Specifically, in the implementation process of acquiring communication parameters, the system first obtains the communication bandwidth parameters of each chip node. For each chip node, the system queries the hardware specifications of its communication interface to obtain the theoretical maximum transmission rate as the bandwidth limit. Then, the system obtains the effective bandwidth through actual testing. Specifically, the system sends fixed-size test data packets between adjacent chip nodes, measures the actual data transmission time, and calculates the effective transmission rate. The system performs multiple tests continuously and takes the average value to eliminate the impact of instantaneous network fluctuations. For different types of communication interfaces, the system adopts corresponding testing methods. For example, for the SPI interface, it measures the clock frequency and data bit width; for the I2C interface, it measures the bus speed and data throughput. Simultaneously, the system acquires the response latency parameters of each chip node by sending request messages and measuring the time interval between receiving response messages to calculate the response latency. The system sends standard messages to each chip node, records the sending timestamp, and records the receiving timestamp when the corresponding response message is received. The difference between the two timestamps is the response latency. To obtain accurate latency data, the system performs multiple rounds of testing and statistically analyzes parameters such as average response latency, maximum response latency, and latency jitter.

[0044] Step 204: Calculate the data transmission time between adjacent chip nodes based on the communication bandwidth parameters and response delay parameters.

[0045] Specifically, in the implementation of data transmission time calculation, the system first determines the size of the standard data packet, typically set to 1024 bytes, as the calculation baseline. For each pair of adjacent chip nodes, the system calculates the pure data transmission time based on the communication bandwidth parameters between them. The pure data transmission time equals the data packet size divided by the effective communication bandwidth. For example, if the data packet size is 1024 bytes and the effective communication bandwidth is 100KB / s, the pure data transmission time is 10.24 milliseconds. Then, the system considers protocol overhead and processing latency. Different communication protocols have different frame headers, checksums, and acknowledgment mechanisms, all of which add extra transmission time. The system adds the corresponding protocol overhead time based on the communication protocol type, typically 10% to 20% of the pure data transmission time. Next, the system incorporates the response latency parameter into the calculation, because in actual communication, the sending node needs to wait for the receiving node's acknowledgment response before sending the next data packet. The final data transmission time equals the pure data transmission time plus the protocol overhead time plus the response latency parameter. The system performs this calculation for each pair of adjacent chip nodes in the inter-chip communication network, establishing a complete transmission time matrix.

[0046] Step 205: Based on data transmission time and historical communication failure records of all chip nodes, calculate the reliability weight of all transmission paths between the main control chip and each chip to be upgraded.

[0047] Specifically, the system first queries the fault log database for historical communication fault records for each chip node, including the number of communication timeouts and data packet losses, and calculates the node failure rate as the number of failures divided by the total number of communications. For each transmission path, the system calculates the path success rate as the product of the success rates of all nodes on the path, where the node success rate equals 1 minus the node failure rate. Then, the system calculates the reliability weight, which is equal to the path success rate multiplied by 0.7 plus the transmission efficiency index multiplied by 0.3.

[0048] Step 206: Using the shortest path algorithm, with reliability weight as the path cost, calculate the optimal transmission path from the main control chip to each chip to be upgraded, and record the optimal transmission path, communication bandwidth parameters, and response delay parameters in the dynamic routing table.

[0049] Specifically, this application employs an improved Dijkstra's shortest path algorithm for path optimization. The system uses the reciprocal of the reliability weight as the path cost; paths with higher reliability weights have lower costs, and the algorithm prioritizes paths with lower costs. Starting with the main control chip, the algorithm gradually expands to adjacent nodes, maintaining a distance table to record the shortest path cost from the main control chip to each node. In each iteration, the algorithm selects the node with the smallest current distance that has not been visited, updates the distance values ​​of its adjacent nodes, and if the path cost to an adjacent node through the current node is smaller, then the shortest path to that adjacent node is updated. The algorithm repeats this process until the optimal transmission path from the main control chip to all chips to be upgraded is found. For each calculated optimal transmission path, the system records complete path information, including the path node sequence, total path cost, expected transmission time, and other key parameters. Then, the system establishes a dynamic routing table, which uses a hash table structure, with the combination of the source chip identifier and the target chip identifier as the key, and the path information as the data item. For each routing table entry, the system records the complete node sequence of the optimal transmission path, as well as the communication bandwidth and response latency parameters of each segment connected along the path, to facilitate parameter adjustment and performance monitoring during data transmission. The system also adds a timestamp and a status flag to each routing table entry; the timestamp records the time the path was calculated or updated, and the status flag indicates whether the path is available.

[0050] Step 30: Receive the IAP upgrade command sent by the host computer, parse the target chip list and firmware version information in the IAP upgrade command, and send the control command to enter IAP mode to each target chip to be upgraded in the target chip list.

[0051] Specifically, in a multi-chip cascaded IAP upgrade system, the host computer needs to send IAP upgrade instructions containing specific upgrade task information to the main control chip. The main control chip must accurately receive and parse these instructions to determine the target chip to be upgraded and the corresponding firmware version. Furthermore, the target chip needs to be switched to IAP mode before subsequent firmware burning operations can be performed.

[0052] The main control chip continuously monitors data packets from the host computer via an external communication interface. When a data packet conforming to the IAP upgrade instruction format is detected, the system verifies the packet's frame header identifier and checksum to confirm its integrity. During parsing, the system extracts the target chip list from the instruction data, including the unique chip ID, chip type code, and node address of each target chip to be upgraded. Simultaneously, it parses the firmware version information, including the new firmware version number, firmware file size, and firmware checksum. The system verifies whether the chips in the target chip list exist in the inter-chip communication network and matches the firmware version information with the target chips. Next, the system finds the optimal transmission path for each target chip to be upgraded based on the dynamic routing table, constructs an IAP mode entry control instruction containing the instruction type, target chip identifier, IAP startup address, and security authentication information, and sends it to each target chip to be upgraded through the optimal transmission path. After receiving the control instruction, the target chip to be upgraded verifies the security authentication information, performs operations such as saving the current running state, jumping to the IAP startup code, and initializing the IAP running environment. Upon successfully entering IAP mode, it sends a confirmation response to the main control chip.

[0053] Step 40: Divide the firmware data corresponding to the firmware version information into multiple data packets, and transmit the data packets in series to each target chip to be upgraded according to the optimal transmission path in the dynamic routing table.

[0054] Specifically, in a multi-chip cascaded IAP upgrade system, firmware data is typically large, and the target chips to be upgraded are distributed across different network nodes. Transmitting the complete firmware data as a single data block would lead to low transmission efficiency and a high risk of transmission errors. Therefore, it is necessary to segment the firmware data corresponding to the firmware version information into multiple data packets. The system first determines the standard size of the data packet to be 1024 bytes based on the maximum transmission unit of each communication interface in the inter-chip communication network, and then segments the firmware data corresponding to each target chip to be upgraded sequentially according to this standard size. A header containing the target chip identifier, data packet sequence number, total number of data packets, data length, and checksum is added to each data packet, and consecutive sequence numbers are assigned to all data packets for the same target chip to be upgraded. During data packet transmission, the system queries the dynamic routing table to find the optimal transmission path from the master control chip to each target chip to be upgraded, obtaining the path node sequence. Data packets are forwarded hop-by-hop from the master control chip according to the path node sequence. After receiving the data packet, the relay chip node determines the next hop node based on the target chip identifier in the packet header and forwards it. Each relay node performs checksum verification before forwarding to ensure data integrity, and requests retransmission if an error is detected. The system employs a parallel transmission strategy to simultaneously send data packets to multiple target chips to be upgraded. After receiving the data packets, the target chips to be upgraded send an acknowledgment message to the main control chip. The main control chip determines the transmission status based on the acknowledgment message and retransmits any unacknowledged data packets.

[0055] As an optional embodiment, the step of dividing the firmware data corresponding to the firmware version information into multiple data packets may further include the following steps: Step 301: Obtain the minimum communication buffer capacity and the maximum number of bytes transmitted in a single transaction in the inter-chip communication network.

[0056] Specifically, the system first scans all chip nodes in the inter-chip communication network and obtains the communication buffer capacity information by querying the hardware configuration registers of each chip. The communication buffer capacity includes the receive buffer size and the transmit buffer size. The system reads the buffer control register of each chip node, extracts the buffer capacity parameters, and records them in the node information table. Then, the system compares the communication buffer capacities of all chip nodes and selects the minimum value as the minimum communication buffer capacity. Simultaneously, the system obtains the maximum number of bytes that can be transmitted in a single transmission for each communication interface, including the maximum transmission capacity of different types of interfaces such as SPI, I2C, and CAN bus. The system queries the transmission control register of each interface, reads the maximum transmission length limit parameter, compares the transmission capabilities of all interfaces, and selects the minimum value as the maximum number of bytes that can be transmitted in a single transmission.

[0057] Step 302: Determine the data packet size based on the minimum communication buffer capacity and the maximum number of bytes transmitted in a single transmission.

[0058] Specifically, the system first analyzes the limitation of the minimum communication buffer capacity on the data packet size. Considering that data packets need to be temporarily stored and processed in the buffer, the data packet size should be less than 80% of the minimum communication buffer capacity to reserve sufficient buffer space for protocol processing and error recovery. Then, the system analyzes the limitation of the maximum number of bytes transmitted in a single transmission. The actual transmission size of the data packet includes the data content and header information; therefore, the data content size should be less than the maximum number of bytes transmitted in a single transmission minus the header size. The system calculates the header size to be typically 32 bytes, containing an incrementing sequence number, the target chip identifier to be upgraded, and the data packet checksum. Finally, the system selects the smaller value between the minimum communication buffer capacity limit and the maximum number of bytes transmitted in a single transmission limit, and then subtracts a safety margin of 64 bytes to obtain the final data packet size.

[0059] Step 303: Divide the firmware data corresponding to the firmware version information into segments according to the data packet size, and assign an incrementing sequence number to each data packet.

[0060] Specifically, after determining the data packet size, the complete firmware data needs to be segmented according to a unified rule, and an ordered data packet sequence needs to be established so that the receiving end can correctly reassemble the firmware data. Therefore, the firmware data corresponding to the firmware version information needs to be segmented sequentially according to the data packet size, and each data packet is assigned an incrementing sequence number. The system first reads the firmware data corresponding to the target chip to be upgraded and calculates the total length of the firmware data. Then, the system calculates the total number of data packets to be segmented based on the determined data packet size, which is equal to the total length of the firmware data divided by the data packet size and rounded up. During the segmentation process, the system starts from the beginning of the firmware data and extracts the data content sequentially according to the data packet size. The first data packet contains data from offset 0 to the data packet size, the second data packet contains data from the data packet size to twice the data packet size, and so on. For the last data packet, if the remaining data length is less than the standard data packet size, the data packet only contains the remaining data content. The system assigns an incrementing sequence number to each data packet, numbering it consecutively starting from 1, to ensure that the receiving end can reassemble the firmware data in the correct order.

[0061] Step 304: Add a data packet header to each data packet containing an incrementing sequence number, the target chip identifier to be upgraded, and a data packet checksum.

[0062] Specifically, the system constructs a header for each data packet, which uses a fixed format and contains multiple fields. The incrementing sequence number field occupies 4 bytes and records the packet's position within the entire firmware data. The target chip identifier field occupies 8 bytes and contains the target chip's unique ID and chip type code, used for network routing and target identification. The data packet checksum field occupies 4 bytes and uses the CRC32 algorithm to calculate the checksum of the data packet content. The system also adds a data length field and a total packet number field to the header, recording the actual data length of the current data packet and the total number of data packets corresponding to this firmware, respectively. During header construction, the system converts the incrementing sequence number to network byte order and writes it to the corresponding field, extracts the target chip identifier from the chip information table and writes it to the identifier field, and calculates the CRC32 checksum for the data packet content and writes it to the checksum field.

[0063] Step 305: Set the packet forwarding flag based on the target chip identifier in the packet header. The packet forwarding flag is used to indicate the number of packet forwardings.

[0064] Specifically, the system uses a previously established dynamic routing table to query the optimal transmission path from the main control chip to each target chip to be upgraded, and counts the number of nodes in the path. The number of packet forwardings equals the number of nodes in the path minus 1, i.e., the number of relay nodes the packet needs to pass through. For each packet, the system determines the corresponding transmission path based on the target chip identifier in the packet header, and then sets the packet forwarding flag to the number of forwardings for that path. The packet forwarding flag occupies 2 bytes of space in the packet header and records the number of forwardings in numerical form. The system sets the forwarding flag before the packet is sent, relay nodes read and update the flag when forwarding the packet, and the target node can verify the correctness of the transmission path by using this flag when receiving the packet.

[0065] Step 306: Prioritize data packets according to their forwarding flags; the more times they are forwarded, the higher their priority.

[0066] Specifically, the system establishes a data packet sending queue and adds all data packets to be sent. During the sorting process, the system reads the forwarding flag of each data packet to obtain the corresponding forwarding count. The system uses a priority sorting algorithm, with the forwarding count as the sorting key; data packets with more forwarding counts are placed at the front of the queue and have a higher sending priority. For data packets with the same forwarding count, the system performs a secondary sorting according to the ascending sequence number to ensure that data packets targeting the same chip are sent in the correct order. After sorting, the system sends data packets in priority order, prioritizing data packets that need to pass through more relay nodes to reduce their waiting time in the network.

[0067] As an optional embodiment, the step of transmitting data packets in series to each target chip to be upgraded according to the optimal transmission path in the dynamic routing table may further include the following steps: Step 401: Based on the optimal transmission path in the dynamic routing table, divide the multiple target cores to be upgraded into multiple serial transmission branches.

[0068] Specifically, the system first analyzes the optimal transmission path from the main control chip to each target chip to be upgraded in the dynamic routing table, extracting the node sequence information for each path. Then, the system identifies common node segments between paths, expanding outwards from the main control chip to find the first fork point—the node where multiple paths begin to diverge. Based on the fork point location, the system groups target chips to be upgraded with the same initial path segment into the same serial transmission branch. Each serial transmission branch contains a main path originating from the main control chip and multiple target chips to be upgraded connected to that main path. The system assigns a unique identifier to each serial transmission branch, recording the number, positional order, and corresponding path information of the target chips to be upgraded within the branch. During the partitioning process, the system prioritizes assigning target chips to be upgraded that are geographically close or have similar communication delays to the same branch to improve transmission coordination.

[0069] Step 402: Obtain the historical fluctuation range of the communication bandwidth parameters and response delay parameters of the first target chip to be upgraded within each serial transmission branch.

[0070] Specifically, the system queries the historical communication logs of the inter-chip communication network, extracting the communication performance data of the first target chip to be upgraded in each serial transmission branch over a past period. Communication bandwidth parameters include actual transmission rate, data throughput, and concurrent processing capability. The system statistically analyzes the changes in these parameters over different time periods, calculating the maximum, minimum, and average values. Response latency parameters include packet processing time, forwarding delay, and acknowledgment response time; the system similarly statistically analyzes the historical changes in these parameters. Based on the statistical data, the system calculates the historical fluctuation range of the communication bandwidth parameter, which is equal to the difference between the maximum and minimum values, as well as the historical fluctuation range of the response latency parameter. The system also analyzes the periodicity and trend of parameter fluctuations, identifying regular factors that may affect transmission performance.

[0071] Step 403: Based on the historical fluctuation range, calculate the upper limit of the transmission capacity and the fluctuation coefficient of the first target chip to be upgraded in each serial transmission branch.

[0072] Specifically, the system first calculates the transmission capacity limit based on the historical maximum value of the communication bandwidth parameter and the historical minimum value of the response delay parameter. The transmission capacity limit represents the maximum data transmission volume the chip can handle under ideal conditions, calculated as the historical maximum value of the communication bandwidth divided by the historical minimum value of the response delay, multiplied by a safety factor of 0.8. Next, the system calculates the fluctuation coefficient, reflecting the stability of the chip's communication performance. The fluctuation coefficient equals the historical fluctuation range of the communication bandwidth parameter divided by the historical average value of the communication bandwidth parameter, plus the result of the historical fluctuation range of the response delay parameter divided by the historical average value of the response delay parameter. A larger fluctuation coefficient indicates more unstable communication performance of the chip, and a higher probability of performance degradation during transmission. The system uses the transmission capacity limit and fluctuation coefficient as key performance indicators for this cascaded transmission branch to guide subsequent data packet allocation and transmission scheduling.

[0073] Step 404: Based on the transmission capacity limit and fluctuation coefficient, the data packets will be divided into a base data packet group and a compensation data packet group according to the increasing sequence number of the data packets.

[0074] Specifically, after determining the transmission capacity of each cascaded transmission branch, data packets need to be allocated reasonably to ensure transmission reliability and efficiency. Considering potential data packet loss and performance fluctuations during network transmission, a primary / backup transmission strategy is required. Therefore, based on the transmission capacity limit and fluctuation coefficient, data packets are divided into a base data packet group and a compensation data packet group according to their ascending sequence number. The system first calculates the size of the base data packet group based on the transmission capacity limit of each cascaded transmission branch. The base data packet group contains the main data packets arranged in ascending sequence number, and its quantity equals the transmission capacity limit multiplied by the time window length. Then, the system calculates the size of the compensation data packet group based on the fluctuation coefficient. The compensation data packet group is used to cope with potential data packet loss during transmission, and its size is equal to the base data packet group size multiplied by the fluctuation coefficient and then multiplied by the redundancy coefficient of 1.2. During data packet partitioning, the system sorts all data packets according to their ascending sequence number, allocating the first part to the base data packet group and the latter part to the compensation data packet group. For each cascaded transmission branch, the system ensures that the base data packet group contains all the critical data packets required by all target chips to be upgraded in that branch, and the compensation data packet group contains backup data packets for error recovery and retransmission.

[0075] Step 405: Send the baseline data packet group to the first target chip to be upgraded in each serial transmission branch. The first target chip to be upgraded receives and forwards the baseline data packet group to the next target chip to be upgraded in the branch. At the same time as the baseline data packet group is transmitted, a compensation data packet group is sent to the first target chip to be upgraded in the serial transmission branch to supplement the data packets lost by each target chip to be upgraded during the reception of the baseline data packet group.

[0076] Specifically, after the data packets are divided, an efficient parallel transmission strategy needs to be implemented to ensure the timely transmission of the main data and provide real-time error recovery capabilities. Therefore, the baseline data packet group needs to be sent to the first target chip to be upgraded in each serial transmission branch. The first target chip to be upgraded receives and forwards the baseline data packet group to the next target chip to be upgraded in the branch. At the same time as the baseline data packet group is transmitted, the compensation data packet group is sent to the first target chip to be upgraded in the serial transmission branch to supplement the data packets lost by each target chip to be upgraded during the reception of the baseline data packet group.

[0077] The system initiates a parallel transmission process, first sending a baseline data packet set to the first target chip to be upgraded in each serial transmission branch. Upon receiving the baseline data packet set, the first target chip to be upgraded determines, based on the target chip identifier in the packet header, which packets need local processing and which need to be forwarded to the next target chip to be upgraded within the branch. The forwarding process employs a pipelined approach, with the chip performing forwarding processing simultaneously with receiving data packets, reducing transmission latency. During the transmission of the baseline data packet set, the system monitors the reception acknowledgment information of each target chip to be upgraded, identifying lost or corrupted data packets. Simultaneously, the system initiates a compensation transmission thread, sending the corresponding data packets from the compensation data packet set to the appropriate serial transmission branch, prioritizing the delivery of compensation data packets to the target chip to be upgraded that experienced data packet loss. The system maintains a transmission status table, tracking the transmission status and acknowledgment of each data packet in real time.

[0078] For example, please see Figure 2 This diagram illustrates the data packet transmission process for multi-chip cascaded IAP upgrades provided in this application embodiment. It comprehensively demonstrates the complete implementation process of the cascaded transmission mechanism based on a dynamic routing table. The process begins at the host computer and establishes a cascaded transmission link through multiple levels of MCU nodes. Each node uses a "flag bit is MCUx" judgment logic to achieve intelligent routing distribution, reflecting the core algorithm in the dynamic routing table that selects the optimal path based on the target chip identifier. When the judgment result is "yes," the node performs the "acquire upgrade firmware package" operation to complete firmware reception; when the judgment result is "no," it performs the "forward" operation to pass the data packet to the next level node, forming a flexible and efficient cascaded transmission network. The "response processing status" and "response processing request" mechanisms in the entire process establish a two-way communication confirmation system, which not only ensures the reliability of data packet transmission but also provides technical support for anomaly detection, status monitoring, and retransmission control. Through distributed routing control and adaptive transmission strategies, efficient and reliable data distribution is achieved during the multi-chip IAP upgrade process, ensuring both transmission efficiency and the security and stability of the entire upgrade process.

[0079] As an optional embodiment, the process of transmitting data packets in series to each target chip to be upgraded according to the optimal transmission path in the dynamic routing table may also include the following steps: Step 501: Monitor the data packet reception status of each target chip to be upgraded in each serial transmission branch.

[0080] Specifically, the system establishes a data packet reception status monitoring mechanism, creating a reception status tracking table for each target chip to be upgraded, recording information on all data packets sent to that chip. During monitoring, the system requires each target chip to be upgraded to send an acknowledgment message after receiving a data packet. The acknowledgment message includes the data packet's incremented sequence number, reception timestamp, and data integrity verification result. The system maintains a timer queue, setting a timeout period for each sent data packet, typically three times the chip's response latency parameter. Within the waiting time, if an acknowledgment message is received for the corresponding data packet, the system marks the data packet's reception status as normal; if no acknowledgment message is received within the timeout period, it is marked as timed out; if an acknowledgment message with a verification error is received, it is marked as corrupted. The system also monitors the arrival time distribution of acknowledgment messages to identify abnormal delay patterns.

[0081] Step 502: When an abnormal chip to be upgraded is detected with an abnormal data packet reception status, the data packet loss rate of the abnormal chip to be upgraded is calculated.

[0082] Specifically, the system first identifies target chips with abnormal reception status, classifying those marked as timeout, damaged, or experiencing continuous delays as abnormal chips to be upgraded. For each abnormal chip, the system counts the total number of data packets sent to the chip and the number of successfully received data packets within the current transmission cycle. The data packet loss rate is calculated as follows: Loss rate equals (total number of sent data packets minus the number of successfully received data packets) divided by the total number of sent data packets multiplied by 100%. The system also analyzes the temporal distribution characteristics of data packet loss to identify whether it is intermittent or persistent. For persistent loss, the system further analyzes the loss pattern to determine whether the loss is due to insufficient chip processing capacity, network congestion, or hardware failure. The system establishes a historical record of the loss rate, tracking the trend of the loss rate for each chip, providing reference data for subsequent adjustments to the transmission strategy.

[0083] Step 503: Based on the packet loss rate, adjust the ratio of the baseline packet group and the compensation packet group in the corresponding serial transmission branch.

[0084] Specifically, the system formulates an adjustment strategy based on the data packet loss rate of the abnormal chip to be upgraded. When the data packet loss rate is below 5%, the system judges it as a minor anomaly and increases the proportion of the compensation data packet group from the original 20% to 30%. When the data packet loss rate is between 5% and 15%, the system judges it as a moderate anomaly and increases the proportion of the compensation data packet group to 50%, while reducing the number of data packets in each batch in the baseline data packet group. When the data packet loss rate exceeds 15%, the system judges it as a severe anomaly, increases the proportion of the compensation data packet group to 70%, and enables a multi-redundancy transmission mode. During the adjustment process, the system recalculates the data packet allocation scheme of this cascaded transmission branch to ensure that the compensation data packet group can cover all potentially lost data packets. The system also considers the transmission needs of other normal chips in this branch to avoid the transmission efficiency of the entire branch being affected by a single abnormal chip.

[0085] Step 504: Set the data packet retransmission waiting time according to the response delay parameters of the abnormal chip to be upgraded.

[0086] Specifically, the system first analyzes the historical response latency parameters of the chip undergoing upgrade, including the average response time, maximum response time, and standard deviation of response time under normal conditions. Considering the potential decrease in the chip's processing capacity under abnormal conditions, the system sets the packet retransmission waiting time to five times the chip's normal average response time plus twice the standard deviation. This setting takes into account the longer processing time the chip may need under abnormal conditions while also allowing sufficient margin for network transmission latency. Different waiting time coefficients are used for different types of anomalies: a larger coefficient for anomalies caused by insufficient processing capacity, a medium coefficient for anomalies caused by unstable network connections, and a smaller coefficient for intermittent errors. The system also establishes a dynamic adjustment mechanism to adjust the waiting time based on the actual response during retransmission, gradually optimizing the retransmission strategy.

[0087] Step 505: If no confirmation of receipt is received from the abnormal chip to be upgraded during the data packet retransmission waiting time, the baseline data packet group and the compensation data packet group are retransmitted according to the adjusted ratio.

[0088] Specifically, the system starts a retransmission waiting timer, continuously listening for confirmation messages from the abnormal chip awaiting upgrade during the waiting time. If a confirmation message is received within the waiting time, the system verifies the integrity of the confirmation message and updates the chip's receiving status, then continues the normal transmission process. If no confirmation message is received by the end of the waiting time, the system determines that a retransmission operation is required. During the retransmission process, the system reorganizes the data packets according to the adjusted ratio in step 503, increasing the number of compensation data packet groups and reducing the batch size of the base data packet group. The system prioritizes retransmitting lost critical data packets, and then sends supplementary redundant data packets. During retransmission, the system adopts a more conservative sending strategy, reducing the sending rate and increasing the time interval between data packets to avoid putting excessive processing pressure on the abnormal chip. The system also establishes a retransmission count limit mechanism. If three consecutive retransmissions fail, the abnormal chip awaiting upgrade is marked as a serious fault state, and the fault handling process is initiated.

[0089] Step 50: After each target chip to be upgraded has received the firmware, perform firmware verification, write the new firmware that has passed the verification into the program storage area of ​​each target chip to be upgraded, and perform the firmware update operation.

[0090] Specifically, in a multi-chip cascaded IAP upgrade system, the firmware data received by each target chip to be upgraded may be erroneous or corrupted during transmission. Directly writing unverified firmware into the program storage area would cause the chip to malfunction. Therefore, firmware verification is necessary after each target chip receives the firmware. Each target chip first reorders the received data packets according to the incrementing sequence number in the packet header, checks if all expected data packets have been received, and then concatenates the firmware data in the data packets according to the incrementing sequence number to reconstruct a complete firmware file. During firmware verification, the system calculates the CRC32 checksum of the reconstructed firmware and compares it with the original firmware checksum to verify the accuracy of data transmission. Simultaneously, it verifies the firmware's digital signature to confirm the firmware's legality and checks the firmware version information and hardware compatibility identifier to ensure compatibility with the target chip. After successful verification, the system backs up the original firmware in the current program storage area to the backup storage area and then erases the old firmware data in the program storage area. The firmware writing process employs a segmented writing strategy, dividing the new firmware into multiple write blocks according to the storage page size and writing them to the program storage area block by block. After each write block is completed, a read-back verification is performed immediately to ensure the correctness of the written data. After the write operation is complete, the system updates the firmware version information, boot address, and verification information to the firmware information area. During the firmware update operation, the system sets the chip restart flag and clears the cache and temporary data, then performs a soft reset to cause the chip to restart and automatically load the new firmware. After the new firmware boots, it performs a self-test to verify that all functional modules are working properly and sends an upgrade completion confirmation message to the main control chip.

[0091] For example, please see Figure 3 This is a flowchart illustrating the IAP upgrade process for a single target chip to be upgraded, provided in an embodiment of this application. Figure 3 This document details the complete internal processing of the target chip from receiving the upgrade command to completing the firmware update. The process begins with "connecting the device to prepare for upgrade," where the chip first sends a command to confirm the connection establishment, then "enters IAP focused mode" to switch to a dedicated firmware upgrade state. A status check to "check if IAP mode has been entered" ensures successful mode switching. In IAP mode, the chip performs a "get firmware package size" operation to obtain the total amount of firmware to be received, preparing for subsequent data reception and storage management. The "packet-based firmware transmission" step demonstrates the specific implementation of the data packet grouping transmission mechanism in this embodiment. The chip receives firmware data step by step according to a predetermined packetization strategy. The crucial "check if packet processing is complete" logic monitors the reception progress and checks integrity, ensuring all firmware data packets are correctly received. Once packet transmission is complete, the chip performs a "write upgrade information" operation to write the new firmware data to the program storage area. Finally, "rebooting the device and waiting for the bootloader program to process" completes the firmware switch and system restart. The entire process embodies the atomicity and reliability requirements of IAP upgrades. Through status queries, progress monitoring, and step-by-step processing, it ensures the security and success rate of the firmware upgrade process. It is the standard implementation of the single-chip upgrade process in the multi-chip serial IAP upgrade scheme of this application.

[0092] As an optional embodiment, the firmware verification step after each target chip to be upgraded has received the firmware may further include the following steps: Step 601: Reassemble all data packets received by each target chip to be upgraded into complete firmware according to their incrementing sequence numbers. Specifically, each target chip to be upgraded first establishes a management table for received data packets, recording the incrementing sequence number, data content, and reception status of each received data packet. The system scans all data packet records in the management table, checking the continuity of the incrementing sequence numbers and identifying any missing sequence numbers. If a missing sequence number is found, the system sends a data packet retransmission request to the main control chip, requesting the retransmission of the data packet with the missing sequence number. After confirming that all necessary data packets have been received, the system sorts the data packets in ascending order of their incrementing sequence numbers. During the reassembly process, the system sequentially extracts the firmware data content from each data packet and concatenates this data content into a continuous data stream according to the incrementing sequence number. During the concatenation process, the system verifies the data length and boundary information of each data packet to ensure the accuracy of the data concatenation. The final complete firmware data is stored in the temporary buffer area of ​​the target chip to be upgraded, awaiting subsequent verification and write operations.

[0093] Step 602: Calculate the checksum of the complete firmware and compare it with the firmware checksum carried in the IAP upgrade instruction.

[0094] Specifically, the system reads the reconstructed complete firmware data from the temporary cache area and calculates the checksum using the same verification algorithm as the original firmware. Standard verification algorithms such as CRC32 or MD5 are typically used to ensure the accuracy and reliability of the verification results. During the calculation, the system reads the firmware data block by block according to a fixed block size, performs verification calculations on each data block, and then accumulates the verification results of each data block to obtain the final checksum value. Simultaneously, the system extracts the original firmware checksum from the previously received IAP upgrade command. This checksum is the reference standard calculated and carried by the main control chip when sending the upgrade command. The system compares the calculated complete firmware checksum bit by bit with the firmware checksum in the IAP upgrade command to check if the two values ​​are exactly the same. The comparison process uses a secure comparison method to avoid security risks such as timing attacks.

[0095] Step 603: If the checksum matches the firmware check value, generate a firmware check pass flag.

[0096] Specifically, after confirming that the checksum and firmware checksum are completely consistent, the system sets a firmware verification pass flag in the control register of the target chip to be upgraded. This flag uses a hardware protection mechanism and can only be set if the verification is successful, preventing malicious tampering. Simultaneously, the system records the verification pass timestamp, firmware version information, and checksum in the chip's non-volatile storage area, forming a complete verification record. The system also generates a verification pass confirmation message, containing the unique identifier of the target chip to be upgraded, firmware version number, verification result, and operation timestamp. The confirmation message is sent to the main control chip for monitoring and management of the overall upgrade progress. The setting of the firmware verification pass flag triggers a state machine transition within the chip, putting the chip into a firmware write preparation state, preparing for subsequent program storage area write operations.

[0097] Step 604: If the checksum does not match the firmware check value, send a check failure message to the main control chip and request retransmission of firmware data.

[0098] Specifically, upon detecting a discrepancy between the checksum and the firmware checksum value, the system immediately halts the current firmware processing flow to prevent erroneous data from being written to the program storage area. The system analyzes the specific reasons for the checksum failure, comparing the difference patterns between the calculated checksum and the original firmware checksum value to preliminarily determine whether it's a single data packet error or a systemic transmission problem. Then, the system constructs a checksum failure message, including the target chip to be upgraded identifier, the calculated checksum value, the original firmware checksum value, error type analysis, and a retransmission request. This message is sent to the main control chip via the inter-chip communication network. Upon receiving this message, the main control chip re-evaluates the transmission strategy. Simultaneously, the system clears erroneous firmware data from the temporary buffer area, releases storage space, and resets the receiving state to prepare for receiving retransmitted firmware data. The system also logs the checksum failure event, including the failure time, error details, and handling measures, providing a reference for subsequent problem analysis and system optimization.

[0099] This application also provides a computer storage medium that can store multiple instructions. The instructions are adapted to be loaded and executed by a processor as described in the above embodiments of a multi-chip cascaded IAP upgrade method. For the specific execution process, please refer to the detailed description of the above embodiments, which will not be repeated here.

[0100] The following describes an electronic device for multi-chip cascaded IAP upgrade provided by an embodiment of this application. Figure 4 This is a schematic diagram of an exemplary hardware structure of an electronic device provided in an embodiment of this application.

[0101] In some embodiments, the multi-chip cascaded IAP upgrade electronic device is a computer device or includes a computer device within the multi-chip cascaded IAP upgrade electronic device. The computer device includes a processor, memory, and a network interface connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the computer device stores data. The network interface of the computer device is used to communicate with other external terminals or servers via a network connection. In some embodiments, the network interface can be a wired network interface; in some embodiments, the network interface can also be a wireless network interface. When the computer program is executed by the processor, it implements the methods described in the embodiments of this application.

[0102] Those skilled in the art will understand that Figure 4The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0103] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0104] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0105] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

Claims

1. A multi-chip cascaded IAP upgrade method, characterized in that, The method includes: Obtain the connection topology information of each chip in a multi-chip device, and construct an inter-chip communication network based on the topology information; Calculate the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network, and establish a dynamic routing table; Receive the IAP upgrade command sent by the host computer, parse the target chip list and firmware version information in the IAP upgrade command, and send the control command to enter IAP mode to each target chip to be upgraded in the target chip list; The firmware data corresponding to the firmware version information is divided into multiple data packets, and the data packets are transmitted in series to each of the target chips to be upgraded according to the optimal transmission path in the dynamic routing table. After each target chip to be upgraded receives the firmware, firmware verification is performed. The new firmware that passes the verification is written into the program storage area of ​​each target chip to be upgraded and the firmware update operation is executed.

2. The multi-chip cascaded IAP upgrade method according to claim 1, characterized in that, The construction of the inter-chip communication network based on the topology information includes: Based on the number and quality of connections of each chip node in the topology information, calculate the importance weight of each chip node in the topology; Based on the length of the connection path and the number of relay nodes in the topology information, the transmission efficiency of each connection path is evaluated. Based on the importance weights and the transmission efficiency, key chips are determined from the topology information; Based on the key chips and topological connections, an inter-chip communication network with trunk paths and branch paths is constructed.

3. The multi-chip cascaded IAP upgrade method according to claim 1, characterized in that, The step of calculating the optimal transmission path from the main control chip to each chip to be upgraded based on the inter-chip communication network and establishing a dynamic routing table includes: The system detects all candidate main control chips with external communication interfaces in a multi-chip device and obtains the processing performance parameters and storage capacity parameters of the candidate main control chips. Based on the processing performance parameters and storage capacity parameters, a weighted calculation is performed, and the candidate main control chip with the highest weighted value and which has established a communication connection with the host computer is selected as the main control chip. Obtain the communication bandwidth parameters and response delay parameters of each chip node in the inter-chip communication network; Calculate the data transmission time between adjacent chip nodes based on the communication bandwidth parameters and response delay parameters; Based on the data transmission time and the historical communication failure records of all chip nodes, calculate the reliability weight of all transmission paths between the main control chip and each chip to be upgraded. Using the shortest path algorithm, the reliability weight is used as the path cost to calculate the optimal transmission path from the main control chip to each chip to be upgraded, and the optimal transmission path, the communication bandwidth parameter, and the response delay parameter are recorded in the dynamic routing table.

4. The multi-chip cascaded IAP upgrade method according to claim 1, characterized in that, The step of dividing the firmware data corresponding to the firmware version information into multiple data packets includes: Obtain the minimum communication buffer capacity and the maximum number of bytes transmitted in a single operation in the inter-chip communication network; The data packet size is determined based on the minimum communication buffer capacity and the maximum number of bytes transmitted in a single transmission. The firmware data corresponding to the firmware version information is divided sequentially according to the size of the data packet, and an incremental sequence number is assigned to each data packet. Add a data packet header to each data packet containing the incrementing sequence number, the target chip identifier to be upgraded, and the data packet checksum; A packet forwarding flag is set based on the target chip identifier to be upgraded in the packet header, and the packet forwarding flag is used to indicate the number of packet forwardings; The data packets are prioritized according to the data packet forwarding flag, with higher priority given a greater number of forwarding attempts.

5. The multi-chip cascaded IAP upgrade method according to claim 1, characterized in that, The step of transmitting the data packets in series to each of the target chips to be upgraded according to the optimal transmission path in the dynamic routing table includes: Based on the optimal transmission path in the dynamic routing table, the multiple target cores to be upgraded are divided into multiple serial transmission branches; Obtain the historical fluctuation range of the communication bandwidth parameters and response delay parameters of the first target chip to be upgraded within each of the serial transmission branches; Based on the historical fluctuation range, calculate the upper limit of the transmission capacity and the fluctuation coefficient of the first target chip to be upgraded in each of the serial transmission branches; Based on the transmission capacity limit and the fluctuation coefficient, the data packets will be divided into a base data packet group and a compensation data packet group according to the increasing sequence number of the data packets; The reference data packet group is sent to the first target chip to be upgraded in each of the serial transmission branches. The first target chip to be upgraded receives and forwards the reference data packet group to the next target chip to be upgraded in the branch. At the same time as the reference data packet group is transmitted, the compensation data packet group is sent to the first target chip to be upgraded in the serial transmission branch to supplement the data packets lost by each target chip to be upgraded during the reception of the reference data packet group.

6. The multi-chip cascaded IAP upgrade method according to claim 5, characterized in that, The step of transmitting the data packets in series to each of the target chips to be upgraded according to the optimal transmission path in the dynamic routing table further includes: Monitor the data packet reception status of each target chip to be upgraded in each of the aforementioned serial transmission branches; When an abnormal chip awaiting upgrade is detected with an abnormal data packet reception status, the data packet loss rate of the abnormal chip awaiting upgrade is calculated. Based on the packet loss rate, adjust the ratio of the baseline packet group and the compensation packet group in the corresponding serial transmission branch; Based on the response delay parameters of the abnormal chip to be upgraded, set the data packet retransmission waiting time; If no confirmation of receipt is received from the abnormal chip to be upgraded during the data packet retransmission waiting time, the baseline data packet group and the compensation data packet group will be retransmitted according to the adjusted ratio.

7. The multi-chip cascaded IAP upgrade method according to claim 1, characterized in that, The firmware verification process after each target chip to be upgraded has received the firmware includes: All data packets received by each of the target chips to be upgraded are reassembled into complete firmware according to their incrementing sequence numbers; Calculate the checksum of the complete firmware and compare it with the firmware checksum carried in the IAP upgrade instruction; If the checksum matches the firmware check value, a firmware check pass flag is generated; If the checksum is inconsistent with the firmware checksum, a checksum failure message is sent to the main control chip and a request is made to retransmit the firmware data.

8. An electronic device for multi-chip cascaded IAP upgrade, characterized in that, The electronic device includes: one or more processors and a memory; the memory is coupled to the one or more processors, the memory is used to store computer program code, the computer program code including computer instructions, and the one or more processors call the computer instructions to cause the electronic device to perform the method as described in any one of claims 1-7.

9. A computer program product containing instructions, characterized in that, When the computer program product is run on an electronic device with a multi-chip cascaded IAP upgrade, the electronic device causes the electronic device to perform the method as described in any one of claims 1-7.

10. A computer-readable storage medium comprising instructions, characterized in that, When the instructions are executed on an electronic device that is upgraded with multi-chip cascaded IAP, the electronic device causes the electronic device to perform the method as described in any one of claims 1-7.

Images