Shared memory device and memory system including same

Abstract

A shared memory device and a memory system including the same are disclosed. The shared memory device includes: a memory bank storing first raw data corresponding to a first cache line stored in a first processor among a plurality of processors; a snoop filter circuit including a first snoop filter entry corresponding to the first cache line and a first entry access count corresponding to the first snoop filter entry; and a migration management circuit which determines the popularity of the first cache line based on the first entry access count and issues a migration request for the first raw data to the first processor based on the popularity.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0125668, filed on September 13, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to semiconductor memory devices. More specifically, this disclosure relates to shared memory devices accessed by multiple processors and memory systems including shared memory devices. Background Technology

[0003] In hierarchical memory systems, dedicated memory can have higher communication speeds than shared memory. Therefore, in some cases, data in shared memory devices can be cached to improve access to data in the shared memory device.

[0004] However, reading an invalid cache line from a shared memory device can cause read latency when the cache line is invalidated (or evicted). Summary of the Invention

[0005] One aspect is the provision of shared memory devices that trigger the migration of raw data and memory systems that include shared memory devices.

[0006] According to one aspect of one or more embodiments, a shared memory device is provided, the shared memory device comprising: a memory bank configured to store first raw data corresponding to a first cache line in a first processor among a plurality of processors; a snooping filter circuit including a first snooping filter entry corresponding to the first cache line and a first entry access count corresponding to the first snooping filter entry; and a migration management circuit configured to determine the heat of the first cache line based on the first entry access count, and to issue a migration request for the first raw data to the first processor based on the heat.

[0007] According to another aspect of one or more embodiments, a memory system is provided, the memory system comprising: a first processor including a cache memory storing a plurality of cache lines; a dedicated memory device for the first processor; and a shared memory device configured to store raw data of a first cache line among the plurality of cache lines, and to determine whether the first cache line is a hot cache line. The first processor is configured to: when the first cache line is determined to be a hot cache line, migrate the raw data from the shared memory device to the dedicated memory device.

[0008] According to another aspect of one or more embodiments, a shared memory device is provided, the shared memory device being configured to communicate with a first processor storing a first cache line, the shared memory device comprising: a snooping filter circuit including a snooping filter entry for the first cache line and an entry access count for the snooping filter entry; a reverse snooping circuit configured to update the entry access count by performing a reverse snooping on the first cache line; and a migration management circuit configured to determine the heat of the first cache line based on the entry access count. Attached Figure Description

[0009] Figure 1 This is a block diagram illustrating a memory system according to an embodiment.

[0010] Figure 2 The embodiments are shown in more detail. Figure 1 A diagram illustrating the configuration of the snooping filter circuit in the memory system.

[0011] Figure 3 This illustrates that, according to an embodiment, cache lines stored in a first cache memory are... Figure 1 A diagram illustrating a situation where the shared memory device of a memory system is invalid.

[0012] Figure 4 This shows in more detail how, according to the embodiments, Figure 1 A diagram illustrating the migration process performed in the memory system.

[0013] Figure 5 This illustrates how to increase according to an embodiment. Figure 2 A diagram illustrating the entry access count of the snooping filter circuit.

[0014] Figure 6 and Figure 7 This illustrates an embodiment. Figure 1 A diagram illustrating the operation of the reverse eavesdropping circuit in a memory system.

[0015] Figure 8 This is a flowchart illustrating the operation of a shared memory device performing a reverse snooping operation according to an embodiment.

[0016] Figure 9 This is a diagram illustrating the effect of a reverse snooping operation on a test cache line according to an embodiment.

[0017] Figure 10 This is a flowchart illustrating how a migration is performed according to an embodiment.

[0018] Figure 11 This shows in more detail how, according to the embodiments, Figure 1 A diagram illustrating the migration process performed in the memory system.

[0019] Figure 12 This is a flowchart illustrating how a migration is performed according to an embodiment.

[0020] Figure 13 This is a block diagram illustrating a memory system according to an embodiment.

[0021] Figure 14 This is a block diagram illustrating a memory system according to an embodiment.

[0022] Figure 15 This illustrates an embodiment. Figure 14 A flowchart of the operation of the first processor in the memory system. Detailed Implementation

[0023] In the following description, various embodiments will be clearly and in detail to the extent that those skilled in the art can readily practice this disclosure. Details such as detailed configurations and structures are provided only to facilitate a thorough understanding of the various embodiments. Therefore, variations of the embodiments described herein can be performed by those skilled in the art without departing from the spirit and scope of this disclosure. Furthermore, for clarity and brevity, descriptions of well-known functions and structures may be omitted. Components in the following drawings or detailed embodiments may be connected to other elements besides those shown in the drawings or described in the detailed embodiments. The terminology used in this specification is defined in consideration of the functionality of this disclosure and is not limited to specific functions. The definitions of terms may be determined based on the details described in the detailed embodiments.

[0024] The constituent elements described with reference to the terms used in the specific implementation (such as drivers or blocks) can be implemented in the form of software, hardware, or a combination thereof. Illustratively, software can be machine code, firmware, embedded code, and / or application software. For example, hardware may include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0025] A hierarchical memory system may include multiple processors, dedicated memory devices for each of the processors, and shared memory devices for the processors. Communication between a processor and its corresponding dedicated memory device can be faster than communication between a processor and its shared memory device.

[0026] Multiple processors can each cache the raw data stored in a shared memory device. The shared memory device ensures cache coherency for each of the multiple processors. For example, the shared memory device can manage snooping filters for each cache line across the multiple processors.

[0027] However, when a cache line initially provided from a shared memory device is invalidated or evicted, excessive read latency may occur when the corresponding processor reads valid data corresponding to the invalid cache line from the shared memory device. One aspect is to provide shared memory devices and memory systems that include shared memory devices to trigger the migration of the original data in order to resolve this excessive latency.

[0028] Figure 1 This is a block diagram illustrating a memory system according to an embodiment. (Refer to...) Figure 1 The memory system MS may include a first processor 11, a second processor 12, a first dedicated memory device DMD1, a second dedicated memory device DMD2, and a shared memory device 100.

[0029] Each of the first processor 11 and the second processor 12 can be one of various processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU). Each of the first processor 11 and the second processor 12 can be implemented as a single processing core or as multiple processing cores.

[0030] Each of the first dedicated memory device DMD1, the second dedicated memory device DMD2, and the shared memory device 100 may be a dynamic random access memory (DRAM) device.

[0031] The first dedicated memory device DMD1 can be used as a dedicated memory device for the first processor 11. For example, in some embodiments, the first processor 11 can communicate directly with the first dedicated memory device DMD1 via a Double Data Rate (DDR) interface. Similarly, the second dedicated memory device DMD2 can be used as a dedicated memory device for the second processor 12. For example, in some embodiments, the second processor 12 can communicate directly with the second dedicated memory device DMD2 via a DDR interface.

[0032] In one embodiment, the first dedicated memory device DMD1 may be referred to as the host memory device of the first processor 11, and the second dedicated memory device DMD2 may be referred to as the host memory device of the second processor 12. However, the embodiments are not limited to these terms.

[0033] The first processor 11 and the second processor 12 can share the shared memory device 100. For example, the first processor 11 and the second processor 12 can communicate with the shared memory device 100 through a "shared memory interface circuit IFC_SM".

[0034] The shared memory device 100 may include a memory bank BNK, a snoop filter circuit 110, a migration management circuit 120, and a back snoop circuit 130. The shared memory device 100 may store data in the memory bank BNK in response to requests from the first processor 11 and the second processor 12, and may output the data stored in the memory bank BNK in response to requests from the first processor 11 and the second processor 12.

[0035] In one embodiment, the shared memory interface circuit IFC_SM may be implemented as a CXL switch that implements a compute fast link (CXL) interface. In this case, the shared memory device 100 may also be referred to as a CXL memory device, and the first processor 11 and the second processor 12 may each be referred to as a CXL host device. However, the embodiments are not limited to these terms.

[0036] The first processor 11 may include a first cache memory 11a, and the second processor 12 may include a second cache memory 12a. Each of the first processor 11 and the second processor 12 may cache raw data stored in the shared memory device 100 or in a corresponding dedicated memory device DMD. For example, the first processor 11 may cache raw data stored in the memory bank BNK or in the first dedicated memory device DMD1 into the first cache memory 11a. Similarly, the second processor 12 may cache raw data stored in the memory bank BNK or in the second dedicated memory device DMD2 into the second cache memory 12a.

[0037] Data stored in the cache memory can be input / output in cache line units. Each of the first processor 11 and the second processor 12 can perform various operations (such as read operations, modify operations, and invalid operations) on the cache line stored in the corresponding cache memory. For example, after raw data stored in the memory bank BNK is cached in both the first processor 11 and the second processor 12, the cache line corresponding to the raw data can be modified individually by each processor.

[0038] Shared memory device 100 can ensure cache coherency of cache lines stored on multiple processors. For example, shared memory device 100 may include snoop filter circuitry 110. Snoop filter circuitry 110 may include multiple snoop filter entries SFE. The multiple snoop filter entries SFE may each correspond to different raw data cached in one or more processors. The multiple snoop filter entries SFE may each represent information about the corresponding raw data. For example, each of the multiple snoop filter entries SFE may represent the device physical address (DPA) of the corresponding raw data within shared memory device 100, the identifier of the processor caching the raw data, and / or the status of the cache line corresponding to the raw data.

[0039] Therefore, even if a single piece of raw data is cached across multiple processors, each of the processors can identify the state of the raw data based on information indicated by the SFE (Snoop Filter Entry). For example, multiple processors can each identify the processor storing the cache line representing the most recent version of a particular piece of raw data (i.e., valid data) based on information presented by the SFE. In this case, cache coherence across the multiple processors can be maintained even if a single piece of raw data is cached across multiple processors.

[0040] In one embodiment, multiple snooping filter entries (SFEs) may each represent information about the original data based on the Modify, Exclusive, Shared, and Invalidate (MESI) protocol. For example, multiple snooping filter entries (SFEs) may each indicate the status of the cache line corresponding to the original data as one of Modify (M), Exclusive (E), Shared (S), and Invalidate (I). See below. Figure 4 Describe the more detailed configuration of each of the multiple snooping filter entries in the SFE.

[0041] Cache lines stored in each of the multiple processors may be invalidated for various reasons. For example, a first cache line stored in the first cache memory 11a may be invalidated when a second cache line "stored in the second cache memory 12a and corresponding to the same original data as the first cache line" is modified; and it may be invalidated when an entry eviction operation is performed for the snooping filter entry SFE corresponding to the first cache line within the snooping filter circuit 110. However, embodiments are not limited to the specific reasons for invalidating cache lines.

[0042] If a particular cache line is invalidated, the processor may need to reread the original data corresponding to that cache line. To illustrate this more concisely, a representative case of a cache line stored in the first cache memory 11a being invalidated will be described below.

[0043] If a first cache line stored in the first cache memory 11a is invalidated, the first processor 11 may need to reread the original data corresponding to the first cache line from the first dedicated memory device DMD1 or the shared memory device 100. Specifically, if the first cache line is a hot cache line (e.g., a cache line frequently accessed by the first processor 11), the first processor 11 may need to read the original data corresponding to the first cache line immediately after the first cache line is invalidated.

[0044] The communication speed between the first processor 11 and the first dedicated memory device DMD1 can be faster than the communication speed between the first processor 11 and the shared memory device 100. Therefore, if the original data corresponding to the first cache line is stored in the first dedicated memory device DMD1 instead of the shared memory device 100, the first processor 11 will be able to access the original data corresponding to the first cache line more quickly after the first cache line stored in the first cache memory 11a is invalidated.

[0045] In other words, if the first cache line is a hot cache line, the time spent by the first processor 11 accessing the original data corresponding to the first cache line again after the first cache line is invalidated can be minimized by migrating the original data corresponding to the first cache line from the shared memory device 100 to the first dedicated memory device DMD1 before the first cache line is invalidated. The following describes how the first processor 11 migrates the original data corresponding to the first cache line (which is a hot cache line) from the shared memory device 100 to the first dedicated memory device DMD1.

[0046] The snooping filter circuit 110 manages multiple entry access counts (EACs) corresponding to multiple snooping filter entries (SFEs). The multiple entry access counts (EACs) can increment whenever an access to a corresponding snooping filter entry (SFE) occurs from multiple processors.

[0047] The shared memory device 100 may include migration management circuitry 120. Migration management circuitry 120 may determine the hotness of each of a plurality of cache lines included in the first cache memory 11a based on a plurality of entry access counts (EACs). For example, migration management circuitry 120 may determine a cache line corresponding to a snooping filter entry (SFE) with an entry access count (EAC) greater than a 'hotness determination threshold' as a hot cache line. The hotness determination threshold may be predetermined.

[0048] The migration management circuit 120 can issue a migration request to the first processor 11 for the original data corresponding to the hot cache line. That is, according to the embodiment, the shared memory device 100 can trigger the migration of the original data corresponding to the hot cache line. Therefore, by triggering the migration of the original data for the hot cache line by the shared memory device 100 before invalidating the hot cache line, the time spent by the first processor 11 re-accessing the original data of the hot cache line can be minimized. (Refer to below...) Figure 3 The situation where a cache line stored in the first cache memory 11a is invalidated by the shared memory device 100 is explained in more detail.

[0049] The first processor 11 may include a data migration unit 11b. The data migration unit 11b can migrate the original data corresponding to a hot cache line from the shared memory device 100 to the first dedicated memory device DMD1 in response to a migration request. In this case, even if the hot cache line is invalidated, the time spent by the first processor 11 accessing the original data corresponding to the invalid cache line can be minimized, thus improving the operating speed of the memory system MS.

[0050] In one embodiment, the data migrater 11b may be implemented as software or as firmware on an operating system running on the first processor 11. However, the embodiments are not limited thereto, and the data migrater 11b may be implemented as dedicated hardware for performing data migration, or as any combination of hardware and software.

[0051] If a valid cache line is stored in the first cache memory 11a, the first processor 11 may not need to read the original data corresponding to the cache line from the shared memory device 100. That is, if a cache hit occurs in the first cache memory 11a, the first processor 11 may not access the shared memory device 100 (i.e., skip the access to the shared memory device 100), and therefore the migration management circuitry 120 may have difficulty determining the hotness of the cache line.

[0052] If the migration management circuit 120 incorrectly determines the hotness of a cache line, the operational performance of the memory system MS may degrade. For example, if the migration management circuit 120 determines that the hotness of a cache line is too low, the state in which the original data corresponding to that cache line is stored in the shared memory device 100 may be preserved. In this case, since the first processor 11 may need to access the original data corresponding to that cache line from the shared memory device 100 after the cache line is invalidated, this may degrade the operational performance of the memory system MS. In contrast, if the migration management circuit 120 determines that the hotness of a cache line is too high, the original data corresponding to cache lines that are not frequently accessed by the first processor 11 can be migrated from the shared memory device 100 to the first dedicated memory device DMD1. In this case, the operational load of the data migrater 11b may increase, and the storage space of the first dedicated memory device DMD1 may be wasted.

[0053] The shared memory device 100 can determine the hotness of cache lines in the first cache memory 11a, taking into account cache hits within the first cache memory 11a. For example, the shared memory device 100 may include a reverse snooping circuit 130. The reverse snooping circuit 130 can perform a reverse snooping operation. That is, the reverse snooping circuit 130 can test the status of cache lines stored in the first cache memory 11a.

[0054] For example, the reverse snooping circuit 130 can invalidate a cache line stored in the first cache memory 11a. If an access from the first processor 11 to a snooping filter entry SFE corresponding to the invalidated cache line occurs within a specific time length after the cache line is invalidated, the reverse snooping circuit 130 can increase the entry access count EAC for the accessed snooping filter entry SFE. In this case, the entry access count EAC of cache lines cached in the first cache memory 11a and repeatedly accessed by the first processor 11 (i.e., cache hits) can also be increased. That is, in one embodiment, the entry access count EAC can reflect the frequency of cache lines cached and hit within the first cache memory 11a.

[0055] Therefore, the migration management circuit 120 can more accurately determine the hotness of the cache line corresponding to the entry access count EAC. In this case, the data migrater 11b can migrate the original data corresponding to the hot cache line to the first dedicated memory device DMD1, thereby improving the operating performance of the memory system MS.

[0056] For the sake of brevity, Figure 1Two processors are shown, but the embodiments are not limited to this. For example, in some embodiments, the shared memory device 100 may be shared by three or more processors.

[0057] In one embodiment, each of the eavesdropping filter circuit 110, migration management circuit 120, and reverse eavesdropping circuit 130 may be implemented as dedicated hardware or as any combination of hardware and software. That is, the embodiments are not limited to the specific way in which each of the eavesdropping filter circuit 110, migration management circuit 120, and reverse eavesdropping circuit 130 is implemented.

[0058] Figure 2 The embodiments are shown in more detail. Figure 1 A diagram illustrating the configuration of the listening filter circuit. (Refer to...) Figure 1 and Figure 2 The eavesdropping filter circuit 110 may include first eavesdropping filter entries SFE1 to fourth eavesdropping filter entries SFE4 and first entry access counts EAC1 to fourth entry access counts EAC4. However, the embodiments are not limited to these. Figures 1 to 2 The number of snoop filter entries SFE and entry access count EAC included in the snoop filter circuit 110 shown in the figure.

[0059] The first snoop filter entry SFE1 to the fourth snoop filter entry SFE4 may correspond to different device physical addresses (DPAs) within the shared memory device 100. That is, the first snoop filter entry SFE1 to the fourth snoop filter entry SFE4 may correspond to different raw data. The first snoop filter entry SFE1 to the fourth snoop filter entry SFE4 may correspond to different cache lines. For example, the first snoop filter entry SFE1 may correspond to a cache line cached based on raw data stored in device physical address DPA "0x1122"; the second snoop filter entry SFE2 may correspond to a cache line cached based on raw data stored in device physical address DPA "0x3344"; the third snoop filter entry SFE3 may correspond to a cache line cached based on raw data stored in device physical address DPA "0x5566"; and the fourth snoop filter entry SFE4 may correspond to a cache line cached based on raw data stored in device physical address DPA "0x7788".

[0060] The snooping filter circuit 110 can manage each of the first snooping filter entries SFE1 to the fourth snooping filter entries SFE4 based on the MESI protocol. That is, each of the first snooping filter entries SFE1 to the fourth snooping filter entries SFE4 may include a processor identifier ID_PR of the processor caching the corresponding raw data and a cache line state CLS indicating the state of the cache line stored in the processor. For example, a first snoop filter entry SFE1 may indicate that the cache line corresponding to the original data stored at device physical address DPA "0x1122" is stored in the first processor 11 in an invalid state; a second snoop filter entry SFE2 may indicate that the cache line corresponding to the original data stored at device physical address DPA "0x3344" is exclusively cached on the first processor 11; a third snoop filter entry SFE3 may indicate that the cache line corresponding to the original data stored at device physical address DPA "0x5566" is cached in a shared state on the first processor 11 and the second processor 12; and a fourth snoop filter entry SFE4 may indicate that the cache line corresponding to the original data stored at device physical address DPA "0x7788" is cached in the first processor 11 in a modified state compared to the original data.

[0061] In some embodiments, the maximum number of eavesdropping filter entries SFE that can be stored in the eavesdropping filter circuit 110 can be determined in advance. That is, the number of eavesdropping filter entries SFE that can be stored in the eavesdropping filter circuit 110 can be limited (e.g., restricted). The maximum number of eavesdropping filter entries SFE that can be stored in the eavesdropping filter circuit 110 may be referred to as the "maximum number of entries".

[0062] In one embodiment, the snooping filter circuit 110 may include a snooping filter entry SFE corresponding to each of the valid cache lines stored in the plurality of processors. For example, if a valid cache line corresponding to raw data stored in the shared memory device 100 is stored in a first cache memory 11a or a second cache memory 12a, the snooping filter circuit 110 may include its corresponding snooping filter entry SFE. On the other hand, if an invalid cache line corresponding to raw data stored in the shared memory device 100 is stored in the first cache memory 11a or the second cache memory 12a, the snooping filter circuit 110 may or may not include the corresponding snooping filter entry SFE.

[0063] First processor 11 and second processor 12 can access any snoop filter entry SFE. For example, first processor 11 and / or second processor 12 can change the state of a cache line stored in cache memory and then update the cache line state indicated by the snoop filter entry SFE by accessing the snoop filter entry SFE. More specifically, first processor 11 can update the cache line corresponding to the original data stored in device physical address DPA "0x3344". In this case, first processor 11 can change the cache line state indicated by second snoop filter entry SFE2 from "exclusive" to "modified". As another example, first processor 11 and / or second processor 12 can store invalid cache lines in cache memory. In this case, first processor 11 and / or second processor 12 can access snoop filter entry SFE to identify the location where valid data corresponding to the invalid cache line is stored (e.g., the original data stored in shared memory device 100, or a valid cache line cached in another processor based on the original data). More specifically, if an invalid cache line is stored in the second cache memory 12a and its corresponding device physical address DPA is "0x7788", then the second processor 12 can access the fourth snoop filter entry SFE4 to identify a valid version of the data corresponding to the invalid cache line cached in the first processor 11. However, the scope of this disclosure is not limited to the specific circumstances and manner in which snoop filter entry SFE is accessed.

[0064] The first entry access count EAC1 to the fourth entry access count EAC4 can correspond to the first snoop filter entry SFE1 to the fourth snoop filter entry SFE4, respectively. Each of the first entry access counts EAC1 to the fourth entry access count EAC4 can represent the number of times the corresponding snoop filter entry has been accessed by multiple processors. For example, the first entry access count EAC1 can represent the number of times the first snoop filter entry SFE1 has been accessed by multiple processors.

[0065] The migration management circuit 120 can determine the hotness of the cache line corresponding to the first entry access count EAC1 through the fourth entry access count EAC4 based on a "hotness determination threshold (hereinafter referred to as "TH_HD")" and the first entry access count EAC1 through the fourth entry access count EAC4. For example, the migration management circuit 120 can determine whether the cache line corresponding to the second snoop filter entry SFE2 is a hot cache line by comparing the second entry access count EAC2 with the hotness determination threshold TH_HD.

[0066] For a more detailed example, the "heat determination threshold TH_HD" could be "15". In this case, as... Figure 2 As shown in the example, because the second entry access count EAC2 (e.g., 17) is greater than the heat determination threshold TH_HD, the migration management circuit 120 can determine the cache line corresponding to the second snooping filter entry SFE2 as a hot cache line. On the other hand, if the second entry access count EAC2 is less than the heat determination threshold TH_HD, the migration management circuit 120 will be able to determine that the cache line corresponding to the second snooping filter entry SFE2 is not a hot cache line. For example, in Figure 2 In the example shown, since the first entry access count EAC1, the third entry access count EAC3, and the fourth entry access count EAC4 are all less than 15, the first snoop filter entry SFE1, the third snoop filter entry SFE3, and the fourth snoop filter entry SFE4 will be determined by the migration management circuit 120 as not hot cache lines.

[0067] Figure 3 This illustrates that, according to an embodiment, cache lines stored in a first cache memory are... Figure 1 A diagram illustrating a situation where the shared memory device is invalid. (Refer to...) Figures 1 to 3 The first cache memory 11a and the second cache memory 12a may each include one or more cache lines CL.

[0068] The first cache memory 11a may include a victim cache line CL_VCT. The victim cache line CL_VCT may be in an active state. The second snoop filter entry SFE2 may correspond to the victim cache line CL_VCT. For example, the second snoop filter entry SFE2 and the victim cache line CL_VCT may correspond to the same device physical address DPA.

[0069] The snooping filter circuit 110 may include a first snooping filter entry SFE1 to an nth snooping filter entry SFEn. The maximum number of entries in the snooping filter circuit 110 can be "n". That is, the snooping filter circuit 110 can be in a full state.

[0070] When the snooping filter circuit 110 is full, the second processor 12 can access the snooping filter circuit 110 (“Circle 1”: Accessing the snooping filter circuit). For example, the second cache memory 12a may include an attack cache line CL_AGGR with an invalid state. In this case, in order to identify the location of valid data corresponding to the attack cache line CL_AGGR, the second processor 12 can look up (e.g., snooping filter query, snooping filter check, snooping filter retrieval, or snooping filter access) the snooping filter entry SFE corresponding to the device physical address DPA from the snooping filter circuit 110 by providing the device physical address DPA of the original data corresponding to the attack cache line CL_AGGR. As another example, the second cache memory 12a may newly cache the original data stored in the shared memory device 100 as the attack cache line CL_AGGR. In this scenario, to identify whether the original data to be newly cached is currently cached in another processor, the second processor 12 can look up the snoop filter entry SFE for the device physical address DPA from the snoop filter circuit 110 by providing the "device physical address DPA of the original data to be newly cached" to the snoop filter circuit 110. However, the embodiments are not limited to the specific cases in which access to the snoop filter circuit 110 occurs.

[0071] The snooping filter circuit 110 may not include snooping filter entries SFE corresponding to the device physical address DPA provided from the second processor 12. For example, the first snooping filter entry SFE1 to the nth snooping filter entry SFEn may each correspond to a device physical address different from the device physical address provided by the second processor 12.

[0072] If the snoop filter entry SFE corresponding to an access to snoop filter circuit 110 is not included in snoop filter circuit 110, snoop filter circuit 110 may add a new snoop filter entry SFE corresponding to an access to snoop filter circuit 110. For example, snoop filter circuit 110 may store a new snoop filter entry SFE corresponding to a received device physical address DPA.

[0073] However, if the snooping filter circuit 110 is full, it can evict at least one of the first snooping filter entries SFE1 to the nth snooping filter entry SFEn to add a new snooping filter entry SFE. In other words, when the snooping filter circuit 110 is full, it can perform an entry eviction operation. In this case, the snooping filter circuit 110 can select one or more victim snooping filter entries SFE_VCT to be evicted from the first snooping filter entry SFE1 to the nth snooping filter entry SFEn (“Circle 2”: SFE_VCT selected when the snooping filter circuit is full). For example, the snooping filter circuit 110 can select the second snooping filter entry SFE2 as the victim snooping filter entry SFE_VCT to add a new snooping filter entry SFE for the received device physical address DPA.

[0074] After selecting the victim snooping filter entry SFE_VCT, the snooping filter circuit 110 can issue an entry eviction decision notification for the victim snooping filter entry SFE_VCT. For example, the snooping filter circuit 110 can provide the entry eviction decision notification for the victim snooping filter entry SFE_VCT to the migration management circuit 120. See below for further details. Figure 4 The operation of migration management circuit 120 in response to entry eviction decision notification is described in more detail.

[0075] In one embodiment, the snooping filter circuit 110 may select the victim snooping filter entry SFE_VCT based on various selection algorithms, such as Least Recently Used (LRU) . However, the embodiments are not limited to the type of algorithm used by the snooping filter circuit 110 to select the victim snooping filter entry SFE_VCT. For example, the snooping filter circuit 110 may select the victim snooping filter entry SFE_VCT based on the cache line state CLS of each of the first snooping filter entries SFE1 to the nth snooping filter entries SFEn.

[0076] The snooping filter circuit 110 can evict the victim snooping filter entry SFE_VCT (“Circle 3”: Evict SFE_VCT). For example, the snooping filter circuit 110 can erase the second snooping filter entry SFE2.

[0077] Snooping filter circuit 110 can add new snooping filter entries SFE (“circle 4”: add new SFE). For example, snooping filter circuit 110 can newly store snooping filter entries SFE for the device physical address DPA received from the second processor 12.

[0078] Shared memory device 100 can invalidate the victim cache line CL_VCT. That is, shared memory device 100 can invalidate the cache line corresponding to the erased second snoop filter entry SFE2. For example, shared memory device 100 can provide an invalidation request REQ_INV (e.g., a reverse invalidation request) for the victim cache line CL_VCT to the first processor 11 (“circle 5”: REQ_INV for CL_VCT). The first processor 11 can invalidate the victim cache line CL_VCT in response to the invalidation request REQ_INV.

[0079] In other words, the victim cache line CL_VCT can be invalidated by the shared memory device 100. Therefore, before issuing an invalidation request REQ_INV for the victim cache line CL_VCT, the shared memory device 100 can issue a migration request for the original data corresponding to the victim cache line CL_VCT based on the popularity of the victim cache line CL_VCT. In this case, the time spent by the first processor 11 accessing the original data corresponding to the victim cache line CL_VCT after it is invalidated can be minimized, thus improving the operating performance of the memory system MS.

[0080] For a more concise explanation, Figure 3 An example is shown in which the victim cache line CL_VCT is invalidated due to an entry eviction operation performed on the victim snooping filter entry SFE_VCT, but the example is not limited to the specific reasons for invalidating the victim cache line CL_VCT.

[0081] For the sake of brevity, Figure 3 The illustration shows an embodiment in which the victim cache line CL_VCT is invalidated after a new snoop filter entry SFE is stored in snoop filter circuit 110, but the embodiment is not limited thereto. For example, the shared memory device 100 may invalidate the victim cache line CL_VCT before evicting the victim snoop filter entry SFE_VCT; or it may invalidate the victim cache line CL_VCT between the time when the victim snoop filter entry SFE_VCT is evicted and the time when the new snoop filter entry SFE is stored.

[0082] Figure 4 This shows in more detail how it is performed according to the embodiments. Figure 1 A diagram illustrating the migration process. Below, for a more concise explanation, we will refer to... Figures 1 to 4 This describes an implementation example of migrating the original data corresponding to the victim cache line CL_VCT before it is invalidated. For example, operations a through d below can be referenced above. Figure 3The operation described is performed between "Circle 2" and "Circle 5".

[0083] Migration management circuit 120 may receive an entry eviction decision notification for victim snooping filter entry SFE_VCT. In this case, migration management circuit 120 may be able to recognize that victim snooping filter entry SFE_VCT is soon eviction from snooping filter circuit 110.

[0084] Migration management circuit 120 can determine the heat level of the victim cache line CL_VCT (a: Determining the heat level of CL_VCT). That is, migration management circuit 120 can determine the heat level of the victim cache line CL_VCT based on the entry access count EAC corresponding to the victim snooping filter entry SFE_VCT. For example, migration management circuit 120 can determine the heat level of the victim cache line CL_VCT by comparing a second entry access count EAC2 with a heat level determination threshold TH_HD. For simplicity, in the following text, it is assumed that the victim cache line CL_VCT is determined to be a hot cache line.

[0085] The memory bank BNK may include multiple page groups (PGs). Each page group may contain multiple data items. The shared memory device 100 may perform input / output operations on a per-page PG basis.

[0086] In one embodiment, the size of a cache line (CL) may be smaller than the size of a page (PG).

[0087] In one embodiment, the raw data corresponding to a cache line CL may be included in a single page PG.

[0088] Migration management circuitry 120 can identify the migration target page PG_MTG containing the raw data of the victim cache line CL_VCT (b: identify the PG_MTG containing the raw data of CL_VCT). For example, migration management circuitry 120 can identify the page PG corresponding to the device physical address DPA indicated by the victim snooping filter entry SFE_VCT as the migration target page PG_MTG. For a more detailed example, the device physical address DPA indicated by the victim snooping filter entry SFE_VCT can be "0x3344", and a specific page PG of the memory bank BNK can store data corresponding to the device physical address DPA in the range of "0x3300" to "0x3400". In this case, migration management circuitry 120 can identify the corresponding page PG as the migration target page PG_MTG.

[0089] The migration management circuit 120 can provide a migration request REQ_MIG for the migration target page PG_MTG to the first processor 11 (c: REQ_MIG of PG_MTG).

[0090] Data migrater 11b can migrate data in the target page PG_MTG in response to a migration request REQ_MIG (d: migrate data in PG_MTG). For example, data migrater 11b can migrate data in the target page PG_MTG to a first dedicated memory device DMD1. In this case, the data in the target page PG_MTG can be stored in the first dedicated memory device DMD1.

[0091] In other words, according to the embodiment, if the victim cache line CL_VCT is a hot cache line, the original data corresponding to the victim cache line CL_VCT can be migrated to the first dedicated memory device DMD1 before the victim cache line CL_VCT is invalidated.

[0092] In one embodiment, the data migrater 11b may perform a migration operation by reading the migration target page PG_MTG from the shared memory device 100 and then writing the read data to the first dedicated memory device DMD1. However, the embodiment is not limited to this, and the data migrater 11b may also migrate data stored in the migration target page PG_MTG to the first dedicated memory device DMD1 by issuing a direct memory access (DMA) command to the shared memory device 100. That is, the embodiment is not limited to the specific way in which the data migrater 11b performs the migration.

[0093] In one embodiment, data migrater 11b can remap virtual addresses used by an application running on the first processor 11 that are mapped to the physical address of the migration target page PG_MTG to the physical address of data newly stored in the first dedicated memory device DMD1. Therefore, after the migration to the migration target page PG_MTG is complete, if an access to the migration target page PG_MTG occurs from an application running on the first processor 11, the first processor 11 can access the first dedicated memory device DMD1 instead of the shared memory device 100.

[0094] In one embodiment, data migrater 11b can migrate an entire page containing the original data corresponding to the victim cache line CL_VCT (e.g., migrate the target page PG_MTG).

[0095] In one embodiment, the shared memory device 100 may be implemented to issue a migration request REQ_MIG only when the amount of raw data corresponding to a hot cache line in the target page PG_MTG exceeds a "migration threshold". In this case, the raw data corresponding to the hot cache line can be migrated more efficiently, thus improving the operational performance of the memory system MS. See below for further details. Figure 11 and Figure 12 The operation of the shared memory device 100 in determining whether to issue a migration request REQ_MIG based on a migration threshold is described in more detail.

[0096] In one embodiment, the shared memory device 100 may collectively request the migration of multiple raw data corresponding to hot cache lines. For example, if the multiple raw data corresponding to hot cache lines are each contained in different page PGs, the shared memory device 100 may migrate the multiple raw data to a single page and then issue a migration request for that page. However, the embodiments are not limited to this.

[0097] Meanwhile, if the victim cache line CL_VCT is determined not to be a hot cache line in operation a described above, the shared memory device 100 may not perform operations b to d described above. For example, if the victim cache line CL_VCT is determined not to be a hot cache line, the shared memory device 100 may immediately send an invalidation request REQ_INV for the victim cache line CL_VCT.

[0098] Figure 5 This illustrates how to increase according to an embodiment. Figure 2 A diagram showing the entry access count. Below, we will refer to... Figures 1 to 5 A method for increasing the access count of the second entry, EAC2, is described representatively. However, the embodiments are not limited thereto, and other entry access counts, EAC, can also be increased in a similar manner.

[0099] Each of the multiple processors has access to the second snoop filter entry SFE2. For example, the first processor 11 or the second processor 12 may access the second snoop filter entry SFE2 to identify the location of valid data for the raw data stored in the device physical address DPA "0x3344".

[0100] As a more detailed example, the first processor 11 may store an invalid cache line corresponding to the original data stored in device physical address DPA "0x3344". The first processor 11 may access the second snooping filter entry SFE2 by providing device physical address DPA "0x3344" to the shared memory device 100 to identify the location of valid data for the original data stored in device physical address DPA "0x3344".

[0101] As another example, the second processor 12 may access the second snoop filter entry SFE2 before performing a new cache on the original data stored in device physical address DPA "0x3344". For example, the second processor 12 may access the second snoop filter entry SFE2 to identify the location where a valid version of the data for the original data stored in device physical address DPA "0x3344" is stored (e.g., memory bank BNK or cache memory of another processor).

[0102] The processor identifier ID_PR and cache line status CLS indicated by the second snoop filter entry SFE2 may vary depending on when an access to the second snoop filter entry SFE2 occurs. Therefore, a detailed description of the processor identifier ID_PR and cache line status CLS of the second snoop filter entry SFE2 is omitted.

[0103] The snooping filter circuit 110 can increment the second entry access count EAC2 by "1" in response to access to the second snooping filter entry SFE2. That is, the second entry access count EAC2 can gradually increase as the second snooping filter entry SFE2 is accessed by multiple processors.

[0104] For a concise explanation, refer to Figure 5 A representative embodiment is described in which any processor accesses the second snooping filter entry SFE2 by providing the device physical address (DPA) corresponding to the second snooping filter entry SFE2 to the snooping filter circuit 110, but the embodiment is not limited thereto. For example, the snooping filter circuit 110 may assign different identifiers to multiple snooping filter entries SFE. In this case, any processor may also access the second snooping filter entry SFE2 by providing the identifier of the second snooping filter entry SFE2 to the snooping filter circuit 110. That is, the embodiment is not limited to the specific method in which access to the snooping filter entry occurs.

[0105] According to an embodiment, if data stored in the device physical address DPA corresponding to the second snooping filter entry SFE2 is cached in the processor and then repeatedly accessed by the processor (e.g., accessed in a cache hit manner), the second entry access count EAC2 may also increase. See below for further details. Figure 6 and Figure 7 A more detailed description of the specific way in which the second entry access count EAC2 increases even when data stored in the device physical address DPA corresponding to the second snoop filter entry SFE2 is accessed in a cache hit manner.

[0106] Figure 6 and Figure 7 This illustrates some embodiments. Figure 1 A diagram illustrating the operation of the reverse eavesdropping circuit.

[0107] First, refer to Figure 6 The reverse eavesdropping circuit 130 can determine one of a plurality of eavesdropping filter entries SFE included in the eavesdropping filter circuit 110 as the test eavesdropping filter entry SFE_TST. For simplicity, it is assumed below that the reverse eavesdropping circuit 130 determines the second eavesdropping filter entry SFE2 as the test eavesdropping filter entry SFE_TST. However, the embodiment is not limited to this, and the reverse eavesdropping circuit 130 can also determine any eavesdropping filter entry SFE as the test eavesdropping filter entry SFE_TST.

[0108] The cache line corresponding to the test snooping filter entry SFE_TST can be called the test cache line CL_TST.

[0109] In one embodiment, the reverse snooping circuit 130 may determine the snooping filter entry SFE whose corresponding cache line status indicates "exclusive" as the test snooping filter entry SFE_TST. However, the embodiment is not limited to this. For example, the reverse snooping circuit 130 may determine the snooping filter entry SFE whose corresponding cache line status indicates "modified" as the test snooping filter entry SFE_TST.

[0110] The snooping circuit 130 can perform a snooping operation on the test cache line CL_TST. In other words, the snooping circuit 130 can test the heat of the test cache line CL_TST. The snooping operation for the test cache line CL_TST is described in more detail below.

[0111] The reverse snooping circuit 130 can send an invalidation request REQ_INV for the test cache line CL_TST. In this case, the first processor 11 can invalidate the test cache line CL_TST in response to the invalidation request REQ_INV.

[0112] After the test cache line CL_TST is invalidated, if the operation of the first processor 11 requires data corresponding to the test cache line CL_TST, the first processor 11 may access the test snoop filter entry SFE_TST. For example, the first processor 11 may access the test snoop filter entry SFE_TST to identify the location of valid data corresponding to the test cache line CL_TST. On the other hand, if the operation of the first processor 11 does not require data corresponding to the test cache line CL_TST after the test cache line CL_TST is invalidated, the first processor 11 may not access the test snoop filter entry SFE_TST. In other words, the first processor 11 may not access the test snoop filter entry SFE_TST until the operation of the first processor 11 requires data corresponding to the test cache line CL_TST.

[0113] If the test cache line CL_TST is frequently accessed data within the first processor 11, then the first processor 11 may access the test snoop filter entry SFE_TST for a short period after the test cache line CL_TST is invalidated. On the other hand, if the test cache line CL_TST is infrequently accessed data within the first processor 11, then the first processor 11 may not access the test snoop filter entry SFE_TST for a long period after the test cache line CL_TST is invalidated.

[0114] The reverse eavesdropping circuit 130 may include a timer TMR. The reverse eavesdropping circuit 130 may use the timer TMR to measure the elapsed time since the issuance of the invalid request REQ_INV for the test cache line CL_TST.

[0115] Access to the test snoop filter entry SFE_TST can occur before the elapsed snoop test time tBSNT, which is the length of time, begins from the time the invalid request REQ_INV for the test cache line CL_TST is issued. The snoop test time tBSNT can be predetermined. The snoop circuit 130 can increment the entry access count EAC corresponding to the test snoop filter entry SFE_TST by "1". For example, the snoop circuit 130 can increment the second entry access count EAC2 by "1".

[0116] In one embodiment, the reverse snooping circuit 130 may increase the entry access count EAC corresponding to the test snooping filter entry SFE_TST by a number other than "1" based on the length of time between the time when the invalid request REQ_INV for the test cache line CL_TST is issued and the time when an access to the test snooping filter entry SFE_TST occurs. For example, if an access to the test snooping filter entry SFE_TST occurs within a very short time after the invalid request REQ_INV for the test cache line CL_TST is issued, the reverse snooping circuit 130 may also increase the entry access count EAC corresponding to the test snooping filter entry SFE_TST by "2". However, the embodiment is not limited to this.

[0117] Reference Figures 1 to 7 Until the backsniff test time tBSNT elapses from the time the invalidation request REQ_INV for the test cache line CL_TST is issued, there may be no access to the test sniff filter entry SFE_TST. In this case, the backsniff circuit 130 can invalidate the test sniff filter entry SFE_TST. For example, the backsniff circuit 130 can change the cache line state CLS (e.g., from "exclusive") indicated by the test sniff filter entry SFE_TST to "invalid".

[0118] The reverse eavesdropping circuit 130 can maintain the entry access count EAC corresponding to the test eavesdropping filter entry SFE_TST. For example, the reverse eavesdropping circuit 130 may not change the second entry access count EAC2. However, the embodiment is not limited to this. For example, the entry access count EAC corresponding to the test eavesdropping filter entry SFE_TST may be reduced to "0" or reduced to "1".

[0119] In one embodiment, the reverse probe circuit 130 may repeatedly perform reverse probe operations for any test probe filter entry SFE_TST at regular time intervals. However, the embodiment is not limited to a specific time when the reverse probe circuit 130 performs the reverse probe operation.

[0120] In one embodiment, the reverse eavesdropping circuit 130 may determine whether to perform a reverse eavesdropping operation based on various parameters, such as the number of eavesdropping filter entries included in the eavesdropping filter circuit 110, the ratio of non-invalid eavesdropping filter entries among the eavesdropping filter entries included in the eavesdropping filter circuit 110, etc. However, the embodiments are not limited to the specific conditions under which the reverse eavesdropping circuit 130 performs a reverse eavesdropping operation.

[0121] According to an embodiment, the heat of the test cache line CL_TST can be reflected in the entry access count EAC corresponding to the test snoop filter entry SFE_TST. In this case, the migration management circuit 120 will be able to determine the heat of the test cache line CL_TST more accurately.

[0122] Figure 8 This is a flowchart illustrating the operation of a shared memory device performing a reverse snooping operation according to an embodiment. (Refer to...) Figures 1 to 8 In operation S110, the shared memory device 100 may determine the test snooping filter entry SFE_TST. For example, the reverse snooping circuit 130 may determine one of a plurality of snooping filter entries SFE included in the snooping filter circuit 110 as the test snooping filter entry SFE_TST.

[0123] In operation S120, the shared memory device 100 may issue an invalidation request REQ_INV for the test cache line CL_TST corresponding to the test snoop filter entry SFE_TST. For example, the reverse snoop circuit 130 may send the invalidation request REQ_INV for the test cache line CL_TST to the first processor 11. In this case, the first processor 11 may invalidate the test cache line CL_TST in response to the invalidation request REQ_INV.

[0124] In operation S130, the shared memory device 100 can determine whether an access to the test snoop filter entry SFE_TST occurs within the reverse snoop test time tBSNT. For example, the reverse snoop circuit 130 can determine whether an access to the test snoop filter entry SFE_TST from the first processor 11 occurs within the reverse snoop test time tBSNT after the above-described operation S120 has been executed.

[0125] If it is determined that an access to the test snoop filter entry SFE_TST has occurred within the reverse snoop test time tBSNT (operation S130, Yes), then the following operation S140 can be performed. If it is determined that no access to the test snoop filter entry SFE_TST has occurred within the reverse snoop test time tBSNT (operation S130, No), then the following operation S150 can be performed.

[0126] In operation S140, the shared memory device 100 may increase the entry access count EAC corresponding to the test snooping filter entry SFE_TST. For example, the reverse snooping circuit 130 may increase the entry access count EAC corresponding to the test snooping filter entry SFE_TST by "1".

[0127] In operation S150, the shared memory device 100 can invalidate the test snoop filter entry SFE_TST. For example, the reverse snoop circuit 130 can change the cache line state CLS indicated by the test snoop filter entry SFE_TST to "invalid".

[0128] In one embodiment, the shared memory device 100 can repeatedly perform a backsnap operation. For example, the backsnap circuit 130 in the shared memory device 100 can update the entry access count EAC corresponding to the test snoop filter entry SFE_TST by repeatedly performing a backsnap operation on the test snoop filter entry SFE_TST. That is, the shared memory device 100 can repeatedly perform the above operations S110 to S150. In this case, even if the first processor 11 accesses the test cache line CL_TST at a high frequency, the entry access count EAC corresponding to the test snoop filter entry SFE_TST can continue to increase. The shared memory device 100 can perform a backsnap operation in a similar manner for each of the multiple snoop filter entries SFE. Therefore, the multiple entry access counts EAC can more accurately reflect the heat of the corresponding cache line CL.

[0129] Figure 9 This is a diagram illustrating the effect of a reverse snooping operation on a test cache line according to an embodiment. (Refer to...) Figures 1 to 9 The test cache line CL_TST can be cached in the first cache memory 11a at cache time point tCACHE. For example, at cache time point tCACHE, the first processor 11 can cache the raw data stored in the device physical address DPA corresponding to the test snooping filter entry SFE_TST in the first cache memory 11a as the test cache line CL_TST.

[0130] The test cache line CL_TST can be invalidated (or evicted) from the first cache memory 11a at the evict time point tEVICT. For example, similar to the reference above. Figure 3 As described, the shared memory device 100 can perform an entry eviction operation on the test snooping filter entry SFE_TST at the eviction time point tEVICT.

[0131] If the shared memory device 100 does not perform a reverse snooping operation, even if the first processor 11 repeatedly accesses the test cache line CL_TST between cache time point tCACHE and eviction time point tEVICT (i.e., even if the test cache line CL_TST is a hot cache line), the entry access count EAC corresponding to the test snooping filter entry SFE_TST may not reflect the access by the first processor 11. In this case, the entry access count EAC corresponding to the test snooping filter entry SFE_TST may not properly reflect the hotness of the test cache line CL_TST.

[0132] In contrast, according to an embodiment, the shared memory device 100 may repeatedly perform backsnap operations between cache time point tCACHE and eviction time point tEVICT. In this case, the test cache line CL_TST may be invalidated concurrently with each backsnap operation (more specifically, during the backsnap test time tBSNT). That is, when the first processor 11 accesses the test cache line CL_TST concurrently with each backsnap operation, the entry access count EAC corresponding to the test snoop filter entry SFE_TST may increase. Therefore, according to an embodiment, the entry access count EAC corresponding to the test snoop filter entry SFE_TST may appropriately reflect the heat of the test cache line CL_TST.

[0133] If backsnap operations are performed repeatedly, the heat of the test cache line CL_TST can be reflected in the entry access count (EAC) even after the cache time point tCACHE. Therefore, the entry access count (EAC) more accurately represents the temporal locality of the test cache line CL_TST. In other words, backsnap operations can be performed even close to the eviction time point tEVICT, thus the entry access count (EAC) more accurately represents the temporal locality of the test cache line CL_TST.

[0134] Figure 10 This is a flowchart illustrating how a migration is performed according to an embodiment. (Refer to...) Figures 1 to 10 In operation S1100, the shared memory device 100 can determine the victim eavesdropping filter entry SFE_VCT. For example, the eavesdropping filter circuit 110 can determine one of the multiple eavesdropping filter entries SFE stored in the eavesdropping filter circuit 110 as the victim eavesdropping filter entry SFE_VCT.

[0135] In operation S1200, the shared memory device 100 can determine whether the victim cache line CL_VCT is hot. For example, the migration management circuit 120 can determine whether the victim cache line CL_VCT is a hot cache line by comparing the entry access count EAC corresponding to the victim snooping filter entry SFE_VCT with the heat determination threshold TH_HD. If the victim cache line CL_VCT is determined to be a hot cache line, operation S1300 can be performed, and if the victim cache line CL_VCT is determined not to be a hot cache line, operation S1500 can be performed.

[0136] In one embodiment, before performing operation S1200, the shared memory device 100 can repeatedly execute the above-mentioned reference. Figure 8 The described reverse snooping operation manages the entry access count (EAC) corresponding to the victim snooping filter entry SFE_VCT. In this case, the heat of the victim cache line CL_VCT can be accurately determined in operation S1200.

[0137] In operation S1300, the shared memory device 100 may provide a migration request REQ_MIG for the migration target page PG_MTG to the first processor 11. For example, the migration management circuit 120 may provide a migration request REQ_MIG for the migration target page PG_MTG corresponding to the device physical address DPA indicated by the victim snooping filter entry SFE_VCT to the first processor 11.

[0138] In operation S1400, the first processor 11 may, in response to a migration request REQ_MIG, migrate data of the migration target page PG_MTG from the shared memory device 100 to the first dedicated memory device DMD1. For example, the data migrater 11b may read the migration target page PG_MTG from the shared memory device 100 and then write the read data to the first dedicated memory device DMD1; or the data migrater 11b may issue a DMA command to the shared memory device 100 to migrate the data of the migration target page PG_MTG from the shared memory device 100 to the first dedicated memory device DMD1. In this case, the data migrater 11b may remap the virtual address used by the application running on the first processor 11 that is mapped to the physical address of the migration target page PG_MTG to the physical address of the newly stored data in the first dedicated memory device DMD1.

[0139] In operation S1500, the shared memory device 100 can evict the victim eavesdropping filter entry SFE_VCT. For example, the eavesdropping filter circuit 110 can evict the victim eavesdropping filter entry SFE_VCT and store a new eavesdropping filter entry SFE.

[0140] Therefore, according to the embodiment, after performing operation S1500, if the first processor 11 needs the original data corresponding to the victim cache line CL_VCT, the first processor 11 can access the first dedicated memory device DMD1 instead of the shared memory device 100. In this case, the original data corresponding to the victim cache line CL_VCT can be read at a faster speed, thus improving the operating performance of the memory system MS.

[0141] Figure 11 This shows in more detail how it is performed according to the embodiments. Figure 1 A diagram illustrating the migration. (Refer to...) Figures 1 to 11 The eavesdropping filter circuit 110 can be implemented as an eavesdropping filter circuit 210, and the migration management circuit 120 can be implemented as a migration management circuit 220. The first cache memory 11a can be implemented as a first cache memory 21a.

[0142] The first cache memory 21a can store multiple cache lines CL. For example, the first cache memory 21a can store first cache lines CLa to fourth cache lines CLd.

[0143] The snooping filter circuit 210 may include multiple snooping filter entries SFE and multiple entry access counts EAC. For example, the snooping filter circuit 210 may include first snooping filter entries SFEa to fourth snooping filter entries SFEd and first entry access counts EACa to fourth entry access counts EACd. The first entry access counts EACa to fourth entry access counts EACd may correspond to the first snooping filter entries SFEa to fourth snooping filter entries SFEd, respectively. (Previously referred to...) Figures 1 to 11 The configuration and functionality of the Entry Access Count (EAC) and the Snooze Filter (SFE) are described, but for the sake of brevity, no further detailed description is provided.

[0144] The listening filter circuit 210 can be compared with the previously referenced Figure 3 The victim eavesdropping filter entry SFE_VCT is selected in a similar manner as described. For example, the eavesdropping filter circuit 210 may select a second eavesdropping filter entry SFEb as the victim eavesdropping filter entry SFE_VCT.

[0145] The migration management circuit 220 can determine whether to issue a migration request REQ_MIG for the migration target page PG_MTG corresponding to the victim snooping filter entry SFE_VCT based on a migration threshold (hereinafter referred to as "TH_MIG").

[0146] First, migration management circuit 220 can identify the migration target page PG_MTG that includes the original data of the victim cache line CL_VCT (A. Identifying the PG_MTG that includes the original data of CL_VCT). For example, migration management circuit 220 can be referenced above. Figure 4 The described operation b identifies the migration target page PG_MTG in a similar manner.

[0147] Migration management circuit 220 can compare the number of hot cache lines corresponding to the migration target page PG_MTG with the migration threshold (B. compare the number of hot CLs corresponding to PG_MTG with TH_MIG).

[0148] More specifically, the migration target page PG_MTG may store data corresponding to device physical addresses (DPAs) in the range of "0x1100" to "0x1200". In this case, the migration management circuit 220 can identify that the corresponding device physical address (DPA) is included in the snooping filter entry SFE within the device physical address range of the migration target page PG_MTG. For example, the migration management circuit 220 can identify a first snooping filter entry SFEa corresponding to device physical address DPA "0x1101", a second snooping filter entry SFEb corresponding to device physical address DPA "0x1142", and a fourth snooping filter entry SFEd corresponding to device physical address DPA "0x1165".

[0149] The migration management circuit 220 can determine the heat of each cache line corresponding to the identified snooping filter entry SFE. For example, the migration management circuit 220 can determine the heat of a first cache line CLA based on a first entry access count EACa; it can determine the heat of a second cache line CLb based on a second entry access count EACb; and it can determine the heat of a fourth cache line CLd based on a fourth entry access count EACd. In other words, the migration management circuit 220 can determine the heat of cache lines corresponding to multiple original data stored in the migration target page PG_MTG.

[0150] The migration management circuit 220 can compare the number of cache lines identified as hot cache lines with a migration threshold TH_MIG. The migration threshold TH_MIG can be an integer greater than or equal to 2. When the number of hot cache lines corresponding to the migration target page PG_MTG is greater than the migration threshold, the migration management circuit 220 can perform the following operations C and D.

[0151] Migration management circuit 120 can provide a migration request REQ_MIG for the target page PG_MTG to the first processor 11 (C. REQ_MIG of PG_MTG). Data migrater 11b can migrate the data of the target page PG_MTG in response to the migration request REQ_MIG (D. Migrate the data of PG_MTG). Operations C and D are similar to those described above. Figure 4 Operations c and d are described, and for the sake of brevity, further detailed descriptions are omitted.

[0152] In one embodiment, migration management circuitry 120 may invalidate the snooping filter entry SFE that states "the corresponding original data corresponds to each cache line on the migration target page PG_MTG".

[0153] On the other hand, if the number of hot cache lines corresponding to the migration target page PG_MTG is not greater than the migration threshold TH_MIG, then the migration management circuit 220 may not perform the above operations C and D.

[0154] In other words, according to the embodiment, the migration management circuit 220 may issue a migration request REQ_MIG for the migration target page PG_MTG only when the target page PG_MTG includes multiple raw data corresponding to more than the migration threshold TH_MIG. In this case, since multiple raw data corresponding to multiple hot cache lines can be migrated in a single migration, the migration efficiency can be improved. Therefore, according to Figure 11 In some embodiments, the operational performance of the memory system MS can be improved.

[0155] In one embodiment, operations A to D described above can be referenced above. Figure 3 The described operation is performed between "Circle 2" and "Circle 5".

[0156] Figure 12 This is a flowchart illustrating how a migration is performed according to an embodiment. (Refer to...) Figures 1 to 12 In operation S2100, the shared memory device 100 can determine the victim eavesdropping filter entry SFE_VCT. Operation S2100 is similar to operation S1100 described above, and therefore will not be described in further detail for the sake of brevity.

[0157] In operation S2200, the shared memory device 100 can determine whether the number of hot cache lines CL corresponding to the migration target page PG_MTG is greater than the migration threshold TH_MIG. For example, the migration management circuit 220 can determine the page PG storing the original data for the cache line corresponding to the victim snooping filter entry SFE_VCT as the migration target page PG_MTG. The migration management circuit 220 can determine the hotness of each cache line corresponding to the original data stored in the migration target page PG_MTG.

[0158] If the number of hot cache lines CL corresponding to the migration target page PG_MTG is greater than the migration threshold TH_MIG (operation S2200, Y), then operation S2300 can be performed. If the number of hot cache lines CL corresponding to the migration target page PG_MTG is less than the migration threshold TH_MIG (operation S2200, No), then operation S2500 can be performed.

[0159] In operation S2300, the shared memory device 100 may provide a migration request REQ_MIG for the target page PG_MTG to the first processor 11. In operation S2400, the first processor 11 may, in response to the migration request REQ_MIG, migrate the data of the target page PG_MTG from the shared memory device 100 to the first dedicated memory device DMD1. In operation S2500, the shared memory device 100 may evict the victim eavesdropping filter entry SFE_VCT. Operations S2300 to S2500 are similar to operations S1300 to S1500 described above, and therefore will not be described in further detail for the sake of brevity.

[0160] Figure 13 This is a block diagram illustrating a memory system according to an embodiment. (Refer to...) Figures 1 to 10 and Figure 13 The memory system MS may include a first processor 11, a second processor 12, a first dedicated memory device DMD1, a second dedicated memory device DMD2, a first shared memory device 100a, and a second shared memory device 100b. That is, the memory system MS may include multiple shared memory devices 100.

[0161] The above has been referenced Figure 1 The configuration and operation of the first processor 11, the second processor 12, the first dedicated memory device DMD1, and the second dedicated memory device DMD2 are described, and therefore, for the sake of brevity, they will not be described in further detail.

[0162] The first shared memory device 100a may include a snooping filter circuit 110a, a migration management circuit 120a, a reverse snooping circuit 130a, and a memory bank BNKa. The second shared memory device 100b may include a snooping filter circuit 110b, a migration management circuit 120b, a reverse snooping circuit 130b, and a memory bank BNKb. For simplicity, a detailed description of the configuration and function of the snooping filter circuit 110, the migration management circuit 120, the reverse snooping circuit 130, and the memory bank BNKb is omitted.

[0163] Memory bank BNKa and memory bank BNKb can store different data. The first shared memory device 100a and the second shared memory device 100b can independently manage multiple snooping filter entries SFE and multiple entry access counts EAC.

[0164] Each of the migration management circuits 120a and 120b can use an independent criterion to determine the heat of a cache line. For example, migration management circuit 120a can determine the heat of the cache line corresponding to each snoop filter entry SFE based on a heat determination threshold TH_HD "15", and migration management circuit 120b can determine the heat of the cache line corresponding to each snoop filter entry SFE based on a heat determination threshold TH_HD "25".

[0165] Therefore, the frequency at which the first shared memory device 100a and the second shared memory device 100b issue migration requests REQ_MIG can vary based on the data access patterns of each of the plurality of processors and the heat determination threshold TH_HD of each of the migration management circuits 120a and 120b. In one embodiment, the first processor 11 may adjust the heat determination threshold TH_HD based on the frequency of occurrence of migration requests REQ_MIG from the shared memory devices (e.g., shared memory device 100, first shared memory device 100a, and / or second shared memory device 100b).

[0166] If migration requests REQ_MIG are received from a specific shared memory device 100 at an excessively high frequency, the first processor 11 may request an increase in the heat determination threshold TH_HD for the corresponding specific shared memory device 100. For example, if migration requests REQ_MIG are received from a first shared memory device 100a at an excessively high frequency, the first processor 11 may request the first shared memory device 100a to increase the heat determination threshold TH_HD to a value higher than "15".

[0167] On the other hand, if a migration request REQ_MIG is received from a specific shared memory device 100 at an excessively low frequency, the first processor 11 may request a reduction in the heat determination threshold TH_HD for that specific shared memory device 100. For example, if a migration request REQ_MIG is received from a second shared memory device 100b at an excessively low frequency, the first processor 11 may request the second shared memory device 100b to reduce the heat determination threshold TH_HD to a value below "25".

[0168] Figure 14 This is a block diagram illustrating a memory system according to an embodiment. (Refer to...) Figures 1 to 14 The memory system MS may include a first processor 31, a second processor 32 and a third processor 33, a first dedicated memory device DMDa, a second dedicated memory device DMDb and a third dedicated memory device DMDc, and a shared memory device 100.

[0169] The first processor 31 to the third processor 33 and the shared memory device 100 can be interconnected via a shared memory interface circuit IFC_SM. For example, the first processor 31 to the third processor 33 can share the shared memory device 100 based on a CXL interface running on the shared memory interface circuit IFC_SM.

[0170] The first processor 31 to the third processor 33 may each include a first cache memory 31a to a third cache memory 33a. The first cache memory 31a to the third cache memory 33a may each cache the data used in the operation of the corresponding processor.

[0171] The first processor 31 to the third processor 33 can be directly connected to the first dedicated memory device DMDa to the third dedicated memory device DMDc, respectively.

[0172] The first processor 31, the second processor 32, the first dedicated memory device DMDa, and the second dedicated memory device DMDb can form a non-uniform memory access (NUMA) structure.

[0173] The third processor 33, which is not included in the NUMA architecture, can only access the directly connected third dedicated memory device DMDc and shared memory device 100, and may not be able to access the first dedicated memory device DMDa and the second dedicated memory device DMDb.

[0174] In contrast, processors included in a NUMA architecture can share dedicated memory devices included in the NUMA architecture. For example, the first processor 31 can also access the second dedicated memory device DMDb, and the second processor 32 can also access the first dedicated memory device DMDa.

[0175] However, in one embodiment, the physical distance between the first processor 31 and the first dedicated memory device DMDa may be shorter than the physical distance between the first processor 31 and the second dedicated memory device DMDb. The first dedicated memory device DMDa may be referred to as the local memory device of the first processor 31, and the second dedicated memory device DMDb may be referred to as the remote memory device of the first processor 31. Due to the difference in physical distance, the first processor 31 can access the local memory device of the first processor 31 at a faster speed than accessing the remote memory device of the first processor 31.

[0176] Similarly, the physical distance between the second processor 32 and the second dedicated memory device DMDb can be shorter than the physical distance between the second processor 32 and the first dedicated memory device DMDa. The second dedicated memory device DMDb can be referred to as the local memory device of the second processor 32, and the first dedicated memory device DMDa can be referred to as the remote memory device of the second processor 32. Due to the difference in physical distance, the second processor 32 can access the local memory device of the second processor 32 at a faster speed than accessing the remote memory device of the second processor 32.

[0177] For a concise explanation, Figure 14 An embodiment is shown in which the first processor 31 and the second processor 32 are connected to the shared memory interface circuit IFC_SM via separate physical interfaces, but the embodiment is not limited thereto. For example, in some embodiments, the first processor 31 and the second processor 32 may be connected to the shared memory interface circuit IFC_SM via a single physical interface.

[0178] Shared memory device 100 may include migration management circuitry 120 and a memory bank BNK. The memory bank BNK may include a migration target page PG_MTG. Similar to previously... Figure 1 The content described herein, please refer to Figure 12 The migration management circuit 120 can issue a migration request REQ_MIG for the target page PG_MTG. For simplicity, it will be assumed in the following text that the migration management circuit 120 provides the migration request REQ_MIG to the first processor 31.

[0179] The first processor 31 may include a data migrater 31b. The data migrater 31b may migrate the target page PG_MTG in response to a migration request REQ_MIG.

[0180] Data migrater 31b can migrate the target page PG_MTG to a dedicated memory device accessible by the first processor 31. For example, data migrater 31b can migrate the target page PG_MTG to a first dedicated memory device DMDa or a second dedicated memory device DMDb.

[0181] Data migrater 31b can determine the migration destination based on the physical distance (or locality) of the first dedicated memory device DMDa and the second dedicated memory device DMDb relative to the first processor 31. For example, data migrater 31b can set the local memory device of the first processor 31 as a high-priority migration destination and the remote memory device of the first processor 31 as a low-priority migration destination. In this case, after migration, the first processor 31 will be able to access the data in the migration target page PG_MTG more quickly.

[0182] Data migrater 31b can temporarily migrate the data of the target page PG_MTG to a separate cache memory allocated to the first processor 31. For example, if the data of the target page PG_MTG cannot be separately stored in the first dedicated memory device DMDa and the second dedicated memory device DMDb, then data migrater 31b can temporarily migrate the data of the target page PG_MTG to the cache memory allocated to the first processor 31. In this case, when the data of the target page PG_MTG can be separately stored in the first dedicated memory device DMDa or the second dedicated memory device DMDb, data migrater 31b can migrate the data stored in the cache memory. However, the embodiments are not limited to this.

[0183] In one embodiment, the cache memory may be a component of one of the components included in the NUMA structure for the operation of the data migrater 31b, or it may be included in... Figure 14 Components in a separate memory device not shown. However, the embodiments are not limited to the specific implementation of the cache memory.

[0184] Figure 15 This illustrates an embodiment. Figure 14 The flowchart shows the operation of the first processor. (Refer to...) Figures 1 to 15 In operation S3100, the first processor 31 may receive a migration request REQ_MIG for the target page PG_MTG. For example, the first processor 31 may receive the migration request REQ_MIG from the shared memory device 100.

[0185] In operation S3200, the first processor 31 may determine whether a local memory device is available. For example, the data migrater 31b may determine whether new data can be stored in the local memory device of the first processor 31 (i.e., the first dedicated memory device DMDa). If the local memory device is determined to be available (operation S3200, Yes), operation S3300 may be performed, and if the local memory device is determined to be unavailable (operation S3200, No), operation S3400 may be performed.

[0186] In operation S3300, the first processor 31 can migrate the data of the migration target page PG_MTG to a local memory device. For example, the first processor 31 can migrate the data of the migration target page PG_MTG to the local memory device of the first processor 31 (i.e., the first dedicated memory device DMDa).

[0187] In operation S3400, the first processor 31 may determine whether a remote memory device is available. For example, the data migrater 31b may determine whether new data can be stored in the remote memory device (i.e., the second dedicated memory device DMDb) of the first processor 31.

[0188] If the remote memory device is determined to be available (S3400, Yes), then the following operation S3500 may be performed. If the remote memory device is determined to be unavailable (S3400, No), then the following operation S3600 may be performed.

[0189] In operation S3500, the first processor 31 can migrate the data of the migration target page PG_MTG to a remote memory device. For example, the first processor 31 can migrate the data of the migration target page PG_MTG to a remote memory device of the first processor 31 (i.e., a second dedicated memory device DMDb).

[0190] In operation S3600, the first processor 31 can migrate the data of the target page PG_MTG to the cache memory.

[0191] In one embodiment, after performing operation S3600, if a local or remote memory device of the first processor 31 becomes available, the data migrater 31b can migrate data stored in the cache memory to the available memory device. However, the embodiments are not limited thereto.

[0192] The above are specific embodiments for carrying out this disclosure. This disclosure may include not only embodiments described above, but also embodiments that are simply designed or readily modified. Furthermore, this disclosure may include techniques that can be readily modified and implemented using the embodiments. Therefore, the scope of this disclosure should not be limited to the embodiments described above, but should be determined by the scope of the appended claims and their equivalents described below.

Claims

1. A shared memory device, comprising: The memory storage is configured to store first raw data corresponding to a first cache line in a first processor among a plurality of processors; The snooping filter circuit includes a first snooping filter entry corresponding to a first cache line and a first entry access count corresponding to the first cache filter entry; as well as The migration management circuit is configured to determine the heat of a first cache line based on a first entry access count, and to issue a migration request for the first raw data to a first processor based on the heat.

2. The shared memory device as claimed in claim 1, wherein, The migration management circuit is configured to identify the first cache line as a hot cache line when the access count of the first entry is greater than the hot threshold.

3. The shared memory device as claimed in claim 1, wherein, The first entry access count increases in response to accesses to the first snooping filter entry from the plurality of processors.

4. The shared memory device of claim 3, further comprising: The reverse snooping circuit is configured to update the first entry access count by repeatedly performing a reverse snooping operation on the first snooping filter entry.

5. The shared memory device as claimed in claim 4, wherein, The reverse eavesdropping circuit is configured as follows: At the first time point within the first time period of performing the reverse snooping operation, an invalid request for the first cache line is provided to the first processor; as well as When an access to the first snooping filter entry occurs between the first time point and the second time point, the access count of the first entry is increased. At the second time point, the reverse snooping test time has elapsed since the first time point.

6. The shared memory device as claimed in claim 5, wherein, The reverse snooping circuit is configured to invalidate the first snooping filter entry based on the fact that no access to the first snooping filter entry occurred between the first time point and the second time point.

7. The shared memory device as claimed in claim 1, wherein, The migration management circuit is configured to issue a migration request based on an entry eviction decision notification from the snooping filter circuit for the first snooping filter entry.

8. The shared memory device according to any one of claims 1 to 7, wherein, The first processor is configured to migrate first raw data to a dedicated memory device for the first processor based on a migration request.

9. The shared memory device as claimed in claim 8, wherein, The memory bank includes a first physical page containing the first original data, and The first processor is configured to migrate the first physical page to a dedicated memory device based on a migration request.

10. The shared memory device of claim 9, wherein, In addition to the first cache line, the first processor also includes one or more cache lines. The first physical page is configured to store one or more original data corresponding to the one or more cache lines, and The migration management circuit is configured as follows: Determine the hotness of each of the one or more cache lines. Based on the popularity of the first cache line and the popularity of each of the one or more cache lines, determine the number of cache lines that are considered hot cache lines among the first cache line and the one or more cache lines. A migration request is issued when the number of cache lines exceeds the migration threshold.

11. A memory system, comprising: The first processor includes a cache memory that stores multiple cache lines; A dedicated memory device for the first processor; as well as A shared memory device is configured to store the raw data of a first cache line among the plurality of cache lines, and to determine whether the first cache line is a hot cache line. The first processor is configured to migrate the original data from the shared memory device to the dedicated memory device when the first cache line is determined to be a hot cache line.

12. The memory system of claim 11, wherein, Shared memory devices include: A snooping filter circuit is configured to store multiple snooping filter entries corresponding to the multiple cache lines and multiple entry access counts corresponding to the multiple snooping filter entries, and to increment the corresponding entry access count in the multiple entry access counts based on the occurrence of an entry access to the corresponding snooping filter entry; and The migration management circuit is configured to determine whether a first cache line is a hot cache line by comparing the access count of a first entry corresponding to a first cache line with a hotness threshold.

13. The memory system of claim 12, wherein, Shared memory devices also include: The snooping circuit is configured to update the first entry access count by repeatedly performing snooping operations on the first snooping filter entry corresponding to the first cache line.

14. The memory system of claim 13, wherein, The reverse eavesdropping circuit is configured as follows: At the first time point within the first time period of performing the reverse snooping operation, an invalid request for the first cache line is provided to the first processor; as well as When an access to the first snooping filter entry occurs between the first time point and the second time point, the access count of the first entry is increased. At the second time point, the reverse snooping test time has elapsed since the first time point.

15. The memory system of claim 14, wherein, The reverse eavesdropping circuit is configured as follows: The first snooping filter entry is invalidated because no access to the first snooping filter entry occurred between the first time point and the second time point.

16. The memory system of claim 12, wherein, The migration management circuit is configured to issue a migration request for the original data to the first processor when the first cache line is determined to be a hot cache line.

17. The memory system of claim 12, wherein, The migration management circuit is configured as follows: After receiving an entry eviction decision notification from the snoop filter circuit for the first snoop filter entry corresponding to the first cache line, a migration request for the original data is issued.

18. The memory system according to any one of claims 12 to 17, wherein, The first processor is configured to adjust the heat threshold based on the frequency of migration requests from the shared memory device.

19. A shared memory device configured to communicate with a first processor storing a first cache line, the shared memory device comprising: The snooping filter circuit includes snooping filter entries for a first cache line and entry access counts for snooping filter entries; The snooping circuit is configured to update the entry access count by performing a snoop on the first cache line; as well as The migration management circuit is configured to determine the heat of the first cache line based on the entry access count.

20. The shared memory device of claim 19, wherein, The snooping circuit is configured to increment the entry access count when an access to a snooping filter entry occurs during the snooping test period after an invalid request for a first cache line is provided to the first processor.

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