Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a non-display area; the display area comprises a plurality of sub-pixels and a plurality of data lines extending in the first direction, the data lines comprise a first data line and a second data line which are adjacent to each other, one first data line is connected with the sub-pixels of two different colors, and one second data line is connected with the sub-pixels of two different colors; the non-display area comprises a data lead, a power lead and a reference lead, and the data lead comprises a first data lead and a second data lead; the first data lead is connected with the first data line, and the second data lead is connected with the second data line; and a power lead and / or a reference lead are / is arranged between the adjacent first data lead and second data lead. According to the invention, signal coupling crosstalk between adjacent data leads can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Multiple data lines are arranged in the display area of ​​the display panel, providing data voltage to the pixel circuits to control the light-emitting devices to display different grayscale brightness levels. Data leads are arranged in the non-display area of ​​the display panel, connecting to the display driver chip. These data leads originate from the boundary between the display and non-display areas and gradually converge to form a fan-shaped arrangement. In this fan-shaped lead area, the distance between adjacent data leads decreases, and the data voltage transition frequency on the data leads is high. This results in severe signal coupling and crosstalk between adjacent data leads, affecting the accuracy of data voltage transmission and consequently impacting display quality. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the technical problem in the prior art where signal coupling crosstalk between adjacent data leads affects display quality.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a display area and a non-display area; the display area includes a plurality of sub-pixels and a plurality of data lines extending along a first direction, the data lines including adjacent first data lines and second data lines, a first data line connecting two sub-pixels of different colors, and a second data line connecting two sub-pixels of different colors; The non-display area includes data leads, power leads, and reference leads. The data leads include a first data lead and a second data lead; the first data lead is connected to a first data line, and the second data lead is connected to a second data line; wherein, A power lead and / or a reference lead are provided between adjacent first and second data leads.

[0005] Secondly, based on the same inventive concept, embodiments of the present invention provide a display device, including a display panel provided in any embodiment of the present invention.

[0006] The display panel and display device provided in this embodiment of the invention have the following beneficial effects: In the non-display area, a first data lead, a second data lead, a power lead, and a reference lead are arranged. The first and second data leads transmit data voltages respectively, the power lead transmits a constant voltage signal, and the reference lead transmits a constant voltage signal for at least a portion of the time during the display of a frame. The first data lead connects to a first data line located in the display area, and the second data lead connects to a second data line located in the display area. The first and second data lines connect to two different color sub-pixels respectively, and are adjacent to each other. Furthermore, a power lead and / or a reference lead are arranged between adjacent first and second data leads in the non-display area. During the display phase, the power lead and / or reference lead act as signal shielding between adjacent first and second data leads, thereby reducing signal crosstalk between the first and second data leads transmitting high-frequency data voltages, improving the accuracy of data voltage transmission on the data leads, and enhancing display quality. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 3 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 4 A signal timing diagram provided in an embodiment of the present invention; Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6A Another timing diagram provided for an embodiment of the present invention; Figure 6B Another timing diagram provided for an embodiment of the present invention; Figure 6C Another timing diagram provided for an embodiment of the present invention; Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8A This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8B A schematic cross-sectional view of a display panel provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 19 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 22 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0011] In related technologies, multiple data leads are arranged in the non-display area of ​​a display panel. The distance between adjacent data leads is relatively short, and the data voltage on these leads switches frequently, resulting in a large coupling capacitance between adjacent data leads. This causes signal interference between adjacent data leads, thus affecting display quality. Therefore, this invention provides a display panel that designs the arrangement of fan-out leads in the non-display area. Power leads and / or reference leads are placed between adjacent data leads. During the display phase, the power leads and / or reference leads act as signal shields between adjacent data leads, reducing signal crosstalk between adjacent data leads. This improves the accuracy of data voltage transmission on the data leads and enhances display quality. Furthermore, in some embodiments of this invention, the arrangement of signal lines in the display area is designed to complement the arrangement of leads in the non-display area. This not only improves signal crosstalk between adjacent data leads in the non-display area but also reduces voltage drop during signal transmission in the display area, further enhancing display quality. Furthermore, the application of routing design for signal leads in non-display areas in DGLD (Dual Gate Line Driving) technology can improve display quality while reducing manufacturing costs. The above are the main technical concepts of this invention. Specific embodiments are provided below to illustrate these technical concepts.

[0012] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 1 As shown, the display panel includes a display area AA and a non-display area NA; the display area AA includes multiple sub-pixels sp, and multiple data lines 10, power lines 30, and reference signal lines 40 extending along a first direction y. Multiple signal lines within the display area AA are arranged along a second direction x, which intersects with the first direction y. To distinguish the signal lines within the display area AA, Figure 1 The diagram shows that data line 10 is a thin line, power line 30 is a thick line, and reference signal line 40 is a dotted line.

[0013] Data line 10 includes adjacent first data line 11 and second data line 12. Adjacent first data line 11 and second data line 12 refer to data lines 10 that do not transmit data voltage between them, but can have signal lines transmitting other signals between them. One first data line 11 connects two different colored sub-pixels sp, and one second data line 12 connects two different colored sub-pixels sp. Figure 1 The diagram only illustrates the arrangement of sub-pixels sp at a local location within the display area AA. Sub-pixels sp include a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. A first data line 11 connects the red sub-pixel R and the green sub-pixel G, and a second data line 12 connects the blue sub-pixel B and the white sub-pixel W. Each sub-pixel includes a light-emitting device and pixel circuitry. The light-emitting device can be, for example, an OLED (Organic Light-Emitting Diode) device.

[0014] The non-display area NA includes data leads 21, power leads 22, and reference leads 23. Data leads 21 include a first data lead 211 and a second data lead 212. The first data lead 211 is connected to the first data line 11, and the second data lead 212 is connected to the second data line 12. The power lead 22 transmits the constant voltage signal required by the power supply line 30, and the reference lead 23 transmits the signal required by the reference signal line 40. The reference lead 23 transmits the constant voltage signal for at least a portion of the time during which a frame of the image is displayed.

[0015] Figure 1 A power lead 22 is provided between the first data lead 211 and the second data lead 212 that are partially adjacent, and a reference lead 23 is provided between the first data lead 211 and the second data lead 212 that are partially adjacent.

[0016] Figure 2 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 2 As shown, the display panel includes a display area AA and a non-display area NA; the display area AA includes multiple sub-pixels sp, and multiple data lines 10, power lines 30, and reference signal lines 40 extending along the first direction y. To distinguish the signal lines within the display area AA, Figure 1The diagram illustrates that data line 10 is a thin line, power line 30 is a thick line, and reference signal line 40 is a dotted line. A first data line 11 connects two different colored sub-pixels sp, and a second data line 12 connects two different colored sub-pixels sp. For example, the first data line 11 connects the red sub-pixel R and the blue sub-pixel B, and the second data line 12 connects the green sub-pixel G and the white sub-pixel W. The non-display area NA is provided with data leads 21, power leads 22, and reference leads 23. Data leads 21 include a first data lead 211 and a second data lead 212. The first data lead 211 is connected to the first data line 11, and the second data lead 212 is connected to the second data line 12. A power lead 22 and a reference lead 23 are positioned between adjacent first data leads 211 and second data leads 212.

[0017] In this embodiment of the invention, a first data lead 211, a second data lead 212, a power lead 22, and a reference lead 23 are arranged in the non-display area NA. The first data lead 211 and the second data lead 212 transmit data voltages respectively, the power lead 22 transmits a constant voltage signal, and the reference lead 23 transmits a constant voltage signal for at least a portion of the time period during which a frame is displayed. The first data lead 211 is connected to the first data line 11 located in the display area AA, and the second data lead 212 is connected to the second data line 12 located in the display area AA. The first data line 11 and the second data line 12 are respectively connected to two different color sub-pixels sp, and the first data line 11 and the second data line 12 are adjacent data lines 10. A power lead 22 and / or a reference lead 23 are provided between adjacent first data leads 211 and second data leads 212 in the non-display area NA. During the display stage, the power lead 22 and / or the reference lead 23 serve as signal shielding between adjacent first data leads 211 and second data leads 212. This reduces signal crosstalk between the first data leads 211 and second data leads 212 that transmit high-frequency data voltages, improves the accuracy of data voltage transmission on the data leads 21, and enhances display quality.

[0018] Existing display panels generally employ SGLD (Single Gate Line Driving) technology, where one gate line drives a single subpixel row. The applicant in this case has been researching and developing SGLD OLED TVs. Considering the need to reduce manufacturing costs, the applicant further developed Dual Gate Line Driving (DGLD) technology. DGLD technology uses two gate lines to drive a subpixel row and a data line connects two subpixels of different colors within the same row. By coordinating two gate lines with multiple data lines, data voltage can be alternately written to multiple subpixels within a single subpixel row during the row driving time, thus driving the subpixel row. Using DGLD technology halves the number of data lines in the display panel, reducing the number of data leads in non-display areas, facilitating a narrower bottom bezel, and reducing the number of data terminals on the display driver chip, thereby lowering manufacturing costs. DGLD OLED is becoming the development trend for large-size panels. Currently, some technical challenges have been encountered during the development of DGLD OLED TVs. Research has revealed that, at the same resolution, the charging time per row of subpixels in DGLD technology is nearly one-third less than that of the original SGLD architecture. This results in a higher frequency of data line signal transmission, making it easier for subpixels in two columns to interfere with each other and cause display defects. Furthermore, in large-size panels, the signal uniformity of power line transmission decreases due to the increased panel size. Therefore, resolving the issues of signal crosstalk between adjacent subpixel columns and power supply voltage uniformity in DGLD technology is extremely urgent.

[0019] To address the problems encountered during the development of DGLD OLED TVs, the inventors of this case considered that crosstalk between two columns of sub-pixels is mainly caused by the high frequency of data signal changes on the data lines and the close spacing between adjacent data leads in the non-display area. Improving the signal coupling crosstalk between adjacent data leads can improve display defects.

[0020] In some implementations... Figure 3 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 3 The diagram illustrates the four sub-pixels sp within the display area AA. Figure 3 The connection method between data line 10 and sub-pixel sp in the central display area AA and Figure 1The embodiment is the same, illustrating a red light-emitting device PD-r, a green light-emitting device PD-g, a blue light-emitting device PD-b, and a white light-emitting device PD-w. A first data line 11 is connected to the pixel circuit 50 corresponding to the red light-emitting device PD-r and the green light-emitting device PD-g, and a second data line 12 is connected to the pixel circuit 50 corresponding to the blue light-emitting device PD-b and the white light-emitting device PD-w. Within the display area AA, multiple sub-pixels sp are arranged in a sub-pixel row spH in the second direction x. Figure 3 The diagram illustrates four sub-pixels sp in a sub-pixel row spH. Within the display area AA, a first scan line S1, a second scan line S2, and a third scan line S3 extending along the second direction x are arranged. The first switching transistor T1 of the odd-numbered sub-pixels sp in the sub-pixel row spH and the first switching transistor T1 of the even-numbered sub-pixels sp are connected, one to the first scan line S1 and the other to the second scan line S2. The control terminals of the second switching transistors T2 of the multiple sub-pixels sp in the sub-pixel row spH are connected to the third scan line S3. A shift register unit is also arranged in the display panel. The first scan line S1 and the second scan line S2 are connected to adjacent stages of multiple cascaded shift register units, and the third scan line S3 is connected to another set of cascaded shift register units.

[0021] like Figure 3 As shown, the display area AA includes a power line 30 and a reference signal line 40 extending along the first direction y. The power line 30 is connected to the power lead 22, and the reference signal line 40 is connected to the reference lead 23. The sub-pixel sp includes a light-emitting device and a pixel circuit 50. The pixel circuit 50 includes a driving transistor Tm, a first switching transistor T1, a second switching transistor T2, and a storage capacitor C. The control terminal of the driving transistor Tm is connected to the first node N1, its first electrode is connected to the power line 30, and its second electrode is connected to the second node N2. The first electrode of the first switching transistor T1 is connected to the data line 10, and its second electrode is connected to the first node N1. The first electrode of the second switching transistor T2 is connected to the reference signal line 40, and its second electrode is connected to the second node N2. One plate of the storage capacitor C is connected to the first node N1, and the other plate is connected to the second node N2. All transistors in the pixel circuit 50 are n-type transistors.

[0022] In addition, such as Figure 3As shown, a first scan line S1, a second scan line S2, and a third scan line S3 extending along the second direction x are arranged within the display area AA. A first data line 11 connects two sub-pixels sp that are adjacent in the second direction x and belong to the same sub-pixel row spH. A second data line 12 connects two sub-pixels sp that are adjacent in the second direction x and belong to the same sub-pixel row spH. The first switch T1 of the odd-numbered sub-pixel sp and the first switch T1 of the even-numbered sub-pixel sp in the sub-pixel row spH are connected, one to the first scan line S1 and the other to the second scan line S2. The control terminals of the second switches T2 of multiple sub-pixel sps in the sub-pixel row spH are connected to the third scan line S3. The first scan line S1 and the second scan line S2 are respectively connected to two adjacent stages of multiple cascaded shift register units. Figure 3 The embodiment was designed using DGLD technology.

[0023] Figure 4 This is a signal timing diagram provided for an embodiment of the present invention. Figure 4 The diagram illustrates the signal timing of the first scan line S1, the second scan line S2, and the third scan line S3 connected to a pixel circuit row, which can be used to drive... Figure 3 Neutron pixel row spH. For example, S1 represents the control signal provided by the first scan line S1, S2 represents the control signal provided by the second scan line S2, and S3 represents the control signal provided by the third scan line S3. Figure 4 As shown, during the period t0 of driving the sub-pixel row, the first scan line S1 first provides a high-level enable signal and the second scan line S2 provides a de-enable signal. The first scan line S1 controls the first switch T1 connected to it to turn on, and at the same time, the first data line 11 and the second data line 12 respectively write data voltage to the first node N1 of the pixel circuit 50 through the corresponding first switch T1. Then, the first scan line S1 provides a de-enable signal and the second scan line S2 provides a high-level enable signal. The second scan line S2 controls the first switch T1 connected to it to turn on, and at the same time, the first data line 11 and the second data line 12 respectively write data voltage to the first node N1 of the pixel circuit 50 through the corresponding first switch T1. The third scan line S3 provides a high-level enable signal to control the second switch T2 of each pixel circuit in the sub-pixel row spH to turn on and write the reference voltage to the second node N2. The period when the third scan line S3 provides a high-level enable signal covers the period when the first scan line S1 provides a high-level enable signal and the period when the second scan line S2 provides a high-level enable signal.

[0024] Figure 3 In this embodiment, a first data line 11 and a second data line 12 can each drive two adjacent columns of sub-pixels, thereby reducing the number of data lines 10 set within the display area AA. Combined with... Figure 4As can be seen from the provided timing diagram, it is understandable that because a first data line 11 and a second data line 12 drive two adjacent columns of sub-pixels respectively, the charging time of each sub-pixel sp is shortened during the period t0 when driving the sub-pixel row, resulting in a higher signal transmission frequency of data line 10. Consequently, the data signal transmission frequency of data leads 21 in the non-display area NA is higher, and the signal crosstalk problem between adjacent data leads 21 becomes more severe. Using the design of this embodiment, a power lead 22 or a reference lead 23 is provided between adjacent first data leads 211 and second data leads 212. This can shield the signal crosstalk between adjacent first data leads 211 and second data leads 212 during the display stage, improve the accuracy of the data voltage transmitted on the data leads 21, solve the problem of mutual interference between adjacent columns of sub-pixels causing display defects encountered during the development of DGLDOLED TVs, and improve display quality. Furthermore, Figure 3 In the DGLD architecture of this embodiment, the number of data lines 10 in the display area AA is halved, and the number of data leads 21 in the non-display area NA is also halved, thereby reserving space for arranging power leads 22 and reference leads 23. Adding power leads 22 between adjacent first data leads 211 and second data leads 212 also helps improve the uniformity of the in-plane power supply voltage, thereby improving display uniformity.

[0025] In other implementations, Figure 5 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5 As shown, the display area AA includes a power line 30 and a reference signal line 40 extending along the first direction y. The power line 30 is connected to the power lead 22, and the reference signal line 40 is connected to the reference lead 23. The sub-pixel sp includes a light-emitting device and a pixel circuit 50. The structure of the pixel circuit 50 is similar to... Figure 3 The implementation methods are the same and will not be repeated here.

[0026] Figure 5 The diagram illustrates the four sub-pixels sp within the display area AA. Figure 5 The connection method between data line 10 and sub-pixel sp in the central display area AA and Figure 2 The embodiment is the same, illustrating a red light-emitting device PD-r, a green light-emitting device PD-g, a blue light-emitting device PD-b, and a white light-emitting device PD-w. A first data line 11 is connected to the pixel circuit 50 corresponding to the red light-emitting device PD-r and the blue light-emitting device PD-b, and a second data line 12 is connected to the pixel circuit 50 corresponding to the green light-emitting device PD-g and the white light-emitting device PD-w. Within the display area AA, multiple sub-pixels sp are arranged in a sub-pixel row spH in the second direction x. Figure 5The diagram illustrates four sub-pixels sp in a sub-pixel row spH. A fourth scan line S4 and a fifth scan line S5 extending along the second direction x are arranged within the display area AA. The fourth scan line S4 is connected to the control terminal of the first switching transistor T1 in the sub-pixel row spH, and the fifth scan line S5 is connected to the control terminal of the second switching transistor T2 in the sub-pixel row spH. Shift register units are also arranged in the display panel; the fourth scan line S4 is connected to the first stage of a cascaded set of multiple shift register units, and the fifth scan line S5 is connected to the first stage of another cascaded set of multiple shift register units.

[0027] Figure 6A This is another timing diagram provided in an embodiment of the present invention. Figure 6A The provided timing can be used for Figure 5 Driven by the pixel circuit in Figure 6A (a) is the operating timing of the pixel circuit 50 in compensation mode. Figure 6A (b) is the operating timing of the pixel driving circuit 50 in display mode. Here, S4 represents the control signal provided by the fourth scan line S4, S5 represents the control signal provided by the fifth scan line S5, and Ref is the signal provided on the reference signal line 40.

[0028] In compensation mode, such as Figure 6A As shown in (a), during the initialization phase t1: the fourth scan line S4 and the fifth scan line S5 provide high-level enable signals to control the first switch T1 and the second switch T2 to turn on respectively. The first switch T1 turns on and writes the data voltage Vdata to the first node N1 through the data line 10. The second switch T2 turns on and writes the reference signal Vref to the second node N2 through the reference signal line 40.

[0029] During the pre-charge phase t2: the fifth scan line S5 provides a low-level inactive signal to control the second switch T2 to turn off, and the pre-charge voltage Vpre is written onto the reference signal line 40.

[0030] During the discharge phase t3: The fifth scan line S5 provides a high-level enable signal to control the second switch T2 to turn on. The driving transistor Tm turns on under the control of the first node N1 potential and charges the second node N2 using the power signal on power line 30. When Vgs = Vth, the driving transistor Tm turns off, and the potential of the second node N2 is charged to Vdata - Vth, where Vth represents the threshold voltage of the driving transistor Tm, and Vgs is the gate-source voltage difference of the driving transistor Tm. Since the second switch T2 is on, the reference signal line 40 is connected to the second node N2, and the potential on the reference signal line 40 jumps from Vpre to Vdata - Vth.

[0031] During the sampling phase t4, the fourth scan line S4 and the fifth scan line S5 provide low-level inactive signals to control the first switch T1 and the second switch T2 to turn off, and the sensing signal Vdata-Vth is acquired through the reference signal line 40.

[0032] The sensing signal acquired by the reference signal line 40 is then provided to an external compensation circuit. The compensation circuit modulates the data voltage of the input image based on the sensing signal to compensate for changes in the characteristics (threshold voltage, mobility, etc.) of the driving transistor Tm in the pixel circuit 50. The compensation mode is a mode that senses the characteristics of the driving transistor Tm in the pixel circuit 50. The characteristics of the driving transistor Tm can be sensed before leaving the factory, or after the display panel has been used for a period of time. Alternatively, the compensation mode can be inserted between display modes.

[0033] In display mode, such as Figure 6A As shown in (b), during the period t0 when the driving sub-pixel row is working, the fourth scan line S4 and the fifth scan line S5 control the first switch T1 and the second switch T2 to turn on, respectively. The first switch T1 turns on and writes the compensated data voltage Vdata to the first node N1 through the data line 10. The second switch T2 turns on and writes the reference signal Vref to the second node N2 through the reference signal line 40. The driving transistor Tm turns on under the control of the compensated data voltage Vdata and generates a driving current, which is provided to the light-emitting device PD, causing the light-emitting device PD to emit light.

[0034] Figure 5 The pixel circuit 50 provided in the embodiment can be adopted Figure 6A The schematic timing is used to compensate for the characteristic changes of the driving transistor Tm through external compensation methods, so as to improve the uniformity of the display.

[0035] Indicative Figure 6B Another timing diagram provided for an embodiment of the present invention. Figure 6B (a) The provided timing is capable of driving Figure 3 In a sub-pixel row spH, multiple pixel circuits operate in compensation mode. Figure 6B (b) The provided timing is capable of driving Figure 3 Multiple pixel circuits in a sub-pixel row spH operate in display mode. Here, S1 represents the control signal provided by the first scan line S1, S2 represents the control signal provided by the second scan line S2, S3 represents the control signal provided by the third scan line S3, and Ref is the signal on the reference signal line 40.

[0036] Combination Figure 3In the first time period Z1, the even-numbered pixel circuit 50 in the sub-pixel row spH sequentially executes the initialization phase t1, pre-charging phase t2, discharging phase t3, and sampling phase t4. Specifically, in the initialization phase t1: the first scan line S1 and the third scan line S3 respectively provide high-level enable signals to control the first switch T1 and the second switch T2 to turn on. The first switch T1 turns on and writes the data voltage Vdata to the first node N1 through the data line 10. The second switch T2 turns on and writes the reference signal Vref to the second node N2 through the reference signal line 40. In the pre-charging phase t2: the third scan line S3 provides a de-enable signal to control the second switch T2 to turn off, and the pre-charging voltage Vpre is written onto the reference signal line 40. During the discharge phase t3: The third scan line S3 provides a high-level enable signal to control the second switch T2 to turn on, driving transistor Tm to turn on under the control of the first node N1 potential. The power signal on power line 30 charges the second node N2, charging its potential to Vdata-Vth. Reference signal line 40 is then connected to the second node N2, and its potential changes from Vpre to Vdata-Vth. During the sampling phase t4: The first scan line S1 and the third scan line S3 provide de-enable signals to control the first switch T1 and the second switch T2 to turn off, respectively. The sensing signal Vdata-Vth is acquired via reference signal line 40. This allows the even-numbered pixel circuit 50 in the sub-pixel row spH to acquire the sensing signal via the corresponding reference signal line 40.

[0037] During the second time period Z2, the odd-numbered pixel circuit 50 in the sub-pixel row spH sequentially executes the initialization phase t1, pre-charging phase t2, discharging phase t3, and sampling phase t4. In the initialization phase t1: the second scan line S2 and the third scan line S3 respectively provide high-level enable signals to control the first switch T1 and the second switch T2 to turn on. The first switch T1 turns on and writes the data voltage Vdata to the first node N1 through the data line 10. The second switch T2 turns on and writes the reference signal Vref to the second node N2 through the reference signal line 40. In the pre-charging phase t2: the third scan line S3 provides a de-enable signal to control the second switch T2 to turn off, and the pre-charging voltage Vpre is written onto the reference signal line 40. During the discharge phase t3: The third scan line S3 provides a high-level enable signal to control the second switch T2 to turn on, driving transistor Tm to turn on under the control of the first node N1 potential. The power signal on the power line 30 charges the second node N2, charging its potential to Vdata-Vth. The potential on the reference signal line 40 jumps from Vpre to Vdata-Vth. During the sampling phase t4: The second scan line S2 and the third scan line S3 respectively provide de-enable signals to control the first switch T1 and the second switch T2 to turn off. The sensing signal Vdata-Vth is acquired via the reference signal line 40. This allows the odd-numbered pixel circuit 50 in the sub-pixel row spH to acquire the sensing signal via the corresponding reference signal line 40.

[0038] Figure 6B (b) The provided timing is capable of driving Figure 3 In a sub-pixel row of spH, multiple pixel circuits operate in display mode. Figure 6B (b) time series and Figure 4 The same applies, so I won't repeat it here. Figure 3 The pixel circuit 50 provided in the embodiment can be adopted Figure 6B The schematic timing is used to compensate for the characteristic changes of the driving transistor Tm through external compensation methods, so as to improve the uniformity of the display.

[0039] Figure 6B It indicated Figure 3 In the neutron pixel row spH, the odd-numbered pixel circuit and the even-numbered pixel circuit respectively acquire the timing of the sensing signal. In other embodiments, Figure 6C Another timing diagram provided for an embodiment of the present invention. Figure 6C As illustrated in (a), in compensation mode, the first scan line S1 and the second scan line S2 provide the same signal, so that the odd-numbered pixel circuit and the even-numbered pixel circuit in the pixel circuit row execute the initialization phase t1, the pre-charge phase t2, the discharge phase t3, and the sampling phase t4 together sequentially. That is, the odd-numbered pixel circuit and the even-numbered pixel circuit in the sub-pixel row spH can simultaneously acquire the sensing signal.

[0040] In some implementations, such as Figure 1 or Figure 2 As shown, the display area AA includes a power line 30 and a reference signal line 40 extending along the first direction y. The power line 30 is connected to the power lead 22, and the reference signal line 40 is connected to the reference lead 23. That is, the power lead 22 transmits the signal required by the power line 30, and the reference lead 23 transmits the signal required by the reference signal line 40. Multiple sub-pixels sp are arranged in an array within the display area AA, and each sub-pixel sp requires the power line 30 and the reference signal line 40 to drive. The first data line 11 and the second data line 12 are alternately routed within the display area AA, meaning no other data lines 10 are placed between adjacent first data lines 11 and second data lines 12. A power line 30 and / or a reference signal line 40 are provided between adjacent first data lines 11 and second data lines 12 within the display area AA to ensure that the power line 30 and the reference signal line 40 provide signals to the sub-pixels sp respectively, avoiding excessive distance between the power line 30 and the sub-pixels sp connected to it, which would increase voltage drop and affect display uniformity. This also avoids the problem of excessive distance between the reference signal line 40 and the sub-pixel sp connected to it, which would increase the voltage drop and affect the accuracy of the sensing signal in the compensation mode, thus affecting the uniformity of the display.

[0041] In some implementations, such as Figure 3 and Figure 5As shown, the display area AA includes multiple power lines 30 extending along the first direction y; the power lead 22 includes a first segment 22a and a second segment 22b, the first segment 22a being connected between the power lines 30 and the second segment 22b, the first segment 22a extending along the first direction y, and the extension direction of the second segment 22b forming an acute angle with the first direction y; the power lines 30 and power leads 22 are connected one-to-one. In related technical solutions, multiple power lines are arranged in the display area AA, and a power bus is arranged in the non-display area NA, with the power lines connected to corresponding power terminals (for connection with the display driver chip) through the power bus. The power bus has a certain width in the non-display area, and the power bus and the multiple data leads are located in different film layers, with the two overlapping and insulated. For example, if a first metal layer and a second metal layer are arranged in the display panel, the data lines in the display area are located in the first metal layer, the scan lines are located in the second metal layer, the data leads in the non-display area are located in the first metal layer, and the power bus is arranged in the second metal layer. In related technologies, the power bus is connected to the power terminals by setting up input terminals. However, the number of input terminals is small, and they are basically located at the edge or middle of multiple leads, without any special design for the lead types on both sides of the input terminals. That is, in related technologies, power leads are not arranged between adjacent data leads. In the embodiment of this invention, the power lines 30 and power leads 22 are connected in a one-to-one correspondence. On the one hand, the power leads 22 can play a signal shielding role between adjacent first data leads 211 and second data leads 212, preventing signal crosstalk between adjacent first data leads 211 and second data leads 212 from affecting the display quality. On the other hand, it can also improve the uniformity of voltage drop on each power line 30 within the display area AA, thereby improving display uniformity.

[0042] In some implementations, such as Figure 3 and Figure 5 As shown, the display area AA includes multiple reference signal lines 40 extending along the first direction y; the reference lead 23 includes a third segment 23a and a fourth segment 23b, the third segment 23a connecting the reference signal lines 40 and the fourth segment 23b, the third segment 23a extending along the first direction y, and the extension direction of the fourth segment 23b forming an acute angle with the first direction y; the reference signal lines 40 and the reference leads 23 are connected in a one-to-one correspondence. (Combined with...) Figure 3 and Figure 5From the schematic diagram of the pixel circuit 50's operation, the reference signal line 40 needs to acquire sensing signals when the pixel circuit is operating in compensation mode. By connecting the reference signal line 40 to the reference lead 23 in a one-to-one correspondence, it ensures that each reference signal line 40 acquires a corresponding sensing signal, thereby sensing the characteristics of the driving transistor Tm. Then, in display mode, the sensor-compensated data voltage is used to drive the pixel circuit, achieving external compensation for the characteristics of the driving transistor Tm. Furthermore, when the pixel circuit is operating in display mode, a constant voltage signal is provided to the reference signal line 40 through the reference lead 23. During the normal display phase of the display panel, the reference lead 23, positioned between adjacent first data leads 211 and second data leads 212, acts as a signal shield, thereby reducing signal crosstalk between the first data leads 211 and second data leads 212 that transmit high-frequency data voltages. This improves the accuracy of the data voltage transmitted on the data leads 21, enhancing display quality.

[0043] In some implementations... Figure 7 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 7 The structure of the display panel is shown in a simplified diagram only; the pixel circuits and light-emitting devices within the display area AA are not shown. Figure 7 As shown, the power lead 22 includes a first segment 22a and a second segment 22b. The first segment 22a connects the power line 30 and the second segment 22b, extending along a first direction y. The extension direction of the second segment 22b forms an acute angle with the first direction y. The power line 30 and the power lead 22 are connected in a one-to-one correspondence. The spacing between two adjacent power lines 30 within the display area AA is D1, and the spacing between two first segments 22a of two adjacent power leads 22 within the non-display area NA is D2, where D1 > D2. In this embodiment, the power lines 30 and the power leads 22 are connected in a one-to-one correspondence, and the power leads 22 serve as signal shielding between adjacent first data leads 211 and second data leads 212. Furthermore, the spacing between the two first segments 22a of two adjacent power leads 22 in the non-display area NA is smaller than the spacing between adjacent power lines 30 in the display area AA. Since multiple signal leads are arranged sequentially in the non-display area NA, and there is no need to arrange the transistor structure of pixel circuits in the non-display area NA, the width of each power lead 22 can be set relatively large, thereby making the spacing between the two first segments 22a of two adjacent power leads 22 relatively small. This can appropriately reduce the spacing between the power lead 22 and the adjacent data lead 21, thereby improving the shielding capability of the power lead 22 for high-frequency data signals on the data lead 21.

[0044] like Figure 7As shown, the distance between two second line segments 22b of two adjacent power supply leads 22 is D0, and D0 < D2. Since there is an acute angle between the extending direction of the second line segment 22b and the first direction y, the distance between two adjacent second line segments 22b is calculated based on the distance between the two second line segments 22b in the direction perpendicular to the extending direction of the second line segment 22b.

[0045] In some other embodiments, Figure 8A FIG. 2 is another schematic diagram of a display panel provided by an embodiment of the present invention. Figure 8A Only a simplified schematic diagram of the structure of the display panel is shown, and the pixel circuits and light-emitting devices in the display area AA are not shown. As Figure 8A shown, the display area AA includes a power supply line 30 extending along the first direction y. The power supply lead 22 includes a first line segment 22a and a second line segment 22b. The first line segment 22a is connected between the power supply line 30 and the second line segment 22b. The first line segment 22a extends along the first direction y, and there is an acute angle between the extending direction of the second line segment 22b and the first direction y. It can Figure 8A also be seen that the distance between two adjacent power supply lines 30 is greater than the distance between two first line segments 22a of two adjacent power supply leads 22.

[0046] In addition, it can Figure 8A be seen that the first line segment 22a includes a first sub-segment 2211 and a second sub-segment 2212. The second sub-segment 2212 is connected between the first sub-segment 2211 and the second line segment 22b. Among them, the distance between two adjacent second sub-segments 2212 is D21, and the distance between two adjacent first sub-segments 2211 is D22, where D21 < D22. The signal leads in the non-display area NA are arranged like the power supply lead 22 to have line segments with different extending directions. After the multiple signal leads are led out from the boundary between the display area AA and the non-display area NA, they gradually converge to form a fan-shaped arrangement. Figure 8AIn this embodiment, the second sub-segment 2212 is connected between the first sub-segment 2211 and the second sub-segment 22b. Therefore, compared to the first sub-segment 2211, the second sub-segment 2212 is relatively farther from the display area AA. Setting the spacing between adjacent second sub-segments 2212 to be smaller, that is, the spacing between adjacent power leads 22 near the convergence point of multiple signal leads, is also smaller. For example, the spacing between adjacent first sub-segments 2211 and adjacent second sub-segments 2212 can be made different by adjusting the width of the sub-segments on the power lead 22. On the one hand, setting the spacing between adjacent second sub-segments 2212 to be smaller near the convergence point of multiple signal leads reduces the distance between the data lead 21 and the power lead 22 between the two second sub-segments 2212, thereby enhancing the shielding capability of the power lead 22 for high-frequency signals on the data lead 21. On the other hand, the first segment 2211 and the second segment 2212 can be set to have different widths, so that the line width of the first segment 22a in the power lead 22 gradually changes, avoiding the change in the distribution of the surrounding electromagnetic field caused by the sudden change in line width on the power lead 22, thereby avoiding poor signal transmission caused by the sudden change in line width and signal crosstalk caused by inductive coupling.

[0047] In some implementations, such as Figure 8A As shown, the width of the second sub-segment 2212 is greater than the width of the first sub-segment 2211. By adjusting the width relationship between the first sub-segment 2211 and the second sub-segment 2212, the spacing between two adjacent second sub-segments 2212 can be made smaller than the spacing between two adjacent first sub-segments 2211. This allows for a smaller spacing between two adjacent second sub-segments 2212 near the convergence point of multiple signal leads, reducing the distance between the data lead 21 and the power lead 22, thereby enhancing the shielding capability of the power lead 22 for high-frequency signals on the data lead 21. Furthermore, by gradually changing the linewidth of the first segment 22a in the power lead 22, changes in the surrounding electromagnetic field distribution caused by abrupt changes in linewidth on the power lead 22 can be avoided, thus preventing poor signal transmission caused by abrupt linewidth changes and signal crosstalk caused by inductive coupling.

[0048] In some implementations, such as Figure 8AAs shown, the non-display area NA includes a power bus 60 extending along a second direction x, which intersects with the first direction y. The power bus 60 is electrically connected to power leads 22. Power leads 22 include a first segment 22a and a second segment 22b. The first segment 22a includes a first sub-segment 2211 and a second sub-segment 2212. The second sub-segment 2212 is connected between the first sub-segment 2211 and the second segment 22b. The second sub-segment 2212 is located on the side of the power bus 60 furthest from the display area AA. The presence of a power bus 60 within the non-display area NA, and its electrical connection to the power leads 22, can even out the voltage drop between the power leads 22 within the non-display area NA, improving the uniformity of the power supply voltage on the power lines 30 at the boundary between the display area AA and the non-display area NA, thereby enhancing display uniformity. In addition, the line segment located on the side of the power bus 60 closer to the display area AA is designated as the first sub-segment 2211, and the line segment located on the side of the power bus 60 farther from the display area AA is designated as the second sub-segment 2212. This design achieves a gradual change in the line width of the power lead 22. It also enables the first sub-segments 2211 to be electrically interconnected at the position where the line width decreases through the power bus extending in the second direction x, thereby compensating for the voltage drop change caused by the line width change and improving the uniformity of the power supply voltage drop on each first sub-segment 2211.

[0049] In some implementations, the data lead 21, power lead 22, and reference lead 23 are located on the same layer, and their routing methods are basically the same. They can all be fabricated in the same process, simplifying the manufacturing process. This also results in a relatively simple display panel film layer structure, shorter processing time, and reduced manufacturing costs.

[0050] Figure 8B This is a schematic cross-sectional view of a display panel provided in an embodiment of the present invention. It is used to illustrate the layer relationships within the display panel. Figure 8B The diagram illustrates a first switching transistor T1 located within the display area AA. The film layer layout of the driving transistor Tm and the second switching transistor T2 in the pixel circuit is basically the same as that of the first switching transistor T1. Figure 8B As shown, the display panel includes a substrate 00 and a first metal layer 01, a semiconductor layer 02, and a second metal layer 03 located on one side of the substrate 00. The first metal layer 01, semiconductor layer 02, and second metal layer 03 are sequentially disposed away from the substrate 00. The active layer of the first switching transistor T1 is located on the semiconductor layer 02, and the material of the semiconductor layer 02 includes metal oxides, such as indium gallium zinc oxide. The gate g, source s, and drain d of the first switching transistor T1 are all located on the second metal layer 03. The power line 30, data line 10, and reference signal line 40 within the display area AA are all located on the first metal layer 01. Figure 8BIt can be seen that the drain d of the first switching transistor T1 is connected to the data line 10 through the first via V1 penetrating the insulating layer. It can be understood that the power supply line 30 is connected to the electrode of the driving transistor Tm located in the second metal layer 03 through a corresponding via, and the reference signal line 40 is connected to the electrode of the second switching transistor T2 located in the second metal layer 03 through a corresponding via. In addition, the scanning lines extending along the second direction x as schematically shown in Figure 3 or Figure 5 in the display area AA may be located in the second metal layer 03. <{

[0051] The power supply bus 60 in the non-display area NA is located in the second metal layer 03, and the power supply lead 22 is located in the first metal layer 01. The power supply bus 60 and the power supply lead 22 are connected through the second via V2 penetrating the insulating layer. In addition, the data lead 21 and the reference lead 23 in the non-display area NA are also located in the first metal layer 01.

[0052] As Figure 8B shown, the power supply bus 60 and the power supply lead 22 are located in different layers, and the power supply bus 60 is electrically connected to the power supply lead 22 through the second via V2 penetrating the insulating layer. Due to the different wiring methods of the power supply bus 60 and the power supply lead 22, setting them in different layers can enable each power supply lead 22 to be connected to the power supply bus 60, thereby balancing the voltage drop difference between the power supply leads 22.

[0053] Figure 7 and Figure 8A In the Figure 1 embodiment, the arrangement of each signal line in the display area AA and the arrangement of each lead in the non-display area NA are the same as those in the Figure 2 embodiment. In some other embodiments,

[0054] In the Figure 2 embodiment, it may also be set as in the Figure 8A embodiment that the power supply line 30 and the power supply lead 22 are connected in one-to-one correspondence. The power supply lead 22 includes a first segment 22a and a second segment 22b. The distance between two adjacent power supply lines 30 in the display area AA is D1, and the distance between two adjacent first segments 22a of two power supply leads 22 in the non-display area NA is D2, where D1 > D2. Figure 2In the embodiment, a power bus 60 extending along the second direction x can also be added. The power bus 60 is electrically connected to the power lead 22, and will not be shown in the figure here.

[0055] In some implementations, multiple sub-pixels sp include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, each with a different color; the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel form a pixel unit; the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are respectively one of a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. Combined with... Figure 1 and Figure 3 As shown, red sub-pixels R, green sub-pixels G, blue sub-pixels B, and white sub-pixels W are arranged in the second direction x to form a pixel unit P. Combined with... Figure 2 and Figure 5 As shown, the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W are in a 2:1 ratio. Two elements are arranged to form a pixel unit P. Figure 1 The diagram illustrates that within pixel unit P, the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W are arranged sequentially. It can be understood that the arrangement order of the four color sub-pixels sp can be varied. Figure 1 This only illustrates one possible scenario. For example, pixel unit P could also contain green sub-pixels G, blue sub-pixels B, white sub-pixels W, and red sub-pixels R arranged in that order. Similarly, Figure 2 The arrangement order of the four color sub-pixels sp within the middle pixel unit P is merely illustrative and is not intended to limit the invention.

[0056] like Figure 3 and Figure 5 As shown, the display area AA includes a power line 30 and a reference signal line 40 extending along the first direction y. The power line 30 is connected to the power lead 22, and the reference signal line 40 is connected to the reference lead 23. The display panel includes a signal line X-1 located in the display area AA and a signal lead X-2 located in the non-display area NA. The signal line X-1 includes a data line 10, a power line 30, and a reference signal line 40. The signal lead X-2 includes a data lead 21, a power lead 22, and a reference lead 23. The arrangement order of the signal line X-1 connected to the same pixel unit P is the same as that of the signal lead X-2. Figure 3 For example, the arrangement order of signal line X-1 connected to the same pixel unit P is power line 30, first data line 11, reference signal line 40, second data line 12, power line 30; the arrangement order of signal lead X-2 is power lead 22, first data lead 211, reference lead 23, second data lead 212, power lead 22. The "same arrangement order" here refers to the order in which the transmitted signals are arranged.

[0057] In this embodiment of the invention, the arrangement order of signal lines X-1 connected to the same pixel unit P is the same as that of signal leads X-2. This allows signal lines X-1 in the display area AA to be sequentially connected to signal leads X-2 in the non-display area NA. This satisfies the driving requirements of the wiring in the display area AA for driving the pixel unit P, while also allowing the power leads 22 and reference leads 23 to be arranged in appropriate positions in the non-display area NA. The power leads 22 and / or reference leads 23 serve as signal shielding between adjacent first data leads 211 and second data leads 212, preventing signal crosstalk of high-frequency data voltages between adjacent first data leads 211 and second data leads 212.

[0058] In some implementations, such as Figure 3 or Figure 5 As shown, power lead 22 includes a first segment 22a and a second segment 22b. The first segment 22a is connected between power line 30 and the second segment 22b. The first segment 22a extends along a first direction y, and the extension direction of the second segment 22b forms an acute angle with the first direction y. Reference lead 23 includes a third segment 23a and a fourth segment 23b. The third segment 23a is connected between reference signal line 40 and the fourth segment 23b. The third segment 23a extends along the first direction y, and the extension direction of the fourth segment 23b forms an acute angle with the first direction y. Data lead 21 includes a fifth segment 21a and a sixth segment 21b. The fifth segment 21a is connected between data line 10 and the sixth segment 21b. The fifth segment 21a extends along the first direction y, and the extension direction of the sixth segment 21b forms an acute angle with the first direction y. Optionally, the area within the non-display area NA where multiple signal leads are arranged includes a center line extending along the first direction y, with the signal leads on both sides of the center line being approximately symmetrically designed. On one side of the center line, the second segment 22b, the fourth segment 23b, and the sixth segment 21b extend in the same direction. This ensures that the routing of the power lead 22, the reference lead 23, and the data lead 21 is approximately the same, allowing each signal lead to gradually converge and form a fan-shaped arrangement after being led out from the boundary between the display area AA and the non-display area NA, so that each signal lead can be connected to its corresponding terminal, and the display driver chip provides signals to the signal leads through the corresponding terminals.

[0059] In some implementations... Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 9 This illustrates a portion of the display panel. For example... Figure 9As shown, the display panel includes a first edge Y1 extending along a first direction y; among the signal lines X-1 connected to the same pixel unit P, at least one power line 30 is at a distance from the first edge Y1 that is less than the distance from the data line 10 to the first edge Y1. Figure 9 The diagram illustrates the arrangement of signal lines X-1 connected to the same pixel unit P in the following order: power line 30, first data line 11, reference signal line 40, second data line 12, power line 30. Therefore, at least one power line 30 is less than the distance from the first edge Y1 to the data line 10. Correspondingly, the arrangement of signal leads X-2 connected to the same pixel unit P in the following order: power lead 22, first data lead 211, reference lead 23, second data lead 212, power lead 22. Therefore, at least one power lead 22 is positioned on the side of data lead 21 closest to the first edge Y1. Multiple pixel units P are arranged in an array within the display area AA. Figure 9 The embodiment enables the first and last signal lines X-1 arranged within the display area AA to be power lines 30, and the first and last signal lines X-2 arranged within the non-display area NA to be power lines 22. The first and last power lines 30 arranged within the display area AA can provide signal shielding at the edge of the display area AA, preventing signals from the wiring in the non-display area NA from interfering with the signals on the data lines 10 within the display area AA. Furthermore, the first and last power lines 22 arranged within the non-display area NA can cooperate to shield external signals, preventing interference with the signal lines X-2 within the fan-out area.

[0060] In other implementations, Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 10 This illustrates a portion of the display panel. For example... Figure 10 The display panel shown includes a first edge Y1 extending along a first direction y; among the signal lines X-1 connected to the same pixel unit P, at least one reference signal line 40 is at a distance from the first edge Y1 less than the distance from the data line 10 to the first edge Y1. Figure 10 The diagram illustrates the arrangement of signal lines X-1 connected to the same pixel unit P in the following order: reference signal line 40, first data line 11, power line 30, second data line 12, reference signal line 40. Therefore, at least one reference signal line 40 is less than the distance from the data line 10 to the first edge Y1. Correspondingly, the arrangement of signal leads X-2 connected to the same pixel unit P in the following order: reference lead 23, first data lead 211, power line 22, second data lead 212, reference lead 23. Therefore, at least one reference lead 23 is positioned on the side of data lead 21 closer to the first edge Y1. Multiple pixel units P are arranged in an array within the display area AA. Figure 10 The embodiment enables the first and last signal lines X-1 arranged within the display area AA to serve as reference signal lines 40, and the first and last signal lines X-2 arranged within the non-display area NA to serve as reference lines 23. The first and last reference signal lines 40 arranged within the display area AA can provide signal shielding, at least during the display phase, preventing signals from the wiring in the non-display area NA from interfering with the signals on the data lines 10 within the display area AA. Furthermore, the first and last reference lines 23 arranged within the non-display area NA can cooperate to shield external signals, at least during the display phase, preventing external signals from interfering with the signal lines X-2 within the fan-out area.

[0061] In some embodiments of the present invention, multiple sub-pixels sp include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel with different colors; the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel form a pixel unit P; the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are respectively one of a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged alternately in the second direction x. That is, in a pixel unit P, the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged in the second direction x. Multiple pixel units P are arranged along the second direction x, and multiple pixel units P are arranged along the first direction y.

[0062] Figure 11 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 11 Only two pixel units P within a sub-pixel row spH of the display area AA are shown. Figure 11 Taking the example of a first sub-pixel comprising a red light-emitting device PD-r, a second sub-pixel comprising a green light-emitting device PD-g, a third sub-pixel comprising a blue light-emitting device PD-b, and a fourth sub-pixel comprising a white light-emitting device PD-w, the following is an example: Figure 11 As can be seen, the first and second sub-pixels adjacent in the second direction x are connected to the first data line 11, and the third and fourth sub-pixels adjacent in the second direction x are connected to the second data line 12. A power line 30 is provided between partially adjacent first data lines 11 and second data lines 12, and a reference signal line 40 is provided between partially adjacent first data lines 11 and second data lines 12. That is, in this embodiment, a power line 30 or a reference signal line 40 is provided between adjacent first data lines 11 and second data lines 12, thereby cooperating to meet the driving requirements for driving the pixel circuit 50.

[0063] With the first sub-pixel, second sub-pixel, third sub-pixel, and fourth sub-pixel arranged in the second direction x to form a pixel unit P, a power line 30 or a reference signal line 40 is provided between adjacent first data lines 11 and second data lines 12, so that most of the power lines 30 in the display area AA, except for the edge of the display area AA, will be as follows: Figure 11 The diagram illustrates the connection to four sub-pixel columns arranged in the second x-direction, and a reference signal line 40 is also connected to these four sub-pixel columns. Since the number of sub-pixel columns connected by a power line 30 is not excessive, the power supply voltage received by each sub-pixel sp is relatively uniform. Similarly, since the number of sub-pixel columns connected by a reference signal line 40 is not excessive, the acquisition of sensing signals using the reference signal line 40 in compensation mode will be relatively accurate, and correspondingly, the reference voltage received by each sub-pixel sp is also relatively uniform in display mode.

[0064] In some embodiments of the present invention, such as Figure 9 As shown, the signal leads X-2 connected to the same pixel unit P are arranged in the following order: power lead 22, first data lead 211, reference lead 23, second data lead 212, and power lead 22. From the perspective of the multiple signal leads X-2 arranged within the non-display area NA, the first data lead 211 and the second data lead 212 can be arranged alternately, with the power lead 22 and the reference lead 23 alternately positioned between adjacent first data leads 211 and second data leads 212. This results in either a power lead 22 or a reference lead 23 being positioned between adjacent first data leads 211 and second data leads 212.

[0065] In other implementations, such as Figure 10 As shown, the arrangement order of the signal leads connected to the same pixel unit P is: reference lead 23, first data lead 211, power lead 22, second data lead 212, and reference lead 23. From the perspective of the multiple signal leads X-2 arranged within the non-display area NA as a whole, the first data lead 211 and the second data lead 212 can be arranged alternately, with the power lead 22 and the reference lead 23 alternately positioned between adjacent first data leads 211 and second data leads 212. This results in either a power lead 22 or a reference lead 23 being positioned between adjacent first data leads 211 and second data leads 212.

[0066] Figure 9 and Figure 10All embodiments can provide a power lead 22 or a reference lead 23 between adjacent first data leads 211 and second data leads 212. During the display stage, the power lead 22 or the reference lead 23 can act as a signal shield between adjacent first data leads 211 and second data leads 212, thereby reducing signal crosstalk between the first data leads 211 and second data leads 212 that transmit high-frequency data voltages, improving the accuracy of data voltage transmission on the data leads 21, and improving display quality.

[0067] In some implementations... Figure 12 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 12 The pixel circuit 50 is only shown in a simplified diagram; its structure can be referenced elsewhere. Figure 3 Example. Figure 12 It can be understood as Figure 3 The embodiment shows a simplified structure of a local area within the display region. For example... Figure 12 As shown, the first sub-pixel sp1 includes a first pixel circuit 51, the second sub-pixel sp2 includes a second pixel circuit 52, the third sub-pixel sp3 includes a third pixel circuit 53, and the fourth sub-pixel sp4 includes a fourth pixel circuit 54. Multiple pixel units P are arranged in a pixel unit column PL in the first direction y. The pixel unit column PL includes a circuit unit column, which includes a first pixel circuit column 51L, a second pixel circuit column 52L, a third pixel circuit column 53L, and a fourth pixel circuit column 54L arranged sequentially in the second direction x, where the second direction x intersects the first direction y. The first pixel circuit column 51L includes multiple first pixel circuits 51 arranged in the first direction y, the second pixel circuit column 52L includes multiple second pixel circuits 52 arranged in the first direction y, the third pixel circuit column 53L includes multiple third pixel circuits 53 arranged in the first direction y, and the fourth pixel circuit column 54L includes multiple fourth pixel circuits 54 arranged in the first direction y. Figure 12 The diagram illustrates the signal line connection method for the two pixel unit columns PL within the display area AA.

[0068] Among them, the signal lines connected to the same pixel unit column PL are: The first data line 11 is located between adjacent first pixel circuit columns 51L and second pixel circuit columns 52L, and the second data line 12 is located between the third pixel circuit column 53L and the fourth pixel circuit column 54L. The first data line 11 connects the pixel circuits in the first pixel circuit column 51L and the second pixel circuit column 52L, and the second data line 12 connects the pixel circuits in the third pixel circuit column 53L and the fourth pixel circuit column 54L. The reference signal line 40 is located between the second pixel circuit column 52L and the third pixel circuit column 53L, and the reference signal line 40 connects the four pixel circuit columns in the pixel unit column PL. One power line 30 is located on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L and connects the first pixel circuit column 51L and the second pixel circuit column 52L. Another power line 30 is located on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L. It can be seen that the power line 30 arranged between two adjacent pixel unit columns PL connects to two pixel circuit columns in the two pixel unit columns PL located on its left and right sides, that is, the power line 30 connects four pixel circuit columns.

[0069] Figure 12 In this implementation, the signal lines connected to the same pixel unit P are arranged in the following order: power line 30, first data line 11, reference signal line 40, second data line 12, and power line 30. This can be combined with... Figure 3 The arrangement of signal leads connected to the same pixel unit P is as follows: power lead 22, first data lead 211, reference lead 23, second data lead 212, power lead 22. The arrangement of signal lines connected to the same pixel unit P is the same as the arrangement of signal leads.

[0070] In another implementation, Figure 13 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 13 As shown, in the signal lines connected to the same pixel unit column PL: The first data line 11 is located between adjacent first pixel circuit columns 51L and second pixel circuit columns 52L, and the second data line 12 is located between the third pixel circuit column 53L and the fourth pixel circuit column 54L. The first data line 11 connects the pixel circuits in the first pixel circuit column 51L and the second pixel circuit column 52L, and the second data line 12 connects the pixel circuits in the third pixel circuit column 53L and the fourth pixel circuit column 54L.

[0071] Power line 30 is located between the second pixel circuit column 52L and the third pixel circuit column 53L. Power line 30 connects to four pixel circuit columns 50 in pixel unit column P. A reference signal line 40 is located on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L and connects the first pixel circuit column 51L and the second pixel circuit column 52L. Another reference signal line 40 is located on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L. It can be seen that the reference signal line 40 arranged between two adjacent pixel unit columns PL connects to two pixel circuit columns in the two pixel unit columns PL located on its left and right sides. That is, this reference signal line 40 connects four pixel circuit columns.

[0072] Figure 13 In this implementation, the signal lines connected to the same pixel unit P are arranged in the following order: reference signal line 40, first data line 11, power line 30, second data line 12, and reference signal line 40. (Refer to...) Figure 3 To understand this, if the signal lines in the display area AA are connected sequentially to the signal leads in the non-display area NA, then the arrangement order of the signal leads connected to the same pixel unit P is: reference lead 23, first data lead 211, power lead 22, second data lead 212, reference lead 23. The arrangement order of the signal lines connected to the same pixel unit P is the same as the arrangement order of the signal leads.

[0073] Figure 12 and Figure 13 The embodiment also requires the arrangement of, for example Figure 3 The diagram shows the first scan line S1, the second scan line S2, and the third scan line S3. Figure 12 and Figure 13 Neutron pixel row adopts Figure 4 The provided timing is used for driving. Figure 12 In this embodiment, except for the first power line 30 and the last power line 30 at the edge of the display area which drive two pixel circuit columns respectively, the remaining power lines 30 drive four pixel circuit columns respectively, and a reference signal line 40 drives four pixel circuit columns. Figure 13 In this embodiment, except for the first reference signal line 40 and the last reference signal line 40 at the edge of the display area which drive two pixel circuit columns respectively, the remaining reference signal lines 40 drive four pixel circuit columns respectively, and one power line 30 drives four pixel circuit columns. Figure 12 and Figure 13The embodiment enables the arrangement of a power line 30 or a reference signal line 40 between adjacent first data lines 11 and second data lines 12. Furthermore, when the signal leads in the non-display area NA are sequentially connected to the signal lines in the display area AA, a power line 22 or a reference lead 23 is provided between adjacent first data lines 211 and second data lines 212. This allows the power line 22 or reference lead 23 to act as signal shielding between adjacent first data lines 211 and second data lines 212 during the display phase, reducing signal crosstalk between the first data lines 211 and second data lines 212 transmitting high-frequency data voltages, improving the accuracy of data voltage transmission on the data lines 21, and enhancing display quality.

[0074] and, Figure 12 and Figure 13 In this embodiment, the number of sub-pixel columns connected by a power line 30 will not be too large, so the power supply voltage received by each sub-pixel sp will be relatively uniform, and the number of power lines 30 arranged in the display area AA can also be reduced, which is conducive to improving the display aperture ratio.

[0075] Figure 12 and Figure 13 In this embodiment, the number of sub-pixel columns connected by a single reference signal line 40 will not be too large. In compensation mode, the reference signal line 40 will be used to collect sensing signals more accurately, and correspondingly, in display mode, the reference voltage received by each sub-pixel sp will be relatively uniform.

[0076] in addition, Figure 12 In this embodiment, a reference signal line 40 connects four pixel circuit columns. Figure 13 In this embodiment, except for the first and last reference signal lines 40 at the edge of the display area, the remaining reference signal lines 40 each drive one of the four pixel circuit columns. That is... Figure 12 One reference signal line 40 is shared by four sub-pixel columns. Figure 13 In this embodiment, most of the reference signal lines 40 are shared by four sub-pixel columns. This reduces the number of reference signal lines 40 arranged within the display area AA, thereby improving the display aperture ratio. Furthermore, it reduces the number of reference leads 23 arranged in the non-display area NA, thus reducing the number of contacts directly connected to the data driver integrated circuit (a circuit used to receive sensing signals in compensation mode and generate compensated data voltages based on the sensing signals) in the display driver chip, which helps reduce the manufacturing cost of the display driver chip.

[0077] In other implementations, Figure 14 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 14As shown, a pixel unit P is formed by arranging a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel with different colors in the second direction x. Figure 14 Taking the example of a first sub-pixel comprising a red light-emitting device PD-r, a second sub-pixel comprising a green light-emitting device PD-g, a third sub-pixel comprising a blue light-emitting device PD-b, and a fourth sub-pixel comprising a white light-emitting device PD-w, the arrangement order of the signal leads X-2 connected to the same pixel unit P is as follows: power lead 22, first data lead 211, reference lead 23, power lead 22, second data lead 212, reference lead 23.

[0078] In another embodiment, Figure 14 By swapping the positions of power line 30 and reference signal line 40 in the display area AA, and swapping the positions of power lead 22 and reference lead 23 in the non-display area NA, the arrangement order of signal leads X-2 connected to the same pixel unit P is as follows: reference lead 23, first data lead 211, power lead 22, reference lead 23, second data lead 212, power lead 22. (This is not illustrated in the attached diagram.)

[0079] Figure 14 The embodiment enables the placement of a power lead 22 and a reference lead 23 between adjacent first data leads 211 and second data leads 212. During the display phase, the power lead 22 and the reference lead 23 act as signal shielding between adjacent first data leads 211 and second data leads 212, thereby reducing signal crosstalk between the first data leads 211 and second data leads 212 that transmit high-frequency data voltages, improving the accuracy of data voltage transmission on the data leads 21, and enhancing display quality.

[0080] In addition, by Figure 14 It can also be seen that in this embodiment, the arrangement order of signal lines X-1 connected to the same pixel unit P is the same as the arrangement order of signal leads X-2. That is, each signal line X-1 in the display area AA is sequentially connected to each signal lead X-2 in the non-display area NA.

[0081] In some implementations... Figure 15 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 15 The pixel circuit 50 is only shown in a simplified diagram; its structure can be referenced elsewhere. Figure 3 Example. For example... Figure 15As shown, the first sub-pixel sp1 includes a first pixel circuit 51, the second sub-pixel sp2 includes a second pixel circuit 52, the third sub-pixel sp3 includes a third pixel circuit 53, and the fourth sub-pixel sp4 includes a fourth pixel circuit 54. Multiple pixel units P are arranged in a pixel unit column PL in the first direction y. The pixel unit column PL includes a circuit unit column, which includes a first pixel circuit column 51L, a second pixel circuit column 52L, a third pixel circuit column 53L, and a fourth pixel circuit column 54L arranged sequentially in the second direction x, where the second direction x intersects the first direction y. The first pixel circuit column 51L includes multiple first pixel circuits 51 arranged in the first direction y, the second pixel circuit column 52L includes multiple second pixel circuits 52 arranged in the first direction y, the third pixel circuit column 53L includes multiple third pixel circuits 53 arranged in the first direction y, and the fourth pixel circuit column 54L includes multiple fourth pixel circuits 54 arranged in the first direction y. Figure 12 The diagram illustrates the signal line connection method for the two pixel unit columns PL within the display area AA.

[0082] Among them, the signal lines connected to the same pixel unit column PL are: The first data line 11 is located between adjacent first pixel circuit columns 51L and second pixel circuit columns 52L, and the second data line 12 is located between the third pixel circuit column 53L and the fourth pixel circuit column 54L. The first data line 11 connects the pixel circuits in the first pixel circuit column 51L and the second pixel circuit column 52L, and the second data line 12 connects the pixel circuits in the third pixel circuit column 53L and the fourth pixel circuit column 54L.

[0083] A reference signal line 40 is located between the second pixel circuit column 52L and the third pixel circuit column 53L, and connects the first pixel circuit column 51L and the second pixel circuit column 52L. Another reference signal line 40 is located on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L, and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L. A power line 30 is located on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L, and connects the first pixel circuit column 51L and the second pixel circuit column 52L. Another power line 30 is located between the second pixel circuit column 52L and the third pixel circuit column 53L, and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L. Alternatively, Figure 15The positions of the power line 30 and the reference signal line 40 are interchanged. One power line 30 is positioned between the second pixel circuit column 52L and the third pixel circuit column 53L, connecting the first pixel circuit column 51L and the second pixel circuit column 52L; the other power line 30 is positioned on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L, connecting the third pixel circuit column 53L and the fourth pixel circuit column 54L. One reference signal line 40 is positioned on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L, connecting the first pixel circuit column 51L and the second pixel circuit column 52L; the other reference signal line 40 is positioned between the second pixel circuit column 52L and the third pixel circuit column 53L, connecting the third pixel circuit column 53L and the fourth pixel circuit column 54L. (No further illustration is provided.)

[0084] Figure 15 In this implementation, the signal lines connected to the same pixel unit P are arranged in the following order: power line 30, first data line 11, reference signal line 40, power line 30, second data line 12, reference signal line 40. The signal leads connected to the same pixel unit P are arranged in the following order: power lead 22, first data lead 211, reference lead 23, power lead 22, second data lead 212, reference lead 23. The arrangement order of the signal lines connected to the same pixel unit P is the same as the arrangement order of the signal leads.

[0085] Figure 15 The embodiment also requires the arrangement of, for example Figure 3 The diagram shows the first scan line S1, the second scan line S2, and the third scan line S3. Figure 15 The sub-pixel row extending along the second direction x can be adopted Figure 4 The provided timing is used for driving. use Figure 15 The design of this embodiment enables a power line 30 and a reference signal line 40 to be arranged between adjacent first data lines 11 and second data lines 12. Furthermore, when the signal leads in the non-display area NA are sequentially connected to the signal lines in the display area AA, a power lead 22 and a reference lead 23 are provided between adjacent first data leads 211 and second data leads 212. This allows the power lead 22 and the reference lead 23 to act as signal shielding between adjacent first data leads 211 and second data leads 212 during the display phase, reducing signal crosstalk between the first data leads 211 and second data leads 212 that transmit high-frequency data voltages, improving the accuracy of the data voltage transmitted on the data leads 21, and enhancing display quality.

[0086] and, Figure 15In this embodiment, one power line 30 drives two pixel circuit columns, meaning one power line 30 connects two sub-pixel columns. In other words, the two sub-pixel columns share one power line 30. Since the number of sub-pixel columns connected by one power line 30 is not excessive, the power supply voltage received by each sub-pixel sp is relatively uniform. Sharing the power line 30 also reduces the number of power lines 30 arranged within the display area AA, thereby improving the display aperture ratio.

[0087] Figure 15 In this embodiment, one reference signal line 40 drives two pixel circuit columns, meaning one reference signal line 40 connects two sub-pixel columns. In other words, the two sub-pixel columns share one reference signal line 40. The number of sub-pixel columns connected by one reference signal line 40 is not excessive. In compensation mode, using the reference signal line 40 to acquire sensing signals is relatively accurate, and correspondingly, in display mode, the reference voltage received by each sub-pixel sp is relatively uniform. Sharing the reference signal line 40 also reduces the number of reference signal lines 40 arranged within the display area AA, thereby improving the display aperture ratio. Furthermore, it reduces the number of reference leads 23 arranged in the non-display area NA, thus reducing the number of contacts directly connected to the data driver integrated circuit in the display driver chip, which helps reduce the manufacturing cost of the display driver chip.

[0088] In other implementations, Figure 16 This is another schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 16 As shown, the display area AA includes a power line 30, a data line 10, and a reference signal line 40 extending along the first direction y. The data line 10 includes an adjacent first data line 11 and a second data line 12. The first data line 11 connects two different color sub-pixels, and the second data line 12 connects two different color sub-pixels. The power line 30 includes a first power line 31 and a second power line 32. The non-display area NA includes a data lead 21, a power lead 22, and a reference lead 23. The data lead 21 includes a first data lead 211 connected to the first data line 11 and a second data lead 212 connected to the second data line 12. The reference lead 23 is connected to the reference signal line 40 in a one-to-one correspondence.

[0089] The power lead 22 includes a first segment 22a and a second segment 22b. The first segment 22a is connected between the power line 30 and the second segment 22b. The first segment 22a extends along a first direction y, and the extension direction of the second segment 22b forms an acute angle with the first direction y. The non-display area NA also includes a power bus 60 extending along a second direction x and a connecting line 70 extending along the first direction y. The power lead 22 is connected to the power bus 60, the first power line 31 is connected to the power lead 22, and one end of the connecting line 70 is connected to the second power line 32, and the other end is connected to the power bus 60. A reference lead 23 is provided between adjacent data leads 21. There are n data leads 21 and n reference leads 23 between two adjacent power leads 22, where n is an integer, 2≤n≤6. Figure 16 The example uses n=4.

[0090] In this embodiment, a reference lead 23 is provided between adjacent first data leads 211 and second data leads 212, and a power lead 22 is provided at intervals of n data leads 21 and n reference leads 23. Therefore, overall, a reference lead 23 is provided between partially adjacent first data leads 211 and second data leads 212, and a reference lead 23 and a power lead 22 are provided between partially adjacent first data leads 211 and second data leads 212. During the display stage, the reference lead 23 and the power lead 22 serve as signal shielding, reducing signal crosstalk between the first data leads 211 and second data leads 212 that transmit high-frequency data voltages.

[0091] In addition, the first power line 31 in the display area AA is connected to the power lead 22, and the power lead 22 is connected to the power bus 60. The second power line 32 is connected to the power bus 60 through the connecting wire 70. The power bus 60 provides power voltage to the second power line 32 in the display area AA, and the power bus 60 can balance the voltage drop difference between the first power line 31 and the second power line 32, thereby improving the uniformity of the power supply voltage in the display area AA.

[0092] In some embodiments, the plurality of sub-pixels include a first sub-pixel sp1, a second sub-pixel sp2, a third sub-pixel sp3, and a fourth sub-pixel sp4, each with a different color; the first sub-pixel sp1, the second sub-pixel sp2, the third sub-pixel sp3, and the fourth sub-pixel sp4 are arranged in a second direction x to form a pixel unit P; the first sub-pixel sp1 includes a first pixel circuit 51, the second sub-pixel sp2 includes a second pixel circuit 52, the third sub-pixel sp3 includes a third pixel circuit 53, and the fourth sub-pixel sp4 includes a fourth pixel circuit 54.

[0093] Multiple pixel units P are arranged into a pixel unit column PL in the first direction y. The pixel unit column PL includes a circuit unit column, which includes a first pixel circuit column 51L, a second pixel circuit column 52L, a third pixel circuit column 53L, and a fourth pixel circuit column 54L arranged sequentially in the second direction x. The first pixel circuit column 51L includes multiple first pixel circuits 51 arranged in the first direction y, the second pixel circuit column 52L includes multiple second pixel circuits 52 arranged in the first direction y, the third pixel circuit column 53L includes multiple third pixel circuits 53 arranged in the first direction y, and the fourth pixel circuit column 54L includes multiple fourth pixel circuits 54 arranged in the first direction y.

[0094] Figure 17 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 17 The pixel circuit 50 is only shown in a simplified diagram; its structure can be referenced elsewhere. Figure 3 Example. Figure 17 This illustrates the signal line connection method for the two pixel unit columns PL within the display area AA. For example... Figure 17 As shown, among the signal lines connected to the same pixel unit column PL: the first data line 11 is located between adjacent first pixel circuit columns 51L and second pixel circuit columns 52L, and the second data line 12 is located between the third pixel circuit column 53L and the fourth pixel circuit column 54L; the first data line 11 connects the pixel circuits in the first pixel circuit column 51L and the second pixel circuit column 52L, and the second data line 12 connects the pixel circuits in the third pixel circuit column 53L and the fourth pixel circuit column 54L. One reference signal line 40 is located between the second pixel circuit column 52L and the third pixel circuit column 53L, and connects the second pixel circuit column 52L and the first pixel circuit column 51L; another reference signal line 40 is located on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L, and connects the fourth pixel circuit column 54L and the third pixel circuit column 53L. One power line 30 is located on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L and connects the first pixel circuit column 51L and the second pixel circuit column 52L; another power line 30 is located on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L and connects the fourth pixel circuit column 54L and the third pixel circuit column 53L. In this embodiment, one reference signal line 40 connects two pixel circuit columns, and except for the first and last power lines 30 arranged in the display area that connect to the two pixel circuit columns, the remaining power lines 30 connect to the four pixel circuit columns respectively.

[0095] Figure 17 The embodiment illustrates the signal line routing at the location of the two pixel unit columns PL, combined with Figure 16 Regarding the wiring method within the non-display NA, when n=4, Figure 17The diagram illustrates three power lines 30, where the first and last power lines 30 are the first power lines 31, and the power lines 30 arranged in the middle are the second power lines 32.

[0096] Figure 18 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 18 The diagram illustrates the signal line connection method for the two pixel unit columns PL within the display area AA. Figure 18 and Figure 17 The difference in the embodiments lies in the arrangement of the power line 30 and the reference signal line 40. For example... Figure 18 As shown, among the signal lines connected to the same pixel unit column PL: one reference signal line 40 is located between the first pixel circuit column 51L and the second pixel circuit column 52L, and connects the first pixel circuit column 51L and the second pixel circuit column 52L; another reference signal line 40 is located between the third pixel circuit column 53L and the fourth pixel circuit column 54L, and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L; one power line 30 is located on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L, and connects the first pixel circuit column 51L and the second pixel circuit column 52L; another power line is located on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L, and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L. In this embodiment, one reference signal line 40 connects two pixel circuit columns, and except for the first and last power lines 30 arranged in the display area that connect two pixel circuit columns, the remaining power lines 30 connect to four pixel circuit columns respectively.

[0097] Figure 18 The embodiment illustrates the signal line routing at the location of the two pixel unit columns PL, combined with Figure 16 Regarding the wiring method within the non-display NA, when n=4, Figure 18 The diagram illustrates three power lines 30, where the first and last power lines 30 are the first power lines 31, and the power lines 30 arranged in the middle are the second power lines 32.

[0098] Figure 19 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 19 The diagram illustrates the signal line connection method for the two pixel unit columns PL within the display area AA. Figure 19 and Figure 17 The difference in the embodiments lies in the arrangement of the power line 30 and the reference signal line 40. For example... Figure 19As shown, among the signal lines connected to the same pixel unit column PL: one reference signal line 40 is located between and connects the first pixel circuit column 51L and the second pixel circuit column 52L; another reference signal line 40 is located between and connects the third pixel circuit column 53L and the fourth pixel circuit column 54L; and a power supply line 30 is located between and connects the second pixel circuit column 52L and the third pixel circuit column 53L. In this embodiment, one reference signal line 40 connects two pixel circuit columns, and one power supply line 30 connects four pixel circuit columns.

[0099] Figure 19 In the embodiment, multiple power lines 30 in the display area can also be divided into a first power line 31 and a second power line 32, and referenced Figure 16 The wiring method for the signal leads in the non-display area NA is as follows: the first power line 31 is connected to the power lead 22, the power lead 22 is connected to the power bus 60, and the second power line 32 is connected to the power bus 60 through the connecting line 70.

[0100] Figure 20 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 20 The diagram illustrates the signal line connection method for the two pixel unit columns PL within the display area AA. Figure 20 and Figure 17 The difference in the embodiments lies in the arrangement of the power line 30 and the reference signal line 40. For example... Figure 20 As shown, among the signal lines connected to the same pixel unit column PL: a reference signal line 40 and a power supply line 30 are located between the second pixel circuit column 52L and the third pixel circuit column 53L; another power supply line 30 and another reference signal line 40 are respectively arranged on the side of the fourth pixel circuit column 54L away from the third pixel circuit column 53L, and on the side of the first pixel circuit column 51L away from the second pixel circuit column 52L. In this embodiment, one reference signal line 40 connects two pixel circuit columns, and one power supply line 30 connects two pixel circuit columns.

[0101] Figure 20 In the embodiment, multiple power lines 30 in the display area can also be divided into a first power line 31 and a second power line 32, and referenced Figure 16 In the wiring method for signal leads within the non-display area (NA), a first power line 31 is connected to a power lead 22, which in turn is connected to a power bus 60. A second power line 32 is connected to the power bus 60 via a connecting line 70. For example... Figure 20 The CCP has indicated four power lines 30, which can be set to n=2. The first and third power lines 30 are the first power lines 31, and the second and fourth power lines 30 are the second power lines 32.

[0102] Figures 17 to 20 The example illustrates the wiring of the signal lines within the display area AA. Figures 17 to 20 The wiring method for signal leads in the non-display area corresponding to the embodiment can be adopted as follows: Figure 16 Design of the implementation example.

[0103] Figure 16 In this embodiment, a reference lead 23 is placed between adjacent first data leads 211 and second data leads 212, and a power lead 22 is placed at intervals of n data leads 21 and n reference leads 23. DGLD technology can reduce the number of data lines in the display area, thus reducing the number of data leads in the non-display area. This technology is applied in display panels using DGLD technology. Figure 16 The design concept in this embodiment can be understood as having relatively ample space in the non-display area to arrange signal leads, thereby allowing for appropriate adjustment of the signal lead widths. For example, the line width of data lead 21 is d1, and the line width of power lead 22 is d2, where d1 ≤ d2 ≤ 10. d1. By increasing the line width of the power supply lead 22, the voltage drop on the power supply lead 22 can be reduced, thereby improving the uniformity of power supply voltage transmission.

[0104] In some implementations, such as Figure 7 or Figure 8A As shown, the line width of power lead 22 is greater than that of data lead 21. Power lead 22 includes a first segment 22a and a second segment 22b. The first segment 22a connects the power line 30 and the second segment 22b, extending along a first direction y. The extension direction of the second segment 22b forms an acute angle with the first direction y. Data lead 21 includes a fifth segment 21a and a sixth segment 21b. The fifth segment 21a connects the data line 10 and the sixth segment 21b, extending along the first direction y. The extension direction of the sixth segment 21b forms an acute angle with the first direction y. Comparing the first segment 22a and the fifth segment 21a with the same extension direction, or comparing the oblique segments second segment 22b and sixth segment 21b, the line width of power lead 22 is greater than that of data lead 21. By setting the power lead 22 to have a relatively large linewidth, the impedance of the power lead 22 can be reduced, thereby reducing the voltage drop on the power lead 22 and improving the uniformity of power voltage transmission. In conjunction with the DGLD technology in this invention, the number of data leads 21 in the non-display area of ​​the display panel using DGLD technology is halved, thus providing sufficient space to accommodate the design of the power lead 22 linewidth.

[0105] In some implementations, the line width of data lead 21 is d1, and the line width of power lead 22 is d2, where d1 = d2, meaning that the line widths of data lead 21 and power lead 22 are not designed differently. This helps to reduce the space occupied by multiple signal leads in the non-display area and facilitates narrowing of the bezel.

[0106] like Figure 7 As shown, the data lead 21 has a line width of d1, and the power lead 22 has a line width of d2. <d2≤5 d1. When designing the line width of power supply lead 22, both the power supply voltage drop and the non-display area layout space were considered. Setting d2>d1 can reduce the voltage drop of the transmitted power supply and improve display uniformity; at the same time, d2 should not be set too large to avoid affecting the space occupied by the arrangement of multiple signal leads.

[0107] In some implementations, the linewidth of the reference lead 23 is equal to the linewidth of the data lead 21. Setting the linewidths of both leads to be the same, when both leads are located in the same metal layer, can improve etching uniformity during fabrication and reduce the error between the linewidth of the lead obtained by the etching process and the design value.

[0108] In some implementations... Figure 21 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 21 As shown, the display area AA includes a power line 30, a reference signal line 40, a first data line 11, and a second data line 12. The first data line 11 is connected to a first data lead 211, and the second data line 12 is connected to a second data lead 212. The power lead 22 includes a first segment 22a and a second segment 22b. The first segment 22a is connected between the power line 30 and the second segment 22b, and extends along a first direction y. The extension direction of the second segment 22b forms an acute angle with the first direction y. The reference lead 23 includes a third segment 23a and a fourth segment 23b. The third segment 23a is connected between the reference signal line 40 and the reference lead 23, and extends along the first direction y. The fourth segment 23b extends in the same direction as the second segment 22b. Data lead 21 includes a fifth segment 21a and a sixth segment 21b. The fifth segment 21a connects the data line 10 and the sixth segment 21b, extending along a first direction y. The sixth segment 21b extends in the same direction as the second segment 22b. The spacing between adjacent second segments 22b and sixth segments 21b is D3, and the spacing between adjacent fourth segments 23b and sixth segments 21b is D4. <D4。

[0109] In this embodiment, the second segment 22b of the power lead 22, the fourth segment 23b of the reference lead 23, and the sixth segment 21b of the data lead 21 are all oblique segments. By setting each signal lead to an oblique segment, multiple signal leads can be drawn out from the boundary between the display area AA and the non-display area NA and gradually converge and arrange themselves into a fan shape, ultimately extending multiple signal leads to the location of the signal terminal (used for connection with the display driver chip). Based on the explanation of the pixel circuit's working principle in the aforementioned embodiments, it can be seen that the power lead 22 provides a constant voltage signal to the power line 30 in both the compensation mode and display mode of the pixel circuit operation; while the reference lead 23 is used to transmit the sensing signal collected by the reference signal line 40 in the compensation mode of the pixel circuit operation and to provide a constant voltage signal to the reference signal line 40 in the display mode of the pixel circuit operation. In this embodiment of the invention, the spacing between adjacent second segment 22b and sixth segment 21b is smaller than the spacing between adjacent fourth segment 23b and sixth segment 21b; that is, the spacing between adjacent power leads 22 and data leads 21 in the diagonal segments is smaller. By differentiating the spacing between adjacent signal leads with different functions, the shielding capability of the power lead 22 on the high-frequency data voltage on the data lead 21 can be enhanced at the location of the power lead 22, effectively reducing signal crosstalk.

[0110] For example, the width of the power lead 22 is greater than the spacing between the power lead 22 and the adjacent data lead 21. While meeting space requirements, making the width of the power lead 22 larger can reduce the voltage drop of the transmitted power supply and increase the spacing between the data leads 21 on both sides of the power lead 22, thus reducing signal crosstalk between the data leads 21.

[0111] For example, the width of the power lead 22 is greater than the spacing between the data lead 21 and the adjacent reference lead 23. Making the power lead 22 wider while meeting space requirements can reduce the voltage drop across the transmitted power supply.

[0112] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 22 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 22 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel 100 has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product.

[0113] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area; the display area includes multiple sub-pixels and multiple data lines extending along a first direction, the data lines include adjacent first data lines and second data lines, one first data line connects two sub-pixels of different colors, and one second data line connects two sub-pixels of different colors; The non-display area includes data leads, power leads, and reference leads. The data leads include a first data lead and a second data lead; the first data lead is connected to a first data line, and the second data lead is connected to a second data line. The power supply lead and / or the reference lead are disposed between adjacent first data leads and second data leads.

2. The display panel according to claim 1, characterized in that, The display area includes a power line and a reference signal line extending along the first direction, wherein the power line is connected to the power lead and the reference signal line is connected to the reference lead; The sub-pixel includes a light-emitting device and a pixel circuit, and the pixel circuit includes a driving transistor, a first switching transistor, a second switching transistor, and a storage capacitor; The control terminal of the driving transistor is connected to the first node, the first electrode is connected to the power line, and the second electrode is connected to the second node. The first electrode of the first switching transistor is connected to the data line, and the second electrode is connected to the first node. The first electrode of the second switching transistor is connected to the reference signal line, and the second electrode is connected to the second node. One plate of the storage capacitor is connected to the first node, and the other plate is connected to the second node.

3. The display panel according to claim 1, characterized in that, The display area includes a power line and a reference signal line extending along the first direction, wherein the power line is connected to the power lead and the reference signal line is connected to the reference lead; The power line and / or the reference signal line are provided between adjacent first data lines and second data lines.

4. The display panel according to claim 1, characterized in that, The display area includes multiple power lines extending along the first direction; each power lead includes a first segment and a second segment, the first segment connecting the power line and the second segment, the first segment extending along the first direction, and the extension direction of the second segment having an acute angle with the first direction; the power line and the power lead are connected in a one-to-one correspondence. And / or, the display area includes multiple reference signal lines extending along the first direction; the reference lead includes a third segment and a fourth segment, the third segment connecting the reference signal line and the fourth segment, the third segment extending along the first direction, and the extension direction of the fourth segment having an acute angle with the first direction; the reference signal line and the reference lead are connected in a one-to-one correspondence.

5. The display panel according to claim 4, characterized in that, The spacing between two adjacent power lines is D1, and the spacing between the two first segments of two adjacent power leads is D2, wherein D1>D2.

6. The display panel according to claim 1, characterized in that, The display area includes a power line extending along the first direction. The power line includes a first segment and a second segment. The first segment is connected between the power line and the second segment. The first segment extends along the first direction, and the extension direction of the second segment has an acute angle with the first direction. The first line segment includes a first sub-segment and a second sub-segment, with the second sub-segment connecting the first sub-segment and the second line segment; wherein the spacing between two adjacent second sub-segments is smaller than the spacing between two adjacent first sub-segments.

7. The display panel according to claim 6, characterized in that, The width of the second sub-segment is greater than the width of the first sub-segment.

8. The display panel according to claim 6, characterized in that, The non-display area includes a power bus extending along a second direction, which intersects the first direction; The power bus is electrically connected to the power leads; wherein... The second sub-segment is located on the side of the power bus away from the display area.

9. The display panel according to claim 1, characterized in that, The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, each with a different color; the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel constitute a pixel unit; The display area includes a power line and a reference signal line extending along the first direction, wherein the power line is connected to the power lead and the reference signal line is connected to the reference lead; The display panel includes signal lines located in the display area and signal leads located in the non-display area. The signal lines include data lines, power lines, and reference signal lines. The signal leads include data leads, power leads, and reference leads. The arrangement order of the signal lines connected to the same pixel unit is the same as the arrangement order of the signal leads.

10. The display panel according to claim 9, characterized in that, The power lead includes a first segment and a second segment, the first segment being connected between the power lead and the second segment; the first segment extends along the first direction, and the extension direction of the second segment forms an acute angle with the first direction; The reference lead includes a third segment and a fourth segment, the third segment connecting the reference signal line and the fourth segment; the third segment extends along the first direction, and the extension direction of the fourth segment forms an acute angle with the first direction; The data lead includes a fifth segment and a sixth segment, the fifth segment being connected between the data line and the sixth segment; the fifth segment extends along the first direction, and the extension direction of the sixth segment forms an acute angle with the first direction.

11. The display panel according to claim 9, characterized in that, The display panel includes a first edge extending along the first direction; In the signal lines connected to the same pixel unit, at least one power line is less than the distance from the data line to the first edge; or, At least one of the reference signal lines is less than the distance of the data line to the first edge.

12. The display panel according to claim 9, characterized in that, The first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged alternately in a second direction, which intersects with the first direction; The first and second sub-pixels adjacent in the second direction are connected to the first data line, and the third and fourth sub-pixels adjacent in the second direction are connected to the second data line; wherein, The power line or the reference signal line is provided between adjacent first data lines and second data lines.

13. The display panel according to claim 9, characterized in that, The arrangement order of the signal leads connected to the same pixel unit is: power lead, first data lead, reference lead, second data lead, power lead; Alternatively, the arrangement order of the signal leads connected to the same pixel unit may be: the reference lead, the first data lead, the power supply lead, the second data lead, and the reference lead.

14. The display panel according to claim 13, characterized in that, The first sub-pixel includes a first pixel circuit, the second sub-pixel includes a second pixel circuit, the third sub-pixel includes a third pixel circuit, and the fourth sub-pixel includes a fourth pixel circuit. A plurality of pixel units are arranged in a pixel unit column in the first direction. The pixel unit column includes a circuit unit column. The circuit unit column includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column arranged sequentially in a second direction, which intersects the first direction. The first pixel circuit column includes a plurality of first pixel circuits arranged in the first direction; the second pixel circuit column includes a plurality of second pixel circuits arranged in the first direction; the third pixel circuit column includes a plurality of third pixel circuits arranged in the first direction; and the fourth pixel circuit column includes a plurality of fourth pixel circuits arranged in the first direction. In the signal lines connected to the same column of pixel units: The first data line is located between the adjacent first pixel circuit column and the second pixel circuit column, and the second data line is located between the third pixel circuit column and the fourth pixel circuit column; The reference signal line is located between the second pixel circuit column and the third pixel circuit column. The reference signal line connects four pixel circuit columns in the pixel unit column. One power line is located on the side of the first pixel circuit column away from the second pixel circuit column and connects the first pixel circuit column and the second pixel circuit column. The other power line is located on the side of the fourth pixel circuit column away from the third pixel circuit column and connects the third pixel circuit column and the fourth pixel circuit column. Alternatively, the power line is located between the second pixel circuit column and the third pixel circuit column, the power line connects four pixel circuit columns in the pixel unit column, one reference signal line is located on the side of the first pixel circuit column away from the second pixel circuit column and connects the first pixel circuit column and the second pixel circuit column, and another reference signal line is located on the side of the fourth pixel circuit column away from the third pixel circuit column and connects the third pixel circuit column and the fourth pixel circuit column.

15. The display panel according to claim 9, characterized in that, The arrangement order of the signal leads connected to the same pixel unit is: power lead, first data lead, reference lead, power lead, second data lead, reference lead; Alternatively, the arrangement order of the signal leads connected to the same pixel unit may be: the reference lead, the first data lead, the power lead, the reference lead, the second data lead, and the power lead.

16. The display panel according to claim 15, characterized in that, The first sub-pixel includes a first pixel circuit, the second sub-pixel includes a second pixel circuit, the third sub-pixel includes a third pixel circuit, and the fourth sub-pixel includes a fourth pixel circuit. A plurality of pixel units are arranged in a pixel unit column in the first direction. The pixel unit column includes the circuit unit column. The circuit unit column includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column arranged sequentially in a second direction, which intersects the first direction. The first pixel circuit column includes a plurality of first pixel circuits arranged in the first direction; the second pixel circuit column includes a plurality of second pixel circuits arranged in the first direction; the third pixel circuit column includes a plurality of third pixel circuits arranged in the first direction; and the fourth pixel circuit column includes a plurality of fourth pixel circuits arranged in the first direction. In the signal lines connected to the same column of pixel units: The first data line is located between the adjacent first pixel circuit column and the second pixel circuit column, and the second data line is located between the third pixel circuit column and the fourth pixel circuit column; One reference signal line is located between the second pixel circuit column and the third pixel circuit column, and connects the first pixel circuit column and the second pixel circuit column; another reference signal line is located on the side of the fourth pixel circuit column away from the third pixel circuit column, and connects the third pixel circuit column and the fourth pixel circuit column; one power line is located on the side of the first pixel circuit column away from the second pixel circuit column, and connects the first pixel circuit column and the second pixel circuit column; another power line is located between the second pixel circuit column and the third pixel circuit column, and connects the third pixel circuit column and the fourth pixel circuit column. Alternatively, one power line is located between the second pixel circuit column and the third pixel circuit column and connects the first pixel circuit column and the second pixel circuit column; another power line is located on the side of the fourth pixel circuit column away from the third pixel circuit column and connects the third pixel circuit column and the fourth pixel circuit column; one reference signal line is located on the side of the first pixel circuit column away from the second pixel circuit column and connects the first pixel circuit column and the second pixel circuit column; and another reference signal line is located between the second pixel circuit column and the third pixel circuit column and connects the third pixel circuit column and the fourth pixel circuit column.

17. The display panel according to claim 1, characterized in that, The power supply lead has a wider wire width than the data lead.

18. The display panel according to claim 1, characterized in that, The data lead has a line width of d1, and the power lead has a line width of d2, where d1 ≤ d2 ≤ 5. d1.

19. The display panel according to claim 1, characterized in that, The line width of the reference lead is equal to the line width of the data lead.

20. The display panel according to claim 1, characterized in that, The data leads, the power leads, and the reference leads are located on the same layer.

21. The display panel according to claim 1, characterized in that, The display area includes power lines and reference signal lines; The power lead includes a first segment and a second segment. The first segment is connected between the power lead and the second segment. The first segment extends along the first direction, and the extension direction of the second segment has an acute angle with the first direction. The reference lead includes a third segment and a fourth segment. The third segment connects the reference signal line and the reference lead. The third segment extends along the first direction, and the fourth segment extends in the same direction as the second segment. The data lead includes a fifth segment and a sixth segment. The fifth segment connects the data line and the sixth segment. The fifth segment extends along the first direction, and the sixth segment extends in the same direction as the second segment. The spacing between adjacent second and sixth line segments is D3, and the spacing between adjacent fourth and sixth line segments is D4. <D4。 22. The display panel according to claim 1, characterized in that, The power lead includes a first segment and a second segment, the first segment being connected between the power lead and the second segment; the first segment extends along the first direction, and the extension direction of the second segment forms an acute angle with the first direction; The display area includes a power line extending along the first direction, the power line including a first power line and a second power line; the non-display area includes a power bus extending along a second direction and a connecting line extending along the first direction, the second direction intersecting the first direction. The power lead is connected to the power bus, the first power line is connected to the power lead, one end of the connecting line is connected to the second power line, and the other end is connected to the power bus; A reference lead is provided between adjacent data leads; The non-display area includes multiple power leads, with n data leads and n reference leads spaced apart between two adjacent power leads, where n is an integer, 2≤n≤6.

23. The display panel according to claim 22, characterized in that, The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel with different colors; the first sub-pixel, the second sub-pixel, the third sub-pixel, and the fourth sub-pixel are arranged in the second direction to form a pixel unit; the first sub-pixel includes a first pixel circuit, the second sub-pixel includes a second pixel circuit, the third sub-pixel includes a third pixel circuit, and the fourth sub-pixel includes a fourth pixel circuit; A plurality of pixel units are arranged in a pixel unit column in the first direction. The pixel unit column includes the circuit unit column. The circuit unit column includes a first pixel circuit column, a second pixel circuit column, a third pixel circuit column, and a fourth pixel circuit column arranged sequentially in the second direction. The first pixel circuit column includes a plurality of first pixel circuits arranged in the first direction. The second pixel circuit column includes a plurality of second pixel circuits arranged in the first direction. The third pixel circuit column includes a plurality of third pixel circuits arranged in the first direction. The fourth pixel circuit column includes a plurality of fourth pixel circuits arranged in the first direction. In the signal lines connected to the same column of pixel units: The first data line is located between the first pixel circuit column and the second pixel circuit column, and the second data line is located between the third pixel circuit column and the fourth pixel circuit column; wherein, One of the reference signal lines is located between the second pixel circuit column and the third pixel circuit column, and another reference signal line is located on the side of the fourth pixel circuit column away from the third pixel circuit column. One power line is located on the side of the first pixel circuit column away from the second pixel circuit column, and another power line is located on the side of the fourth pixel circuit column away from the third pixel circuit column. Alternatively, one of the reference signal lines is located between the first pixel circuit column and the second pixel circuit column, another reference signal line is located between the third pixel circuit column and the fourth pixel circuit column, one power line is located on the side of the first pixel circuit column away from the second pixel circuit column, and another power line is located on the side of the fourth pixel circuit column away from the third pixel circuit column. Alternatively, one of the reference signal lines is located between the first pixel circuit column and the second pixel circuit column, another reference signal line is located between the third pixel circuit column and the fourth pixel circuit column, and the power line is located between the second pixel circuit column and the third pixel circuit column; Alternatively, one of the reference signal lines and one of the power lines are located between the second pixel circuit column and the third pixel circuit column; another power line and another reference signal line are respectively arranged on the side of the fourth pixel circuit column away from the third pixel circuit column and on the side of the first pixel circuit column away from the second pixel circuit column.

24. The display panel according to claim 22, characterized in that, The data lead has a line width of d1, and the power lead has a line width of d2, where d1 ≤ d2 ≤ 10. d1.

25. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1 to 24.

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