Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a driving circuit; the driving circuit comprises N stages of shifting registers which are cascaded with one another; in the same shift register, a first node control module is used for receiving an input signal and a scanning control signal and controlling a signal of a first node; the second node control module is used for receiving a scanning control signal, a first reset clock signal and a first voltage signal and controlling a signal of a second node; the first mutual control module is used for receiving a second voltage signal and a signal of a first node and controlling a signal of a second node; the first voltage stabilization control module is used for receiving a third voltage signal and a signal of a first node and controlling the signal of a third node; the second mutual control module is used for receiving the second voltage signal, the signal of the second node and the signal of the third node and controlling the signal of the first node; and the output module is used for receiving a signal of the first node, a signal of the second node, a second voltage signal and a second clock signal, and controlling a gate driving signal of an output end.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In the display panel industry, integrated gate-driven array (GOA) technology has become the mainstream technology due to its ability to save chip costs and achieve narrow bezels. Low-temperature polycrystalline silicon (LTPS) technology is widely used in many display devices due to its advantages such as high electron mobility, high resolution, and low power consumption.

[0003] To reduce costs, LTPS products in the display field are gradually switching from the traditional C-MOS (Complementary Metal-Oxide-Semiconductor) process to the N-MOS (N-type Metal-Oxide-Semiconductor) process.

[0004] However, the anti-interference capability and stability of the GOA circuit in N-MOS products are lower than those of C-MOS circuits. Especially in high-temperature and high-brightness applications, N-MOS devices are prone to characteristic shifts after prolonged operation, leading to abnormal node potentials within the GOA circuit, which in turn causes output signal failure and results in abnormalities such as horizontal stripes and flickering on the display. Summary of the Invention

[0005] This invention provides a display panel and display device that can solve the problem of inaccurate gate drive signals caused by transistor leakage in shift registers, thereby improving the display effect of the display panel.

[0006] According to one aspect of the present invention, a display panel is provided, comprising: a driving circuit; The driving circuit includes at least one set of N-stage shift registers cascaded together; the shift registers include a first node control module, a second node control module, a first voltage regulation control module, a first mutual control module, a second mutual control module, and an output module; In the same shift register: The first node control module is used to receive input signals and scan control signals, and to control the signals of the first node; The second node control module is used to receive the scan control signal, the first reset clock signal, and the first voltage signal, and to control the signals of the second node; The first mutual control module is used to receive the second voltage signal and the signal from the first node, and to control the signal from the second node; The first voltage regulation control module is used to receive the third voltage signal and the signal from the first node, and to control the signal from the third node; The second mutual control module is used to receive the second voltage signal, the signal of the second node, and the signal of the third node, and to control the signal of the first node; The output module is used to receive the signal from the first node, the signal from the second node, the second voltage signal, and the second clock signal, and to control the gate drive signal at the scan output terminal. Wherein, the gate drive signal of the shift register of the i-th stage is the input signal of the shift register of the j-th stage; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

[0007] According to another aspect of the present invention, a display panel is provided, comprising: a driving circuit; The driving circuit includes at least one set of N-stage shift registers cascaded together; the shift registers include a first node control module, a second node control module, a first mutual control module, a first transistor, a second transistor, a third transistor, and an output module; In the same shift register: The first node control module is used to receive input signals and scan control signals, and to control the signals of the first node; The second node control module is used to receive the scan control signal, the first reset clock signal, and the first voltage signal, and to control the signals of the second node; The first mutual control module is used to receive the second voltage signal and the signal from the first node, and to control the signal from the second node; The gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor receives the third voltage signal, and the second terminal of the first transistor is electrically connected to the third node; The first terminal of the second transistor receives the second voltage signal, the gate of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the third node; The first electrode of the third transistor is electrically connected to the third node, the gate of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the first node; The output module is used to receive the signal from the first node, the signal from the second node, the second voltage signal, and the second clock signal, and to control the gate drive signal of the scan output terminal. Wherein, the gate drive signal of the shift register of the i-th stage is the input signal of the shift register of the j-th stage; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

[0008] According to another aspect of the present invention, a display device is provided, comprising: the display panel described above.

[0009] In this embodiment of the invention, a first node control module is configured to control the signals of the first node based on input signals and scan control signals. A second node control module is configured to control the signals of the second node based on scan control signals, a first reset clock signal, and a first voltage signal. An output module is configured to control the gate drive signal at the scan output terminal based on the signals of the first node, the second node, a second voltage signal, and a second clock signal, thereby driving the pixel circuit to perform corresponding light emission and display. Furthermore, a first mutual control module is configured to ensure that the second node is disabled when the first node is enabled, and a second mutual control module is configured to ensure that the first node is disabled when the second node is enabled. Furthermore, the first voltage regulation control module is electrically connected to the second mutual control module at the third node. When the signal at the first node is at the enable level, the signal at the third node becomes the third voltage signal. This achieves isolation between the second voltage signal and the first node, preventing the second voltage signal from being written to the first node when the second mutual control module fails to turn off properly, and preventing signal inaccuracies at the first node due to leakage current when the second mutual control module can turn off properly. This effectively improves the accuracy and stability of the signal at the first node, thereby ensuring the stability and accuracy of the gate drive signal output by the output module. It also effectively avoids problems such as horizontal stripes, flickering, or bright lines on the display screen, thus effectively improving the display effect of the display panel.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention. Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 12 and Figure 13 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 14 and Figure 15 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention; Figure 17 and Figure 18 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention; Figure 19 This is a timing diagram of a shift register driver provided in an embodiment of the present invention; Figure 20 This is a driving timing diagram of a display panel provided in an embodiment of the present invention; Figure 21 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 22 This is a driving timing diagram for another display panel provided in an embodiment of the present invention; Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0013] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0014] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0015] As introduced in the background section, traditional GOA circuits use the C-MOS process, incorporating both N-type and P-type MOSFETs, offering advantages such as low power consumption, strong anti-interference capabilities, and high driving power. However, the C-MOS process requires the integration of both N-type and P-type transistors, resulting in a large number of photomasks, complex manufacturing processes, and high production costs. Therefore, the traditional C-MOS process is gradually being replaced by a single type of N-type metal-oxide-semiconductor process (i.e., N-MOS process). Its simpler process reduces the number of photomasks, thus lowering costs. However, under the same design specifications, the reliability of the GOA circuit in N-MOS products is somewhat lower than that of C-MOS process display panels. Especially under high-temperature environments and high display brightness conditions, the threshold voltage of the N-type MOSFET will shift significantly, leading to an increase in the transistor's off-state current. This disrupts the voltage of critical nodes within the GOA circuit, causing distortion of the output signal waveform. This results in the inability to accurately drive the pixel circuit for accurate display, causing problems such as horizontal stripes, flickering, or bright lines in the displayed image, severely affecting the display effect.

[0016] To address the aforementioned technical problems, embodiments of the present invention provide a display panel, comprising: a driving circuit; the driving circuit includes N cascaded shift registers; each shift register includes a first node control module, a second node control module, a first voltage regulation control module, a first mutual control module, a second mutual control module, and an output module; within the same shift register: the first node control module receives an input signal and a scan control signal to control the signal of the first node; the second node control module receives a scan control signal, a first reset clock signal, and a first voltage signal to control the signal of the second node; the first mutual control module receives a second voltage signal... The signal and the signal of the first node control the signal of the second node; the first voltage regulation control module is used to receive the third voltage signal and the signal of the first node, and control the signal of the third node; the second mutual control module is used to receive the second voltage signal, the signal of the second node and the signal of the third node, and control the signal of the first node; the output module is used to receive the signal of the first node, the signal of the second node, the second voltage signal and the second clock signal, and control the gate drive signal of the scan output terminal; wherein, the gate drive signal of the i-th stage shift register is the input signal of the j-th stage shift register; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

[0017] By adopting the above technical solution, a first node control module is set to control the signal of the first node according to the input signal and the scan control signal. A second node control module is set to control the signal of the second node according to the scan control signal, the first reset clock signal, and the first voltage signal. An output module is set to control the gate drive signal of the scan output terminal according to the signals of the first node, the second node, the second voltage signal, and the second clock signal, thereby driving the pixel circuit to perform corresponding light emission display. Furthermore, a first mutual control module is set to ensure that the second node is disabled when the first node is enabled, and a second mutual control module is set to ensure that the first node is disabled when the second node is enabled. Furthermore, the first voltage regulation control module is electrically connected to the second mutual control module at the third node. When the signal at the first node is at the enable level, the signal at the third node becomes the third voltage signal. This achieves isolation between the second voltage signal and the first node, preventing the second voltage signal from being written to the first node when the second mutual control module fails to turn off properly, and preventing signal inaccuracies at the first node due to leakage current when the second mutual control module can turn off properly. This effectively improves the accuracy and stability of the signal at the first node, thereby ensuring the stability and accuracy of the gate drive signal output by the output module. It also effectively avoids problems such as horizontal stripes, flickering, or bright lines on the display screen, thus effectively improving the display effect of the display panel.

[0018] The above is the core idea of ​​this invention. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention. The technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 1 and Figure 2 The display panel 100 includes a driving circuit 10; the driving circuit 10 includes at least one set of N-stage shift registers G (G1, G2, ..., Gi, ..., Gj, ..., Gn-1, Gn) cascaded together; the shift register G includes a first node control module 110, a second node control module 120, a first voltage regulation control module 130, a first mutual control module 140, a second mutual control module 150, and an output module 160; in the same shift register G: the first node control module 110 is used to receive the input signal Inf and the scan control signal U2d, and control the signal of the first node N1; the second node control module 120 is used to receive the scan control signal U2d, the first reset clock signal Rstf, and the first voltage signal Vgh, and control the signal of the second node N2; the first mutual control module 140 is used to receive... The second voltage signal Vgl and the signal of the first node N1 control the signal of the second node N2; the first voltage regulation control module 130 is used to receive the third voltage signal Vdd and the signal of the first node N1 to control the signal of the third node N3; the second mutual control module 150 is used to receive the second voltage signal Vgl, the signal of the second node N2 and the signal of the third node N3 to control the signal of the first node N1; the output module 160 is used to receive the signal of the first node N1, the signal of the second node N2, the second voltage signal Vgl and the output control signal out to control the gate drive signal Gout of the scan output terminal; wherein, the gate drive signal Gout of the i-th stage shift register Gi is the input signal Inf of the j-th stage shift register Gj; i, j and N are all positive integers, i≠j and i and j are both less than or equal to N.

[0020] For example, the driving circuit 10 can be located in the non-display area A1 of the display panel 100, and the pixel circuit 20 can be located in the display area A2. This allows the display area A2 to have a higher pixel density, which is beneficial to improving the display effect.

[0021] Continue to refer to Figure 2 and Figure 3The scan output terminal GOUT of the i-th stage shift register Gi can be electrically connected to the signal input terminal INF of the y-th stage shift register Gj. This allows the gate drive signal Gout(i) of the i-th stage shift register Gi to be the input signal Inf of the j-th stage shift register Gj. The i-th stage shift register Gi and the j-th stage shift register Gj can be two adjacent shift registers, in which case j can be equal to i+1. Alternatively, the i-th stage shift register Gi and the j-th stage shift register Gj can also be two non-adjacent shift registers, in which case ji can be a positive integer greater than or equal to 2. Under the premise of achieving the core inventive points of this embodiment, the values ​​of i and j are not specifically limited in this embodiment.

[0022] For ease of description, unless otherwise specified, the embodiments of the present invention will use the i-th level shift register Gi and the j-th level shift register Gj as two adjacent shift registers as examples to illustrate the technical solutions of the embodiments of the present invention.

[0023] Continue to refer to Figure 1 and Figure 2 In the same shift register G, the first node control module 110 and the output module 160 are electrically connected to the first node N1. The first node control module 110 receives the input signal Inf, which is electrically connected to the signal input terminal INF, and the scan control terminal U2D, which is electrically connected to receive the scan control signal U2d. For the first-stage shift register G1, its signal input terminal INF can be electrically connected to the start signal terminal STV, so that its input signal Inf can be the start signal Stv provided by the start signal terminal STV, so that the first-stage shift register G1 can at least respond to the start signal Stv and the scan control signal U2d to provide corresponding signals to the first node N1. For shift registers G other than the first-stage shift register G1, their signal input terminal INF can be electrically connected to the scan output terminal GOUT of the previous-stage shift register G, so that their input signal Inf is the gate drive signal Gout output by the previous-stage shift register G. This allows each stage of shift register G to provide corresponding signals to the first node N1 in response to at least the gate drive signal Gout of the previous-stage shift register G and the scan control signal U2d. In an exemplary embodiment, when the input signal Inf is at the enable level, the signal controlled by the first node control unit 110 to the first node N1 is the same as the scan control signal U2d.

[0024] The second node control module 120 is electrically connected to the output module 160 at the second node N2. The second node control module 120 is also electrically connected to the scan control terminal U2D, the first reset clock terminal RSFT, and the first voltage terminal VGH, respectively, to receive the scan control signal U2d, the first reset clock signal RSFT, and the first voltage signal Vgh. It is capable of providing corresponding signals to the second node N2 in response to the scan control signal U2d, the first reset clock signal RSFT, and the first voltage signal Vgh. In an exemplary embodiment, when the scan control signal U2d and the first reset clock signal RSFT are at the enable level, the signal controlled by the second node control module 120 at the second node N2 is the same as the first voltage signal Vgh.

[0025] The output module 160 is electrically connected to the first node N1, the second node N2, the second voltage terminal VGL, and the output control terminal OUT, respectively, to receive the signals of the first node N1, the second node N2, the second voltage signal VGL, and the output control signal OUT. When the signal of the first node N1 is at the enable level, the control gate drive signal Gout is kept consistent with the output control signal OUT, and when the signal of the second node N2 is at the enable level, the control gate drive signal Gout is kept consistent with the second voltage signal Vck.

[0026] The gate drive signal Gout is provided to the pixel circuit 20 in the display area A2 through the scan signal line. When the gate drive signal Gout is enabled, it can control the corresponding transistor in the pixel circuit 20 to turn on, and when the gate drive signal Gout is disabled, it can control the corresponding transistor in the pixel circuit 20 to turn off, so that the pixel circuit 20 can drive the light-emitting element to emit light at least in response to the gate drive signal Gout.

[0027] It is understood that when the transistor electrically connected to the scan output terminal of the shift register G is an NMOS transistor, the enable level of the gate drive signal Gout is a high voltage signal, and the disable level of the gate drive signal Gout is a low voltage signal. Conversely, when the transistor electrically connected to the scan output terminal of the shift register G is a PMOS transistor, the enable level of the gate drive signal Gout is a low voltage, and the disable level of the gate drive signal Gout is a high voltage. This embodiment of the invention does not specifically limit this. Accordingly, the enable levels of each signal mentioned in this embodiment of the invention can be signals capable of controlling the conduction of modules or transistors electrically connected to that signal, while the disable levels of each signal are signals controlling the conduction and deactivation of modules or transistors electrically connected to that signal. These will not be elaborated further below.

[0028] For ease of description, unless otherwise specified, the embodiments of the present invention use the example of each module in the shift register having a high enable level and a low disable level to illustrate the technical solutions of the embodiments of the present invention.

[0029] Furthermore, the first voltage signal Vgh and the second voltage signal Vgl are two signals with opposite polarities, i.e., one is a high voltage and the other is a low voltage. Unless otherwise specified, the embodiments of the present invention will use the example of the first voltage signal Vgh being a high voltage and the second voltage signal Vgl being a low voltage to illustrate the technical solution of the embodiments of the present invention. Here, a high level is a signal with a larger amplitude compared to a low level; that is, both high and low levels may be signals greater than 0V, or in other cases, both high and low levels may be signals less than or equal to 0V. The embodiments of the present invention do not specifically limit this.

[0030] Based on the above embodiments, the shift register can also be configured to include a first mutual control module 140, a second mutual control module 150, and a first voltage regulation control module 130 to improve the stability and accuracy of the gate drive signal Gout output from the scan output terminal GOUT. Specifically, the control terminal of the first mutual control module 140 can be electrically connected to the first node N1, the input terminal of the first mutual control module 140 can be electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl, and the output terminal of the first mutual control module 140 can be electrically connected to the second node N2. When the signal of the first node N1 is at an enable level, the first mutual control module 140 can transmit the second voltage signal Vgl provided by the second voltage terminal VGL to the second node N2, enabling the first mutual control module 140 to control the signal of the second node N2 according to the signal of the first node N1, so that the polarity of the signal of the second node N2 is opposite to that of the signal of the first node N1.

[0031] For the first voltage regulation control module 130, its control terminal can be electrically connected to the first node N1, its input terminal can be electrically connected to the third voltage terminal VDD to receive the third voltage signal Vdd, and its output terminal can be electrically connected to the second mutual control module 150 to the third node N3. Then, when the signal of the first node N1 is at the enable level, the first voltage regulation control module 130 can transmit the third voltage signal Vdd provided by the third voltage terminal VDD to the third node N3, so that the signal of the third node N3 is the same as the third voltage signal Vdd.

[0032] The input terminal of the second inter-control module 150 can be electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The control terminal of the second inter-control module 150 is electrically connected to the second node N2, and the output terminal of the second inter-control module 150 is electrically connected to the first node N1. Furthermore, the second inter-control module 150 is also electrically connected to the first voltage regulation control module 130 at the third node N3. The third node N3 can be located in the signal transmission path from the second voltage terminal VGL to the first node N1, thus isolating the second voltage terminal VGL from the first node N1. When the signal at the second node N2 is at the enable level, the second inter-control module 150 can transmit the second voltage signal Vgl from the second voltage terminal VGL to the first node N1 through the third node N3. This allows the second inter-control module 150 to control the signal at the first node N1 according to the signal at the second node N2, making the signal at the first node N1 opposite to the signal at the second node N2.

[0033] During one working cycle of shift register G, its second node N2 remains enabled for a long time after the output module 160 outputs an enable level. This allows the output module 160 to keep the gate drive signal Gout continuously disabled after outputting the enable level of the gate drive signal Gout in a display frame. As a result, the transistors in the second inter-control module 150 will be in the on state for a long time. Especially under high temperature and high brightness working conditions, this causes the threshold voltage of the transistors in the second inter-control module 150 to shift, so when the second node N2 jumps to the disabled level in the next display frame, it is impossible to control the transistors to turn off normally. Based on this, when the signal of the second node N2 is at an enabled level, the first voltage regulation control module 130 is turned on under the control of the enable signal of the first node N1, so that the third voltage signal Vdd of the third voltage terminal VDD is written to the third node N3. Then, when the transistor in the second inter-control module 150 cannot be normally turned off under the control of the disabled level of the second node N2 due to characteristic offset, the signal transmitted from the third node N3 to the first node N1 is the third voltage signal Vdd instead of the second voltage signal Vgl, which can ensure the accuracy of the signal of the first node N1, thereby ensuring the accuracy of the gate drive signal Gout output by the output module 160. Alternatively, when the signal of the second node N2 is at an enabled level, if the transistor in the second inter-control module 150 can be normally turned off under the control of the disabled level of the second node N2, then the third node N3 has a higher voltage signal Vdd, which can effectively reduce the leakage current from the first node N1 to the third node N3, can ensure the stability and accuracy of the signal of the first node N1, and can further improve the accuracy of the gate drive signal output by the output module 160, thereby effectively improving the display effect.

[0034] For example, the first voltage signal Vgh is multiplexed into the third voltage signal Vdd. In this way, when the first voltage regulation control module 130 is turned on, the signal of the third node N3 is the high voltage first voltage signal Vgh. Thus, when the transistor in the second inter-control module 150 cannot be turned off normally, the first voltage signal Vgh is transmitted from the third node N3 to the first node N1 to regulate the high voltage signal of the first node N1. Alternatively, when the transistor in the second inter-control module 150 can be turned off normally, the signal written by the third node N3 is the first voltage signal Vgh, which can reduce the leakage current from the first node N1 to the third node N3, thereby regulating the signal of the first node N1.

[0035] In another feasible embodiment, the voltage of the first voltage signal Vgh is V1; the voltage of the third voltage signal Vdd is V3; 0 ≤ V3 ≤ 2 × V1, and the voltage of the third voltage signal Vdd is adjustable. Thus, the voltage value of the third voltage signal Vdd can be adjusted according to the signal requirements of the first node N1. For example, when the first node N1 is at a high voltage, if the signal of the first node N1 decreases due to leakage current, the voltage of the first node N1 can be increased by increasing the voltage of the third voltage signal Vdd to maintain its accurate potential. This allows the first node N1 to accurately control the output module 160 to output an accurate gate drive signal Gout.

[0036] The display panel provided in this embodiment of the invention includes a first node control module to control the signals of the first node based on input signals and scan control signals, a second node control module to control the signals of the second node based on scan control signals, a first reset clock signal, and a first voltage signal, and an output module to control the gate drive signal of the scan output terminal based on the signals of the first node, the second node, a second voltage signal, and a second clock signal, thereby driving the pixel circuit to perform corresponding light emission display. Furthermore, a first mutual control module ensures that the second node is disabled when the first node is enabled, and a second mutual control module ensures that the first node is disabled when the second node is enabled. The signal at the first node is at the enable level, and is electrically connected to the second inter-control module via the first voltage regulator module to the third node. When the signal at the first node is at the enable level, the signal at the third node is a third voltage signal. This achieves isolation between the second voltage signal and the first node, preventing the second voltage signal from being written to the first node when the second inter-control module fails to turn off properly, and preventing signal inaccuracies at the first node due to leakage current when the second inter-control module can turn off properly. This effectively improves the accuracy and stability of the signal at the first node, thereby ensuring the stability and accuracy of the gate drive signal output by the output module. It effectively avoids problems such as horizontal stripes, flickering, or bright lines on the display screen, thus effectively improving the display effect of the display panel.

[0037] Optional, Figure 3 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the first voltage regulation control module 130 includes a first transistor M1; the gate of the first transistor M1 is electrically connected to the first node N1, the first terminal of the first transistor M1 receives the third voltage signal Vdd, and the second terminal of the first transistor M1 is electrically connected to the third node N3.

[0038] Specifically, the first node N1 can control the first transistor M1 to be turned on or off. When the first node N1 is at the enabled level, it controls the first transistor M1 to be turned on, so that the third voltage signal Vdd provided by the third voltage terminal VDD can be transmitted from the first terminal of the first transistor M1 to its second terminal, thereby enabling the third voltage signal Vdd to be transmitted to the third node N3. When the first node N1 is at the disabled level, it controls the first transistor M1 to be turned off, and the third voltage signal VDD cannot be transmitted to the third node N3.

[0039] Optional, Figure 4 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 4As shown, the second mutual control module 150 includes: a first node mutual control unit 151 and a first isolation voltage regulator unit 152; the first node mutual control unit 151 is used to receive the second voltage signal Vgl and the signal of the second node N2, and control the signal of the third node N3; the first isolation voltage regulator unit 152 is used to receive the signal of the second node N2 and the signal of the third node N3, and control the signal of the first node N1.

[0040] Specifically, the input terminal of the first node mutual control unit 151 can be electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The control terminal of the first node mutual control unit 151 is electrically connected to the second node N2, and the output terminal of the first node mutual control unit 151 is electrically connected to the third node N3. When the first node mutual control unit 151 can be normally turned on and off, when the signal from the second node N2 controls the first node mutual control unit 151 to turn on, the received second voltage signal Vgl is transmitted to the third node N3. Conversely, when the signal from the second node N2 controls the first node mutual control unit 151 to turn off, the received second voltage signal Vgl cannot be transmitted to the third node N3.

[0041] The input terminal of the first isolation voltage regulator unit 152 can be electrically connected to the third node N3, the control terminal of the first isolation voltage regulator unit 152 can be electrically connected to the second node N2, and the output terminal of the first isolation voltage regulator unit 152 can be electrically connected to the first node N1. When the first isolation voltage regulator unit 152 can be normally turned on and off, when the signal from the second node N2 controls the first isolation voltage regulator unit 152 to turn on, the voltage of the third node N3 can be transmitted to the first node N1 through the first isolation voltage regulator unit 152. When the signal from the second node N2 controls the first isolation voltage regulator unit 152 to turn off, the voltage of the third node N3 cannot be transmitted to the first node N1 through the first isolation voltage regulator unit 152.

[0042] When the first node inter-control unit 151 cannot be normally turned off under the control of the signal of the second node N2 due to the threshold voltage offset, the second voltage signal Vgl provided by the second voltage terminal VGL is always transmitted to the third node N3 through the first node inter-control unit 151. At this time, the first voltage regulation control module 130 is turned on under the control of the first node N1, so that the third voltage signal Vdd provided by the third voltage terminal VDD is written to the third node N3. When the voltage of the third voltage signal Vdd is greater than the voltage of the second voltage signal Vgl, the signal of the third node N3 is consistent with the third voltage signal Vdd, so that the signal of the third node N3 is the high-level third voltage signal Vdd. Thus, if the first isolation voltage regulator unit 152 can be normally turned off under the control of the signal from the second node N2, the high-level signal of the third node N3 can reduce the leakage current from the first node N1 to the third node N3, thereby ensuring the stability and accuracy of the signal from the first node N1. When the first isolation voltage regulator unit 152 cannot be normally turned off under the control of the signal from the second node N2 due to the threshold voltage offset, the third node N3 transmits a high-level third voltage signal Vdd to the first node N1 instead of a low-level second voltage signal Vgl, which can also ensure the accuracy and stability of the signal from the first node N1. This can achieve voltage regulation of the signal from the first node N1 and isolation between the first node N1 and the second voltage terminal VGL, effectively improving the accuracy of the signal from the first node N1.

[0043] Optional, Figure 5 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 5 As shown, the first node mutual control unit 151 includes a second transistor M2. The first terminal of the second transistor M2 receives a second voltage signal Vgl. The gate of the second transistor M2 is electrically connected to the second node N2, and the second terminal of the second transistor M2 is electrically connected to the third node N3.

[0044] Specifically, when the threshold voltage of the second transistor M2 does not shift, the second transistor M2 can be turned on or off under the control of the second node N2. When the second transistor M2 is turned on, it can transmit the second voltage signal Vgl received at the first terminal to its second terminal and transmit the second voltage signal Vgl to the third node N3. When the second transistor M2 is turned off, the second voltage signal Vgl cannot be transmitted to the third node N3.

[0045] Optional, see reference Figure 5 The first isolation voltage regulator unit 152 includes a third transistor M3; the first electrode of the third transistor M3 is electrically connected to the third node N3, the gate of the third transistor M3 is electrically connected to the second node N2, and the second electrode of the third transistor M3 is electrically connected to the first node N1.

[0046] Specifically, when the threshold voltage of the third transistor M3 is not offset, the third transistor M3 can be turned on or off under the control of the second node N2. When the third transistor M3 is turned on, it can transmit the signal of the third node N3 to the first node N1, so that the signal of the first node N1 is consistent with that of the third node N3. When the third transistor M3 is turned off, the circuit between the third node N3 and the first node N1 is broken, so that the signal of the third node N3 cannot be transmitted to the first node N1.

[0047] For example, if the second node N2 remains at the enabled level for an extended period, the threshold voltage of the second transistor M2 may shift due to prolonged conduction, preventing it from turning off properly. Consequently, the second voltage signal Vgl at the second voltage terminal VGL is continuously transmitted to the third node N3 via the second transistor M2. When the signal at the first node N1 is at the enabled level, the first transistor M1 in the first voltage regulation control module 130 is turned on, writing the third voltage signal Vdd to the third node N3. At this time, if the voltage of the third voltage signal Vdd is greater than the voltage of the second voltage signal Vgl, the signal at the third node N3 can be kept consistent with the third voltage signal Vdd, resulting in a high-level signal at the third node N3. Thus, if the threshold voltage of the third transistor M3 does not shift and can be normally turned off under the control of the signal from the second node N2, the high-level signal of the third node N3 can reduce the leakage current from the first node N1 to the third node N3, thereby ensuring the stability and accuracy of the signal from the first node N1. Conversely, if the threshold voltage of the third transistor M3 shifts due to prolonged conduction and cannot be normally turned off under the control of the non-enabled level of the second node N2, the third node N3 transmits a high-level third voltage signal Vdd to the first node N1 instead of a low-level second voltage signal Vgl, which also ensures the accuracy and stability of the signal from the first node N1. In other words, the third transistor M3 can regulate the voltage of the signal from the first node N1 and isolate the first node N1 from the second voltage terminal VGL, effectively improving the accuracy of the signal from the first node N1.

[0048] Optional, Figure 6 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 6As shown, the output module 160 includes a first output unit 161 and a second output unit 162. The first output unit 161 receives the signal from the first node N1 and the output control signal out, and the first output unit 161 is electrically connected to the scan output terminal GOUT. The first output unit 161 is used to control the signal transmission path of the output control signal out to the scan output terminal GOUT according to the signal from the first node N1. The second output unit 162 receives the signal from the second node N2 and the second voltage signal Vgl, and the second output unit 162 is electrically connected to the scan output terminal GOUT. The second output unit 162 is used to control the signal transmission path of the second voltage signal Vgl to the scan output terminal GOUT according to the signal from the second node N2.

[0049] Specifically, the input terminal of the first output unit 161 can be electrically connected to the output control terminal OUT to receive the output control signal out. The control terminal of the first output unit 161 is electrically connected to the first node N1, and the second terminal of the first output unit 161 is electrically connected to the scan output terminal GOUT. When the signal of the first node N1 is at the enable level, the first output unit 161 can transmit the output control signal out provided by the output control terminal OUT to the scan output terminal GOUT, so that the gate drive signal Gout is consistent with the second clock signal CK2. The input terminal of the second output unit 162 is electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The control terminal of the second output unit 162 is electrically connected to the second node N2, and the output terminal of the second output unit 162 is electrically connected to the scan output terminal GOUT. When the signal of the second node N2 is at the enable level, the second output unit 162 can transmit the second voltage signal Vgl provided by the second voltage terminal VGL to the scan output terminal GOUT, so that the gate drive signal Gout is consistent with the second voltage signal Vgl.

[0050] Optional, Figure 7 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 7 As shown, the first output unit 161 includes a fourth transistor M4 and a first capacitor C1; the first terminal of the fourth transistor M4 receives the output control signal out, the gate of the fourth transistor M4 and the first terminal of the first capacitor C1 are electrically connected to the first node N1, and the second terminal of the fourth transistor M4 and the second terminal of the first capacitor are both electrically connected to the scan output terminal GOUT.

[0051] Specifically, the fourth transistor M4 can be turned on or off under the control of the first node N1. When the fourth transistor M4 is on, it can transmit the output control signal out received at its first electrode to the scan output terminal GOUT, so that the gate drive signal Gout output by the scan output terminal GOUT is consistent with the output control signal out. When the fourth transistor M4 is off, the output control terminal OUT and the scan output terminal GOUT are disconnected, and the output control signal out cannot be transmitted to the scan output terminal GOUT. The first capacitor C1 is used to store the signal of the first node N1, which can keep the signal of the first node N1 stable, so that when the signal of the first node N1 is at the enable level, the gate drive signal Gout remains stable.

[0052] Optional, continue to refer to Figure 7 The second output unit 162 includes a fifth transistor M5. The first terminal of the fifth transistor M5 receives a second voltage signal Vgl, the gate of the fifth transistor M5 is electrically connected to the second node N2, and the second terminal of the fifth transistor M5 is electrically connected to the scan output terminal GOUT. Thus, the fifth transistor M5 can be turned on or off under the control of the second node N2. When it is on, it can transmit the second voltage signal Vgl received by its first terminal to the scan output terminal GOUT, so that the gate drive signal Gout output by the scan output terminal GOUT is consistent with the second voltage signal Vgl. When the fifth transistor M5 is off, the second voltage terminal VGL is disconnected from the scan output terminal GOUT, and the second voltage signal Vgl cannot be transmitted to the scan output terminal GOUT.

[0053] Optional, continue to refer to Figure 6 The shift register G also includes a storage module 170; one end of the storage module 170 receives the second voltage signal Vgl, and the other end of the storage module 170 is electrically connected to the second node N2.

[0054] Specifically, by setting the storage module 170 to be electrically connected between the second voltage terminal VGL and the second node N2, the storage module 170 can store the signal of the second node N2, which can keep the signal of the second node N2 stable. Thus, when the signal of the second node N2 is at the enable level, the gate drive signal Gout output by the scan output terminal GOUT can be kept stable.

[0055] For example, continue to refer to Figure 7The storage module 170 may include a second capacitor C2. The first end of the second capacitor C2 is electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The second end of the second capacitor C2 is electrically connected to the second node N2. Thus, the second capacitor C2 can store the second node N2 and can keep the gate drive signal Gout output by the scan output terminal GOUT stable when the signal of the second node N2 is at the enable level.

[0056] Optional, Figure 8 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 8 As shown, the first node control module 110 includes a first input unit 111; the first input unit 111 is used to receive the input signal Inf and the scan control signal U2d to control the signal of the first node N1.

[0057] Specifically, the input terminal of the first input unit 111 can be electrically connected to the scan control terminal U2D to receive the scan control signal U2d, the control terminal of the first input unit 111 can be electrically connected to the signal input terminal INF to receive the input signal Inf, and the output terminal of the first input unit 111 can be electrically connected to the first node N1. Then, the first input unit 111 can be turned on or off under the control of the input signal Inf, and can transmit the scan control signal U2d to the first node N1 when it is on, and cannot transmit the scan control signal U2d to the first node N1 when it is off.

[0058] For example, Figure 9 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 9 As shown, the first input unit 111 includes an eighth transistor M8. The first terminal of the eighth transistor M8 is electrically connected to the scan control terminal U2D to receive the scan control signal U2d. The gate of the eighth transistor M8 is electrically connected to the signal input terminal INF to receive the input signal Inf. The second terminal of the eighth transistor M8 is electrically connected to the first node N1. Therefore, the eighth transistor M8 can be turned on or off under the control of the input signal Inf. When it is on, it can transmit the scan control signal U2d to the first node N1, and when it is off, it cannot transmit the scan control signal U2d to the first node N1, thus enabling control of the signals at the first node N1.

[0059] Optional, see reference Figure 8 The second node control module 120 includes a second input unit 121 and a second node control unit 122; the second input unit 121 is used to receive the scan control signal U2d and the first reset clock signal Rstf to control the signal of the fifth node N5; the second node control unit 122 is used to receive the signal of the fifth node N5 and the first voltage signal Vgh to control the signal of the second node N2.

[0060] Specifically, the input terminal of the second input unit 121 can be electrically connected to the first reset clock terminal RSFT to receive the first reset clock signal Rstf. The control terminal of the second input unit 121 can be electrically connected to the scan control terminal U2D to receive the scan control signal U2d. The output terminal of the second input unit 121 can be electrically connected to the control terminal of the second node control unit 122 at the fifth node N5. Then, the second input unit 121 can be turned on or off under the control of the scan control signal U2d, and when on, it can transmit the first reset clock signal Rstf provided by the first reset clock terminal RSFT to the fifth node. The input terminal of the second node control unit 122 can be electrically connected to the first voltage terminal VGH to receive the first voltage signal Vgh. The output terminal of the second node control unit 122 can be electrically connected to the second node N2. Then, the second node control unit 122 can be turned on or off under the control of the signal from the fifth node N5, and when on, it can transmit the first voltage signal Vgh provided by the first voltage terminal VGH to the second node N2, thus controlling the signal of the second node N2.

[0061] For example, refer to Figure 9 The second input unit 121 can be configured to include a ninth transistor M9. The first terminal of the ninth transistor M9 is electrically connected to the first reset clock terminal RSFT to receive the first reset clock signal Rstf. The gate of the ninth transistor M9 is electrically connected to the scan control terminal U2D to receive the scan control signal U2d. The second terminal of the ninth transistor M9 is electrically connected to the control terminal of the second node control unit 122 at the fifth node N5. Thus, the ninth transistor M9 can be turned on or off under the control of the scan control signal U2d, and when turned on, it can transmit the first reset clock signal Rstf provided by the first reset clock terminal RSFT to the fifth node N5.

[0062] For example, continue to refer to Figure 9 The second node control unit 122 may include a tenth transistor M10. The first terminal of the tenth transistor M10 is electrically connected to the first voltage terminal VGH to receive the first voltage signal Vgh. The gate of the tenth transistor M10 is electrically connected to the fifth node N5, and the second terminal of the tenth transistor M10 is electrically connected to the second node N2. The tenth transistor M10 can be turned on or off under the control of the signal of the fifth node N5, and when it is turned on, it can transmit the first voltage signal Vgh provided by the first voltage terminal VGH to the second node N2.

[0063] For example, continue to refer to Figure 9The first mutual control module 140 may include an eleventh transistor M11. The first terminal of the eleventh transistor M11 is electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The gate of the eleventh transistor M11 is electrically connected to the first node N1, and the second terminal of the eleventh transistor M11 is electrically connected to the second node N2. The eleventh transistor M11 can be turned on or off under the control of the first node N1, and when turned on, it can transmit the second voltage signal Vgl provided by the second voltage terminal VGL to the second node N2. This allows it to control the signal of the second node N2 to be at a disabled level when the signal at the first node N1 is at an enabled level, thus realizing mutual control between the first node N1 and the second node N2.

[0064] Optional, Figure 10 This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 10 As shown, the first node control module 110 further includes an isolation unit 112 and a voltage regulator unit 113; the isolation unit 112 is electrically connected to the sixth node N6 and the first input unit 111, and is also electrically connected to the first node N1, and the isolation unit 112 receives a set clock signal Set; the isolation unit 112 is used to control the signal transmission path between the sixth node N6 and the first node N1 according to the set clock signal Set; the voltage regulator unit 113 is electrically connected to the fifth node N5, the sixth node N6 and the first node N1 respectively; the voltage regulator unit 113 is used to control the signal transmission path between the sixth node N6 and the first node N1 according to the signal of the fifth node N5.

[0065] Specifically, the input terminal of the isolation unit 112 can be electrically connected to the first input unit 111 at the sixth node N6, the output terminal of the isolation unit 112 can be electrically connected to the first node N1, and the control terminal of the isolation unit 112 can be electrically connected to the set clock terminal SET to receive the set clock signal Set. Then, the isolation unit 112 can be turned on or off under the control of the set clock signal Set, and when it is turned on, it can transmit the signal of the sixth node N6 to the first node N1, which can prevent the changes of the sixth node N6 from affecting the signal of the first node N1, and realize the isolation between the sixth node N6 and the first node N1. In addition, the input terminal of the voltage regulator unit 113 is electrically connected to the sixth node N6, the control terminal of the voltage regulator unit 113 is electrically connected to the fifth node N5, and the output terminal of the voltage regulator unit 113 is electrically connected to the first node N1. Thus, the voltage regulator unit 113 can be turned on or off under the control of the fifth node N5, and when it is turned on, it transmits the signal of the sixth node N6 to the first node N1, so that the signal of the sixth node N6 can be transmitted to the first node N1 through the isolation unit 112 and the voltage regulator unit 113 respectively, and the signal of the first node N1 can be regulated.

[0066] For example, Figure 11This is a schematic diagram of another shift register provided in an embodiment of the present invention, such as... Figure 11 As shown, the isolation unit 112 includes a twelfth transistor M12. The first terminal of the twelfth transistor M12 is electrically connected to the second terminal of the eighth transistor M8 in the first input unit 111 at the sixth node N6. The second terminal of the twelfth transistor M12 is electrically connected to the first node N1. The gate of the twelfth transistor M12 is electrically connected to the set clock terminal SET to receive the set clock signal Set. The twelfth transistor M12 can be turned on or off under the control of the set clock signal Set. When it is turned on, it can transmit the signal of the sixth node N6 to the first node N1, which can prevent the change of the sixth node N6 from affecting the signal of the first node N1, thus realizing the isolation between the twelfth transistor M12 and the first node N1.

[0067] Continue to refer to Figure 11 The voltage regulator unit 113 includes a thirteenth transistor M13. The first electrode of the thirteenth transistor M13 is electrically connected to the sixth node N6, the gate of the thirteenth transistor M13 is electrically connected to the fifth node N5, and the second electrode of the thirteenth transistor M13 is electrically connected to the first node N1. The thirteenth transistor M13 can be turned on or off under the control of the fifth node N5. When it is turned on, it transmits the signal of the first node N1 to the sixth node N6. When the first reset clock signal Rstf is high, it transmits the low-level signal of the first node N1 to the sixth node N6 to reset the signal of the sixth node N6.

[0068] Optional, continue to refer to Figure 10 The shift register G also includes a third mutual control module 180; the third mutual control module 180 is connected to the sixth node N6 and the second node N2 respectively, and the third mutual control module 180 receives the second voltage signal Vgl; the third mutual control module 180 is used to control the signal of the second node N2 according to the signal of the sixth node N6 and the second voltage signal Vgl.

[0069] Specifically, the input terminal of the third mutual control module 180 can be electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The control terminal of the third mutual control module 180 is electrically connected to the sixth node N6, and the output terminal of the third mutual control module 180 is electrically connected to the second node N2. Then, the third mutual control module 180 can be turned on or off under the control of the sixth node N6. When it is turned on, it can transmit the second voltage signal Vgl provided by the second voltage terminal VGL to the second node N2. When the sixth node N6 is at the enabled level, it can ensure that the second node N2 is at the disabled level.

[0070] For example, refer to Figure 11The third mutual control module 180 includes a fourteenth transistor M14. The first terminal of the fourteenth transistor M14 is electrically connected to the second voltage terminal VGL to receive the second voltage signal Vgl. The gate of the fourteenth transistor M14 is electrically connected to the sixth node N6, and the second terminal of the fourteenth transistor M14 is electrically connected to the second node N2. The fourteenth transistor M14 can be turned on or off under the control of the sixth node N6, and when it is turned on, it can transmit the second voltage signal Vgl provided by the second voltage terminal VGL to the second node N2.

[0071] Optional, continue to refer to Figure 10 The first node N1 includes a first sub-node N1a and a second sub-node N1b; the shift register G also includes a voltage regulation and protection module 190; the voltage regulation and protection module 190 is electrically connected to the first node control module 110 at the first sub-node N1a, and the voltage regulation and protection module 190 is electrically connected to the output module 160 at the second sub-node N1b, and the voltage regulation and protection module 190 receives a first voltage signal Vgh; the voltage regulation and protection module 190 is used to stabilize the voltage of the first sub-node N1a.

[0072] Specifically, refer to the following: Figure 9The voltage regulation and protection module 190 can remain in the conducting state under the control of the first voltage signal Vgh and transmit the signal of the first sub-node N1a to the second sub-node N1b. When the first sub-node N1a is at a high level (assuming it is Vgh), the second sub-node N1b is also at a high level. Due to the bootstrap effect of the first capacitor C1, the potential of the second sub-node N1b can be pulled up to a voltage greater than Vgh (e.g., 2×Vgh). At this time, the voltage regulation and protection module 190 can isolate the second sub-node N1b from the first sub-node N1a, prevent the potential of the first sub-node N1a from rising, and keep the voltage of the first sub-node N1a at the level of the first sub-node N1a. Furthermore, since the output module 160 is electrically connected to the scan output terminal GOUT, and the scan output terminal GOUT is electrically connected to the scan signal line in the display area A2, if the potential of the scan signal output terminal GOUT suddenly increases due to static electricity or other reasons, it will be conducted to the first node N1 through the first capacitor C1, and then flow back to the driver chip through the first node control module 110, damaging the driver chip. In this embodiment of the invention, a voltage regulation protection module 190 is set between the first sub-node N1a and the second sub-node N1b, and the voltage regulation protection module 190 is electrically connected to the first voltage terminal VGH. Thus, when the potential of the second sub-node N1b suddenly increases due to static electricity or other reasons, the voltage regulation protection module 190 can be controlled to turn off, so that the potential of the first sub-node N1a is less than or equal to a preset voltage value, preventing high potential backflow to the driver chip. Furthermore, when the potential of the scan output terminal GOUT is normal, the voltage regulation protection module 190 can continue to conduct under the control of the first voltage signal Vgh of the first voltage terminal VGH, without affecting the normal operation of the shift register G.

[0073] For example, refer to Figure 11The voltage regulation and protection module 190 includes a fifteenth transistor M15. The first terminal of the fifteenth transistor M15 is electrically connected to the first sub-node N1a, and the second terminal of the fifteenth transistor M15 is electrically connected to the second sub-node N1b. The gate of the fifteenth transistor M15 is connected to the first voltage terminal VGH to receive the first voltage signal Vgh. The first terminal of the fifteenth transistor M15 can be the source, and the second terminal can be the drain. When the voltage of the second sub-node N1b is normal, the fifteenth transistor M15 can remain in the conducting state under the control of the first voltage signal Vgh. The current flows from the first terminal of the fifteenth transistor M15 to its second terminal, which can isolate the signals of the first sub-node N1a and the second sub-node N1b. When the first sub-node N1a is at a high level (assuming it is Vgh), the second sub-node N1b is also at a high level. Due to the bootstrap effect of the first capacitor C1, the potential of the second sub-node N1b can be pulled up to a voltage greater than Vgh (e.g., 2×Vgh). At this time, the fifteenth transistor M15 can isolate the second sub-node N1b from the first sub-node N1a, preventing the potential of the first sub-node N1a from rising, so that the voltage of the first sub-node N1a is maintained at the first sub-node N1a. Furthermore, if the voltage of its second child node N1b increases abnormally, until it is much higher than that of the first child node N1a, it may cause the current to reverse, that is, the current will flow from the second terminal of the fifteenth transistor M5 to the first terminal until the voltage of the first terminal rises to such that Vgs < Vth (where Vgs is the gate-source voltage of the fifteenth transistor M5 and Vth is the threshold voltage of the fifteenth transistor M5), causing the fifteenth transistor M5 to turn off, thereby preventing the voltage of the first child node N1a from continuing to rise. Thus, by stabilizing the voltage of the first child node N1a, the driver chip can be protected from high voltage damage.

[0074] In the above embodiments, the fourth transistor M4 and the fifth transistor M5 can both be PMOS transistors or both are NMOS transistors. Preferably, both the fourth transistor M4 and the fifth transistor M5 are NMOS transistors. When both the fourth transistor M4 and the fifth transistor M5 are NMOS transistors, since the fifth transistor M5 in the second output unit 162 is controlled by the second node N2, there is also a problem of threshold voltage shift due to prolonged conduction. This shift is particularly pronounced under high-temperature environments and high display brightness operating conditions.

[0075] Based on the aforementioned technical issues Figure 12 and Figure 13 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figure 12 or Figure 13The shift register G also includes a second voltage regulation control module 1100; the second voltage regulation control module 1100 is used to receive the third voltage signal Vdd and the signal of the first node N1, and control the signal of the fourth node N4; the second output unit 162 is also used to receive the signal of the fourth node N4, and control the gate drive signal Gout according to the second voltage signal Vgl, the signal of the second node N2 and the signal of the fourth node N4.

[0076] Specifically, the control terminal of the second voltage regulation control module 1100 can be electrically connected to the first node N1, the input terminal of the second voltage regulation control module 1100 can be electrically connected to the third voltage terminal VDD to receive the third voltage signal Vdd, and the output terminal of the second voltage regulation control module 1100 can be electrically connected to the second output unit 162 to the fourth node N4. Then, when the signal of the first node N1 is at the enable level, the second voltage regulation control module 1100 can transmit the third voltage signal Vdd provided by the third voltage terminal VDD to the fourth node N4, so that the signal of the fourth node N4 is the same as the third voltage signal Vdd.

[0077] The fourth node N4 can be located in the signal transmission path from the second voltage terminal VGL to the scan output terminal GOUT, enabling isolation between the second voltage terminal VGL and the scan output terminal GOUT. When the signal of the second node N2 is at the enable level, the signal of the first node N1 is at the disable level, causing the second voltage regulation control module 1100 to be turned off and unable to transmit the third voltage signal Vdd to the fourth node N4. At this time, the second output unit 162 can transmit the second voltage signal Vgl provided by the second voltage terminal VGL to the scan output terminal GOUT through the fourth node N4, making the gate drive signal Gout the second voltage signal Vgl. When the signal at the second node N2 is disabled, the signal at the first node N1 is enabled, controlling the first voltage regulation module 130 to conduct. This allows the third voltage signal Vdd from the third voltage terminal VDD to be transmitted to the fourth node N4. If the transistor in the second output unit 162 cannot be normally turned off under the control of the disabled level of the second node N2 due to threshold offset, the signal transmitted from the third node N3 to the scan output terminal GOUT will be the third voltage signal Vdd instead of the second voltage signal Vgl. This ensures the accuracy of the gate drive signal Gout output by the scan output terminal GOUT. Alternatively, if the transistor in the second output unit 162 can be normally turned off under the control of the disabled level of the second node N2 when the signal at the second node N2 is disabled, then the third voltage signal Vdd at the fourth node N4 will be high. This effectively reduces leakage current from the scan output terminal GOUT to the fourth node N4, similarly improving the accuracy of the gate drive signal Gout, thereby effectively improving the display effect.

[0078] Optional, Figure 14 and Figure 15 This is a schematic diagram of another shift register provided in an embodiment of the present invention, see reference. Figure 14 or Figure 15 The second voltage regulation control module 1100 includes a sixth transistor M6; the first terminal of the sixth transistor M6 receives a third voltage signal Vdd, the gate of the sixth transistor M6 is electrically connected to the first node N1, and the second terminal of the sixth transistor M6 is electrically connected to the fourth node N4.

[0079] Specifically, the sixth transistor M6 can be turned on or off under the control of the signal of the first node N1, and when it is turned on, it can transmit the third voltage signal Vdd provided by the third voltage terminal VDD to the fourth node N4, so that the signal of the fourth node N4 is the third voltage signal Vdd.

[0080] Optional, continue to refer to Figure 14 or Figure 15 The second output unit 162 includes a fifth transistor M5 and a seventh transistor M7; the first terminal of the fifth transistor M5 receives the second voltage signal Vgl, the gate of the fifth transistor M5 is electrically connected to the second node N2, and the second terminal of the fifth transistor M5 is electrically connected to the fourth node N4; the first terminal of the seventh transistor M7 is electrically connected to the fourth node N4, the gate of the seventh transistor M7 is electrically connected to the second node N2, and the second terminal of the seventh transistor M7 is electrically connected to the scan output terminal GOUT.

[0081] Specifically, when the threshold voltage of the fifth transistor M5 is not offset, the fifth transistor M5 can be turned on or off under the control of the second node N2. When the fifth transistor M5 is on, it can transmit the second voltage signal Vgl received at the first terminal to its second terminal and write the second voltage signal Vgl to the fourth node N4. When the fifth transistor M5 is off, the second voltage signal Vgl cannot be transmitted to the fourth node N4. When the threshold voltage of the seventh transistor M7 is not offset, the seventh transistor M7 can be turned on or off under the control of the second node N2. When the seventh transistor M7 is on, it can transmit the signal from the fourth node N4 to the scan output terminal GOUT, making the gate drive signal Gout output by the scan output terminal GOUT consistent with the signal of the fourth node N4. When the seventh transistor M7 is off, the circuit between the fourth node N4 and the scan output terminal GOUT is broken, so that the signal of the fourth node N4 cannot be transmitted to the scan output terminal GOUT.

[0082] For example, if the fifth transistor M5 cannot be turned off normally due to a shift in the threshold voltage, the second voltage signal Vgl will always be transmitted to the fourth node N4 through the fifth transistor M5. When the signal at the first node N1 is at the enable level, the sixth transistor M6 in the second voltage regulation control module 1100 will be turned on. Since the first node N1 is at the enable level, the sixth transistor M6 will be fully turned on, while the second node N2 is at the non-enable level, so the fifth transistor M5 will not be fully turned on. Therefore, the drive current of the sixth transistor M6 is greater than the drive current of the fifth transistor M5, making the fourth node N4 consistent with the third voltage signal Vdd. Thus, if the threshold voltage of the seventh transistor M7 does not shift and it can be normally turned off under the control of the signal from the second node N2, the high-level signal from the fourth node N4 can reduce the leakage current from the scan output terminal GOUT to the fourth node N4. This prevents the seventh transistor M7, in its off-state state, from affecting the potential of the scan output terminal GOUT due to its small leakage current, thereby ensuring the stability and accuracy of the gate drive signal Gout output by the scan output terminal GOUT. Conversely, when the threshold voltage of the seventh transistor M7 shifts and it cannot be normally turned off under the control of the signal from the second node N2, the fourth node N4 transmits a high-level third voltage signal Vdd to the scan output terminal GOUT instead of a low-level second voltage signal Vgl, which also ensures the accuracy and stability of the gate drive signal Gout. In this way, the seventh transistor M7 can achieve voltage regulation of the gate drive signal Gout and isolation between the scan output terminal GOUT and the second voltage terminal VGL, effectively improving the accuracy and stability of the gate drive signal Gout.

[0083] It should be noted that in the above embodiments, the scanning control terminal U2D is a forward scanning control terminal, and the signal it provides is the forward scanning control signal U2d. The signal input terminal INF is a forward signal input terminal, and the input signal Inf it provides is a forward input signal. When performing forward scanning on each row of pixel circuits 20 in the display area A2 (e.g., scanning from top to bottom), the forward scanning control signal U2d can be controlled to remain at the enable level. In another feasible real-time example of the present invention, Figure 16 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 17 and Figure 18 This is a schematic diagram of another shift register structure provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 16 and Figure 17 or in conjunction with references Figure 16 and Figure 18The shift register G can also be configured to include a negative scan control terminal D2U for providing a negative scan control signal D2u, and a negative signal input terminal INB for providing a negative input signal Inb. This allows the negative scan control signal D2u to be kept at an enabled level during negative scanning of each row of pixel circuits 20 in the display area A2 (e.g., scanning from bottom to top). The start signal terminal STV can also be configured to include a positive start signal terminal STVF and a negative scan signal terminal STVB. During positive scanning, the positive start signal stvf output by the positive start signal terminal STVF is at an enabled level, and the negative start signal stvb output by the negative scan signal terminal STVB is at a disabled level. In each shift register G, the positive signal input terminal INF of the first-stage shift register G1 is electrically connected to the positive start signal terminal STVF to receive the positive start signal stvf. In other shift register units G, the positive signal input terminal INF of the Gi-stage shift register unit is electrically connected to the scan output terminal GOUT of the Gi-1 stage shift register unit. During forward scanning, the forward scan control signal U2d is kept at the enabled level and the positive start signal stvf includes the enabled level, while the negative scan control signal D2u is kept at the disabled level and the negative start signal stvb is kept at the disabled level. This enables each shift register G to output a gate drive signal Gout that is shifted sequentially with an effective level in the forward scan direction. Furthermore, in each shift register G, the negative signal input terminal INB of the last shift register (i.e., the Nth shift register Gn) is electrically connected to the negative start signal terminal STVB to receive the negative start signal stvb. In other shift register units G, the negative signal input terminal INB of the Gi-level shift register unit is electrically connected to the scan output terminal GOUT of the Gi+1-level shift register unit. During negative scanning, the negative scan signal D2u is kept at the enable level and the negative start signal stvb includes an active level, while the positive scan control signal U2d is kept at the disabled level and the positive start signal stvf is kept at the disabled level, so that each shift register G outputs a gate drive signal Gout that is shifted sequentially with an active level in the negative scan direction.

[0084] At this time, the first input unit 111 in the first node control module 110 may further include a sixteenth transistor M16. The first terminal of the sixteenth transistor M16 is electrically connected to the scan control terminal D2U to receive the scan control signal D2u. The gate of the sixteenth transistor M16 is connected to the negative signal input terminal INB to receive the negative input signal Inb. The second terminal of the sixteenth transistor M16 is electrically connected to the first node N1. Alternatively, when the first node control module 110 includes an isolation unit 112 and a voltage regulator unit 113, the second terminal of the sixteenth transistor M16 may be electrically connected to the sixth node N6. The second input unit 121 in the second node control module 120 may include a seventeenth transistor M17. The first terminal of the seventeenth transistor M17 is electrically connected to the second reset clock terminal RSTB to receive the second reset clock signal Rstb. The gate of the seventeenth transistor M17 is electrically connected to the negative scan control terminal D2U to receive the negative input signal Inb. The second terminal of the seventeenth transistor M17 is electrically connected to the fifth node N5.

[0085] In one exemplary embodiment, taking an example where all transistors in the shift register are NMOS transistors, Figure 19 This is a driving timing diagram of a shift register provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 18 and Figure 19 Taking the forward scanning phase as an example, the scanning control signal U2d remains at a high level during the forward scanning phase, while the negative scanning control signal D2u remains at a low level.

[0086] Taking the first-stage shift register G1 as an example, in stage t1, the input signal Inf (i.e., the positive start signal Stvf) and the set clock signal Set (i.e., the first clock signal ck1) of the first-stage shift register G1 are at high level, controlling the eighth transistor M8 and the lower twelfth transistor M12 in the first-stage shift register G1 to turn on, so that the scan control signal U2d is transmitted to the first node N1 in sequence through the eighth transistor M8, the sixth node N6 and the lower twelfth transistor M12. The signals V_N1 of the first node N1 and V_N6 of the sixth node N6 are both at high level, so the fourth transistor M4 in the output module 160 is turned on, and the output control signal Out is transmitted to the scan output terminal GOUT through the fourth transistor M4, so that the gate drive signal Gout is the output control signal Out. Since the output control signal Out (i.e., the second clock signal ck2) is at low level at this time, the gate drive signal Gout is at level. Simultaneously, the signal V_N1 of the first node N1 controls the eleventh transistor M11 in the first inter-control module 130, the first transistor M1 in the first voltage regulation control module 140, and the sixth transistor M6 in the second voltage regulation control module 1100 to all conduct. The signal V_N6 of the sixth node N6 controls the fourteenth transistor M14 in the third inter-control module 180 to conduct, causing the second voltage signal Vgl to be transmitted to the second node N2 through the eleventh transistor M11 and the fourteenth transistor M14, respectively. The signal V_N2 of the second node N2 is at a low level. The third voltage signal Vdd is transmitted to the third node N3 through the first transistor M1, and to the fourth node N4 through the sixth transistor M6, causing the signals V_N3 of the third node N3 and V_N4 of the fourth node N4 to be at a high level. Therefore, the fourth and fifth transistors M5 and the seventh transistor M7 in the output module 160 are turned off. At this time, if the threshold voltage of the second transistor M2 does not shift, the second transistor M2 can be turned off under the control of the second node N2, and the third node N3 is the third voltage signal Vdd; however, if the threshold voltage of the second transistor M2 shifts and cannot be turned off under the control of the second node N2, the second voltage signal Vgl is transmitted to the third node N3 through the second transistor in the second inter-control module 150. At this time, the third node N3 is still the high-level third voltage signal Vdd, so that when the third transistor M3 does not shift its threshold and can be turned off under the control of the second node N2, the high level of the third node N3 can prevent the voltage of the first node N1 from dropping due to leakage current, and when the third transistor M3 shifts its threshold and cannot be turned off under the control of the second node N2, the high-level signal of the third node N3 is written to the first node N1 without affecting the accuracy of the signal of the first node N1.In addition, when the first reset clock signal Rstf is low, the fifth node N5 is low, which turns off the tenth transistor M10. The first voltage signal Vgh cannot be written to the second node N2, and the second node N2 remains low.

[0087] During the t2 to t4 phase, the set clock signal Set, the output control signal Out, and the reset clock signal Rsft are all at low level. Since D2u remains at low level, the transition of the second reset clock signal Rstb will not affect the potential of each node. The signal V_N1 of the first node N1 remains at high level because no new signal is written. The state of each transistor is consistent with that of the t1 phase and remains unchanged. The gate drive signal Gout remains at low level.

[0088] During stage t5, the input signal Inf, the set clock signal Set, and the first reset clock signal Rsft are at low levels. The eighth transistor M8, the twelfth transistor M12, and the tenth transistor M10 are turned off. The signal V_N1 at the first node N1 remains high because no new signal is written. The states of each transistor are consistent with those in stage t1 and remain unchanged. Simultaneously, the output control signal Out is high, causing the gate drive signal Gout output from the scan output terminal GOUT to be high. During this stage, if the threshold voltage of the fifth transistor M5 does not shift, the fifth transistor M5 can be turned off under the control of the second node N2, and the fourth node N4 is the third voltage signal Vdd. However, if the threshold voltage of the fifth transistor M5 shifts and cannot be turned off under the control of the second node N2, the second voltage signal Vgl is transmitted to the third node N3 through the fifth transistor M5. At this time, the fourth node N4 is still the high-level third voltage signal Vdd. This ensures that when the seventh transistor M7 does not shift its threshold and can be turned off under the control of the second node N2, the high level of the fourth node N4 can prevent the gate drive signal Gout at the scan output terminal GOUT from being reduced due to leakage current. Furthermore, when the seventh transistor M7 shifts its threshold and cannot be turned off under the control of the second node N2, the high-level signal of the third node N3 is transmitted to the scan output terminal GOUT without affecting the accuracy of the gate drive signal Gout.

[0089] During stage t6, the input signal Inf, the set clock signal Set, and the first reset clock signal Rsft are all low. Since no new signal is written, the signal V_N1 of the first node N1 remains high, and the states of each transistor remain unchanged, consistent with stage t1. Simultaneously, the output control signal out jumps to low, and the gate drive signal Gout goes low.

[0090] During stage t7, the input signal Inf, the set clock signal Set, and the output control signal Out are all low, while the first reset clock signal Rsft is high. The high level of the first reset clock signal Rsft is written to the fifth node N5 through the ninth transistor M9. Since the signal at the fifth node N5 is high, the tenth transistor M10 is turned on, and the first voltage signal Vgh is written to the second node N2 through the tenth transistor M10, making the second node N2 high. Then, the second transistor M2 and the third transistor M3 in the second inter-control module 150, and the fifth transistor M5 and the seventh transistor M7 in the output module 160 are turned on. The second voltage signal Vgl is written to the first node N1 through the second transistor M2, the third node N3, and the third transistor M3, and is also transmitted to the scan output terminal GOUT through the fifth transistor M5, the fourth node N4, and the seventh transistor M7. The third node N3, the first node N1, and the fourth node N4 are low, and the gate drive signal Gout is low. Then the first transistor M1 and the sixth transistor M6 are turned off, so that the third voltage signal Vdd cannot be transmitted to the third node N3 and the fourth node N4, and the eleventh transistor M11 is turned off, so that the second voltage signal Vgl cannot be transmitted to the second node N2. The second node N2 remains at a high level, and the third node N3 and the fourth node N4 remain at a low level.

[0091] After stage t7, since the input signal Inf remains low, the first node N1 remains low, and the fourth transistor M4 remains off. Therefore, the transition of the first reset clock signal Rsft will not affect the state of the gate drive signal Gout, so the gate drive signal Gout remains low until the input signal Inf transitions to high again, and the above stages are repeated.

[0092] Figure 20 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 16 , Figure 18 and Figure 20The display panel 100 may further include a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4, for providing the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, respectively. It may also include a first power signal line VF and a second power signal line VB, for providing the positive scan control signal U2d and the negative scan control signal D2u, respectively. The set clock signal Set of the set clock terminal SET of each shift register G is shifted sequentially; the second reset clock signal Rstb of the second reset clock terminal RSTB of each shift register G is shifted sequentially; the output control signal Out of the output control terminal OUT of each shift register G is shifted sequentially; and the first reset clock signal Rstf of the first reset clock terminal RSTF of each shift register G is shifted sequentially. In this way, the shift registers G of two adjacent stages can be electrically connected to different clock signal lines, so that each clock signal line can be electrically connected to fewer shift register units, reducing the load on each clock signal line and ensuring the accuracy of the scan signal output by each shift register unit.

[0093] Continue to refer to Figure 16 , Figure 18 and Figure 20Before the first gate drive signal Gout1 output by the first-stage shift register G1 jumps to the enable level in stage t5, the first clock signal ck1 is at the enable level in stage t1, the second clock signal ck2 is at the enable level in stage t3, the first gate drive signal Gout1 output by the first-stage shift register G1 outputs the enable level in stage t5, the third clock signal ck3 is at the enable level, and the fourth clock signal ck4 is at the enable level in stage t7 after the scan signal Gout1 output by the first-stage shift register G1 jumps to the disable level. Correspondingly, the enable level of the third gate drive signal Gout3 output by the third-stage shift register G3 is shifted by one clock cycle of the first clock signal ck1 compared to the enable level of the first gate drive signal Gout1 output by the first-stage shift register G1. This ensures that the clock signals received by the third-stage shift register G3 have the same transition pattern as the clock signals received by the first-stage shift register G1. Therefore, the same clock inputs in odd-numbered shift registers G can share the same clock signal line. Specifically, in each odd-numbered shift register G, the set clock input SET shares the first clock signal line CK1, the second reset clock input RSTB shares the second clock signal line CK2, the output control input OUT shares the third clock signal line CK3, and the first reset clock input RSTF shares the fourth clock signal line CK4. Based on the same principle, the clock signals received by each even-numbered shift register G have the same transition pattern. Therefore, adjacent even-numbered shift registers G can also share the same clock signal line. In each even-numbered shift register G, the set clock terminal SET shares the third clock signal line CK3, the second reset clock terminal RSTB shares the fourth clock signal line CK4, the output control terminal OUT shares the first clock signal line CK1, and the first reset clock terminal RSTF shares the second clock signal line CK2. This ensures that each shift register unit 10 can output a normal scan signal while reducing the number of clock signal lines and simplifying the circuit structure.

[0094] For example, Figure 21 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 22 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 17 , Figure 21 and Figure 22The shift registers G electrically connected to the pixel circuits 20 in odd-numbered rows can be cascaded sequentially, as can the shift registers G electrically connected to the pixel circuits 20 in even-numbered rows. Assuming that the shift registers G electrically connected to the pixel circuits 20 in odd-numbered rows constitute the first shift register unit group 11, and the shift registers G electrically connected to the pixel circuits 20 in even-numbered rows constitute the second shift register unit group 12, then the first shift register unit group 11 and the second shift register unit group 12 can be located on opposite sides of the display area A2, or the first shift register unit group 11 and the second shift register unit group 12 can both be located on the same side of the display area A2 (not shown in the figure). This embodiment of the invention does not specifically limit this.

[0095] At this time, the start signal terminal STV may include a first positive start signal terminal STVF1, a first negative start signal terminal STVB1, a second positive start signal terminal STVF2, and a second negative start signal terminal STVB2. The positive signal input terminal INF of the first-stage shift register G1 may be electrically connected to the first positive start terminal STVF1 to receive the first positive start signal Stvf1, the positive signal input terminal INF of the second-stage shift register G2 may be electrically connected to the second positive start terminal STVF2 to receive the second positive start signal Stvf2, and the last stage shift register (not shown in the figure) in the first shift register unit group 11 may be electrically connected to the first negative start terminal STVB1 to receive the first negative start signal Stvb1, and the last stage shift register (not shown in the figure) in the second shift register unit group 12 may be electrically connected to the second negative start terminal STVB2 to receive the second negative start signal Stvb2.

[0096] During the forward scan phase, the first forward start signal Stvf1 and the second forward start signal Stvf2 sequentially output enable levels (i.e., high levels), while the first negative start signal Stvb1 and the second negative start signal Stvb2 remain at disable levels (i.e., low levels). Furthermore, the forward scan control signal U2d remains at a high level and the negative scan control signal U2d remains at a low level. This causes the first-stage shift register G1 and the second-stage shift register G2 to sequentially output the effective level of the gate drive signal Gout. In other words, assuming that the gate drive signal Gout output by the first-stage shift register G1 is the first gate drive signal Gout1 and the gate drive signal Gout output by the second-stage shift register G2 is the second gate drive signal Gout2, the effective levels of the first gate drive signal Gout1 and the second gate drive signal Gout2 are shifted sequentially. Since the shift registers G electrically connected to the pixel circuits 20 in odd-numbered rows are cascaded sequentially, and the shift registers G electrically connected to the pixel circuits 20 in even-numbered rows are cascaded sequentially, the effective level of the gate drive signal Gout received by each row of pixel circuits 20 along the forward scanning direction is shifted sequentially, enabling the row-by-row scanning of each row of pixel circuits 20 in the forward scanning direction.

[0097] During the negative scanning phase, the first negative start signal Stvb1 and the second negative start signal Stvb2 sequentially output enable levels (high levels), while the first positive start signal Stvf1 and the second positive start signal Stvf2 remain at disable levels (low levels). Furthermore, the negative scan control signal U2d remains high and the positive scan control signal U2d remains low (not shown in the figure). Based on a similar principle, the effective level of the gate drive signal Gout received by each row of pixel circuits 20 along the negative scanning direction is sequentially shifted, enabling row-by-row scanning of each row of pixel circuits 20 in the negative scanning direction.

[0098] By cascading the shift registers G electrically connected to the pixel circuits 20 in odd-numbered rows and the shift registers G electrically connected to the pixel circuits 20 in even-numbered rows, and by setting the first positive start signal Stvf1 and the second positive start signal Stvf2 to output enable levels (i.e., high levels) in the forward scanning phase, while the forward scanning control signal U2d remains high and the negative scanning control signal U2d remains low, and by setting the first negative start signal Stvb1 and the second negative start signal Stvb2 to output enable levels (i.e., high levels) in the negative scanning phase, while the negative scanning control signal U2d remains high and the forward scanning control signal U2d remains low, the interval between the enable levels of the gate drive signals Gout received by the pixel circuits 20 in adjacent rows is shortened, which reduces the refresh time of the display screen and improves the display effect.

[0099] Based on the same inventive concept, embodiments of the present invention also provide a display panel, in conjunction with reference to the reference. Figure 1 and Figure 5 The display panel 100 includes a driving circuit 10, which includes N-stage shift registers G cascaded together. The shift registers G include a first node control module 110, a second node control module 120, a first mutual control module 140, a first transistor M1, a second transistor M2, a third transistor M3, and an output module 160. Within the same shift register G: the first node control module 110 receives the input signal Inf and the scan control signal U2d to control the signal of the first node N1; the second node control module 120 receives the scan control signal U2d, the first reset clock signal Rstf, and the first voltage signal Vgh to control the signal of the second node N2; the first mutual control module 140 receives the second voltage signal Vgl and the signal of the first node N1 to control the signal of the second node N2; the gate of the first transistor M1 is electrically connected to the first node N1. The first terminal of transistor M1 receives the third voltage signal Vdd, and the second terminal of transistor M1 is electrically connected to the third node N3; the first terminal of transistor M2 receives the second voltage signal Vgl, and the gate of transistor M2 is electrically connected to the second node N2, and the second terminal of transistor M2 is electrically connected to the third node N3; the first terminal of transistor M3 is electrically connected to the third node N3, the gate of transistor M3 is electrically connected to the second node N2, and the second terminal of transistor M3 is electrically connected to the first node N1; the first terminal of transistor M3 is electrically connected to the third node N3, the gate of transistor M3 is electrically connected to the second node N2, and the second terminal of transistor M3 is electrically connected to the first node N1; wherein, the gate drive signal Gout of the i-th stage shift register G is the input signal Inf of the j-th stage shift register G; i, j, and N are all positive integers, i ≠ j, and i and j are both less than or equal to N.

[0100] The display panel provided in this embodiment of the invention, by setting a first node control module to control the signal of the first node according to the input signal and the scan control signal, by setting a second node control module to control the signal of the second node according to the scan control signal, the first reset clock signal and the first voltage signal, and by setting an output module to control the gate drive signal of the scan output terminal according to the signal of the first node, the signal of the second node, the second voltage signal and the second clock signal, can drive the pixel circuit to perform corresponding light emission display. Furthermore, by setting a first mutual control module to ensure that the second node is disabled when the first node is enabled, and by setting a second transistor and a third transistor to ensure that the first node is enabled when the second node is enabled, the second node is disabled. The signal is at a non-enabled level and is electrically connected to the third node through the first transistor. When the signal of the first node is enabled, the signal of the third node is a third voltage signal. This can isolate the second voltage signal from the first node, prevent the second voltage signal from being written to the first node when the second and third transistors cannot be turned off normally, and prevent the signal inaccuracy of the first node due to leakage current when the second and third transistors can be turned off normally. This can effectively improve the accuracy and stability of the signal of the first node, thereby ensuring the stability and accuracy of the gate drive signal output by the output module. This can effectively avoid problems such as horizontal stripes, flickering or bright lines on the display screen, thereby effectively improving the display effect of the display panel.

[0101] Optional, see reference Figure 7 , Figure 9 or Figure 11 The output module 160 includes a fourth transistor M4, a fifth transistor M5, and a first capacitor C1. The first terminal of the fourth transistor M4 receives the output control signal out, the second terminal of the fourth transistor M4 is electrically connected to the first node N1 through the first capacitor C1, and the second terminal of the fourth transistor M4 is electrically connected to the scan output terminal GOUT. The first terminal of the fifth transistor M5 receives the second voltage signal Vgl, the gate of the fifth transistor M5 is electrically connected to the second node N2, and the second terminal of the fifth transistor M5 is electrically connected to the scan output terminal GOUT.

[0102] Optional, see reference Figures 14-15 and Figures 16-18 In any of the accompanying drawings, the shift register G further includes a sixth transistor M6, and the output module 160 further includes a seventh transistor M7; the first terminal of the sixth transistor M6 receives a third voltage signal Vdd, the gate of the sixth transistor M6 is electrically connected to the first node N1, and the second terminal of the sixth transistor M6 and the second terminal of the fifth transistor M5 are electrically connected to the fourth node N4; the first terminal of the seventh transistor M7 is electrically connected to the fourth node N4, the gate of the seventh transistor M7 is electrically connected to the second node N2, and the second terminal of the seventh transistor M7 is electrically connected to the scan output terminal GOUT.

[0103] Based on the same inventive concept, embodiments of the present invention also provide a display device, which includes the display panel provided in any embodiment of the present invention. Therefore, the display device provided in the embodiments of the present invention includes the technical features of the display panel provided in any embodiment of the present invention, and can achieve the beneficial effects of the display panel provided in any embodiment of the present invention. The similarities can be referred to the above description of the display panel provided in the embodiments of the present invention, and will not be repeated here.

[0104] For example, Figure 23 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 23 As shown, the display device 200 includes the display panel 100 provided in this embodiment of the invention. The display device 200 provided in this embodiment of the invention can be any electronic product with display function, including but not limited to the following categories: mobile phones, televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc., and this embodiment of the invention does not make any special limitations on these categories.

[0105] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A display panel, characterized in that, include: Drive circuit; The driving circuit includes at least one set of N-stage shift registers cascaded together; the shift registers include a first node control module, a second node control module, a first voltage regulation control module, a first mutual control module, a second mutual control module, and an output module; In the same shift register: The first node control module is used to receive input signals and scan control signals, and to control the signals of the first node; The second node control module is used to receive the scan control signal, the first reset clock signal, and the first voltage signal, and to control the signals of the second node; The first mutual control module is used to receive the second voltage signal and the signal from the first node, and to control the signal from the second node; The first voltage regulation control module is used to receive the third voltage signal and the signal from the first node, and to control the signal from the third node; The second mutual control module is used to receive the second voltage signal, the signal of the second node, and the signal of the third node, and to control the signal of the first node; The output module is used to receive the signal from the first node, the signal from the second node, the second voltage signal, and the second clock signal, and to control the gate drive signal at the scan output terminal. Wherein, the gate drive signal of the shift register of the i-th stage is the input signal of the shift register of the j-th stage; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

2. The display panel according to claim 1, characterized in that, The first voltage regulation control module includes a first transistor; The gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor receives the third voltage signal, and the second terminal of the first transistor is electrically connected to the third node.

3. The display panel according to claim 1, characterized in that, The second mutual control module includes: a first node mutual control unit and a first isolation voltage regulator unit; The first node mutual control unit is used to receive the second voltage signal and the signal of the second node, and control the signal of the third node; The first isolation voltage regulator unit is used to receive signals from the second node and the third node, and to control the signals of the first node.

4. The display panel according to claim 3, characterized in that, The first node interconnection unit includes a second transistor, the first terminal of the second transistor receives the second voltage signal, the gate of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the third node.

5. The display panel according to claim 3, characterized in that, The first isolation voltage regulator unit includes a third transistor; The first electrode of the third transistor is electrically connected to the third node, the gate of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the first node.

6. The display panel according to claim 1, characterized in that, The first voltage signal is multiplexed into the third voltage signal.

7. The display panel according to claim 1, characterized in that, The voltage of the first voltage signal is V1; the voltage of the third voltage signal is V3; 0≤V3≤2×V1, and the voltage of the third voltage signal is adjustable.

8. The display panel according to claim 1, characterized in that, The output module includes a first output unit and a second output unit; The first output unit receives the signal from the first node and the second clock signal, and the first output unit is electrically connected to the scan output terminal; the first output unit is used to control the signal transmission path of the second clock signal to the scan output terminal according to the signal from the first node; The second output unit receives the signal from the second node and the second voltage signal, and the second output unit is electrically connected to the scan output terminal; the second output unit is used to control the signal transmission path of the second voltage signal to the scan output terminal according to the signal from the second node.

9. The display panel according to claim 8, characterized in that, The first output unit includes a fourth transistor and a first capacitor; The first terminal of the fourth transistor receives the second clock signal, the gate of the fourth transistor and the first terminal of the first capacitor are electrically connected to the first node, and the second terminal of the fourth transistor and the second terminal of the first capacitor are both electrically connected to the scan output terminal.

10. The display panel according to claim 8, characterized in that, The second output unit includes a fifth transistor; The first electrode of the fifth transistor receives the second voltage signal, the gate of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the scan output terminal.

11. The display panel according to claim 8, characterized in that, The shift register also includes a second voltage regulation control module; The second voltage regulation control module is used to receive the third voltage signal and the signal from the first node, and to control the signal from the fourth node; The second output unit is also used to receive the signal from the fourth node and control the gate drive signal according to the second voltage signal, the signal from the second node and the signal from the fourth node.

12. The display panel according to claim 11, characterized in that, The second voltage regulation control module includes a sixth transistor; The first terminal of the sixth transistor receives the third voltage signal, the gate of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the fourth node.

13. The display panel according to claim 11, characterized in that, The second output unit includes a fifth transistor and a seventh transistor; The first terminal of the fifth transistor receives the second voltage signal, the gate of the fifth transistor is electrically connected to the second node, and the second terminal of the fifth transistor is electrically connected to the fourth node; The first electrode of the seventh transistor is electrically connected to the fourth node, the gate of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the scan output terminal.

14. The display panel according to claim 1, characterized in that, The first node control module includes a first input unit; The first input unit is used to receive the input signal and the scan control signal, and to control the signal of the first node.

15. The display panel according to claim 14, characterized in that, The second node control module includes a second input unit and a second node control unit; The second input unit is used to receive the scan control signal and the first reset clock signal, and to control the signal of the fifth node; The second node control unit is used to receive the signal from the fifth node and the first voltage signal, and to control the signal of the second node.

16. The display panel according to claim 15, characterized in that, The first node control module also includes an isolation unit and a voltage regulator unit; The isolation unit is electrically connected to the first input unit at the sixth node, and is also electrically connected to the first node. The isolation unit receives a third clock signal. The isolation unit is used to control the signal transmission path between the sixth node and the first node according to the third clock signal. The voltage regulator unit is electrically connected to the fifth node, the sixth node, and the first node, respectively; the voltage regulator unit is used to control the signal transmission path between the sixth node and the first node according to the signal from the fifth node.

17. The display panel according to claim 16, characterized in that, The shift register further includes a third mutual control module; the third mutual control module is connected to the sixth node and the second node respectively, and the third mutual control module receives the second voltage signal; The third mutual control module is used to control the signal of the second node based on the signal of the sixth node and the second voltage signal.

18. The display panel according to claim 1, characterized in that, The first node includes a first child node and a second child node; the shift register also includes a voltage regulation and protection module; The voltage regulation and protection module is electrically connected to the first node control module at the first sub-node, and the voltage regulation and protection module is electrically connected to the output module at the second sub-node, and the voltage regulation and protection module receives the first voltage signal; The voltage regulation and protection module is used to stabilize the voltage of the first sub-node.

19. The display panel according to claim 1, characterized in that, The shift register further includes: a storage module; One end of the storage module receives the second voltage signal, and the other end of the storage module is electrically connected to the second node.

20. A display panel, characterized in that, include: Drive circuit; The driving circuit includes at least one set of N-stage shift registers cascaded together; the shift registers include a first node control module, a second node control module, a first mutual control module, a first transistor, a second transistor, a third transistor, and an output module; In the same shift register: The first node control module is used to receive input signals and scan control signals, and to control the signals of the first node; The second node control module is used to receive the scan control signal, the first reset clock signal, and the first voltage signal, and to control the signals of the second node; The first mutual control module is used to receive the second voltage signal and the signal from the first node, and to control the signal from the second node; The gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor receives a third voltage signal, and the second terminal of the first transistor is electrically connected to the third node; The first terminal of the second transistor receives the second voltage signal, the gate of the second transistor is electrically connected to the second node, and the second terminal of the second transistor is electrically connected to the third node; The first electrode of the third transistor is electrically connected to the third node, the gate of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the first node; The output module is used to receive the signal from the first node, the signal from the second node, the second voltage signal, and the second clock signal, and to control the gate drive signal of the scan output terminal. Wherein, the gate drive signal of the shift register of the i-th stage is the input signal of the shift register of the j-th stage; i, j and N are all positive integers, i ≠ j and i and j are both less than or equal to N.

21. The display panel according to claim 20, characterized in that, The output module includes a fourth transistor, a fifth transistor, and a first capacitor; The first terminal of the fourth transistor receives the second clock signal, the second terminal of the fourth transistor is electrically connected to the first node through the first capacitor, and the second terminal of the fourth transistor is electrically connected to the scan output terminal; The first electrode of the fifth transistor receives the second voltage signal, the gate of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the scan output terminal.

22. The display panel according to claim 21, characterized in that, The shift register further includes a sixth transistor, and the output module further includes a seventh transistor; The first terminal of the sixth transistor receives the third voltage signal, the gate of the sixth transistor is electrically connected to the first node, and the second terminal of the sixth transistor is electrically connected to the second terminal of the fifth transistor at the fourth node; The first electrode of the seventh transistor is electrically connected to the fourth node, the gate of the seventh transistor is electrically connected to the second node, and the second electrode of the seventh transistor is electrically connected to the scan output terminal.

23. A display device, characterized in that, include: The display panel according to any one of claims 1 to 22.

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