Display device and display method

Abstract

The invention provides a display device and a display method, the display device comprises a system-on-chip, a processing module, a time schedule controller and a display panel, and the system-on-chip is connected with the processing module through a signal transmission port; the system-on-chip is used for outputting an initial hot plug detection signal through the signal transmission port; the initial hot plug detection signal corresponds to different display modes through different pulse modes; the processing module is used for decoding the initial hot plug detection signal to generate at least two control signals; and the time schedule controller is used for performing signal combination on the at least two control signals to generate a target signal, and controlling the display panel to switch among at least three display modes based on the target signal. Therefore, the technical problem that switching of multiple display modes cannot be achieved through a single physical pin is solved, and the interface design flexibility and the cost effectiveness of the display device are improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and display method. Background Technology

[0002] In recent years, esports has become a significant growth area for the display industry, with monitor technology continuously evolving towards higher resolutions and refresh rates. This process has given rise to refresh rate doubling technology based on Dual Line Gate (DLG), which doubles the refresh rate by reducing the vertical resolution. For example, a UD 60Hz monitor can achieve an FHD 120Hz display effect through 2x DLG technology and a QHD 90Hz display effect through 1.5x DLG technology. This technological evolution has led to a diversification of display modes, requiring flexible switching between normal mode, 1.5x DLG mode, and 2x DLG mode. In the early days, when only 2x DLG technology existed, the client could switch between normal and 2x DLG modes by applying a high or low level to the timing controller function pin through a single input interface pin. However, with the introduction of 1.5x DLG mode, the need to switch between three display modes rendered the single-pin control scheme ineffective. Existing technology requires at least two independent pins to complete the switching operation of the three modes, severely limiting the flexibility of display device interface design and cost control. Summary of the Invention

[0003] This application provides a display device and display method that can switch between multiple display modes through a single signal transmission port, thereby improving the interface design flexibility and cost-effectiveness of the display device.

[0004] In a first aspect, the display device provided in the embodiments of this application includes a system-on-a-chip (SoC), a processing module, a timing controller, and a display panel. The SoC is connected to the processing module through a signal transmission port, and the timing controller is connected to both the processing module and the display panel. The system-on-a-chip (SoC) is used to output an initial hot-plug detection signal through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns; the system-on-a-chip (SoC) is used to output an initial hot-plug detection signal through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns. The processing module is used to decode the initial hot-plug detection signal and generate at least two control signals; The timing controller is used to combine the at least two control signals to generate a target signal, and control the display panel to switch between at least three display modes based on the target signal.

[0005] Secondly, the display method provided in the embodiments of this application is applied to a display device, and the method includes: An initial hot-plug detection signal is output through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns; the initial hot-plug detection signal is output through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns. The initial hot-plug detection signal is decoded to generate at least two control signals; The at least two control signals are combined to generate a target signal, and the display panel is controlled to switch between at least three display modes based on the target signal.

[0006] In summary, the display device and display method provided in this application include a system-on-a-chip (SoC), a processing module, a timing controller, and a display panel. The SoC is connected to the processing module via a signal transmission port, and the timing controller is connected to both the processing module and the display panel. The SoC outputs an initial hot-plug detection signal through the signal transmission port, and the initial hot-plug detection signal corresponds to different display modes through different pulse patterns. The processing module decodes the initial hot-plug detection signal to generate at least two control signals. The timing controller combines the control signals to generate a target signal and controls the display panel to switch between at least three display modes based on the target signal. This solves the technical problem of not being able to achieve multiple display mode switching through a single physical pin and improves the interface design flexibility and cost-effectiveness of the display device. Attached Figure Description

[0007] The present invention will be further described below with reference to the accompanying drawings. It should be noted that the accompanying drawings described below are merely for illustrating some embodiments of the present invention. Those skilled in the art can obtain other drawings based on the above drawings without any creative effort.

[0008] Figure 1 A schematic diagram of a display device provided for an embodiment of this application.

[0009] Figure 2 This is an exemplary schematic diagram of multi-mode switching in an embodiment of this application.

[0010] Figure 3 This is an exemplary schematic diagram of a pulse mode in an embodiment of this application.

[0011] Figure 4 This is an exemplary schematic diagram of a circuit in which the hot-plug detection signal passes through two flip-flops in an embodiment of this application.

[0012] Figure 5This is an exemplary schematic diagram of signals A, B, and C in an embodiment of this application.

[0013] Figure 6 This is an exemplary schematic diagram of the analog waveforms of signals A, B, and C in three modes in the embodiments of this application.

[0014] Figure 7 This is an exemplary circuit diagram of signals B and C passing through a logic gate in an embodiment of this application.

[0015] Figure 8 for Figure 7 An exemplary schematic diagram showing the correspondence between signals and devices. Detailed Implementation

[0016] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0017] In this invention, the terms "first," "second," etc., are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the aforementioned process, method, product, or apparatus.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily imply that all embodiments are the same, nor are they independent or alternative embodiments mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] This application provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0020] In one embodiment, Figure 1 A schematic diagram of a display device provided for an embodiment of this application, as shown below. Figure 1As shown, the display device 100 includes a system-on-a-chip 101, a processing module 102, a timing controller 103, and a display panel 104. The system-on-a-chip 101 is connected to the processing module 102 through a signal transmission port, and the timing controller 103 is connected to both the processing module 102 and the display panel 104. The system-on-chip (SoC) 101 is used to output an initial hot plug detect (HPD) signal through a signal transmission port; the initial hot plug detect signal corresponds to different display modes through different pulse modes.

[0021] The processing module 102 is used to decode the initial hot-plug detection signal and generate at least two control signals.

[0022] The timing controller (TCON) 103 is used to combine at least two control signals to generate a target signal, and control the display panel 104 to switch between at least three display modes based on the target signal.

[0023] The system-on-a-chip (SoC) 101, which can be an integrated circuit chip, is capable of performing complex signal processing and control tasks. SoC 101 acts as the main control unit, connected to the processing module 102 via a signal transmission port, and is responsible for outputting the initial signal. The timing controller 103 is connected to both the processing module 102 and the display panel 104, receiving instructions from the processing module 102 and driving the display panel 104. The processing module 102 is a circuit or logic unit used to receive and process specific signals. Its function is to analyze, convert, or decode the received signals to generate new control instructions or data. The timing controller 103 is responsible for receiving control signals from the processing module 102, generating the timing signals required to drive the display panel 104, thereby controlling the pixel display and refresh of the display panel 104. The display panel 104 is the output part of the display device, such as a liquid crystal display panel or an OLED display panel, used to display images or video content according to the signals provided by the timing controller 103. A signal transmission port can be a physical interface used to transmit electrical or data signals between different electronic components, such as a physical pin of a system-on-a-chip 101. A hot-plug detection signal can be a signal used to detect changes in the connection status of a device. It typically indicates the insertion or removal of a device through specific level changes or pulse sequences, and can indicate the function of switching display modes. A pulse mode can be different pulse sequences or waveform characteristics used in the hot-plug detection signal, with each mode corresponding to a specific display mode. A display mode can be different states or configurations of the display panel 104 during operation, such as a regular refresh rate mode, a multiplied refresh rate mode, etc. A control signal can be an electrical signal generated by the processing module 102 and sent to the timing controller 103, used to instruct the timing controller 103 to perform a specific operation or switch to a specific operating state. Signal combination can refer to the process by which the timing controller 103 processes multiple received control signals according to a preset logical relationship to generate a comprehensive target signal. The target signal can be the result of the signal combination, which is directly used to drive the timing controller 103 to control the display panel 104 to switch to a specific display mode.

[0024] Specifically, the system-on-chip 101 is configured to output an initial hot-plug detection signal through a signal transmission port. This initial hot-plug detection signal is not merely used for traditional device connection detection; it is given a new function: corresponding to different display modes through its different pulse patterns. For example, it can be preset to different numbers of pulses, pulses of different widths, or pulse sequences of different frequencies, with each pulse pattern defined to indicate a specific display mode.

[0025] Processing module 102 is configured to receive and decode the hot-plug detection signal. The decoding process may include analyzing the signal's waveform characteristics, pulse count, or duration to identify the specific pulse pattern sent by system-on-chip 101. Based on the identification result, processing module 102 generates at least two control signals. These control signals can be independent level signals or digital signals with specific encoding; their number and encoding method depend on the number and complexity of the display modes to be switched. For example, multiple independent output pins can be used to output high and low level signals respectively, or encoded data can be transmitted via a serial communication protocol.

[0026] The timing controller 103 is configured to receive at least two control signals from the processing module 102 and combine the at least two control signals. Signal combination can be implemented using simple logic gates; for example, multiple control signals can be input into a logic circuit to generate a comprehensive target signal based on a preset logical relationship. The level state or encoded value of this target signal will uniquely indicate the display mode that needs to be switched.

[0027] Therefore, the timing controller 103 controls the display panel 104 to switch between at least three display modes based on the target signal. For example, when the target signal is in the first state, the timing controller 103 drives the display panel 104 into the normal mode; when the target signal is in the second state, the timing controller 103 drives the display panel 104 into the first frequency multiplication mode; and when the target signal is in the third state, the timing controller 103 drives the display panel 104 into the second frequency multiplication mode. This switching mechanism allows the display panel 104 to flexibly switch between multiple preset display modes based on a single hot-plug detection signal issued by the system-on-a-chip 101, thereby meeting the display requirements of different application scenarios.

[0028] As an example, the signal transmission port can be a pin, such as pin35; the front-end HPD signal passes through two flip-flops, and different signals are output through pin35. The signals are processed by the circuit and transmitted to TCON, where TCON performs mode switching.

[0029] This application utilizes different pulse patterns of the hot-plug detection signal output by the system-on-a-chip 101 to indicate multiple display modes. The processing module 102 decodes and generates control signals, which are then combined by the timing controller 103 to control the switching of the display panel 104. This effectively solves the problem of requiring multiple pins for multi-mode switching in traditional DLG technology, enabling flexible switching of the display panel 104 between at least three display modes through a single signal transmission port. This reduces interface complexity and improves the integration of the display device and the user experience.

[0030] In some embodiments of this application, how to efficiently and reliably transmit control signals to the timing controller 103 and ensure that the timing controller 103 can accurately generate target signals based on the combination state of the signals, thereby achieving precise display mode switching, is a problem that needs further consideration.

[0031] Based on this, in one embodiment, at least two control signals include a first control signal and a second control signal; the timing controller 103 is connected to the processing module 102 through a communication interface; the communication interface includes at least a first interface and a second interface; the timing controller 103 is also used to: receive the first control signal through the first interface, receive the second control signal through the second interface; and combine the signals based on the level states of the first control signal and the second control signal to generate a target signal.

[0032] The first control signal and the second control signal are generated by the processing module 102 based on the decoding result of the hot-plug detection signal. They respectively carry different display mode information indicated by the hot-plug detection signal. For example, the level states of the two control signals (such as high level or low level) can encode different mode selections, providing the timing controller 103 with explicit mode switching instructions.

[0033] The communication interface is the physical and logical channel for data and control signal transmission between the processing module 102 and the timing controller 103. This communication interface can take various forms; for example, it can be a set of parallel dedicated signal lines, a serial bus interface, or other connection methods capable of signal transmission. The first interface and the second interface are specific ports or pins in the communication interface, used to receive the first control signal and the second control signal respectively, ensuring the independence and reliability of signal transmission and avoiding signal confusion or interference.

[0034] After receiving the first control signal and the second control signal, the timing controller 103 performs a level-state logic combination. For example, the timing controller 103 can have a built-in combinational logic circuit whose input is connected to the first interface and the second interface, and whose output generates the target signal. This combination can be a simple AND, OR, or NOT gate operation, or a more complex lookup table implementation, to map the level states of the two control signals to a specific target signal. In this way, the timing controller 103 can directly and quickly determine the required display mode based on the level combination of the input control signals and generate the corresponding target signal to drive the display panel 104.

[0035] This application improves the reliability and clarity of control signal transmission by defining a first control signal and a second control signal, and establishing a dedicated communication path including the first and second interfaces between the processing module 102 and the timing controller 103. The timing controller 103 can directly and accurately combine the signals based on the level states of the two independent control signals to generate the target signal. This signal combination method simplifies the internal logic design of the timing controller 103, reduces implementation complexity, and effectively avoids potential errors in the signal transmission or combination process. Therefore, it ensures that the timing controller 103 can accurately parse the display mode information indicated by the hot-plug detection signal, thereby achieving stable, fast, and correct switching of the display panel 104 between different modes, improving the overall performance of the display device and the user experience.

[0036] In some embodiments of this application, how to explicitly associate different pulse modes of the hot-plug detection signal with specific display modes, and how to precisely trigger the switching of display modes through specific combinations of control signals, still need to be further refined and specified to ensure that the system can accurately and reliably respond to changes in external signals and adjust the display state.

[0037] Based on this, in one embodiment, the pulse mode includes a low-level pulse, a high-level pulse, and two consecutive high-level pulses; the display mode includes a normal mode corresponding to the low-level pulse, a 1.5x frequency multiplication function mode corresponding to the two consecutive high-level pulses, and a 2x frequency multiplication function mode corresponding to the high-level pulse; the timing controller 103 is further configured to: control the display panel 104 to switch to the normal mode when the first control signal is a first low level and the second control signal is a second low level, and the target signal is a combination of low and low levels; control the display panel 104 to switch to the 1.5x frequency multiplication function mode when the first control signal is a first high level and the second control signal is a second high level, and the target signal is a combination of high and high levels; and control the display panel 104 to switch to the 2x frequency multiplication function mode when the first control signal is a first high level and the second control signal is a second low level, and the target signal is a combination of high and low levels.

[0038] The pulse mode refers to the specific manifestation of the hot-plug detection signal output by the system-on-a-chip 101. These pulses carry different display mode information through their unique timing characteristics. A low-level pulse refers to the hot-plug detection signal remaining low for a period of time, typically indicating a default or basic connection state, and can serve as a reference signal for the system to identify the normal mode. A high-level pulse refers to the hot-plug detection signal transitioning from low to high and then back to low for a period of time, forming an independent, brief high-level signal. Its duration or width can be preset to distinguish different functional modes. Two consecutive high-level pulses refer to the hot-plug detection signal appearing two high-level pulses consecutively within a period of time, possibly separated by a brief low level or directly consecutively. This mode encodes more complex functional instructions through the number and sequence of pulses.

[0039] Display modes represent the operating states of the display panel 104 under different performance requirements. Normal mode typically refers to the display panel 104 operating at its default or standard refresh rate, resolution, and color depth, suitable for most everyday display needs. The 1.5x multiplier mode increases the refresh rate or internal clock frequency of the display panel 104 to 1.5 times that of normal mode, providing smoother dynamic images or supporting specific display effects. The 2x multiplier mode increases the refresh rate or internal clock frequency of the display panel 104 to twice that of normal mode, further enhancing display performance, such as for high frame rate games or professional graphics applications. By switching modes, the user experience can be optimized or the requirements of specific application scenarios can be met.

[0040] After receiving the control signal generated by the processing module 102, the timing controller 103 combines the signals and generates a target signal to control the switching of the display panel 104. Specifically, when the first control signal is a first low level and the second control signal is a second low level, the timing controller 103 recognizes this specific level combination as a preset instruction and generates a corresponding target signal. This target signal is used to control the display panel 104 to switch to the normal mode, ensuring stable operation of the display device in its basic state. When the first control signal is a first high level and the second control signal is a second high level, the timing controller 103 recognizes this combination of high and low levels as another instruction and generates a corresponding target signal. This target signal is used to control the display panel 104 to switch to the 1.5x frequency multiplier mode to improve display performance. When the first control signal is a first high level and the second control signal is a second low level, the timing controller 103 recognizes this combination of high and low levels as a third instruction and generates a corresponding target signal. This target signal is used to control the display panel 104 to switch to the 2x frequency multiplier mode to achieve higher display performance. Based on the explicit combination logic of the control signal level states, the timing controller 103 can accurately parse the instructions from the processing module 102 and reliably control the display panel 104 to switch between different display modes according to the pulse pattern of the hot-plug detection signal.

[0041] This application defines the correspondence between various pulse modes of the hot-plug detection signal (low-level pulse, one high-level pulse, two consecutive high-level pulses) and specific display modes of the display panel 104 (normal mode, 1.5x frequency multiplication mode, 2x frequency multiplication mode). Based on this, it further specifies how the timing controller 103 generates a target signal based on specific level combinations of the first and second control signals (e.g., low level and low level, high level and high level, high level and low level), and precisely controls the display panel 104 to switch to the corresponding display mode. This effectively solves the ambiguity and uncertainty that may exist in display mode switching in the basic scheme, ensuring that the system can accurately and efficiently adjust the working state of the display panel 104 according to the intent of the external hot-plug detection signal. Through this mechanism, the display device can flexibly switch between multiple performance modes, thereby optimizing the user experience and improving the adaptability and response speed of the display system to different application scenarios.

[0042] In some embodiments of this application, how to ensure that the processing module 102 can accurately generate a stable and correct control signal based on the complex pulse pattern (e.g., pulse number and level changes) of the hot-plug detection signal, and effectively control the transmission of the signal to avoid signal transmission errors or unnecessary power consumption, is a problem that needs further consideration.

[0043] Based on this, in one embodiment, the processing module 102 includes at least two triggers and at least two switching devices; the output of each trigger is connected to the control terminal of a switching device, and the output of the switching device is connected to a communication interface; the triggers are used to generate a first control signal and a second control signal according to the number of pulses and level changes of the hot-plug detection signal; the switching devices are used to turn on or off according to the level state of the first control signal or the second control signal, so as to transmit the first control signal to the first interface and the second control signal to the second interface.

[0044] The switching device can be an electronic component capable of being turned on or off based on the level of a control signal. Here, the switching device is used to turn on or off according to the level of a first or second control signal to transmit the first control signal to a first interface and the second control signal to a second interface. For example, when the corresponding control signal is high, the switching device is on, allowing the signal to pass; when the control signal is low, the switching device is off, preventing the signal from passing. This controlled transmission mechanism ensures that the decoded control signal is sent to the timing controller 103 only when needed, thus avoiding the transmission of invalid signals and helping to reduce system power consumption. The output of each flip-flop is connected to the control terminal of a switching device, and the control signal generated by the flip-flop directly controls the on / off state of the corresponding switching device. The output of the switching device is connected to the communication interface, ensuring that the control signal can be accurately delivered to the timing controller 103.

[0045] As an example, the signal transmission port can be a pin, such as pin35; Figure 2 This is an exemplary schematic diagram of multi-mode switching in an embodiment of this application, such as... Figure 2 As shown, this is a 1-to-multi-mode configuration. The initial hot-plug detection signal output by the SoC can be denoted as the HPD1 signal; the HPD1 signal can be denoted as signal A; the first control signal can be denoted as signal B, which can be understood as output to control switch signal 1; the second control signal can be denoted as signal C, which can be understood as output to control switch signal 2. Figure 3 This is an exemplary schematic diagram of a pulse mode in an embodiment of this application, such as... Figure 3 As shown, different signals are output through pin 35 of the system-on-a-chip 101, and the signals are processed by the circuit before being transmitted to the TCON for mode switching control. Since the TCON cannot directly recognize special waveforms, signal processing is required through circuit design. The front-end HPD1 signal is separated into two signals, B and C, controlling the switches, by two flip-flops. Figure 4 This is an exemplary schematic diagram of a circuit in an embodiment of this application where the hot-plug detection signal passes through two flip-flops, as shown below. Figure 4 As shown. Figure 5This is an exemplary schematic diagram of signals A, B, and C in an embodiment of this application, as shown below. Figure 5 As shown. Figure 6 This is an exemplary schematic diagram of the analog waveforms of signals A, B, and C in three modes, as shown in the embodiments of this application. Figure 6 As shown, the waveform above is the normal mode where A outputs a low level, and B and C output a low level; the middle waveform is the 2x DLG mode where A and B output a high-level signal, and C outputs a low level; the waveform below is the 1.5x DLG mode where A outputs a high-level signal twice, B outputs a high-level signal at the beginning of the first switch, and C outputs a high level on the second switch.

[0046] In this application, the processing module 102, by introducing triggers and switching devices, can more accurately decode and transmit the hot-plug detection signal. The triggers effectively capture the number of pulses and level changes of the hot-plug detection signal, converting them into stable and reliable first and second control signals, thereby improving the accuracy of signal decoding. Simultaneously, the switching devices turn on or off according to the level state of the control signals, achieving precise control over the transmission of the control signals. This avoids invalid or erroneous control signals being transmitted to the timing controller 103, ensuring that the signals received by the timing controller 103 are effectively filtered and processed, thereby improving the reliability and stability of display mode switching.

[0047] In some embodiments of this application, if the type of switching device and its linkage with the control signal are not clearly defined, the stability of signal transmission or the accuracy of control may be affected, especially in scenarios where precise on or off switching is required based on the level of the control signal to ensure correct signal transmission.

[0048] Based on this, in one embodiment, the switching device is a transistor or a logic gate switch; at least two flip-flops include a first flip-flop and a second flip-flop, and at least two switching devices include a first switching device and a second switching device; the output terminal of the first flip-flop is connected to the control terminal of the first switching device; the output terminal of the second flip-flop is connected to the control terminal of the second switching device; the output terminal of the first switching device is connected to a first interface; the output terminal of the second switching device is connected to a second interface; the first switching device is turned on when the first control signal is a first high level and turned off when the first control signal is a first low level; the second switching device is turned on when the second control signal is a second high level and turned off when the second control signal is a second low level.

[0049] In signal transmission, the choice of switching device type is crucial for reliable signal transmission, as it is a key component in the signal path. When the switching device is a transistor, such as a field-effect transistor (FET) or a bipolar junction transistor (BJT), it precisely controls the conduction or cutoff of the main current path (such as the source-drain of the FET or the collector-emitter of the BJT) by the level of its control electrode (such as the gate of the FET or the base of the BJT). Transistors have advantages such as fast response speed, relatively low power consumption, and ease of integration, enabling rapid response and efficient transmission of control signals. When the switching device is a logic gate switch, such as a CMOS transmission gate or an analog switch, it controls the internal signal path through logic control signals to achieve signal selection or isolation.

[0050] The at least two triggers, including a first trigger and a second trigger, and the at least two switching devices, including a first switching device and a second switching device, define the internal structure of the processing module 102 for generating and transmitting control signals. The first trigger is responsible for generating a first control signal, and the second trigger is responsible for generating a second control signal.

[0051] The output of the first flip-flop is connected to the control terminal of the first switching device, and the output of the second flip-flop is connected to the control terminal of the second switching device, thus establishing a direct link from the generation of the control signal to the driving of the switching device.

[0052] The output terminal of the first switching device is connected to the first interface, and the output terminal of the second switching device is connected to the second interface, further clarifying the specific path for the control signal to be transmitted from the processing module 102 to the timing controller 103. Thus, when the corresponding switching device is turned on, the first control signal and the second control signal can be transmitted to the timing controller 103 through the first interface and the second interface respectively, providing a clear physical channel for the timing controller 103 to receive and process the control signal.

[0053] The first switching device is turned on when the first control signal is at a first high level and turned off when the first control signal is at a first low level; the second switching device is turned on when the second control signal is at a second high level and turned off when the second control signal is at a second low level, thus defining the precise operating logic of the switching devices. This ensures that the signal can be reliably transmitted when the control signal is in a valid (high level) state, and that the signal path is effectively blocked when the control signal is in an invalid (low level) state, avoiding unnecessary signal transmission or interference.

[0054] This application specifies the switching devices in the processing module 102 as transistors or logic gate switches, and clarifies the precise on / off logic between the first and second switching devices and the first and second control signals. This ensures that when the first or second control signal is at a high level, the corresponding switching device can reliably turn on, accurately transmitting the signal to the corresponding interface of the timing controller 103; when the control signal is at a low level, the switching device reliably turns off, effectively isolating the signal. The device selection and control logic effectively avoid signal transmission instability or malfunctions caused by unclear switching device types or inaccurate control, thereby improving the reliability and accuracy of the control signals transmitted from the processing module 102 to the timing controller 103, and thus ensuring the stability and correctness of the display panel 104 switching between different display modes.

[0055] In some embodiments of this application, due to factors such as environmental interference, device aging, or transient failure, triggers or switching devices may malfunction, causing deviations in the combination of control signals transmitted to the timing controller 103, which may in turn cause the display panel 104 to switch to an incorrect display mode, affecting the stability of the system and the user experience.

[0056] Based on this, in one embodiment, the processing module 102 further includes an AND logic gate, the input of which is connected to the output of the flip-flop; the AND logic gate is used to logically combine the first control signal and the second control signal to generate a verification signal, which is used to verify the effectiveness of the signal combination of the first control signal and the second control signal to avoid malfunction of the switching device.

[0057] The AND gate receives the first and second control signals as inputs and performs a logical AND operation on them to generate a verification signal. For example, when both the first and second control signals are high, the AND gate outputs a high-level verification signal; under other input combinations, it outputs a low-level verification signal. The generated verification signal provides an additional verification mechanism to confirm whether the combination of the first and second control signals conforms to the expected valid state.

[0058] In this application, an AND logic gate is introduced in the processing module 102 to logically combine the first and second control signals to generate a verification signal, which can monitor the combination status of the control signals in real time. When the control signal combination is abnormal, the verification signal can promptly indicate this, thereby preventing the switching device from malfunctioning when receiving an incorrect control signal. This improves the reliability of signal transmission, effectively prevents erroneous switching of display modes due to incorrect control signals, and thus enhances the stability and reliability of the display device.

[0059] In some embodiments of this application, simply preventing malfunctions of switching devices may not be sufficient to fully guarantee the accuracy of display mode switching. If the status information of the signal combination is not fed back to the timing controller 103 in a timely or accurate manner, it may still lead to malfunctions of the display mode, affecting the user experience.

[0060] Based on this, in one embodiment, the logic gate is also used to provide state information based on the combination of verification signal feedback signals to avoid display mode malfunctions.

[0061] In this process, after generating the verification signal, the AND gate further transmits the validity or specific pattern information of the signal combination represented by the verification signal to the timing controller 103 in a recognizable form. The verification signal itself is the result of logically combining the first and second control signals, and its state (e.g., high or low level) directly reflects whether a specific combination of the two control signals meets the preset validity conditions. By feeding back this state information, the timing controller 103 can obtain additional assurance regarding whether the received control signals have undergone internal logic verification by the processing module 102. In specific implementation, various methods can be adopted. For example, the AND gate can be configured with an independent output port, directly connecting the level state of the verification signal as a feedback signal line to a dedicated input pin of the timing controller 103. The timing controller 103 can obtain the state information of the signal combination in real time by monitoring the level change of this pin. Another method is to encode the verification signal into the existing communication interface, for example, by implicitly transmitting verification information by changing specific timing parameters (such as pulse width, edge interval) of the first or second control signal, or by adding a status bit to the communication protocol to explicitly carry the state of the verification signal. The timing controller 103 needs to have the corresponding decoding capability to parse the feedback information. This technical feature aims to ensure, through the aforementioned feedback mechanism, that the mode switching operation of the display panel 104 is based on accurate and verified control signals. Malfunctions in the display mode can lead to abnormal display images, refresh rate mismatches, color distortion, and other problems, severely impacting user experience and device performance. By receiving and parsing the feedback signal combination status information, the timing controller 103, upon receiving the first and second control signals, will not immediately execute the display mode switch but will wait for or simultaneously confirm the feedback information. Only when the feedback information clearly indicates that the currently received control signal combination is valid and meets expectations will the timing controller 103 trigger the corresponding display mode switch. If the feedback information indicates that the signal combination is invalid or abnormal, the timing controller 103 can take preventative measures, such as maintaining the current display mode or entering a safe mode, thereby effectively preventing malfunctions in the display mode caused by incorrect or unverified control signals.

[0062] In this application, the logic gates not only generate verification signals to prevent malfunctions of the switching devices, but also, more importantly, provide feedback status information of the signal combination based on the verification signal. Thus, when the timing controller 103 receives the first control signal and the second control signal for signal combination, it can simultaneously obtain the validity or specific mode information of the combination after logical verification within the processing module 102. The timing controller 103 can use the feedback status information to perform secondary confirmation on the received control signal, ensuring that it is a valid combination verified by the internal logic of the processing module 102. Therefore, even if there is transient interference during signal transmission or an anomaly occurs within the processing module 102, the timing controller 103 can promptly identify and avoid switching the display mode based on erroneous or unverified signals, thereby significantly improving the accuracy and reliability of display mode switching, effectively preventing malfunctions of the display mode, and ensuring stable operation of the display device and a good user experience.

[0063] In some embodiments of this application, when there are multiple combinations of control signals that may correspond to different display modes, the display device may have difficulty accurately identifying and confirming the currently active specific display mode, especially when multiple control signals are at a high level at the same time, which may lead to ambiguity or response delay in display mode switching.

[0064] Based on this, in one embodiment, the logic gate is also used to generate a high-level verification signal when both the first control signal and the second control signal are high, and to determine the state information of the signal combination as the interface signal mapping logic when the timing controller 103 switches to the 1.5 times frequency multiplication function mode.

[0065] Specifically, when both the first and second control signals are high, the two input signals received by the AND gate are also high. In digital logic, a high level typically represents a logic "1" or a preset effective voltage range, indicating that the corresponding control signal has been activated. Under this condition, the AND gate outputs a high-level verification signal according to its logic function. This high-level verification signal serves as a clear indication that the specific input conditions have been met and can be used for subsequent logic judgments or control operations. When the AND gate generates a high-level verification signal, this signal is the interface signal mapping logic required to instruct the timing controller 103 to switch to the 1.5x frequency multiplier function mode. It can accurately identify and respond to specific combinations of control signals, thereby triggering the expected display mode switching. The interface signal mapping logic refers to the specific signal configuration or sequence that the timing controller 103 needs to receive and process to implement a specific display mode (e.g., the 1.5x frequency multiplier function mode).

[0066] As an example, the first interface can be denoted as GPIO1; the second interface can be denoted as GPIO2; the hot-plug detection signal output by the SoC can be denoted as HPD1 signal; HPD1 signal can be denoted as signal A; the first control signal can be denoted as signal B, which can be understood as output to control switch signal 1; the second control signal can be denoted as signal C, which can be understood as output to control switch signal 2; signal B and signal C are combined with a logic gate to generate signal D. Figure 7 This is an exemplary circuit diagram illustrating how signals B and C pass through a logic gate in an embodiment of this application, as shown below. Figure 7 As shown, when signals B and C are ANDed together, the high and low levels of GPIO1 and GPIO2 signals transmitted by signal D to TCON are determined. This means that in normal mode, TCON GPIO1 receives a low level of signal B; in 2x frequency multiplication mode (2x DLG), TCON GPIO1 receives a high level of signal B; and in 1.5x frequency multiplication mode (1.5x DLG), TCON GPIO2 receives a high level of signal C. Figure 8 for Figure 7 An exemplary schematic diagram showing the correspondence between signals and devices, such as... Figure 8 As shown in the diagram, the above circuit conversion enables at least three modes of switching for the same root pin control on the client side.

[0067] This application solves the ambiguity problem of display mode recognition under multiple signal combinations by mapping the interface signal mapping logic, where both the first and second control signals are high-level, to the high-level verification signal generated by the logic gate, which directly corresponds to the trigger timing controller 103 switching to the 1.5 times frequency multiplication function mode. When the display device receives a specific hot-plug detection signal, it can more stably and accurately enter the 1.5 times frequency multiplication function mode, improving the reliability of display mode switching and user experience.

[0068] In some implementations, the hot-plug detection signal is susceptible to electromagnetic interference, line noise, and other factors during transmission, leading to signal waveform distortion or glitches. If the processing module 102 directly decodes the noisy signal, it may incorrectly identify the pulse pattern, thereby generating inaccurate control signals. This could ultimately cause the timing controller 103 to misjudge the display mode, affecting the normal switching of the display panel 104 and the stability of the display effect.

[0069] Based on this, in one embodiment, the processing module 102 further includes a filtering circuit connected to the signal transmission port for filtering the hot-plug detection signal to obtain the target hot-plug detection signal.

[0070] Specifically, the filtering circuit can be implemented in various ways. For example, it can be an RC low-pass filter composed of resistors and capacitors. By appropriately selecting the resistor and capacitor values, noise components higher than the fundamental frequency of the hot-plug detection signal can be filtered out while maintaining signal integrity. Alternatively, LC filters, active filters, or digital filters can be used to adapt to different noise environments and performance requirements. Through filtering, it can be ensured that the subsequent processing module 102 receives a high-quality hot-plug detection signal, laying the foundation for accurate decoding and control signal generation.

[0071] This application preprocesses the hot-plug detection signal by introducing a filtering circuit connected to the signal transmission port in the processing module 102. This effectively solves the problem of noise interference affecting the hot-plug detection signal during transmission. The filtering circuit removes noise and glitches from the signal, making the hot-plug detection signal received by the processing module 102 more stable and pure. This improves the accuracy of the decoding of the hot-plug detection signal by the processing module 102, ensuring that different pulse modes can be correctly identified and accurate first and second control signals can be generated. Therefore, the timing controller 103 can combine signals based on accurate control signals to generate the correct target signal, thereby reliably controlling the display panel 104 to switch between normal mode, 1.5x frequency multiplier mode, and 2x frequency multiplier mode. This avoids display mode malfunctions caused by signal interference, greatly improving the stability of the display device and the user experience.

[0072] In some implementations, the hot-plug detection signal may be subject to noise interference or signal distortion, causing the processing module 102 to misjudge the signal, which in turn leads to incorrect or unstable switching of the display mode, affecting the normal operation of the display device and the user experience.

[0073] Based on this, in one embodiment, the processing module 102 further includes: a detector connected to the filtering circuit for detecting the rising and falling edges of the target hot-plug detection signal; a timer connected to the detector for monitoring the pulse parameters corresponding to the rising and falling edges; and a timing controller 103 for determining that the pulses in the target hot-plug detection signal are valid pulses and triggering the switching of the display mode when the pulse parameters are within a preset range; and determining that the pulses in the target hot-plug detection signal are invalid pulses and not triggering the switching of the display mode when the pulse parameters are not within the preset range.

[0074] Specifically, a detector is a circuit or module used to identify changes in the level of an input signal. In digital signal processing, rising and falling edges are transient transition points where a signal changes from low to high or from high to low. A detector can be a comparator circuit that compares a target hot-plug detection signal with a reference voltage, outputting an indication signal when the signal voltage exceeds or falls below the reference voltage. It can also be a digital logic circuit, such as a D flip-flop or an edge detector, used to capture transient changes in the signal. It is connected to a filter circuit to ensure that the detected signal is filtered, reducing false detections caused by noise.

[0075] A timer is a circuit or module used to measure time intervals. In this case, it's used to measure parameters such as the pulse width, period, or duty cycle of a hot-plug detection signal. This parameter is crucial for determining whether the pulse signal conforms to a preset specification. A timer can be a counter that starts counting when a rising edge is detected and stops counting when a falling edge is detected, thus obtaining the pulse width. Alternatively, the pulse period can be determined by measuring the time between consecutive rising or falling edges. Timers are typically driven by a high-frequency clock source to provide accurate time measurements.

[0076] The timing controller 103 acts as the decision-maker here, determining whether the received hot-plug detection signal conforms to the expected valid pulse based on the pulse parameters provided by the timer. The timing controller 103 may contain a logic judgment unit that presets a set of threshold ranges for pulse parameters, such as minimum pulse width, maximum pulse width, and minimum period. When the pulse parameters measured by the timer fall within the preset range, the timing controller 103 determines it as a valid pulse and continues to execute subsequent display mode switching logic. Conversely, if the pulse parameters exceed the range, they are determined as invalid pulses, ignored, and no display mode switching is triggered, thereby avoiding malfunctions caused by abnormal signals.

[0077] This application introduces a detector and a timer, and a timing controller 103 judges the validity of the pulse parameters of the hot-plug detection signal. This application can accurately identify the rising and falling edges of the hot-plug detection signal and measure its pulse width, period, and other key parameters. The timing controller 103 compares these parameters with a preset range, effectively distinguishing between normal, valid hot-plug detection signals and signals affected by noise or abnormalities. When an invalid pulse is detected, the display mode switching is not triggered, thus avoiding malfunctions caused by signal distortion or noise. This significantly improves the stability and reliability of the display device in complex electromagnetic environments, ensures the accuracy of display mode switching, and ultimately optimizes the user experience. This application also proposes a display method using the above-mentioned display device. The method includes outputting an initial hot-plug detection signal through a signal transmission port; the initial hot-plug detection signal corresponding to different display modes through different pulse modes; decoding the initial hot-plug detection signal to generate at least two control signals; combining the at least two control signals to generate a target signal; and controlling the display panel 104 to switch between at least three display modes based on the target signal.

[0078] The details of the display method can be found in the previous description of the display device, and will not be repeated here.

[0079] The display device and display method provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. The above modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display device, characterized in that, It includes a system-on-a-chip, a processing module, a timing controller, and a display panel. The system-on-a-chip is connected to the processing module through a signal transmission port, and the timing controller is connected to both the processing module and the display panel. The system-on-a-chip (SoC) is used to output an initial hot-plug detection signal through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns; the system-on-a-chip (SoC) is used to output an initial hot-plug detection signal through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns. The processing module is used to decode the initial hot-plug detection signal and generate at least two control signals; The timing controller is used to combine the at least two control signals to generate a target signal, and control the display panel to switch between at least three display modes based on the target signal.

2. The display device according to claim 1, characterized in that, The at least two control signals include a first control signal and a second control signal; the timing controller is connected to the processing module via a communication interface; the communication interface includes at least a first interface and a second interface; the timing controller is further configured to: The first control signal is received through the first interface, and the second control signal is received through the second interface; The target signal is generated by combining the signals based on the level states of the first control signal and the second control signal.

3. The display device according to claim 2, characterized in that, The pulse mode includes a low-level pulse, one high-level pulse, and two consecutive high-level pulses; the display mode includes a normal mode corresponding to the low-level pulse, a 1.5x frequency multiplier function mode corresponding to the two consecutive high-level pulses, and a 2x frequency multiplier function mode corresponding to the one high-level pulse; the timing controller is further configured to: When the first control signal is at a first low level and the second control signal is at a second low level, the target signal is a combination of the first low level and the second low level, controlling the display panel to switch to the normal mode; When the first control signal is at a first high level and the second control signal is at a second high level, the target signal is a combination of the first high level and the second high level, controlling the display panel to switch to the 1.5 times frequency multiplication function mode; When the first control signal is at a first high level and the second control signal is at a second low level, the target signal is a combination of the first high level and the second low level, controlling the display panel to switch to the 2x frequency multiplication function mode.

4. The display device according to claim 2, characterized in that, The processing module includes at least two triggers and at least two switching devices; the output of each trigger is connected to the control terminal of one of the switching devices, and the output of the switching device is connected to the communication interface. The trigger is used to generate the first control signal and the second control signal based on the number of pulses and level changes of the hot-plug detection signal; The switching device is used to turn on or off according to the level state of the first control signal or the second control signal, so as to transmit the first control signal to the first interface and the second control signal to the second interface.

5. The display device according to claim 4, characterized in that, The switching device is a transistor or a logic gate switch; the at least two flip-flops include a first flip-flop and a second flip-flop, and the at least two switching devices include a first switching device and a second switching device; the output terminal of the first flip-flop is connected to the control terminal of the first switching device. The output of the second trigger is connected to the control terminal of the second switching device; the output of the first switching device is connected to the first interface; the output of the second switching device is connected to the second interface. The first switching device is turned on when the first control signal is at a first high level, and turned off when the first control signal is at a first low level; The second switching device is turned on when the second control signal is at a second high level and turned off when the second control signal is at a second low level.

6. The display device according to claim 4, characterized in that, The processing module also includes an AND gate, the input of which is connected to the output of the flip-flop; The AND logic gate is used to logically combine the first control signal and the second control signal to generate a verification signal. The verification signal is used to verify the effectiveness of the signal combination of the first control signal and the second control signal, and to avoid malfunction of the switching device.

7. The display device according to claim 6, characterized in that, The AND logic gate is also used to feed back the state information of the signal combination based on the verification signal, so as to avoid malfunction of the display mode.

8. The display device according to claim 7, characterized in that, The AND logic gate is also used to generate a high-level verification signal when both the first control signal and the second control signal are high, and to determine the state information of the signal combination as the interface signal mapping logic that triggers the timing controller to switch to the 1.5 times frequency multiplication function mode.

9. The display device according to any one of claims 1-8, characterized in that, The processing module further includes a filtering circuit connected to the signal transmission port for filtering the hot-plug detection signal to obtain the target hot-plug detection signal.

10. The display device according to claim 9, characterized in that, The processing module further includes: A detector, connected to the filter circuit, is used to detect the rising and falling edges of the target hot-plug detection signal; A timer, connected to the detector, is used to monitor the pulse parameters corresponding to the rising edge and the falling edge; The timing controller is further configured to determine that the pulse in the target hot-plug detection signal is a valid pulse when the pulse parameter is within a preset range, and trigger the switching of the display mode; and to determine that the pulse in the target hot-plug detection signal is an invalid pulse when the pulse parameter is not within the preset range, and not trigger the switching of the display mode.

11. A display method, characterized in that, The method of using the display device according to any one of claims 1-10 includes: An initial hot-plug detection signal is output through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns; the initial hot-plug detection signal is output through the signal transmission port; the initial hot-plug detection signal corresponds to different display modes through different pulse patterns. The initial hot-plug detection signal is decoded to generate at least two control signals; The at least two control signals are combined to generate a target signal, and the display panel is controlled to switch between at least three display modes based on the target signal.

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