Display panel, display module and electronic equipment
By designing a shift register group for the gate drive circuit differently in the irregularly shaped display panel, the problem of uneven display brightness in the irregularly shaped display panel is solved, the scanning signal response speed of each sub-display area is matched, and the display effect is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-31
- Publication Date
- 2026-03-13
Smart Images
Figure CN121661953A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic devices, and more particularly to a display panel, display module, and electronic device. Background Technology
[0002] With the development of display technology, electronic devices such as mobile phones and tablets are gradually adopting narrow bezels or even bezel-less designs, and the application of irregularly shaped display panels in electronic devices is becoming increasingly widespread. For example, common irregularly shaped display panels include those with rounded corners on the four sides of a rectangular display panel, or those with cutout structures on the display panel. Irregularly shaped display panels often exhibit varying lengths of metal traces in different display areas, while the shift registers in the gate drive circuit used to drive each metal trace typically have the same driving capability. This results in differences in display brightness across different display areas, affecting the display effect. Summary of the Invention
[0003] This application provides a display panel, a display module, and an electronic device to improve the uniformity of display brightness and enhance the display effect of the display panel.
[0004] In a first aspect, this application provides a display panel, which includes a display area and a non-display area. The display area includes a first sub-display area and X second sub-display areas. Each of the first and second sub-display areas has multiple metal traces arranged along a first direction. The lengths of the metal traces in the first and second sub-display areas are different from the lengths of the metal traces in the second sub-display areas. The non-display area is provided with a gate driving circuit, which includes a first shift register group and X second shift register groups, where X is a positive integer and X≥1. Each first shift register group includes multiple first shift registers, and each second shift register group includes multiple second shift registers. Each first and second shift register includes a signal output terminal and a transistor, with the transistor coupled to the signal output terminal. The signal output terminals of the multiple first shift registers are connected one-to-one with each metal trace in the first sub-display area. The X second shift register groups are configured one-to-one with each of the X first sub-display areas, and the signal output terminals of each second shift register in each second shift register group are connected one-to-one with each metal trace in the corresponding second sub-display area. In this application, the channel width-to-length ratio of the transistor in the first shift register is different from that of the transistor in the second shift register. Through this design, the first shift register and the second shift register can achieve different driving capabilities. Therefore, the driving capability of the first shift register can be matched with the metal traces in the first sub-display area, and the driving capability of the second shift register can be matched with the metal traces in the second sub-display area. This can reduce the difference in the response speed of the scan signal in the first sub-display area and the response speed of the scan signal in the second sub-display area, which helps to achieve uniform display brightness of the display panel and improve the display effect of the display panel.
[0005] In some implementations, the first shift register and the second shift register also include capacitors, which are coupled to the transistors in their respective shift registers. The size of the capacitor in the first shift register is different from that in the second shift register, so that the first shift register and the second shift register can achieve different driving capabilities. This can reduce the difference in the response speed of the scan signal in the first sub-display area and the response speed of the scan signal in the second sub-display area, which helps to achieve a uniform brightness display effect on the display panel.
[0006] In some embodiments, the non-display area may include a first sub-non-display area and a second sub-non-display area. The first sub-non-display area surrounds the display area, and at least a portion of the second sub-non-display area is surrounded by an Mth second sub-display area, where M is a positive integer greater than or equal to 1 and M ≤ X. A gate driving circuit is disposed within the first sub-non-display area. The metal trace within the Mth second sub-display area includes a first sub-section, a winding section, and a second sub-section. The first and second sub-sections extend along a second direction, respectively. The winding section connects the first and second sub-sections and extends in a bent manner along one edge of the second sub-non-display area. The length of the metal trace within the Mth second sub-display area is greater than the length of the metal trace within the first sub-display area. Based on this wiring arrangement, the channel width-to-length ratio of the transistor in the second shift register of the Mth second shift register group is greater than that of the transistor in the first shift register. This allows the second shift register in the Mth second shift register group to obtain better driving capability, thereby reducing the difference in the response speed of the scan signal in the Mth second sub-display area and the response speed of the scan signal in the first sub-display area, and enabling the Mth second sub-display area and the first sub-display area to achieve uniform display brightness.
[0007] For example, the shape of the second sub-display area can be circular, racetrack-shaped, rectangular, rounded rectangle, teardrop-shaped, etc. The second sub-display area can be used to set any one or more combinations of cameras, earpieces, light sensors, proximity sensors, iris recognition sensors, and fingerprint recognition sensors of electronic devices.
[0008] In some implementations, the second sub-non-display area is connected to the first sub-non-display area, and a portion of the second sub-non-display area is surrounded by the Mth second sub-display area. The Mth second sub-display area contains m metal traces, where m is a positive integer and m ≥ 1. The m metal traces are arranged sequentially away from the second sub-non-display area, and their lengths gradually increase in the direction away from the second sub-non-display area. The Mth second shift register group includes m second shift registers connected one-to-one with each of the m metal traces. The channel width-to-length ratio of the transistors in the m second shift registers gradually increases to ensure that the response speeds of the scan signals within the Mth second sub-display area AA2-M are approximately the same, thereby achieving uniform brightness display in the Mth second sub-display area.
[0009] In some other implementations, the entire second sub-display area is surrounded by the Mth second sub-display area. The Mth second sub-display area contains m metal traces, where m1 metal traces are arranged sequentially along the side furthest from the second sub-display area, and their lengths gradually increase along this side. Similarly, m2 metal traces are arranged sequentially along the other side furthest from the second sub-display area, and their lengths gradually increase along this side. m, m1, and m2 are all positive integers greater than or equal to 1, and m = m1 + m2. The Mth second shift register group includes m second shift registers, where m1 second shift registers are connected one-to-one with m1 metal traces, and m2 second shift registers are connected one-to-one with m2 metal traces. The channel width-to-length ratio of the transistors in the m1 second shift registers gradually increases, and the channel width-to-length ratio of the transistors in the m2 second shift registers gradually increases. This design allows the response speed of the scanning signal in each metal trace within the Mth second sub-display area to be approximately the same, thereby enabling the Mth second sub-display area to achieve uniform brightness display.
[0010] In some implementations, the channel width-to-length ratio of the transistor in the first shift register is r1, and the maximum value of the channel width-to-length ratio of the transistors in each of the Mth second shift register groups is r2. r1 and r2 satisfy: (r2-r1) / r1≤35%. A gate drive circuit that satisfies this condition can effectively balance the response speed of the scan signals of the first sub-display area and the Mth second sub-display area, enabling uniform brightness display in the first sub-display area and the Mth second sub-display area.
[0011] Furthermore, r1 and r2 satisfy: (r2-r1) / r1≤10%.
[0012] In some implementations, the non-display area includes a first sub-non-display area, which surrounds the display area. The Nth second sub-display area is separated from the first sub-non-display area by an irregular edge. The length of the metal traces in the Nth second sub-display area is less than the length of the metal traces in the first sub-display area, where N is a positive integer and N≤X. The aspect ratio of the channel region of the transistor in the Nth second shift register group is less than that of the first shift register. This reduces the driving capability of the second shift registers in the Nth second shift register group to some extent, thereby reducing the difference in the response speed of the scan signal in the Nth second sub-display area and the first sub-display area, achieving uniform display brightness between the Nth second sub-display area and the first sub-display area.
[0013] In some implementations, the Nth second sub-display area has n metal traces arranged sequentially along the direction close to the edge of the irregular shape, with the length of the n metal traces gradually decreasing along this direction. n is a positive integer and n≥1. The Nth second shift register group includes n second shift registers connected one-to-one with each of the n metal traces. The channel width-to-length ratio of the transistors in the n second shift registers gradually decreases. This design allows the response speed of the scan signal in each metal trace within the Nth second sub-display area to be approximately the same, thereby achieving uniform brightness display in the Nth second sub-display area.
[0014] In some implementations, the channel width-to-length ratio of the transistor in the first shift register is r1, and the minimum channel width-to-length ratio of the transistors in each of the Nth second shift register groups is r3. r1 and r3 satisfy: (r1-r3) / r1≤35%. A gate drive circuit that satisfies this condition can effectively balance the response speed of the scan signals of the first sub-display area and the Nth second sub-display area, enabling uniform brightness display in the first sub-display area and the Nth second sub-display area.
[0015] Furthermore, r1 and r3 satisfy: (r1-r3) / r1≤10%.
[0016] Secondly, this application also provides a display module, which includes a cover plate and a display panel as described in any of the embodiments of the first aspect. The cover plate is fixed to the light-emitting side of the display panel to protect and prevent dust from entering the display panel. This display module can achieve uniform display brightness based on the display panel.
[0017] Thirdly, this application also provides an electronic device, which includes a housing and the display module described in the second aspect above, with the display module fixedly connected to the housing. The electronic device can utilize the display module to achieve a display function, and because the display module can achieve uniform brightness display, the electronic device has high display quality. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0019] Figure 2 This is a schematic diagram of the structure of the display module provided in the embodiments of this application;
[0020] Figure 3 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;
[0021] Figure 4 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;
[0022] Figure 5 This is a schematic diagram of another display panel structure provided in an embodiment of this application;
[0023] Figure 6 for Figure 4 The diagram shows the correspondence between the gate drive circuit and the gate lines of the display panel.
[0024] Figure 7 This is a schematic diagram of the structure of a shift register provided in an embodiment of this application;
[0025] Figure 8 A schematic diagram of a cross-sectional structure of a transistor provided in an embodiment of this application;
[0026] Figure 9a A top view of a transistor provided in an embodiment of this application;
[0027] Figure 9b Another top view of the transistor provided in an embodiment of this application;
[0028] Figure 9c Another top view of the transistor provided in an embodiment of this application;
[0029] Figure 10 A partial enlarged view of a display panel provided in an embodiment of this application;
[0030] Figure 11 A partial enlarged view of another display panel provided in an embodiment of this application;
[0031] Figure 12 A partial enlarged view of another display panel provided in an embodiment of this application.
[0032] Figure label:
[0033] 1000 - Electronic equipment; 1100 - Display module; 1200 - Housing; 1300 - Timing controller; 1400 - System controller; 100 - Display panel;
[0034] 101 - Irregular edge; 110 - Gate drive circuit; 111 - Shift register; 1111 - First shift register; 1112 - Second shift register;
[0035] 110A - First shift register group; 110B - Second shift register group; 110B-M - Mth second shift register group;
[0036] 110B-N - Nth second shift register group; 01 - Substrate; 02 - Semiconductor layer; 03 - Gate; 04 - Source; 05 - Drain;
[0037] 06 - First insulating layer; 07 - Second insulating layer; AA - Display area; AA1 - First sub-display area; AA2 - Second sub-display area;
[0038] AA2-M - The Mth second sub-display area; AA2-N - The Nth second sub-display area; BB - Non-display area; BB1 - The first non-display area;
[0039] spx - sub-pixel; G - metal trace; B - data line; TFT - transistor; 200 - cover plate. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. The terms expressing position and direction described in the embodiments of this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings of the embodiments of this application are only for illustrating relative positional relationships and do not represent actual scale.
[0041] It should be noted that specific details are set forth in the following description to facilitate understanding of this application. However, the embodiments of this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the embodiments of this application. Therefore, this application is not limited to the specific embodiments disclosed below.
[0042] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. (Reference) Figure 1 As shown, the electronic device 1000 provided in this application embodiment can be a mobile phone, tablet PC, personal computer, wearable device (such as a smartwatch, virtual reality (VR) glasses, smart bracelet), vehicle display device, or other devices with display functions, which will not be listed here. Figure 1 The electronic device 1000 of the embodiment shown is illustrated using a mobile phone as an example.
[0043] The electronic device 1000 may include a display module 1100 and a housing 1200. The display module 1100 and the housing 1200 are fixedly connected and enclose a receiving space. The display module 1100 can display images, videos, user-inputted information, information provided to the user, and various menus or interfaces of the electronic device, enabling human-computer interaction. The receiving space formed by the display module 1100 and the housing 1200 accommodates various functional modules and electronic components of the electronic device 1000, including but not limited to circuit boards, batteries, camera modules, processors, charging management modules, communication modules, sensor modules, audio modules, speakers, receivers, microphones, etc., to enable the electronic device to perform multiple functions.
[0044] In some embodiments, the housing 1200 may include a rear housing and a middle frame, with one side of the middle frame fixedly connected to the rear housing and the other side of the middle frame fixedly connected to the display module 1100. Exemplarily, the display module 1100 and the rear housing may be respectively fixed to the two sides of the middle frame by adhesive bonding.
[0045] Figure 2 This is a schematic diagram of the structure of the display module 1100 provided in an embodiment of this application. (See reference...) Figure 2 As shown, the display module 1100 can be a flat screen or a curved screen. The display module 1100 includes a display panel 100 and a cover plate 200. The cover plate 200 is fixed to the light-emitting side of the display panel 100, and the cover plate 200 is mainly used to protect the display panel 100 and prevent dust. The material of the cover plate 200 can be, but is not limited to, glass or plastic. The display panel 100 can be a liquid crystal display (LCD), an organic light emitting diode (OLED), an active-matrix organic light emitting diode (AMOLED), a flexible light-emitting diode (FLED), a mini light emitting diode (Mini-Led), a micro light emitting diode (MicroLed), a micro organic light emitting diode (Micro-OLED), a quantum dot light emitting diode (QLED), etc.
[0046] In other embodiments, the electronic device may also be a foldable phone, in which case it may include two housings. Furthermore, the electronic device may include a hinge mechanism, with each housing rotatably connected to the hinge mechanism to switch between an unfolded and folded state when rotated around the hinge mechanism. A display panel is fixed to one side of the two housings, and to accommodate the folded and unfolded states of the electronic device, the display panel may be a flexible panel. The types of flexible panels can be referred to the examples described in the foregoing embodiments, and will not be repeated here.
[0047] Figure 3 This is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of this application. (Reference) Figure 3 As shown in this embodiment, the display panel 100 includes a display area AA and a non-display area BB. The display area AA includes multiple pixel units arranged in an array, each pixel unit including multiple sub-pixels spx of different colors. For example, a pixel unit may include red sub-pixels, green sub-pixels, and blue sub-pixels, allowing for color mixing to achieve color display. Alternatively, a pixel unit may include red sub-pixels, green sub-pixels, blue sub-pixels, and white sub-pixels, also allowing for color mixing to achieve color display. Of course, in practical applications, the emission color of the sub-pixels spx in a pixel unit can be designed and determined according to the actual application environment, and is not limited here.
[0048] The display area AA also includes multiple metal traces G and multiple data lines D. The metal traces G are arranged along a first direction x, and the data lines D are arranged along a second direction y. The metal traces are used to transmit scan signals for the pixel units, and the data lines are used to transmit data signals for the pixel units. The first direction x can be the length direction of the display device, and the second direction y can be the width direction of the display device. Within the display area AA, a row of sub-pixels is connected to the same metal trace G, and a column of sub-pixels is connected to the same data line D.
[0049] The non-display area BB includes a gate driver on array (GOA) circuit 110, which is connected to multiple metal traces G to send scan signals to the metal traces G. Additionally, the non-display area BB also includes a source driver chip 120, which is connected to a data line D to input data voltage to the data line D. Exemplarily, there can be multiple source driver chips 120, with different source driver chips 120 connected to different data lines D. Figure 2 This illustration uses only two source driver chips 120 as an example. In practical applications, the number of source driver chips 120 can be determined based on the resolution of the display panel 100 and the data output channels of the source driver chips 120.
[0050] Continue to refer to Figure 3 The electronic device 1000 also includes a timing controller 1300 and a system controller 1400. The timing controller 1300 is connected to the gate driving circuit 110 and the source driving chip 120, respectively. When the display panel 100 is working, the system controller 1400 acquires the display grayscale information of the image to be displayed in each display frame (this display grayscale information includes a digital signal carrying the corresponding grayscale value for each sub-pixel in the display panel), processes the display grayscale information, and sends it to the timing controller 1300. After receiving the display grayscale information, the timing controller 1300 sends control signals (such as frame trigger signals and clock signals) to the gate driving circuit 110 and processes the display grayscale information before sending it to the source driving chip 120. The gate driving circuit 110 inputs a scan signal to the metal trace G according to the received control signal. The source driver chip 120 receives the display grayscale information, converts the received display grayscale information into an analog signal, and then inputs the actual data voltage to the data line D to write the data voltage into the sub-pixel spx, thereby enabling the display panel 100 to realize the screen display function.
[0051] Figure 4 This is a schematic diagram of the structure of a display panel 100 provided in an embodiment of this application. (Reference) Figure 4 As shown in the embodiments of this application, the display panel 100 can be an irregularly shaped display panel. Here, an irregularly shaped display panel can be understood as the display panel 100 having a shape other than a conventional rectangle. In the display panel, the display area AA includes a first sub-display area AA1 and a second sub-display area AA2. The first sub-display area AA1 is a conventional display area, and the second sub-display area AA2 is an irregularly shaped display area. The number of second sub-display areas AA2 can be X, where X is a positive integer greater than or equal to 1. The second sub-display area AA2 can be diverse; for example, the second sub-display area AA2 can be an area with irregular edges, or it can be an area with partial openings or slots.
[0052] For example, in Figure 4In the illustrated embodiment, the non-display area BB includes a first sub-non-display area BB1, which surrounds the entire display area AA. The four corners of the display area AA are rounded, or the outer contour of the display area AA can be understood as a rounded rectangle. Along the length of the display panel 100, the top of the display area AA is separated from the first sub-non-display area BB1 by an irregular edge 101, and the bottom of the display area AA is separated from the first sub-non-display area BB1 by another irregular edge 101. Therefore, the top area of the display area AA can be regarded as a second sub-display area AA2 with an irregular edge 101, and the bottom area of the display area AA can also be regarded as a second sub-display area AA2 with an irregular edge 101.
[0053] In some embodiments, the non-display area BB may further include a second sub-non-display area BB2, at least a portion of which is surrounded by a local area of the display area AA. The local area surrounding the second sub-non-display area BB2 may also be regarded as a second sub-display area AA2. The second sub-display area AA2 extends along the width direction of the display panel 100, and the two sides of the second sub-display area AA2 may extend to the left edge and the right edge of the entire display area AA, respectively. The left edge of the display area AA can be understood as the edge separating the left side of the display area AA from the first sub-non-display area BB1, and the right edge of the display area AA can be understood as the edge separating the right side of the display area AA from the first sub-non-display area BB1.
[0054] In a specific implementation, the second non-display area BB2 can be positioned near the top of the display panel 100 or near the bottom of the display area AA, for example... Figure 4 The diagram illustrates a scenario where the second sub-non-display area BB2 is located at the top of the display panel 100. The second sub-non-display area BB2 can be used to set any one or more combinations of a camera, earpiece, light sensor, proximity sensor, iris recognition sensor, and fingerprint recognition sensor of an electronic device.
[0055] In this embodiment, the second sub-non-display area BB2 can be completely surrounded by the second sub-display area AA2. In this case, the second sub-non-display area BB2 is equivalent to a hole formed in the second sub-display area AA2. The shape of the second sub-non-display area BB2 can be... Figure 4 The circle shown can also be a racetrack shape, rectangle, rounded rectangle, teardrop shape, etc., and this application does not limit this. Furthermore, there can be one or more second sub-non-display areas BB2. When there are multiple second sub-non-display areas BB2, they can be arranged along the width direction of the display panel 100 or along the length direction of the display panel 100.
[0056] Figure 5This is a schematic diagram of another display panel 100 provided in an embodiment of this application. (See reference...) Figure 5 As shown in the embodiment of this application, a portion of the second sub-non-display area BB2 is surrounded by the second sub-display area AA2, and the portion of the second sub-non-display area BB2 not surrounded by the second sub-display area AA2 is connected to the first sub-non-display area BB1. This type of display panel 100 can also be called a "notch screen". In this case, the second sub-non-display area BB2 can be an approximately rounded rectangle, or it can be a semi-circle, a semi-racetrack shape, etc., and this application does not limit it in this regard.
[0057] Please continue to refer to this. Figure 4 and Figure 5 In this embodiment, each metal trace G within the first sub-display area AA1 extends along a second direction, and the lengths of each metal trace G within the first sub-display area AA1 are approximately the same. For example, the length of each metal trace G within the first sub-display area AA1 is l.
[0058] In X second sub-display areas AA2, the Mth second sub-display area AA2-M is defined as being configured to surround at least a portion of the second sub-non-display area BB, where M is a positive integer less than or equal to X. Each metal trace G within the Mth second sub-display area AA2-M includes a first sub-part G1, a second sub-part G2, and a winding part G3. The first sub-part G1 and the second sub-part G2 extend along a second direction y, and the winding part G3 connects the first sub-part G1 and the second sub-part G2, extending in a bent shape along one edge of the second sub-non-display area BB2. In specific implementations, the shape of the winding part G3 can be designed according to the shape of the second sub-non-display area BB2; for example, the winding part G3 can be an arc shape or a broken line shape. It is easy to understand that the length of the metal trace G within the Mth second sub-display area AA2-M is greater than the length of the metal trace G within the first sub-display area AA1, that is, the length of the metal trace G within the Mth second sub-display area AA2-M is greater than 1.
[0059] In the X second sub-display areas AA2, the Nth second sub-display area AA2-N is defined as being separated from the first sub-non-display area BB1 by an irregular edge 101, where N is a positive integer less than or equal to X. Since the width of the Nth second sub-display area AA2-N is less than the width of the first sub-display area AA1, the length of the metal trace G within the Nth second sub-display area AA2-N is less than the length of the metal trace G within the first sub-display area AA1; that is, the length of the metal trace G within the Nth second sub-display area AA2-N is less than 1.
[0060] It should be noted that in practical applications, since the second sub-non-display area BB2 is usually located at the top or bottom of the display panel 100, the Mth second sub-display area AA2-M and the Nth second sub-display area AA2-N will be relatively close, and even partially overlap. In this case, the two second sub-display areas AA2 can be distinguished according to the length of the metal trace G. Among them, the metal trace G with a length greater than l can be regarded as the metal trace G in the Mth second sub-display area AA2-M, and the metal trace G with a length less than l can be regarded as the metal trace G in the Nth second sub-display area AA2-M.
[0061] Figure 6 for Figure 4 The diagram shows the correspondence between the gate drive circuit 110 and the metal trace G of the display panel 100. (See reference...) Figure 6 As shown in this embodiment, the gate driving circuit 110 is disposed in the first sub-non-display area BB1. The gate driving circuit 110 includes a plurality of cascaded shift registers 111, and the plurality of shift registers 111 are configured one-to-one with a plurality of metal traces G. Each shift register 111 includes a signal output terminal Output, and the signal output terminal Output of each shift register 111 is connected to a corresponding metal trace G to send a scan signal to the metal trace G.
[0062] Figure 7 A schematic diagram of the structure of a shift register 111 provided in an embodiment of this application is shown below. (See also...) Figure 6 and Figure 7As shown, in this embodiment, the shift register 111 may include four thin film transistors (TFTs) and two capacitors. The four transistors are transistor T1, transistor T2, transistor T3, and transistor T4, and the two capacitors are capacitor C1 and capacitor C2. In this configuration, the first terminal of the first transistor T1 is connected to the clock signal terminal CLK1, the second terminal of the first transistor T1 is connected to the signal output terminal Output, and the gate of the first transistor T1 is connected to the first node P1; the first terminal of the second transistor T2 is connected to the signal output terminal Output, the second terminal of the second transistor T2 is connected to the high-potential signal terminal VGH, and the gate of the second transistor T2 is connected to the second node P2; the first terminal of the third transistor T3 is connected to the first node P1, the second terminal of the third transistor T3 is connected to the high-potential signal terminal VGH, and the gate of the third transistor T3 is connected to the second node P2; the first terminal of the fourth transistor T4 is connected to the signal input terminal Input, the second terminal of the fourth transistor T4 is connected to the first node P1, and the gate of the fourth transistor T4 is connected to the clock signal terminal CLK2; the two ends of capacitor C1 are connected to the first node P2 and the signal output terminal Output, respectively; the two ends of capacitor C2 are connected to the second node P2 and the high-potential signal terminal VGH, respectively; and the second node P2 is connected to the reset signal terminal Reset. It should be noted that the Output terminal of the current stage shift register 111, in addition to outputting a scan signal to the corresponding metal trace, can also serve as the Reset terminal of the previous stage shift register 111 and the Input terminal of the next stage.
[0063] For each of the above transistors, the first terminal can be the source and the second terminal can be the drain; or, the first terminal can be the drain and the second terminal can be the source. Furthermore, each transistor can be an N-type transistor or a P-type transistor; this application does not limit this.
[0064] Figure 8 This is a schematic cross-sectional view of a transistor TFT provided in an embodiment of this application. (Reference) Figure 8As shown, a transistor TFT may include a substrate 01, a semiconductor layer 02, a gate 03, a source 04, a drain 05, a first insulating layer 06, and a second insulating layer 07. The semiconductor layer 02, the first insulating layer 06, the gate 03, and the second insulating layer 07 are sequentially stacked on the substrate 01. The source 04 and the drain 05 are disposed on the side of the second insulating layer 07 facing away from the substrate 01. The semiconductor layer 02 includes a source contact region and a drain contact region. The source 04 is connected to the source contact region through a via, and the drain 05 is connected to the drain contact region through a via. The area covered by the orthogonal projection of the gate 03 onto the semiconductor layer 02 is the channel region 021 of the transistor. When the voltage of the gate 03 of the transistor TFT is less than its turn-on voltage, the channel region 021 is not conductive, and no current flows between the source 04 and the drain 05, so the transistor TFT is in the off state; when the voltage of the gate 03 of the transistor TFT is greater than or equal to its turn-on voltage, the source 04 and the drain 05 can be turned on through the channel region 021, so the transistor TFT is in the on state.
[0065] Please refer to the above. Figure 6 and Figure 7 When shift register 111 is working, in the first stage, the clock signal terminal CLK2 outputs a high-level signal, the fourth transistor T4 turns on, charging the first node P1 to a high level, and the first transistor T1 also turns on. However, since the clock signal terminal CLK1 is low at this time, the signal output terminal Output of shift register 111 does not output a high level. In the second stage, the signal input terminal Input inputs a low-level signal, turning off the fourth transistor T4. At this time, the reset signal has not yet arrived, the second node P2 is low, so the second transistor T2 and the third transistor T3 remain off, the charge of capacitor C1 is maintained, and the first transistor T1 is still on. When the clock signal terminal C... After LK1 inputs a high-level signal, the potential of the first node P1 is raised, causing the signal output terminal Output to output a high-level scan signal to the corresponding metal trace. In the third stage, the reset signal terminal Reset of shift register 111 inputs a high-level signal, raising the potential of the second node P2. The second transistor T2 and the third transistor T3 are thus turned on. The second transistor T2 and the third transistor T3 can be kept in the on state by the charge of capacitor C2. The two ends of capacitor C1 are connected to the high-level signal terminal VGH, causing capacitor C1 to discharge. As the clock signal terminal CLK1 changes from a high level to a low level, the first transistor T1 is turned off, and the signal output terminal Output outputs a low-level signal.
[0066] As can be seen from the above description, both the first transistor T1 and the second transistor T2 are coupled to the signal output terminal Output. The first transistor T1 can be used to output a high-level signal at the signal output terminal Output when it is turned on, while the second transistor T2 can be used to output a low-level signal at the signal output terminal Output when it is turned on. Therefore, the first transistor T1 can also be called a pull-up transistor, and correspondingly, the second transistor T2 can also be called a pull-down transistor. The magnitude of the output voltage / current of the first transistor T1 and the second transistor T2 can affect the magnitude of the output voltage / current at the signal output terminal Output, that is, it affects the driving capability of the shift register 111, or the response speed of the scan signal output by the shift register 111.
[0067] In addition, capacitor C1 is used to store the gate voltage driving the first transistor T1, and capacitor C2 is used to store the gate voltage driving the second transistor T2. Therefore, the storage capacity (capacitance) of capacitors C1 and C2 will also affect the driving capability of shift register 111. It should be noted that... Figure 7 The circuit structure of shift register 111 shown is only an example. In other implementations, shift register 111 can also be designed with multiple clock signal lines and more transistors, but details will not be elaborated here.
[0068] Please refer to this again. Figure 6 Since the lengths of the metal traces G in the first sub-display area AA1 and the metal traces G in each of the second sub-display areas AA2 are different, the loads of the metal traces G in the first sub-display area AA1 and the metal traces G in each of the second sub-display areas AA2 are different. If each shift register 111 adopts the same design, it will cause a difference in the response speed of the scan signal output to the first sub-display area AA1 and the second sub-display area AA2. This will lead to uneven writing data of the sub-pixels in the first sub-display area AA1 and the sub-pixels in the second sub-display area AA2, causing uneven display brightness in the first sub-display area AA1 and the second sub-display area AA2, and affecting the display effect of the display panel 100.
[0069] To address the aforementioned issues, embodiments of this application can differentiate the design of multiple shift registers 111 in the gate drive circuit 110 to suppress or eliminate the problem of uneven data writing between sub-pixels in the first sub-display area AA1 and the second sub-display area AA2, thereby reducing the difference in display brightness between the first sub-display area AA1 and the second sub-display area AA2.
[0070] Figure 10 This is a partial enlarged view of a display panel 100 provided in an embodiment of this application. (See reference) Figure 10As shown in this embodiment, the gate drive circuit 110's multiple shift registers 111 can be divided into a first shift register group 110A and X second shift register groups 110B. The first shift register group 110A includes multiple first shift registers 1111, and the second shift register groups include multiple second shift registers 1112. The output terminal Output of each first shift register 1111 in the first shift register group 110A is connected one-to-one with each metal trace G within the first sub-display area AA1. The X second shift register groups 110B are configured one-to-one with X second sub-display areas AA2. The output terminal Output of each second shift register 1112 in each second shift register group 110B is connected one-to-one with each metal trace G within the corresponding second sub-display area AA2. For example, the output terminal Output of each second shift register 1112 in the Mth second shift register group 110B-M is connected one-to-one with each metal trace G in the Mth second sub-display area AA2-M.
[0071] In some embodiments, differentiating the multiple shift registers of the gate drive circuit may include having a different size for the capacitor in the first shift register 1111 than for the capacitor in the second shift register 1112. The capacitor here may be a capacitor coupled to a pull-up transistor or a pull-down transistor, for example… Figure 7 The illustrated embodiment shows capacitors C1 and C2. The size of the capacitors determines their energy storage capacity, which in turn affects the driving capability of the shift register.
[0072] By designing the capacitor sizes of the first shift register 1111 and the second shift register 1112 to have different values, the first shift register 1111 and the second shift register 1112 can achieve different driving capabilities. This allows the driving capability of the first shift register 1111 to match the metal trace G in the first sub-display area AA1, and the driving capability of the second shift register 1112 to match the metal trace G in the second sub-display area AA2. In this way, the response speed of the scan signal in the first sub-display area AA1 and the response speed of the scan signal in the second sub-display area AA2 can tend to be consistent, enabling the display panel 100 to achieve a uniform brightness display effect.
[0073] In other embodiments, differentiating the multiple shift registers of the gate drive circuit 110 may further include: the channel width-to-length ratio of the transistor in the first shift register 1111 is different from the channel width-to-length ratio of the transistor in the second shift register 1112. Here, the transistor can be a transistor coupled to the signal output terminal (Output) of the shift register, for example... Figure 7The illustrated embodiment includes a pull-up transistor (first transistor T1) and a pull-down transistor (second transistor T2). In practical applications, the channel width-to-length ratio of the pull-up transistor in the shift register can be differentiated, as can the channel width-to-length ratio of the pull-down transistor in the shift register, or both the pull-up and pull-down transistors can be differentiated simultaneously. This application does not impose any limitations on this. A larger channel width-to-length ratio results in a smaller on-resistance in the channel region, leading to a larger output voltage / current and better driving capability of the shift register.
[0074] By designing the channel width-to-length ratio of the transistor in the first shift register 1111 and the channel width-to-length ratio of the transistor in the second shift register 1112 to different values, the first shift register 1111 and the second shift register 1112 can achieve different driving capabilities. This can reduce the difference in the response speed of the scan signal in the first sub-display area AA1 and the response speed of the scan signal in the second sub-display area AA2, which helps the display panel 100 achieve a uniform brightness display effect.
[0075] In addition, in this embodiment, since the difference in response speed of scanning signals in different sub-display areas can be weakened by the differentiated design of the shift register, the winding requirements of the metal traces in the second sub-display area AA2 can be reduced, and there is no need to make special designs for the formation process of the metal traces in the second sub-display area AA2, which helps to simplify the winding design in the second sub-display area AA2.
[0076] Figure 9a A top view of a transistor TFT provided in an embodiment of this application. (Reference) Figure 9a As shown in the figure, in this embodiment, the source 04, drain 05, and gate 03 are all rectangular structures. The width of the channel region is W, and the length of the channel region is L. The width-to-length ratio of the channel region is W / L. Therefore, changing the width W and / or the length L of the channel region can change the width-to-length ratio of the channel region.
[0077] For example, increasing the width-to-length ratio of a trench region can be achieved by increasing the width W of the trench region without changing its length L; or by decreasing the length L of the trench region without changing its width W; or by increasing the width W of the trench region while simultaneously decreasing its length L. Conversely, decreasing the width-to-length ratio of a trench region can be achieved by decreasing the width W of the trench region without changing its length L; or by increasing the length L of the trench region without changing its width W; or by decreasing the width W of the trench region while simultaneously increasing its length L.
[0078] Figure 9b Another top view of the transistor TFT provided in an embodiment of this application. (See reference) Figure 9b As shown, in this embodiment, the source 04 and drain 05 can each be a comb-shaped structure, and the gate 03 is a rectangular structure. The comb teeth of the source 04 and the comb teeth of the drain 05 are arranged alternately. The width of the channel region is shown as W in the figure, and the length of the channel region is shown as L in the figure.
[0079] It can be seen that increasing the number of comb teeth in the source electrode 04 and the drain electrode 05 increases the width of the channel region; conversely, decreasing the number of comb teeth in the source electrode 04 and the drain electrode 05 decreases the width of the channel region. Increasing the spacing between adjacent comb teeth in the source electrode 04 and the drain electrode 05 increases the length of the channel region; conversely, decreasing the spacing between adjacent comb teeth in the source electrode 04 and the drain electrode 05 decreases the length of the channel region. Therefore, this embodiment can change the width-to-length ratio of the channel region by altering its length and width.
[0080] Figure 9c Another top view of the transistor TFT provided in an embodiment of this application. (See reference) Figure 9c As shown, in this embodiment, the source 04, drain 05, and gate 03 are all comb-shaped structures. The comb teeth of the source 04 and the drain 05 are arranged alternately, and the comb teeth of the gate 03 are located between the comb teeth of the source 04 and the drain 05. The width of the channel region W = W1 + W2 + W3 + W4 + W5, and the length of the channel region is shown as L in the figure.
[0081] It can be seen that increasing the number of comb teeth in the source 04, the drain 05, and the gate 03 increases the width of the channel region; conversely, decreasing the number of comb teeth in the source 04, the drain 05, and the gate 03 decreases the width of the channel region. Increasing the spacing between adjacent comb teeth in the source 04 and the drain 05 increases the length of the channel region; conversely, decreasing the spacing between adjacent comb teeth in the source 04 and the drain 05 decreases the length of the channel region. Therefore, this embodiment can change the channel region's aspect ratio by altering its length and width.
[0082] It should be noted that, Figures 9a-9c The transistor TFT structure shown is only one example. Other structures can also be used for transistor TFTs, which will not be elaborated on here.
[0083] refer to Figure 10As shown in the embodiment of this application, the channel width-to-length ratio of the transistor in the second shift register 1112 of the Mth second shift register group 110B-M is greater than that of the transistor in the first shift register 1111. This allows the second shift register 1112 in the Mth second shift register group 110B-M to obtain better driving capability. Since the length of the metal trace G in the Mth second sub-display area AA2-M is greater than the length of the metal trace G in the first sub-display area AA1, enhancing the driving capability of the second shift register 1112 in the Mth second shift register group 110B can reduce the difference in the response speed of the scan signal in the Mth second sub-display area AA2-M and the first sub-display area AA1, thereby achieving uniform display brightness between the Mth second sub-display area AA2-M and the first sub-display area AA1. It should be noted that in the Mth second shift register group 110B-M, the channel width-to-length ratio of the transistor in the second shift register 1112 can be increased by referring to the method provided in the aforementioned embodiment, and the specific details will not be repeated here.
[0084] Continue to refer to Figure 10 As shown, the Mth second sub-display area AA2-M has m metal traces G, where m1 metal traces G are arranged sequentially along the side away from the second sub-non-display area BB2, and m2 metal traces G are arranged sequentially along the other side away from the second sub-non-display area BB2. The Mth second shift register group 110B-M includes m second shift registers 1112, where m1 second shift registers 1112 are connected one-to-one with m1 metal traces G, and m2 second shift registers 1112 are connected one-to-one with m2 metal traces G. Here, m, m1, and m2 are all positive integers greater than or equal to 1, and m = m1 + m2.
[0085] Along the direction away from the second sub-display area BB2, the winding portion of m1 metal traces G gradually increases, thus the length of m1 metal traces G gradually increases. Similarly, along the other side away from the second sub-display area BB2, the winding portion of m2 metal traces G gradually increases, thus the length of m2 metal traces G also gradually increases. To solve the problem of uneven brightness within the Mth second sub-display area AA2-M caused by this difference, in a specific implementation, the channel width-to-length ratio of the transistors in the m1 second shift registers 1112 corresponding to m1 metal traces G can be gradually increased, and the channel width-to-length ratio of the transistors in the m2 second shift registers 1112 corresponding to m2 metal traces G can be gradually increased, thereby making the response speed of the scanning signal in each metal trace G within the Mth second sub-display area AA2-M approximately the same.
[0086] In this embodiment, the channel width-to-length ratio of the transistors in each of the first shift registers 1111 in the first shift register group 110A is r1, and the maximum value of the channel width-to-length ratio of each of the second shift registers 1112 in the Mth second shift register group 110B-M is r2. r1 and r2 satisfy: (r2-r1) / r1≤35%. Further, r1 and r2 satisfy: (r2-r1) / r1≤10%. It has been verified that the gate drive circuit that satisfies the above conditions can effectively balance the response speed of the scan signals of the first sub-display area AA1 and the Mth second sub-display area AA2-M, so that the first sub-display area AA1 and the Mth second sub-display area AA2-M can achieve uniform brightness display. For example, the aspect ratio of the pull-down transistor of each of the first shift registers 1111 in the first shift register group 110A is 150um / 5um, and the aspect ratio of the channel region of the pull-down transistor of one of the second shift registers 1112 in the Mth second shift register group 110B-M is 200um / 5um.
[0087] Figure 11 A partial enlarged view of another display panel 100 provided in an embodiment of this application. (See reference...) Figure 11 As shown in the embodiment of this application, the Mth second sub-display area AA2-M can also be provided with m metal traces G. These m metal traces G can be located on the same side of the second sub-non-display area BB2, that is, the m metal traces G are arranged sequentially in a direction away from the second sub-non-display area BB2. The Mth second shift register group 110B-M includes m second shift registers 1112, and the m second shift registers 1112 are connected one-to-one with the m metal traces G. Wherein, m is a positive integer greater than or equal to 1.
[0088] Along the direction away from the second sub-display area BB2, the winding portion of the m metal traces G gradually increases, thus the length of the m metal traces G gradually increases. When designing the Mth second shift register group 110B-M, the channel width-to-length ratio of the transistors in the m second shift registers 1112 within the Mth second shift register group 110B-M can be gradually increased, thereby ensuring that the response speed of each scan signal within the Mth second sub-display area AA2-M is approximately the same.
[0089] Similarly, in this embodiment, the channel width-to-length ratio of the transistors in each of the first shift registers 1111 in the first shift register group 110A is r1, and the maximum value of the channel width-to-length ratio of each of the second shift registers 1112 in the Mth second shift register groups 110B-M is r2. r1 and r2 satisfy: (r2-r1) / r1≤35%, and further, r1 and r2 satisfy (r2-r1) / r1≤10%. This design can effectively balance the response speed of the scanning signals of the first sub-display area AA1 and the Mth second sub-display areas AA2-M, enabling the first sub-display area AA1 and the Mth second sub-display areas AA2-M to achieve uniform brightness display.
[0090] Table 1 shows a comparison of the data after differential design of the first shift register 1111 in the first shift register group 110A and the second shift register 1112 in the Mth second shift register group 110B-M. Row A represents the data of a certain second shift register 1112 in the Mth second shift register group 110B-M before differential design; row B represents the data of the first shift register 1111 in the first shift register group 110A; and *row A represents the data of a certain second shift register 1112 in the Mth second shift register group 110B-M after differential design. It can be seen that by increasing the channel width of the pull-down transistor of the second shift register 1112 in the Mth second shift register group 110B-M, the pull-up time and pull-down time of the second shift register 1112 are both shortened by a certain amount of time. Moreover, the shortened pull-up time and pull-down time are approximately the same as those of the first shift register 1111 in the first shift register group 110A. This indicates that this design can effectively suppress the difference in the response speed of the scan signal in the Mth second sub-display area AA2-M and the response speed of the scan signal in the first sub-display area AA1, so that the Mth second sub-display area AA2-M and the first sub-display area AA1 can achieve uniform brightness display.
[0091] Table 1
[0092] Pull-up transistor pull-down transistor Pull-up time pull-down time Row A W / L = 47um / 3.5um W / L = 179um / 3.5um 0.19us 0.17us B line W / L = 47um / 3.5um W / L = 179um / 3.5um 0.16us 0.14us * Row A W / L = 47um / 3.5um W / L = 279um / 3.5um 0.16us 0.15us
[0093] Figure 12 A partial enlarged view of another display panel 100 provided in an embodiment of this application. (See reference...) Figure 12As shown in this embodiment, the channel width-to-length ratio of the transistor in the second shift register 1112 of the Nth second shift register group 110B-N is smaller than that of the first shift register 1111. This reduces the driving capability of the second shift register 1112 in the Nth second shift register group 110B-N to some extent. Since the length of the metal trace G in the Nth second sub-display area AA2-N is smaller than the length of the metal trace G in the first sub-display area AA1, reducing the driving capability of the second shift register 1112 in the Nth second shift register group 110B-N can reduce the difference in the response speed of the scan signal in the Nth second sub-display area AA2-N and the first sub-display area AA1, thus achieving uniform display brightness between the Nth second sub-display area AA2-N and the first sub-display area AA1. It should be noted that in the Nth second shift register group 110B-N, the channel width-to-length ratio of the transistor in the second shift register 1112 can be increased or decreased in accordance with the method provided in the aforementioned embodiments, and the specific details will not be repeated here.
[0094] It is easy to understand that reducing the aspect ratio of the transistors in the shift register can also reduce the size of the shift register to a certain extent, thereby reducing the area occupied by the shift register in the first sub-non-display area BB1, which in turn helps to reduce the size of the first sub-non-display area BB1, and provides feasibility for the narrow bezel design of the display panel 100.
[0095] In this embodiment, the Nth second sub-display area AA2-N includes n metal traces G, which are arranged sequentially along the direction close to the irregular edge 101. The Nth second shift register group 110B-N includes n second shift registers 1112, which are connected one-to-one with the n metal traces G. Here, n is a positive integer greater than or equal to 1.
[0096] Along the direction close to the irregular edge 101, the width of the Nth second sub-display area AA2-N gradually decreases, thus the length of the n metal traces G gradually decreases. When designing the Nth second shift register group 110B-N, the channel width-to-length ratio of the transistors in the n second shift registers 1112 within the Nth second shift register group 110B-N can be gradually reduced, thereby ensuring that the response speed of each scan signal within the Nth second sub-display area AA2-N is approximately the same.
[0097] In this embodiment, the channel width-to-length ratio of the transistors in each of the first shift registers 1111 in the first shift register group 110A is r1, and the minimum channel width-to-length ratio of each of the second shift registers 1112 in the Nth second shift register group 110B-N is r3. r1 and r3 satisfy: (r1-r3) / r1≤35%. Further, r1 and r3 satisfy: (r1-r3) / r1≤10%. It has been verified that the gate drive circuit that satisfies the above conditions can effectively balance the response speed of the scanning signals of the first sub-display area AA1 and the Nth second sub-display area AA2-N, so that the first sub-display area AA1 and the Nth second sub-display area AA2-N can achieve uniform brightness display.
[0098] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A display panel, characterized in that, Includes display area and non-display area; The display area includes a first sub-display area and X second sub-display areas. The first sub-display area and the second sub-display areas are respectively provided with metal traces arranged along a first direction. The length of the metal traces in the first sub-display area is different from the length of the metal traces in the second sub-display areas. The non-display area is provided with a gate driving circuit, which includes a first shift register group and X second shift register groups. Each first shift register group includes multiple first shift registers, and each second shift register group includes multiple second shift registers. Each first shift register and each second shift register includes a signal output terminal and a transistor coupled to the signal output terminal. The signal output terminal of each first shift register is connected one-to-one with each metal trace in the first sub-display area. The X second shift register groups are configured one-to-one with each of the X second sub-display areas, and the signal output terminal of each second shift register in each second shift register group is connected one-to-one with each metal trace in the corresponding second sub-display area. The channel width-to-length ratio of the transistors in the first shift registers is different from that of the transistors in the second shift registers. Where X is a positive integer and X≥1.
2. The display panel as described in claim 1, characterized in that, The first shift register and the second shift register also include capacitors, which are coupled to the transistor; The size of the capacitor in the first shift register is different from the size of the capacitor in the second shift register.
3. The display panel as described in claim 1 or 2, characterized in that, The non-display area includes a first sub-non-display area and a second sub-non-display area, the first sub-non-display area is arranged around the display area, and at least a portion of the second sub-non-display area is surrounded by the Mth second sub-display area; The metal trace in the Mth second sub-display area includes a first sub-part, a winding part, and a second sub-part. The first sub-part and the second sub-part extend along a second direction, respectively. The winding part connects the first sub-part and the second sub-part, and the winding part extends in a bent shape along one edge of the second sub-non-display area. The length of the metal trace in the Mth second sub-display area is greater than the length of the metal trace in the first sub-display area, and the channel width-to-length ratio of the transistor in the second shift register in the Mth second shift register group is greater than the channel width-to-length ratio of the transistor in the first shift register. Where M is a positive integer greater than or equal to 1 and M≤X.
4. The display panel as described in claim 3, characterized in that, The second sub-non-display area is connected to the first sub-non-display area, and a portion of the second sub-non-display area is surrounded by the Mth second sub-display area; The Mth second sub-display area is provided with m metal traces, which are arranged sequentially in a direction away from the second sub-non-display area, and the length of the m metal traces gradually increases in the direction away from the second sub-non-display area. The Mth second shift register group includes m second shift registers that are connected one-to-one with the m metal traces, and the channel width-to-length ratio of the transistors in the m second shift registers gradually increases; Where m is a positive integer and m≥1.
5. The display panel as described in claim 3, characterized in that, The entire second sub-display area is surrounded by the Mth second sub-display area; The Mth second sub-display area is provided with m metal traces, wherein m1 metal traces are arranged sequentially along the side away from the second sub-non-display area, and the length of the m1 metal traces gradually increases along the side away from the second sub-non-display area; m2 metal traces are arranged sequentially along the other side away from the second sub-non-display area, and the length of the m2 metal traces gradually increases along the other side away from the second sub-non-display area. The Mth second shift register group includes m second shift registers, wherein m1 second shift registers are connected one-to-one with the m1 metal traces, and m2 second shift registers are connected one-to-one with the m2 metal traces. The channel width-to-length ratio of the transistors in the m1 second shift registers gradually increases, and the channel width-to-length ratio of the transistors in the m2 second shift registers gradually increases. Where m, m1, and m2 are all positive integers greater than or equal to 1, and m = m1 + m2.
6. The display panel as described in claim 4 or 5, characterized in that, The channel width-to-length ratio of the transistor in the first shift register is r1, and the maximum value of the channel width-to-length ratio of the transistor in each of the Mth second shift register groups is r2. r1 and r2 satisfy: (r2-r1) / r1≤35%.
7. The display panel as described in any one of claims 1-6, characterized in that, The non-display area includes a first sub-non-display area, which is arranged around the display area; The Nth second sub-display area is separated from the first sub-non-display area by an irregular edge, and the length of the metal trace in the Nth second sub-display area is less than the length of the metal trace in the first sub-display area. The channel width-to-length ratio of the transistor in the second shift register of the Nth second shift register group is smaller than the channel width-to-length ratio of the first shift register; Where N is a positive integer and N≤X.
8. The display panel as described in claim 7, characterized in that, The Nth second sub-display area is provided with n metal traces, which are arranged sequentially along the direction close to the edge of the irregular shape, and the length of the n metal traces gradually decreases along the direction close to the edge of the irregular shape. The Nth second shift register group includes n second shift registers that are connected one-to-one with the n metal traces, and the channel width-to-length ratio of the transistors in the n second shift registers gradually decreases; Where n is a positive integer and n≥1.
9. The display panel as described in claim 8, characterized in that, The channel width-to-length ratio of the transistor in the first shift register is r1, and the minimum channel width-to-length ratio of the transistor in each of the Nth second shift register groups is r3. r1 and r3 satisfy: (r1-r3) / r1≤35%.
10. A display module, characterized in that, It includes a cover plate and a display panel as described in any one of claims 1-9, wherein the cover plate is disposed on the light-emitting side of the display panel.
11. An electronic device, characterized in that, It includes a housing and the display module as described in claim 10, wherein the display module is fixedly connected to the housing.