Display device and display panel

Abstract

The invention discloses a display device and a display panel. The present disclosure provides a display panel including a display area provided with sub-pixels, and a non-display area outside of the display area that does not display an image, and a display device including the display panel and a driving circuit configured to drive the display panel, the non-display area including a test area in which the sub-pixels are electrically connected to the display area. A plurality of test transistors corresponding to the plurality of transistors included in the sub-pixel are provided for detecting an operating characteristic.

Description

Technical Field

[0001] This disclosure relates to an apparatus, and more specifically, for example but not limited to, to a display device and a display panel, and more specifically, to a display device and a display panel including a test transistor capable of accurately analyzing the flicker characteristics of a driving transistor. Background Technology

[0002] In today's information society, display devices used to present images or visual information to users are becoming increasingly important. The demand for such display devices has led to the rapid development of display technology, and various types of display devices have been developed and are widely used, such as liquid crystal displays (LCDs), plasma displays, quantum dot displays, organic light-emitting displays (e.g., OLEDs), and inorganic light-emitting displays.

[0003] Among these display devices, organic light-emitting display devices, by using organic light-emitting diodes (OLEDs) as self-emissive elements, have high response speeds and advantages in contrast, luminous efficiency, brightness, and viewing angle.

[0004] An organic light-emitting display device may include organic light-emitting diodes disposed in a plurality of sub-pixels disposed in a display panel, and may display an image by means of light emitted from each sub-pixel through a drive current flowing through each organic light-emitting diode controlled by a corresponding drive transistor.

[0005] The descriptions provided in the background section should not be construed as prior art simply because they are mentioned in or associated with that section. The background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0006] The inventors of this disclosure have recognized that, for example, a display device can be configured to operate at different driving frequencies based on input image data. In this embodiment, the operating characteristics of the transistors driving the sub-pixels may change when the driving frequency changes, which may result in flickering during the change of driving frequency.

[0007] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features, and advantages be included in this description and within the scope of this disclosure. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure.

[0008] To address this problem, the inventors of this disclosure have invented a display device and display panel that can accurately analyze the interface characteristics of a layer that can represent the operating characteristics of a transistor relative to changes in the driving frequency.

[0009] One or more aspects of this disclosure may provide a display device and a display panel including at least one test transistor disposed in a non-display area of ​​the display panel and configured to accurately reflect the capacitance-voltage characteristics of the transistor.

[0010] One or more aspects of this disclosure may provide a display device and a display panel including at least one test transistor, the at least one test transistor being configured to reduce the effect of capacitance formed by the overlap of the active layer and the gate, and being able to accurately analyze the flicker characteristics of the transistor by analyzing the interface characteristics of the layer adjacent to the active layer.

[0011] According to one or more exemplary embodiments of the present disclosure, a display device may be provided, comprising a display panel including a display area having sub-pixels including driving transistors and a non-display area outside the display area where no image is displayed, and a driving circuit driving the display panel. In one or more aspects, the non-display area may include a test area in which a plurality of test transistors are connected in parallel for detecting flicker characteristics of at least one driving transistor.

[0012] According to one or more exemplary embodiments of this disclosure, a display panel may be provided, comprising a display area in which subpixels including driving transistors are disposed, and a non-display area outside the display area in which no image is displayed. In one or more aspects, the non-display area may include a test area in which a plurality of test transistors are connected in parallel for detecting flicker characteristics of at least one driving transistor.

[0013] According to one or more aspects of this disclosure, display devices and display panels can provide the effect or advantage of accurately analyzing the interface characteristics of a layer that can represent the operating characteristics of transistors relative to changes in driving frequency.

[0014] According to one or more aspects of this disclosure, display devices and display panels can provide the effects or advantages of achieving process optimization by including at least one test transistor, wherein the at least one test transistor is disposed in a non-display area of ​​the display panel and is configured to accurately reflect the capacitance-voltage characteristics of the transistor.

[0015] According to one or more aspects of this disclosure, display devices and display panels, by including at least one test transistor configured to reduce the effects of capacitance formed by the overlap of the active layer and the gate, can provide the effect or advantage of accurately analyzing the flicker characteristics of the transistor by analyzing the interface characteristics of the layers adjacent to the active layer.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed inventive concept. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this disclosure. The drawings illustrate aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure. In the drawings:

[0018] Figure 1 An example display device according to aspects of this disclosure is shown schematically;

[0019] Figure 2 An example system of a display device according to aspects of this disclosure is shown;

[0020] Figure 3 An example sub-pixel circuit of a display device according to aspects of this disclosure is shown;

[0021] Figure 4 This is an exemplary cross-sectional view of transistors included in sub-pixels in a display device according to aspects of this disclosure;

[0022] Figures 5A to 5C This illustrates an example state of downloading a stream when the transistor is running;

[0023] Figure 6 An example capacitance-voltage (CV) characteristic of a transistor according to frequency is shown;

[0024] Figure 7 This is an example plan view of a display device according to aspects of this disclosure;

[0025] Figure 8 An example configuration structure of a test transistor in a test area of ​​a display device according to aspects of this disclosure is shown;

[0026] Figure 9 This is an example plan view of a test transistor in a test area for detecting the CV characteristics of a driving transistor in a display device, according to aspects of this disclosure.

[0027] Figure 10 It is in accordance with aspects of this disclosure along Figure 9An exemplary cross-sectional view of the first test transistor taken by line AB in the diagram;

[0028] Figure 11 It is in accordance with aspects of this disclosure along Figure 9 An exemplary cross-sectional view of the first test transistor taken from line CD;

[0029] Figure 12 This is an example plan view of a second test transistor arranged in a test area for detecting the CV characteristics of an oxide switching transistor in a display device, according to aspects of this disclosure.

[0030] Figure 13 It is in accordance with aspects of this disclosure along Figure 12 An exemplary cross-sectional view of the second test transistor taken from line AB in the diagram;

[0031] Figure 14 It is in accordance with aspects of this disclosure along Figure 12 An exemplary cross-sectional view of the second test transistor taken from line CD;

[0032] Figure 15 This is an example plan view of a third test transistor in a test area for detecting the CV characteristics of a polysilicon switching transistor in a display device, according to aspects of this disclosure.

[0033] Figure 16 It is in accordance with aspects of this disclosure along Figure 15 An exemplary cross-sectional view of the third test transistor taken from line AB in the diagram;

[0034] Figure 17 It is in accordance with aspects of this disclosure along Figure 15 An example cross-sectional view of the third test transistor taken from line CD;

[0035] Figure 18A and Figure 18B This is a graph showing example CV characteristics when a low voltage is applied to the lower gate of a test transistor in a display device according to aspects of this disclosure; and

[0036] Figure 19A and Figure 19B This is a graph showing an example CV characteristic of a display device according to aspects of this disclosure when the lower gate of a test transistor is grounded.

[0037] Throughout the accompanying drawings and detailed description, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustration, and convenience, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0038] Reference will now be made in detail to embodiments of this disclosure, examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or configurations associated with this document will be omitted where such descriptions would be deemed to unnecessarily obscure the essential points of the inventive concept. The described progression of processing steps and / or operations is exemplary; however, the order of steps and / or operations is not limited to that set forth herein, except that they must occur in a specific order, and can be varied as is known in the art. The same reference numerals always denote the same elements. The names of the elements used in the following description may be chosen solely for convenience of writing the specification and may therefore differ from the names used in actual products.

[0039] The advantages and features of this disclosure, as well as its implementation methods, will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope.

[0040] Any implementation described as an "example" in this article is not necessarily to be interpreted as preferred or superior to other implementations.

[0041] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. When denoteing elements in the drawings using reference numerals, the same elements will be indicated by the same reference numerals, even though these elements are shown in different drawings. In the following description of the present disclosure, detailed descriptions of known functions and configurations incorporated herein may be omitted where they might make the subject matter of the disclosure considerably unclear. Unless used with the term “only,” terms such as “comprising,” “having,” “containing,” “including,” “constituting,” and “composed of” as used herein are generally intended to allow for the addition of other components. Unless the context clearly indicates otherwise, elements described in the singular are intended to include multiple elements, and vice versa.

[0042] Furthermore, the terms “first,” “second,” “A,” “B,” “(a),” “(b),” etc., may be used to describe elements included in the embodiments of this disclosure. These terms are used only to distinguish one element from another; therefore, the related elements should not be construed as being limited by these terms, as they are not used to define a particular order or priority. Furthermore, the expressions “first element,” “second element,” and / or “third element” should be understood to refer to one of the first, second, and third elements, or any or all combinations of the first, second, and third elements. For example, A, B, and / or C may refer only to A, only to B, or only to C; any or some combinations of A, B, and C; or all of A, B, and C.

[0043] Unless otherwise stated, when describing a component or layer as “connected,” “joined,” or “adhered” to another component or layer, a component or layer may be directly connected, joined, or adhered to another component or layer, or indirectly connected, joined, or adhered to another component or layer, with one or more intermediate components or layers “set” or “intercalated” between the components or layers. Furthermore, the other component may be included in one or more of two or more components that are connected, combined, joined, or in contact with each other.

[0044] Unless otherwise stated, descriptions of elements or layers "contacting" or "overlapping" with other elements or layers indicate that elements or layers can not only directly contact or overlap with other elements or layers, but also indirectly contact or overlap through one or more intermediate elements or layers "set" or "inserted" between elements or layers.

[0045] When describing positional relationships, such as when using terms like "above," "over," "below," "over," "beside," "adjacent," etc., to describe the positional relationship between two components, one or more other components may be located between the two components, unless more restrictive terms such as "exactly," "directly," or "tightly" are used. For example, when an element or layer is set "on" another element or layer, a third element or layer may be inserted between it. Furthermore, the terms "left," "right," "top," "bottom," "down," "up," "upper," "lower," etc., refer to any frame of reference. When describing temporal relationships, when the temporal sequence is described as, for example, "after," "following," "next," or "before," discontinuous situations may be included, unless more restrictive terms such as "only," "immediately," or "directly" are used. When interpreting an element, even if no explicit description of such an error or tolerance range is provided, the element should be interpreted as including an error or tolerance range. Furthermore, the term "may" fully encompasses all the meanings of the term "able to." The term "at least one" should be understood to include any or all combinations of one or more associated listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" covers all combinations of the three listed elements, combinations of any two of the three elements, and each individual element, the first element, the second element, and the third element. The expressions "first element," "second element," and / or "third element" should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C may refer only to A, only to B, or only to C; any or some combinations of A, B, and C; various exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Additionally, for ease of illustration, the scale of the elements shown in the drawings sometimes differs from the actual scale. Therefore, the illustrated elements are not limited to the specific scale shown in the drawings.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments pertain. It should also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and should not be interpreted in an idealized or overly formal sense unless explicitly defined herein. For example, the terms “part” or “unit” can be applied to, for example, a single circuit or structure, an integrated circuit, a computational block of a circuit arrangement, or any structure configured to perform the functions described herein that would be understood by one of ordinary skill in the art.

[0047] Instead, these implementations may be provided to make this disclosure thorough and complete enough to help those skilled in the art to fully understand the scope of this disclosure.

[0048] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure may be coupled or combined in part, and may interoperate and be technology-driven in various ways. Embodiments of this disclosure may be performed independently of each other, or may be performed together in an interdependent relationship.

[0049] In the following, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Additionally, for ease of explanation, the scale of the elements shown in the drawings may sometimes differ from the actual scale. Therefore, the illustrated elements are not limited to the specific scale shown in the drawings.

[0050] Figure 1 An example display device according to various aspects of this disclosure is illustrated schematically.

[0051] refer to Figure 1 In one or more exemplary embodiments, the display device 100 may include a display panel 110 and at least one driving circuit configured to drive the display panel 110.

[0052] The display panel 110 may include a display area DA where images can be displayed and a non-display area NDA where images are not displayed. The non-display area NDA may also be referred to as an inactive area, a border, or a border area.

[0053] Display panel 110 may include a plurality of subpixels SP for image display. For example, the plurality of subpixels SP may be disposed in display area DA. In one or more aspects, at least one subpixel SP may be disposed in non-display area NDA. At least one subpixel SP disposed in non-display area NDA may be referred to as a dummy subpixel.

[0054] The display panel 110 may include multiple signal lines for driving multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL and multiple gating lines GL. Depending on the structure of the sub-pixel SP, in addition to the multiple data lines DL and multiple gating lines GL, the signal lines may also include other signal lines. For example, such signal lines may include driving voltage lines, reference voltage lines, etc.

[0055] Multiple data lines (DL) and multiple gating lines (GL) can intersect each other. Each of the multiple data lines (DL) can extend in a first direction. Each of the multiple gating lines (GL) can extend in a second direction different from the first direction. For example, the first direction can be a column or vertical direction, and the second direction can be a row or horizontal direction. Here, the column and row directions do not necessarily represent absolute directions, but rather relative directions. For example, the column direction can be vertical, and the row direction can be horizontal. In another example, the column direction can be horizontal, and the row direction can be vertical.

[0056] At least one driving circuit may include a data driving circuit 130 configured to drive multiple data lines DL and a gating driving circuit 120 configured to drive multiple gating lines GL. At least one driving circuit may also include a timing controller 140 configured to control the data driving circuit 130 and the gating driving circuit 120.

[0057] The data driving circuit 130 can be a circuit for driving multiple data lines DL, and can output data signals (which can be referred to as data voltages) corresponding to the image signals to the multiple data lines DL. The gating driving circuit 120 can be a circuit for driving multiple gating lines GL, and can generate gating signals and provide the generated gating signals to the multiple gating lines GL. The gating signals can include at least one scan signal and at least one light emission signal.

[0058] The timing controller 140 can start scanning pixels according to a corresponding timing set in each frame, and can control the data drive at a timing set for scanning one or more corresponding pixels. The timing controller 140 can convert image data received from external devices or systems (e.g., host system 200) into a data signal form that can be read by the data drive circuit 130, and then provide the converted image data to the data drive circuit 130.

[0059] The timing controller 140 can receive display drive control signals and image data from the external host system 200. For example, the display drive control signals may include vertical synchronization signals, horizontal synchronization signals, input data enable signals, clock signals, etc.

[0060] The timing controller 140 can generate a data drive control signal DCS and a gating drive control signal GCS based on the display drive control signal received from the host system 200. The timing controller 140 can control the drive operation and timing of the data drive circuit 130 by providing the data drive control signal DCS to the data drive circuit 130. The timing controller 140 can control the drive operation and timing of the gating drive circuit 120 by providing the gating drive control signal GCS to the gating drive circuit 120.

[0061] The data driver circuit 130 may include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit (SDIC) may include a shift register, latch circuit, digital-to-analog converter, output buffer, etc. In one or more aspects, each source driver integrated circuit (SDIC) may also include an analog-to-digital converter (ADC).

[0062] In one or more aspects, each source driver integrated circuit (SDIC) may be connected to the display panel 110 via tape-on-brush (TAB) technology, or to conductive pads, such as the pads of the display panel 110, via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. However, the aspects of this disclosure are not limited thereto.

[0063] The gating drive circuit 120 can provide a gating signal with an on-level voltage, a gating signal with an off-level voltage, or a gating signal with both on-level and off-level voltages, according to the control of the timing controller 140. The gating drive circuit 120 can sequentially drive multiple gating lines GL by sequentially providing gating signals with on-level voltages to multiple gating lines GL.

[0064] The gating drive circuit 120 may include one or more gating drive integrated circuits (GDICs).

[0065] In one or more aspects, the gate drive circuit 120 may be connected to the display panel 110 via tape-on-board (TAB) technology, or to conductive pads, such as the pads of the display panel 110, via chip-on-glass (COG) technology or chip-on-panel (COP) technology, or to the display panel 110 via chip-on-film (COF) technology. However, the aspects of this disclosure are not limited thereto. In one or more aspects, the gate drive circuit 120 included in the display device 100 may be disposed in the non-display area NDA of the display panel 110 via gate-in-panel (GIP) technology. The gate drive circuit 120 may be disposed on the substrate or connected to the substrate. In the example of the display device 100 where the gate drive circuit 120 is implemented via gate-in-panel (GIP) technology, the gate drive circuit 120 may be disposed in the non-display area NDA of the substrate. In one or more aspects, when the gate drive circuit 120 is implemented via chip-on-glass (COG) technology or chip-on-film (COF) technology, the gate drive circuit 120 may be connected to the substrate SUB.

[0066] In one or more aspects, at least one of the data driving circuit 130 and the gating driving circuit 120 may be disposed in the display area DA. For example, at least one of the data driving circuit 130 and the gating driving circuit 120 may be configured not to overlap with the sub-pixel SP, or may be configured to overlap with one or more or all of the sub-pixels SP.

[0067] The data driving circuit 130 may be located and / or electrically connected to, but not limited to, only one side or edge (e.g., the upper or lower part) of the display panel 110. In one or more aspects, depending on the driving scheme, panel design, etc., the data driving circuit 130 may be provided and / or electrically connected to at least two of the two sides or edges (e.g., the upper and lower parts) or four sides or edges (e.g., the upper, lower, left, and right sides) of the display panel 110.

[0068] The gating drive circuit 120 may be located and / or electrically connected to, but not limited to, only one side or edge (e.g., left or right) of the display panel 110. In one or more aspects, depending on the driving scheme, panel design, etc., the gating drive circuit 120 may be provided and / or electrically connected to at least two of the two sides or edges (e.g., left and right portions) or four sides or edges (e.g., left, right, top, and bottom) of the display panel 110, but is not limited thereto.

[0069] The timing controller 140 can be implemented in a separate component from the data drive circuitry 130, or integrated with the data drive circuitry 130, such that the timing controller 140 and the data drive circuitry 130 can be implemented in a single integrated circuit. The timing controller 140 can be a controller used in typical display technologies, or a control device / apparatus capable of performing additional control functions beyond the typical functions of a timing controller. In one or more embodiments, the timing controller 140 can be one or more other control circuits different from the timing controller, or a circuit or component within a control device / apparatus. The timing controller 140 can be implemented using various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0070] The timing controller 140 can be mounted on a printed circuit board or flexible printed circuit, and can be electrically connected to the data drive circuit 130 and the gating drive circuit 120 via the printed circuit board or flexible printed circuit, etc. The timing controller 140 can send signals to and receive signals from the data drive circuit 130 via one or more predetermined interfaces. For example, such interfaces may include a low-voltage differential signaling (LVDS) interface, an embedded point-to-point clock interface (EPI), a serial peripheral interface (SPI), etc.

[0071] In one or more aspects, the display device 100 may be a liquid crystal display device, a self-emissive display device in which light is emitted from the display panel 110 itself, etc. In an example where the display device 100 is a self-emissive display device, each of the plurality of sub-pixels SP included in the display device 100 may include a light-emitting element such as an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, a miniature light-emitting diode, etc. In one or more aspects, the display device 100 may be an organic light-emitting display device in which an organic light-emitting diode (OLED) is used to implement the light-emitting element. In one or more aspects, the display device 100 may be an inorganic light-emitting display device in which a light-emitting diode based on an inorganic material is used to implement the light-emitting element. In one or more aspects, the display device 100 may be a quantum dot display device in which the light-emitting element is implemented using quantum dots, which are self-emissive semiconductor crystals.

[0072] Figure 2 An example system of a display device 100 according to aspects of this disclosure is shown.

[0073] refer to Figure 2 In one or more exemplary embodiments, the data driving circuit 130 and the gating driving circuit 120 included in the display device 100 may be implemented by chip-on-film (COF) technology and gate-in-panel (GIP) technology, respectively, wherein various technologies such as tape-on-board (TAB) technology, chip-on-glass (COG) technology, COF technology, etc.

[0074] In the example where the gating drive circuit 120 is implemented using GIP technology, multiple gating drive integrated circuits (GDICs) included in the gating drive circuit 120 can be directly disposed in the non-display area NDA of the display panel 110. In this example, the gating drive integrated circuits (GDICs) can receive various types of signals (e.g., clock signals, gating high signals, gating low signals, etc.) required to generate scan signals through gating drive related signal lines disposed in the non-display area NDA.

[0075] In one or more aspects, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 may be mounted on one or more corresponding source films (SFs), and one side of each source film (SF) may be electrically connected to the display panel 110. In one or more aspects, lines for electrically connecting one or more source driver integrated circuits (SDICs) and the display panel 110 may be respectively disposed on the upper part of one or more source films (SFs).

[0076] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between one or more source driver integrated circuits (SDICs) and other units or devices, and a control printed circuit board (CPCB) for mounting control components and several types of electrical units or devices.

[0077] In one or more aspects, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be connected to at least one source printed circuit board SPCB. For example, one side of the source film SF on which the source driver integrated circuit SDIC is mounted may be electrically connected to at least one source printed circuit board SPCB, and the other side may be electrically connected to the display panel 110.

[0078] The timing controller 140 and power management circuit 150 can be mounted on a control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gating drive circuit 120. The power management circuit 150 can supply various levels of voltage or current to the display panel 110, the gating drive circuit 120, the data drive circuit 130, etc., or control the various levels of voltage or current to be supplied.

[0079] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be electrically connected to each other via at least one connector, such as a flexible printed circuit (FPC), a flexible flat cable (FFC), etc. In one or more aspects, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0080] The display device 100 may also include a setup board 170 electrically connected to a control printed circuit board (CPCB). The setup board 170 may be referred to as a power board. A main power management circuit 160 configured to manage all the power of the display device 100 may be mounted on the setup board 170. The main power management circuit 160 may interoperate with the power management circuit 150.

[0081] In an example where the display device 100 includes the power management circuit 150, setting board 170, control printed circuit board CPCB, etc., as described above, one or more driving voltages generated by the setting board 170 can be transmitted to the power management circuit 150 of the control printed circuit board CPCB. The power management circuit 150 can transmit one or more driving voltages required for display driving or feature value sensing to the source printed circuit board SPCB via a flexible printed circuit FPC or a flexible flat cable FFC. The one or more driving voltages transmitted to the source printed circuit board SPCB can be provided to the display panel 110 via one or more source driver integrated circuits SDIC, and are used to enable one or more specific sub-pixels SP to emit light or sense one or more sub-pixels SP.

[0082] In one or more aspects, each sub-pixel SP included in the display panel 110 of the display device 100 may include circuit elements such as light-emitting elements (e.g., organic light-emitting diodes OLEDs), driving transistors for driving the light-emitting elements, etc.

[0083] The type and number of circuit elements included in each sub-pixel SP can vary depending on the type of panel (e.g., LCD panel, OLED panel, etc.), the functions provided, the design scheme / features, etc.

[0084] Figure 3 An example subpixel circuit of a display device 100 according to aspects of this disclosure is shown.

[0085] Reference Figure 3 In one or more exemplary embodiments, each of the plurality of sub-pixels SP or one or more sub-pixels included in the touch display device 100 may include a first to a seventh switching transistor (T1 to T7), a driving transistor DRT, a storage capacitor Cst, and a light-emitting element ED.

[0086] In one or more aspects, the light-emitting element (ED) can be a self-emitting element, such as an organic light-emitting diode (OLED), an inorganic light-emitting diode, a quantum dot light-emitting diode, a micro light-emitting diode, a mini light-emitting diode, etc.

[0087] In one or more aspects, the second to fourth switching transistors (T2 to T4), the sixth switching transistor T6, and the seventh switching transistor T7 may be P-type transistors. In one or more aspects, the first switching transistor T1 and the fifth switching transistor T5 may be N-type transistors.

[0088] The driving transistor DRT can be either a P-type or an N-type transistor. It should be noted that... Figure 3 A P-type drive transistor DRT is shown as an example, but aspects of this disclosure are not limited thereto.

[0089] P-type transistors are relatively more reliable than N-type transistors. In the example using a P-type drive transistor DRT, since a high drive voltage VDD can be applied to its source at a fixed or constant rate when driving the light-emitting element ED, the application of a P-type drive transistor DRT can provide the advantage of preventing or reducing fluctuations in the current flowing to the light-emitting element ED due to the capacitor Cst. Therefore, the drive transistor DRT can stably provide the current for driving the light-emitting element ED.

[0090] When the P-type driving transistor DRT is connected to the anode of the light-emitting element ED in the configuration, and the P-type driving transistor DRT operates in the saturation region, the P-type driving transistor DRT can provide a constant current to the light-emitting element ED regardless of changes in the threshold voltage, resulting in relatively high reliability.

[0091] In the sub-pixel circuit based on the above configuration, the N-type transistor can be an oxide transistor formed using an oxide semiconductor, for example, a transistor having a channel formed using an oxide semiconductor such as indium, gallium, zinc oxide, indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), etc. The P-type transistor can be a silicon transistor formed using a semiconductor such as silicon, for example, a transistor having a polycrystalline silicon channel formed by a low-temperature process called LTPS or low-temperature polycrystalline silicon.

[0092] Oxide transistors can have relatively lower leakage current than silicon transistors.

[0093] Considering these characteristics, at least a portion of the driving transistor DRT or switching transistor included in the sub-pixel SP can be an oxide transistor.

[0094] For example, the driving transistor DRT, the first switching transistor T1 connected to the gate of the driving transistor DRT, and the fifth switching transistor T5 can be oxide transistors.

[0095] For example, the remaining switching transistors (T2, T3, T4, T6, and T7) can be low-temperature polysilicon transistors.

[0096] According to these examples, each or one or more of the sub-pixels SP included in the display device 100 may include a driving transistor DRT and a first set of switching transistors (T1 and T5) as oxide transistors and a second set of switching transistors (T2, T3, T4, T6 and T7) as low-temperature polysilicon transistors.

[0097] When a drive transistor DRT implemented as an oxide transistor is used, the display device 100 can provide the effect or advantage of preventing or reducing leakage current flowing to the gate of the drive transistor DRT, thereby reducing or eliminating unwanted image artifacts (such as flicker).

[0098] In one or more aspects, to improve current characteristics in the on-state and provide high reliability, the driving transistor DRT may have a dual-gate structure including an upper gate and a lower gate.

[0099] It should be noted that, depending on the input voltage, the source and drain of a switching transistor can be referred to as the drain and source, respectively.

[0100] A first scan signal SCAN1 can be applied to the gate of a first switching transistor T1. The second electrode (e.g., drain) of the first switching transistor T1 can be connected to the gate N2 of a driving transistor DRT. The first electrode (e.g., source) of the first switching transistor T1 can be connected to the second electrode (e.g., drain) N3 of the driving transistor DRT.

[0101] The first switching transistor T1 can be turned on by the first scan signal SCAN1, and a current path is formed between the gate N2 and the second electrode N3 of the driving transistor DRT through the storage capacitor Cst, wherein a high driving voltage VDD is fixedly applied to one of the electrodes.

[0102] The first switching transistor T1 can be an N-type MOS transistor formed as an oxide transistor. Since N-type MOS transistors use electrons instead of holes as charge carriers, they can provide a faster carrier mobility than P-type MOS transistors, thus providing a faster switching speed.

[0103] In one or more aspects, the first switching transistor T1 may have a multi-gate structure to reduce or eliminate leakage current due to charge injection when driving the display device 100 to display an image. For example, a dual-gate structure in which two gates are connected as one may be used.

[0104] The second scan signal SCAN2 can be applied to the gate of the second switching transistor T2. A data voltage Vdata can be provided to the first electrode (e.g., source) of the second switching transistor T2. The second electrode (e.g., drain) of the second switching transistor T2 can be connected to the first electrode (e.g., source) N1 of the driving transistor DRT. The second switching transistor T2 can be turned on by the second scan signal SCAN2, allowing the data voltage Vdata to be delivered to the first electrode (e.g., source) N1 of the driving transistor DRT.

[0105] When the first switching transistor T1 is turned on, since the data voltage Vdata is supplied to the first electrode (e.g., the source) N1 of the driving transistor DRT through the second switching transistor T2, the difference (Vdata-Vth) between the data voltage Vdata and the threshold voltage Vth of the driving transistor DRT can be sampled and supplied to the gate N2 of the driving transistor DRT. According to this operation, the first switching transistor T1 can be referred to as the sampling transistor, and the first scan signal SCAN1 can be referred to as the sampling scan signal.

[0106] A light-emitting signal EM can be applied to the gate of the third switching transistor T3. A high drive voltage VDD can be applied to the first electrode (e.g., the source) of the third switching transistor T3. The second electrode (e.g., the drain) of the third switching transistor T3 can be connected to the first electrode (e.g., the source) N1 of the driving transistor DRT. The third switching transistor T3 can be turned on by the light-emitting signal EM, allowing the high drive voltage VDD to be delivered to the first electrode (e.g., the source) N1 of the driving transistor DRT.

[0107] The light-emitting signal EM can be applied to the gate of the fourth switching transistor T4. The first electrode (e.g., the source) of the fourth switching transistor T4 can be connected to the second electrode (e.g., the drain) N3 of the driving transistor DRT.

[0108] The second electrode (e.g., drain) of the fourth switching transistor T4 can be connected to the anode N4 of the light-emitting element ED. The fourth switching transistor T4 can be turned on by the light-emitting signal EM and allow the drive current Id to flow to the anode N4 of the light-emitting element ED.

[0109] The third scan signal SCAN3 can be applied to the gate of the fifth switching transistor T5. For example, the third scan signal SCAN3 can be a signal with a different phase than the first scan signal SCAN1, which is applied to another sub-pixel SP at a different location than the sub-pixel SP to which the third scan signal SCAN3 is applied. For example, when the first scan signal SCAN1 is applied to the nth gate line, the third scan signal SCAN3 can be provided using the first scan signal SCAN1 applied to the (n-1)th gate line. For example, the third scan signal SCAN3 can be provided by using the first scan signal SCAN1 delivered through a different gate line GL, depending on the phase in which the display panel 110 is driven.

[0110] An initialization voltage Vini can be applied to the second electrode (e.g., the drain) of the fifth switching transistor T5. The first electrode (e.g., the source) of the fifth switching transistor T5 can be connected to the gate N2 of the driving transistor DRT and the storage capacitor Cst. The fifth switching transistor T5 can be turned on by the third scan signal SCAN3, allowing the initialization voltage Vini to be applied to the gate N2 of the driving transistor DRT. According to this operation, the fifth switching transistor T5 can be referred to as the initialization transistor, and the third scan signal SCAN3 can be referred to as the initialization scan signal.

[0111] In one or more aspects, the fifth switching transistor T5 may have a multi-gate structure to reduce or eliminate leakage current due to charge injection when driving the display device 100 to display an image. For example, a dual-gate structure in which two gates are connected as one may be used.

[0112] The fourth scan signal SCAN4 can be applied to the gate of the sixth switching transistor T6. The reset voltage VAR can be applied to the first electrode (e.g., the source) of the sixth switching transistor T6. The second electrode (e.g., the drain) of the sixth switching transistor T6 can be connected to the anode N4 of the light-emitting element ED. The sixth switching transistor T6 can be turned on by the fourth scan signal SCAN4, allowing the reset voltage VAR to be delivered to the anode N4 of the light-emitting element ED.

[0113] The fifth scan signal SCAN5 can be applied to the gate of the seventh switching transistor T7. The bias voltage VOBS can be applied to the first electrode (e.g., the source) of the seventh switching transistor T7. The second electrode (e.g., the drain) of the seventh switching transistor T7 can be connected to the first electrode (e.g., the source) N1 of the driving transistor DRT.

[0114] For example, the fifth scan signal SCAN5 can be a signal with a different phase than the third scan signal SCAN3, which is applied to another sub-pixel SP at a different location than the sub-pixel SP to which the fifth scan signal SCAN5 is applied. For example, when the third scan signal SCAN3 is applied to the nth gate line, the fifth scan signal SCAN5 can be provided using the third scan signal SCAN3 applied to the (n-1)th gate line. For example, the fifth scan signal SCAN5 can be provided by using the third scan signal SCAN3 delivered through different gate lines GL, depending on the phase in which the display panel 110 is driven.

[0115] Since the fifth scan signal SCAN5 is used to apply the bias voltage VOBS to the drive transistor DRT, it can be expected that the fifth scan signal SCAN5 is different from the second scan signal SCAN2 used to apply the data voltage Vdata.

[0116] The gate N2 of the driving transistor DRT can be connected to the second electrode (e.g., the drain) of the first switching transistor T1. The first electrode (e.g., the source) N1 of the driving transistor DRT can be connected to the second electrode (e.g., the drain) of the second switching transistor T2. The second electrode (e.g., the drain N3) of the driving transistor DRT can be connected to the first electrode (e.g., the source) of the first switching transistor T1.

[0117] The driving transistor DRT can be turned on by the voltage difference between the gate N2 and the first electrode (e.g., the source) N1, and can provide a driving current Id to the light-emitting element ED.

[0118] The first electrode (e.g., source) and the second electrode (e.g., drain) of the first switching transistor T1 can be connected to the second electrode (e.g., drain) N3 and the gate N2 of the driving transistor DRT, respectively. When the first switching transistor T1 is turned on, the threshold voltage of the driving transistor DRT can be sampled and compensated by applying the data voltage Vdata to the first electrode (e.g., source) N1 of the driving transistor DRT.

[0119] A high drive voltage VDD can be applied to one side or electrode of the storage capacitor Cst, and its other side or electrode can be connected to the gate N2 of the drive transistor DRT. The storage capacitor Cst can store the voltage at the gate N2 of the drive transistor DRT.

[0120] The anode N4 of the light-emitting element ED can be connected to the second electrode (e.g., drain) of the fourth switching transistor T4 and the second electrode (e.g., drain) of the sixth switching transistor T6. A base voltage VSS with a low level voltage can be applied to the cathode of the light-emitting element ED.

[0121] The light-emitting element ED can emit light at a predetermined luminous intensity by the drive current Id provided by the drive transistor DRT.

[0122] In one or more aspects, an initialization voltage Vini may be provided to stabilize the change in capacitance formed by the gate N2 of the driving transistor DRT, and a reset voltage VAR may be provided to reset the anode N4 of the light-emitting element ED.

[0123] When the fourth switching transistor T4, which is controlled by the light-emitting signal EM, is turned off, and a reset voltage VAR is supplied to the anode N4 of the light-emitting element ED, the anode N4 of the light-emitting element ED can be reset.

[0124] The sixth switching transistor T6, which supplies the reset voltage VAR, can be connected to the anode N4 of the light-emitting element ED.

[0125] In order to enable the driving operation of the driving transistor DRT and the reset operation of the anode N4 of the light-emitting element ED to be performed separately, the third scan signal SCAN3 for driving and / or initializing the driving transistor DRT and the fourth scan signal SCAN4 for controlling the supply of the reset voltage VAR to the anode N4 of the light-emitting element ED can be supplied as different signals from each other.

[0126] In one or more aspects, when the switching transistors T5 and T6, which are used to provide the initialization voltage Vini and the reset voltage VAR, are turned on, the fourth switching transistor T4, which interconnects the drain N3 of the driving transistor DRT and the anode N4 of the light-emitting element ED, can be turned off, thereby preventing or reducing the flow of the drive current Id from the driving transistor DRT to the anode N4 of the light-emitting element ED, and preventing or reducing the influence of any voltage other than the reset voltage VAR on the anode N4.

[0127] As in Figure 3 The sub-pixel circuit shown in the diagram, which includes eight transistors (DRT, T1, T2, T3, T4, T5, T6, and T7) and a storage capacitor Cst, can be referred to as an 8T1C structure.

[0128] Here, in one or more exemplary embodiments, the 8T1C structure can be applied to various sub-pixel circuit structures, such as... Figure 1 The structure and number of transistors and capacitors included in each of the sub-pixels SP in the display device 100 shown can be changed according to design requirements. In one or more aspects, each of the plurality of sub-pixels SP may have the same structure, or one or more of the plurality of sub-pixels SP may have a structure different from the remaining sub-pixels SP.

[0129] Figure 4 This is an exemplary cross-sectional view of the transistors included in the sub-pixel SP in the display device 100 according to aspects of this disclosure.

[0130] refer to Figure 4 In one or more exemplary embodiments, the display device 100 may include a first buffer layer BUF1 disposed on a substrate SUB.

[0131] The light-shielding layer LS, used to block light, can be placed on the buffer layer BUF1.

[0132] The second buffer layer BUF2 can be configured to cover the light-shielding layer LS.

[0133] The first active layer ACT1, which is included in the first transistor TG1, can be disposed on the second buffer layer BUF2.

[0134] The first transistor TG1 can be one of the switching transistors implemented as a low-temperature polysilicon transistor among the switching transistors included in the sub-pixel SP. For example, in Figure 3 In the sub-pixel, the second to fourth switching transistors (T2, T3 and T4) and the sixth and seventh switching transistors (T6 and T7) can be implemented as low-temperature polycrystalline silicon transistors.

[0135] The first gate insulating layer GI1 can be disposed on the first active layer ACT1.

[0136] At least one first gate GE1, including a gate material, may be disposed on a first gate insulating layer GI1. The gate material may be an opaque conductive material with low resistance, such as aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), etc. In one or more aspects, the gate material may be formed as a multilayer structure, wherein at least one transparent conductive material (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), etc.) and at least one opaque conductive material are stacked sequentially or alternately.

[0137] At least one first gate GE1 can be used as the gate of the first transistor TG1 and as the lower gate of the second transistor TG2 disposed at a position spaced apart from the first transistor TG1.

[0138] For example, the second transistor TG2 can be a switching transistor implemented as an oxide transistor in a sub-pixel. Figure 3 In the sub-pixel, the first switching transistor T1 and the fifth switching transistor T5 can be implemented as oxide transistors.

[0139] In one or more aspects, the second transistor TG2 may have a dual-gate structure including an upper gate and a lower gate. In this embodiment, the first gate GE1 may be used as the lower gate of the second transistor TG2.

[0140] The first interlayer insulating layer ILD1 can be configured such that it covers the first gate GE1.

[0141] The third buffer layer BUF3 can be placed on the first interlayer insulation layer ILD1.

[0142] The second gate GE2, which includes gate material, can be disposed on the third buffer layer BUF3.

[0143] The second gate GE2 can be the lower gate of the third transistor TG3, which is located at a position spaced apart from the second transistor TG2.

[0144] For example, the third transistor TG3 can be a driving transistor DRT that is implemented as an oxide transistor in a sub-pixel.

[0145] In one or more aspects, the third transistor TG3 may have a dual-gate structure including an upper gate and a lower gate. In this embodiment, the second gate GE2 may be the lower gate of the third transistor TG3.

[0146] For example, the second transistor TG2 and the third transistor TG3, which are implemented as oxide transistors, may respectively include a lower gate GE1 and a lower gate GE2 disposed in different layers in the vertical direction.

[0147] The fourth buffer layer BUF4 can be configured such that it covers the second gate GE2 on the third buffer layer BUF3.

[0148] The second active layer ACT2, included in the second transistor TG2, and the third active layer ACT3, included in the third transistor TG3, can be disposed on the fourth buffer layer BUF4.

[0149] The second active layer ACT2 can be the active layer of the second transistor TG2 implemented as an oxide transistor, and the third active layer ACT3 can be the active layer of the third transistor TG3 implemented as a driving transistor of an oxide transistor.

[0150] The second gate insulating layer GI2 can be configured to cover the second active layer ACT2 and the third active layer ACT3.

[0151] Two or more third gates GE3, including gate material, may be disposed on the second gate insulating layer GI2.

[0152] One of the two or more third gates GE3 may be the upper gate of the second transistor TG2, and the other third gate GE3 may be the upper gate of the third transistor TG3.

[0153] The second interlayer insulating layer ILD2 can be configured such that it covers two or more third gates GE3.

[0154] Multiple source-drain patterns can be set on the second interlayer insulating layer ILD2.

[0155] The source-drain pattern may include any one of molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), chromium (Cr), aluminum (Al), and alloys formed by combinations thereof.

[0156] One source-drain pattern can be the first source SE1 and the first drain DE1 of the first transistor TG1. Another source-drain pattern can be the second source SE2 and the second drain DE2 of the second transistor TG2. Yet another source-drain pattern can be the third source SE3 and the third drain DE3 of the third transistor TG3.

[0157] In one or more aspects, portions of at least two of the source-drain patterns can be electrically connected, respectively, to the second active layer ACT2 of the second transistor TG2 and the third active layer ACT3 of the third transistor TG3 through contact holes of the second interlayer insulating layer ILD2 and the second gate insulating layer GI2.

[0158] In one or more aspects, at least one portion of the remaining source-drain pattern in the source-drain pattern may be electrically connected to the first active layer ACT1 of the first transistor TG1 through contact holes of the second interlayer insulating layer ILD2, the second gate insulating layer GI2, the fourth buffer layer BUF4, the third buffer layer BUF3, the first interlayer insulating layer ILD1, and the first gate insulating layer GI1.

[0159] The planarization layer PLN can be configured such that it covers the source-drain pattern. The planarization layer PLN may include an organic insulating material such as acrylic resin. In one or more aspects, the driving transistor DRT and one or more switching transistors (e.g., T1 and T5) included in the sub-pixel SP may have a dual-gate structure including an upper gate and a lower gate to improve current characteristics in the on-state and provide high reliability.

[0160] In this respect, when the display panel 110 is driven to display an image, charge injection may occur along the active layer ACT during the process of the switching transistor connected to the driving transistor DRT being turned on and off, which may lead to leakage current flow. Therefore, unwanted image artifacts, such as flickering, may occur.

[0161] Figures 5A to 5C An example state of downloading the flow carrier is shown when the transistor is operating, and Figure 6 An example CV characteristic of a transistor is shown according to frequency.

[0162] refer to Figures 5A to 5C In one or more aspects, the active layer ACT of the transistor may include conductive semiconductor patterns (ACT_S and ACT_D) on a substrate (not shown), wherein the source SE and drain DE of the channel layer ACT_C are electrically connected to the conductive semiconductor patterns, respectively. In one or more aspects, the upper gate TGE may overlap with the channel layer ACT_C, wherein a gate insulating layer GI is present.

[0163] The channel layer ACT_C can be a region doped with various impurities and having a semiconductor surface. The channel layer ACT_C can include different semiconductor materials or different semiconductor material layers, such as the bulk semiconductor material of the substrate (e.g., silicon), silicon germanium (SiGe), or silicon carbide (SiC).

[0164] In the case of an N-type transistor, the conductive semiconductor patterns (ACT_S and ACT_D) electrically connected to the source (SE) and drain (DE) can be regions doped with N-type impurities. The conductive semiconductor patterns (ACT_S and ACT_D) can be formed by ion implantation or diffusion. For example, a rapid thermal annealing process can be used to activate the implanted impurities during the process of forming the conductive semiconductor patterns (ACT_S and ACT_D).

[0165] The gate insulating layer GI may include a dielectric material such as silicon oxide. In one or more aspects, the gate insulating layer GI may include one or more other suitable dielectric materials for circuit performance and fabrication integration. For example, the gate insulating layer GI may include a high-k dielectric material layer such as a metal oxide, metal nitride, or metal oxynitride. The high-k dielectric material layer may include metal oxides such as ZrO2, Al2O3, and HfO2 formed by any suitable method, such as metal-organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE).

[0166] The upper gate TGE may include metals such as aluminum, copper, tungsten, metal silicides, metal alloys, doped polysilicon, another suitable conductive material, or a combination thereof. The upper gate TGE may include multiple conductive films designed as capping layers, work function metal layers, barrier layers, and filler metal layers (e.g., aluminum or tungsten).

[0167] For example, when an N-type transistor is turned on by a high-level gate voltage TGE applied to the upper gate, carriers in the channel layer ACT_C can be trapped to form a channel. Figure 5A ).

[0168] In this state, when the gate voltage applied to the upper gate TGE changes from a high level to a low level, a momentary backlash may sometimes occur due to the change in gate voltage. That is, the conductive semiconductor patterns (ACT_S, ACT_D) can be temporarily connected to the channel layer ACT_C, and this can cause a momentary change in potential. Figure 5B ).

[0169] Following this recoil phenomenon, the carriers trapped in the channel layer ACT_C can be released, and charge injection can occur, injecting carriers into the conductive semiconductor patterns (ACT_S and ACT_D). Due to this charge injection, leakage current may flow in the driving transistor. Figure 5C ).

[0170] As mentioned above, when leakage current flows to the upper gate TGE of the transistor, changes in brightness may occur, which in turn may lead to some image artifacts such as flickering.

[0171] This phenomenon can occur not only in transistors with dual gates, but also in transistors with a single gate as the upper gate.

[0172] In particular, when the display device 100 operates at a low driving frequency, the leakage current caused by charge injection, which causes a time delay of several seconds, may be one of the reasons for the worsening of the flickering phenomenon.

[0173] In this case, such as Figure 6 As shown, the CV (capacitance-voltage) characteristic curve of the driving transistor can be shifted according to the driving frequency.

[0174] For example, the flicker characteristics of a transistor can be analyzed based on the voltage deviation Vfb of a transistor with the same capacitance at different first and second driving frequencies.

[0175] In order to accurately measure the deviation Vfb in the voltage according to the driving frequency, it is desirable to minimize or reduce the overlapping capacitance formed by the transistor gate.

[0176] Therefore, in order to accurately analyze the characteristics of one or more transistors, the display device 100 may include at least one test transistor in the non-display area NDA of the display panel 110. The detected operating characteristics of at least one test transistor in the non-display area NDA represent the operating characteristics of the corresponding transistor in the display area DA. Therefore, the detected operating characteristics of at least one test transistor are representative of the operating characteristics of the corresponding transistor in the display area DA.

[0177] Figure 7 This is an example plan view of a display device 100 according to aspects of this disclosure.

[0178] refer to Figure 7 In one or more exemplary embodiments, the display panel 110 included in the display device 100 may include a display area DA and a non-display area NDA, wherein at least one sub-pixel SP in the display area DA is configured to emit light, and no image is displayed in the non-display area NDA.

[0179] In one or more aspects, the display device 100 may include a test region 200 in a non-display region NDA located outside the display region DA to analyze the characteristics of one or more transistors located in the display region DA.

[0180] Test area 200 may include multiple test areas (200a, 200b and / or 200c) to detect the CV characteristics of transistors with different structures.

[0181] For example, a first test transistor for detecting the CV characteristics of a drive transistor DRT implemented as an oxide transistor can be disposed in a first test region 200a. For example, the CV characteristics of the first test transistor can be detected and represent the CV characteristics of the drive transistor DRT.

[0182] A second test transistor for detecting the CV characteristics of an oxide switching transistor can be disposed in a second test region 200b. For example, the CV characteristics of the second test transistor can be detected and represent the CV characteristics of the oxide switching transistor. Finally, a third test transistor for detecting the CV characteristics of a silicon switching transistor can be disposed in a third test region 200c. For example, the CV characteristics of the third test transistor can be detected and represent the CV characteristics of the silicon switching transistor.

[0183] To detect the CV characteristics of transistors located in the display area DA, multiple test transistors can be connected in parallel, allowing a capacitance greater than a certain threshold (level) to accumulate.

[0184] For example, the test transistors formed in each test region 200 can be connected in parallel, so that capacitance ranging from 5pF to 20pF can accumulate in the parallel-connected test transistors.

[0185] The first test area 200a can be located in the portion of the non-display area NDA that is furthest from the data driving circuit 130 relative to the display area DA. When the first test area 200a is located in the portion of the non-display area NDA that is furthest from the data driving circuit 130, the first test area 200a can have a straight structure.

[0186] The second test area 200b and the third test area 200c can be located at the corner of the non-display area NDA adjacent to the data driving circuit 130. When the second test area 200b and the third test area 200c are located at the corner of the non-display area NDA, the second test area 200b and the third test area 200c can have a non-straight structure, which has at least one curved portion.

[0187] Figure 8 An example configuration structure of a test transistor in a test area of ​​a display device 100 according to aspects of this disclosure is shown.

[0188] refer to Figure 8 In one or more exemplary embodiments, the display device 100 may include a test region 200 in which a plurality of test transistors TTR are connected in parallel in a portion of the non-display region NDA adjacent to the outer edge of the display region DA.

[0189] For example, a first test region 200a, configured with one or more test transistors TTR for detecting the CV characteristics of the drive transistor DRT, can be positioned relative to the display region DA at a location opposite to the data drive circuit 130.

[0190] Multiple test transistors (TTRs) used to detect the CV characteristics of the driving transistor (DRT) can be arranged in parallel in the first test region 200a. For example, 300 or fewer test transistors (TTRs) can be connected in parallel in the test region 200.

[0191] Since the test transistors TTRs configured in the first test region 200a are positioned for detecting the CV characteristics of the driving transistor DRT, the test transistors TTRs are connected in parallel, allowing the capacitance formed in the test transistors TTRs to accumulate. For example, multiple test transistors TTRs can be connected, allowing the accumulation of capacitance ranging from 5pF to 20pF, thus enabling the detection of the CV characteristics of the driving transistor DRT.

[0192] It should be noted that the parallel connection of multiple test transistors (TTRs) can mean that the multiple test transistors (TTRs) are configured such that the drains (DE) of the test transistors are connected to each other and the sources (SE) of the test transistors are connected to each other.

[0193] According to this structure, when multiple test transistors (TTRs) are connected in parallel, the capacitances formed in the test transistors (TTRs) can be added together, and the resulting capacitance can be detected as the capacitance of the test transistors (TTRs).

[0194] To detect the flicker characteristics of the drive transistor DRT using the test transistor TTR, it may be necessary to accurately detect the interface characteristics of the buffer layer through each lower gate and accurately detect the interface characteristics of the gate insulating layer through each upper gate.

[0195] Therefore, it is desirable to minimize or reduce the overlap capacitance formed between the gate and one or more other metal electrodes (e.g., corresponding source and drain electrodes).

[0196] In one or more aspects, the display device 100 may reduce such overlap capacitance based on a structure in which the lower gate of the test transistor TTR is configured not to overlap perpendicularly with the corresponding source and drain (SE and DE). That is, the lower gate of the test transistor TTR does not overlap with the source and drain.

[0197] Furthermore, based on the structure in which the lower gate of each test transistor TTR is electrically connected to the corresponding base metal layer, the display device 100 can reduce the resistive component of the test transistor TTR and accurately detect the CV characteristics of the transistor.

[0198] It should be understood here that the structure of the test transistor TTR can vary depending on the type of transistor used to detect CV characteristics.

[0199] Figure 9 This is an example plan view of a first test transistor arranged in a test area for detecting the CV characteristics of a driving transistor in a display device 100, according to aspects of this disclosure. Figure 10 It is in accordance with aspects of this disclosure along Figure 9 An example cross-sectional view of the first test transistor taken from line AB. Figure 11 It is in accordance with aspects of this disclosure along Figure 9 An example cross-sectional view of the first test transistor taken from line CD.

[0200] refer to Figure 9 and Figure 10 In one or more exemplary embodiments, a first test area 200a (e.g., ) is provided in the display device 100. Figure 7 and Figure 8 The first test transistor TTR1 in the first test area 200a) can be disposed in a portion of the non-display area NDA using the same process as at least one driving transistor DRT disposed in the display area DA. Therefore, the first test transistor TTR1 and at least one driving transistor DRT are disposed on the same layer.

[0201] In one or more aspects, the first test transistor TTR1 may include a base metal layer BSM disposed on a substrate SUB.

[0202] The base metal layer BSM can be disposed in the same layer as the first gate GE1 using the first gate metal material used to form the first gate GE1.

[0203] The base metal layer BSM can be electrically connected to the second gate GE2, which serves as the lower gate of the drive transistor DRT, to reduce the resistance of the second gate GE2. The base metal layer BSM can apply a voltage less than or equal to a threshold to the second gate GE2 to detect the CV characteristics of the first test transistor TTR1.

[0204] The first interlayer insulating layer ILD1 can be configured to cover the base metal layer BSM, and the third buffer layer BUF3 can be disposed on the first interlayer insulating layer ILD1. The second gate GE2 can be disposed on the third buffer layer BUF3. The second gate GE2 can be used as the lower gate or bottom gate of the first test transistor TTR1.

[0205] In these structures, the second gate GE2 is configured such that it does not overlap with the third source SE3 and the third drain DE3 located above the second gate GE2 in the vertical direction.

[0206] For example, the second gate GE2 can be located between the overlapping regions OA that overlap with the third source SE3 and the third drain DE3 in the vertical direction.

[0207] The fourth buffer layer BUF4 can be disposed on the second gate GE2, and the third active layer ACT3, which is implemented as an oxide semiconductor, can be disposed on the fourth buffer layer BUF4.

[0208] The second gate insulating layer GI2 and the third gate GE3 are sequentially disposed on the third active layer ACT3. The third gate GE3 can be referred to as the upper gate or top gate of the first test transistor TTR.

[0209] The third gate GE3 may include the same material as the second gate GE2.

[0210] The second interlayer insulating layer ILD2 can be disposed on the third gate GE3.

[0211] Contact holes can be formed by etching corresponding portions of the second interlayer insulating layer ILD2 and the second gate insulating layer GI2 to expose a portion of the third active layer ACT3, and the third source SE3 and the third drain DE3 in contact with the third active layer ACT3 can be formed through the contact holes.

[0212] In this structure, even when the third source SE3 and the third drain DE3 are arranged on the overlapping region OA in the vertical direction, since the second gate GE2 is not arranged in the overlapping region OA, the overlapping capacitance formed between at least one of the third source SE3 and the third drain DE3 and the second gate GE2 can be minimized or reduced.

[0213] In one or more aspects, one or more driving transistors DRT disposed in the display area DA can be configured such that the second gate GE2 overlaps or does not overlap with at least one of the third source SE3 and the third drain DE3 in the vertical direction.

[0214] refer to Figure 9 and Figure 11 In one or more exemplary embodiments, the second gate GE2 of the first test transistor TTR1 disposed in a portion of the non-display area NDA of the display device 100 can be electrically connected to the base metal layer BSM below the second gate GE2 via the first connection line CL1.

[0215] This structure reduces the resistance component of the second gate GE2, enabling more accurate detection of the CV characteristics of the first test transistor TTR1.

[0216] The first connection line CL1 can be disposed in the same layer as the third source SE3 and the third drain DE3, and electrically interconnect the second gate GE2 and the base metal layer BSM.

[0217] In one or more aspects, the first connection line CL1 may be positioned so as not to overlap with the third source SE3 and the third drain DE3 in the vertical direction. This minimizes or reduces the overlap capacitance formed between the first connection line CL1 and at least one of the third source SE3 and the third drain DE3.

[0218] In one or more aspects, the driving transistors DRT disposed in the display area DA may not include the first connection line CL1, and therefore, the second gate GE2 of each driving transistor DRT may not be electrically connected to the base metal layer BSM located below the second gate GE2.

[0219] The CV characteristics of the first test transistor TTR1 can be accurately detected by grounding the base metal layer BSM or applying a low voltage less than or equal to the reference value.

[0220] Figure 12 This is an example plan view of a second test transistor disposed in a test area for detecting the CV characteristics of an oxide switching transistor in a display device 100, according to aspects of this disclosure. Figure 13 It is in accordance with aspects of this disclosure along Figure 12 An example cross-sectional view of the second test transistor taken from line AB in the diagram. Figure 14 It is in accordance with aspects of this disclosure along Figure 12 An example cross-sectional view of the second test transistor taken from line CD.

[0221] Reference Figures 12 to 14 In one or more exemplary embodiments, a second test area 200b is provided in the display device 100 (e.g., Figure 7 The second test transistor TTR2 in the second test area 200b) can be disposed in a portion of the non-display area NDA using the same process as at least one oxide switching transistor disposed in the switching transistors disposed in the display area DA. Therefore, the second test transistor TTR2 is disposed on the same layer as at least one oxide switching transistor.

[0222] In one or more aspects, the second test transistor TTR2 may include a base metal layer BSM disposed on a substrate SUB.

[0223] The base metal layer BSM can be located below the first gate GE1 and is a metal layer separate from the first gate GE1.

[0224] The base metal layer BSM can be electrically connected to the first gate GE1, which serves as the lower gate of the oxide switching transistor, to reduce the resistance of the first gate GE1. The base metal layer BSM can apply a voltage less than or equal to a threshold to the first gate GE1 to detect the CV characteristics of the second test transistor TTR2 corresponding to the oxide switching transistor.

[0225] The second buffer layer BUF2 can be configured to cover the base metal layer BSM, and the first gate insulating layer GI1 can be disposed on the second buffer layer BUF2.

[0226] The first gate GE1 can be disposed on the first gate insulating layer GI1, and the first interlayer insulating layer ILD1 can be configured such that the first interlayer insulating layer ILD1 covers the first gate GE1.

[0227] The first gate GE1 can be used as the lower gate or bottom gate of the second test transistor TTR2.

[0228] The third buffer layer BUF3 and the fourth buffer layer BUF4 can be sequentially disposed on the first interlayer insulation layer ILD1.

[0229] In these structures, the first gate GE1 is configured such that the first gate GE1 does not overlap with the second source SE2 and the second drain DE2 located above the first gate GE1 in the vertical direction.

[0230] For example, the first gate GE1 can be located between the overlapping regions OA that overlap with the second source SE2 and the second drain DE2 in the vertical direction.

[0231] The second active layer ACT2, the second gate insulating layer GI2, and the third gate GE3 can be sequentially disposed on the fourth buffer layer BUF4. The third gate GE3 can be referred to as the upper gate or top gate of the second test transistor TTR2.

[0232] The third gate GE3 may include the same material as the first gate GE1.

[0233] The second interlayer insulating layer ILD2 can be disposed on the third gate GE3.

[0234] Contact holes can be formed by etching corresponding portions of the second interlayer insulating layer ILD2 and the second gate insulating layer GI2 to expose a portion of the second active layer ACT2, and the second source SE2 and the second drain DE2 in contact with the second active layer ACT2 can be formed through the contact holes.

[0235] In this structure, even when the second source SE2 and the second drain DE2 are arranged on the overlapping region OA in the vertical direction, since the first gate GE1 is not arranged in the overlapping region OA, the overlapping capacitance formed between at least one of the second source SE2 and the second drain DE2 and the first gate GE1 can be minimized or reduced.

[0236] In one or more aspects, one or more oxide switching transistors disposed in the display area DA can be configured such that the second gate GE1 overlaps or does not overlap with at least one of the second source SE2 and the second drain DE2 in the vertical direction.

[0237] In one or more aspects, the first gate GE1 of the second test transistor TTR2 disposed in a portion of the non-display area NDA of the display device 100 can be electrically connected to the base metal layer BSM below the first gate GE1 via the second connection line CL2.

[0238] This structure reduces the resistivity of the first gate GE1, enabling more accurate detection of the CV characteristics of the second test transistor TTR2.

[0239] The second connection line CL2 can be disposed in the same layer as the second source SE2 and the second drain DE2, and the first gate GE1 and the base metal layer BSM are electrically interconnected through a contact hole.

[0240] In one or more aspects, the second connection line CL2 may be positioned so as not to overlap with the second source SE2 and the second drain DE2 in the vertical direction. This minimizes or reduces the overlap capacitance formed between the second connection line CL2 and at least one of the second source SE2 and the second drain DE2.

[0241] In one or more aspects, the oxide switching transistor disposed in the display area DA may not include the second connection line CL2, and therefore, the first gate GE1 of each oxide switching transistor may not be electrically connected to the base metal layer BSM located below the first gate GE1.

[0242] The CV characteristics of the second test transistor TTR2 can be accurately detected by grounding the base metal layer BSM or by applying a low voltage less than or equal to the reference value.

[0243] Figure 15 This is an example plan view of a third test transistor in a test area for detecting the CV characteristics of a polysilicon switching transistor in a display device 100, according to aspects of this disclosure. Figure 16 It is in accordance with aspects of this disclosure along Figure 15An example cross-sectional view of the third test transistor taken from line AB. Figure 17 It is in accordance with aspects of this disclosure along Figure 15 An example cross-sectional view of the third test transistor taken from line CD.

[0244] refer to Figures 15 to 17 In one or more exemplary embodiments, a third test area 200c (e.g.,) is provided in the display device 100. Figure 7 The third test transistor TTR3 in the third test area 200c) can be disposed in a portion of the non-display area NDA using the same process as at least one polysilicon switching transistor disposed in the display area DA. Therefore, the third test transistor TTR3 is disposed on the same layer as at least one polysilicon switching transistor.

[0245] In one or more aspects, the third test transistor TTR3 may include a base metal layer BSM disposed on a substrate SUB.

[0246] The base metal layer (BSM) can be a metal layer placed below the light-shielding layer (LS).

[0247] The base metal layer (BSM) can be electrically connected to the light-shielding layer (LS) of the polysilicon switching transistor to reduce the resistance of the LS. The base metal layer (BSM) can apply a voltage less than or equal to a threshold value to the LS to detect the CV characteristics of the third test transistor (TTR3) corresponding to the polysilicon switching transistor.

[0248] The first buffer layer BUF1 can be configured to cover the base metal layer BSM, and the light-shielding layer LS can be configured on the first buffer layer BUF1. The light-shielding layer LS is located between the base metal layer BSM and the first active layer ACT1.

[0249] The second buffer layer BUF2 can be configured to cover the light-shielding layer LS, and the first active layer ACT1 can be configured on the second buffer layer BUF2.

[0250] The first gate insulating layer GI1 can be disposed on the first active layer ACT1.

[0251] The first gate GE1 can be disposed on the first gate insulating layer GI1, and the first interlayer insulating layer ILD1 can be configured such that the first interlayer insulating layer ILD1 covers the first gate GE1.

[0252] The third buffer layer BUF3 and the fourth buffer layer BUF4 can be sequentially disposed on the first interlayer insulation layer ILD1.

[0253] In these structures, the light-shielding layer LS is configured such that it does not overlap with the first source SE1 and the first drain DE1 located above the light-shielding layer LS in the vertical direction.

[0254] Therefore, the light-shielding layer LS can be located between the overlapping regions OA that overlap with the first source SE1 and the first drain DE1 in the vertical direction.

[0255] The second gate insulating layer GI2 and the second interlayer insulating layer ILD2 can be disposed on the fourth buffer layer BUF4.

[0256] Contact holes can be formed to expose a portion of the first active layer ACT1 by etching corresponding portions of the second interlayer insulating layer ILD2, the second gate insulating layer GI2, the fourth buffer layer BUF4, the third buffer layer BUF3, the first interlayer insulating layer ILD1, and the first gate insulating layer GI1.

[0257] A first source SE1 and a first drain DE1 can be formed that are in contact with the first active layer ACT1 through a contact hole.

[0258] In these structures, even when the first source SE1 and the first drain DE1 are arranged in the vertical direction on the overlapping region OA, since the light-shielding layer LS is not arranged in the overlapping region OA, the overlapping capacitance formed between at least one of the first source SE1 and the first drain DE1 and the light-shielding layer LS can be minimized or reduced.

[0259] In one or more aspects, one or more polysilicon switching transistors disposed in the display area DA may be configured such that the light-shielding layer LS may or may not overlap with at least one of the first source SE1 and the first drain DE1 in the vertical direction.

[0260] In one or more aspects, the light-shielding layer LS of the third test transistor TTR3 disposed in a portion of the non-display area NDA of the display device 100 can be electrically connected to the base metal layer BSM below the light-shielding layer LS via a third connection line CL3.

[0261] This structure reduces the resistivity of the light-shielding layer LS, enabling more accurate detection of the CV characteristics of the third test transistor TTR3.

[0262] The third connection line CL3 can be located in the same layer as the first source SE1 and the first drain DE1, and the light-shielding layer LS and the base metal layer BSM can be electrically interconnected through a contact hole.

[0263] In one or more aspects, the third connection line CL3 may be positioned so as not to overlap with the first source SE1 and the first drain DE1 in the vertical direction. This minimizes the overlap capacitance formed between the third connection line CL3 and at least one of the first source SE1 and the first drain DE1.

[0264] In one or more aspects, the polysilicon switching transistor disposed in the display area DA may not include the third connection line CL3, so that the light-shielding layer LS of each polysilicon switching transistor may not be electrically connected to the base metal layer BSM located below the light-shielding layer LS.

[0265] The CV characteristics of the third test transistor TTR3 can be accurately detected by grounding the base metal layer BSM or by applying a low voltage less than or equal to the reference value.

[0266] Figure 18A and Figure 18B This is a graph showing an example CV characteristic when a low voltage is applied to the lower gate of a test transistor in a display device 100 according to aspects of this disclosure. Figure 19A and Figure 19B This is a graph showing an example CV characteristic of a display device according to aspects of this disclosure when the lower gate of a test transistor is grounded.

[0267] refer to Figure 18A and Figure 18B In one or more aspects, the display device 100 can detect the CV characteristics of the test transistor TTR by applying test voltages (CVH and CVL) to the gates (TGE and BGE) of the test transistor TTR disposed in the test region 200.

[0268] For example, such as Figure 18A As shown in the circuit diagram, the test pads of the source (SE) and drain (DE) of the test transistor TTR can be electrically connected. In this configuration, a first test voltage CVL can be applied to the lower gate (BGE), and a second test voltage CVH can be applied to the upper gate (TGE). Figure 18A ).

[0269] For example, the first test voltage CVL applied to the lower gate BGE can have a lower voltage than the second test voltage CVH applied to the upper gate TGE.

[0270] In this state, the CV characteristics of the test transistor TTR can be detected while the second test voltage CVH applied to the upper gate TGE is changed.

[0271] In this example, it can be seen that the capacitance in the CV characteristic of the test transistor TTR changes drastically relative to the second test voltage CVH of 0V. Therefore, for both low-frequency and high-frequency driving frequencies, the flicker characteristics of the test transistor TTR can be analyzed by detecting the deviation of the second test voltage CVH at the point where the capacitance changes drastically. Figure 18B ).

[0272] refer to Figure 19A and Figure 19B In one or more aspects, the display device 100 can detect the CV characteristics of the test transistor TTR by grounding the lower gate BGE of the test transistor TTR disposed in the test area 200 and applying a test voltage CVH to its upper gate TGE.

[0273] For example, such as Figure 19A The circuit diagram shows that the test pads of the source (SE) and drain (DE) of the test transistor TTR can be electrically connected. In this configuration, the lower gate (BGE) can be grounded, and the test voltage (CVH) can be applied to the upper gate (TGE). Figure 19A ).

[0274] In this state, the CV characteristics of the test transistor TTR can be detected while the test voltage CVH applied to the upper gate TGE is changed.

[0275] In this example, it can be seen that the capacitance in the CV characteristic of the test transistor TTR changes drastically relative to the test voltage CVH of 0V. Therefore, for both low-frequency and high-frequency driving conditions, the flicker characteristics of the test transistor TTR can be analyzed by detecting the deviation of the test voltage CVH at the point where the capacitance changes drastically. Figure 19B ).

[0276] As described above, since the display device 100 has a configuration in which the lower gate of the test transistor TTR is configured not to overlap perpendicularly with the corresponding source and drain (SE and DE), the display device 100 can provide the effect or advantage of reducing the overlap capacitance and reducing the error of the CV characteristics of the test transistor.

[0277] Furthermore, since the display device 100 has a configuration in which the lower gate of the test transistor TTR is electrically connected to the base metal layer, the display device 100 can provide the effect or advantage of reducing the resistive component of the test transistor TTR and accurately detecting the CV characteristics of the test transistor TTR.

[0278] The exemplary implementations described herein will be briefly described below.

[0279] According to one or more exemplary embodiments described herein, a display device may be provided, comprising a display panel and a driving circuit. The display panel includes a display area having sub-pixels including driving transistors and a non-display area outside the display area that does not display an image, and is configured to drive the display panel. In one or more aspects, the non-display area may include a test area, wherein a plurality of test transistors are connected in parallel for detecting flicker characteristics of at least one driving transistor.

[0280] In one or more aspects, multiple test transistors may be configured such that the drains of the multiple test transistors are connected to each other and the sources of the multiple test transistors are connected to each other.

[0281] In one or more aspects, the test area can be located away from the drive circuit.

[0282] In one or more aspects, at least one driving transistor and multiple test transistors may be oxide transistors.

[0283] In one or more aspects, the plurality of test transistors may include a base metal layer disposed on a substrate, a first gate disposed on the base metal, an active layer disposed on the first gate, a second gate disposed on the active layer, and drain and source electrodes contacting various portions of the active layer, wherein the first gate may be configured such that the first gate does not overlap with the drain and source electrodes in the vertical direction.

[0284] In one or more aspects, the first gate may be electrically connected to the base metal layer via a connecting line.

[0285] In one or more aspects, the interconnects may be located in the same layer as the drain and source, and electrically interconnect the first gate and the base metal layer through contact holes.

[0286] In one or more aspects, the base metal layer may be grounded for use in detecting capacitance-voltage characteristics via a second gate.

[0287] In one or more aspects, in order to detect the capacitance-voltage characteristics through the upper gate, a first test voltage may be provided to the base metal layer, and a second test voltage greater than the first test voltage may be provided to the upper gate.

[0288] In one or more aspects, the base metal layer, the first gate, and the second gate may comprise the same material.

[0289] In one or more aspects, the plurality of test transistors may include a base metal layer disposed on a substrate, a shielding metal layer disposed on the base metal layer, an active layer disposed on the shielding metal layer, a gate disposed on the active layer, and a drain and a source contacting various portions of the active layer, wherein the shielding metal layer may be electrically connected to the base metal layer via a connecting wire.

[0290] In one or more aspects, the connecting wires may be disposed in the same layer as the drain and source, and the shielding metal layer and the base metal layer may be electrically interconnected through contact holes.

[0291] In one or more aspects, the base metal layer may be grounded for use in sensing capacitance-voltage characteristics via the gate.

[0292] In one or more aspects, in order to detect the capacitance-voltage characteristics through the gate, a first test voltage may be provided to the base metal layer, and a second test voltage greater than the first test voltage may be provided to the gate.

[0293] In one or more aspects, the base metal layer, the shielding metal layer, and the gate may comprise the same material.

[0294] According to one or more exemplary embodiments described herein, a display panel may be provided comprising a display area in which subpixels, including driving transistors, are disposed, and a non-display area outside the display area in which no image is displayed. In one or more aspects, the non-display area may include a test area in which a plurality of test transistors are connected in parallel for detecting flicker characteristics of at least one driving transistor.

[0295] The above description has been presented to enable any person skilled in the art to make, use, and practice the technical features of this disclosure, and has been provided as examples in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of this disclosure. The above description and drawings provide examples of the technical features of this disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of this disclosure.

[0296] Cross-reference to related applications

[0297] This application claims priority to Korean Patent Application No. 10-2024-0125523, filed on September 13, 2024, with the Korean Intellectual Property Office, which is incorporated herein by reference for all purposes, as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display panel includes a display area with sub-pixels for displaying images and a non-display area located outside the display area that does not display images; as well as A driving circuit configured to drive the display panel; The non-display area includes a test area, which includes a plurality of test transistors, and the detected operating characteristics of the plurality of test transistors represent the operating characteristics of at least one of the plurality of transistors in the sub-pixel.

2. The display device according to claim 1, wherein, The test area includes: A first test area, located in the non-display area, includes at least one first test transistor, the at least one first test transistor corresponding to at least one oxide driving transistor among the plurality of transistors included in the sub-pixel; and A second test area is located in the non-display area. The second test area includes at least one second test transistor, which corresponds to at least one oxide switching transistor among the plurality of transistors included in the sub-pixel.

3. The display device according to claim 2, wherein, The at least one first test transistor includes: The base metal layer on the substrate; The lower gate overlapping the base metal layer; The first active layer overlapping with the lower gate; The upper gate overlapping the first active layer; and The first drain electrode is in contact with the first portion of the first active layer, and the first source electrode is in contact with the second portion of the first active layer, respectively. Wherein, the lower gate does not overlap with the first drain and the first source.

4. The display device according to claim 3, wherein, The base metal layer comprises the same material as the lower gate of the at least one oxide switching transistor.

5. The display device according to claim 3, wherein, The lower gate comprises the same material as the lower gate of the at least one oxide drive transistor. The first active layer comprises the same material as the active layer of the at least one oxide driving transistor. Wherein, the upper gate comprises the same material as the upper gate of the at least one oxide driving transistor, and The first source electrode comprises the same material as the source electrode of the at least one oxide driving transistor, and the first drain electrode comprises the same material as the drain electrode of the at least one oxide driving transistor.

6. The display device according to claim 3, further comprising: A first connection line electrically connects the lower gate and the base metal layer.

7. The display device according to claim 6, wherein, The first connection line comprises the same material as the first source and the first drain, and the first connection line electrically connects the lower gate and the base metal layer through a contact hole.

8. The display device according to claim 6, wherein, The base metal layer is grounded, and the detected operating characteristics include the capacitance-voltage characteristics detected through the upper gate.

9. The display device according to claim 6, wherein, The detected operating characteristics include the capacitance-voltage characteristics detected by the upper gate, while a first test voltage is applied to the base metal layer and a second test voltage greater than the first test voltage is applied to the upper gate.

10. The display device according to claim 2, wherein, The at least one second test transistor includes: The base metal layer on the substrate; The lower gate overlapping the base metal layer; The second active layer overlapping the lower gate; The upper gate overlapping the second active layer; and A second drain and a second source are connected, with the second drain contacting a first portion of the second active layer and the second source contacting a second portion of the second active layer. Wherein, the lower gate does not overlap with the second drain and the second source.

11. The display device according to claim 10, wherein, The lower gate comprises the same material as the lower gate of the at least one oxide switching transistor. The second active layer comprises the same material as the active layer of the at least one oxide switching transistor. Wherein, the upper gate comprises the same material as the upper gate of the at least one oxide switching transistor, and The second source electrode comprises the same material as the source electrode of the at least one oxide switching transistor, and the second drain electrode comprises the same material as the drain electrode of the at least one oxide switching transistor.

12. The display device according to claim 10, further comprising: The second connection line electrically connects the lower gate and the base metal layer.

13. The display device according to claim 12, wherein, The second connection line is in the same layer as the second drain and the second source, and the second connection line electrically connects the lower gate and the base metal layer through a contact hole.

14. The display device according to claim 12, wherein, The base metal layer is grounded, and the detected operating characteristics include the capacitance-voltage characteristics detected through the upper gate.

15. The display device according to claim 12, wherein, The detected operating characteristics include the capacitance-voltage characteristics detected by the upper gate, while a first test voltage is applied to the base metal layer and a second test voltage greater than the first test voltage is applied to the lower gate.

16. The display device according to claim 2, wherein, The upper gate of the at least one oxide driving transistor and the upper gate of the at least one oxide switching transistor are in the same layer, and the lower gate of the at least one oxide driving transistor and the lower gate of the at least one oxide switching transistor are in different layers.

17. The display device according to claim 2, wherein, The test area also includes: A third test area, located in the non-display area, includes at least one third test transistor corresponding to at least one polysilicon switching transistor among the plurality of transistors included in the sub-pixel.

18. The display device according to claim 17, wherein, The at least one third test transistor includes: The base metal layer on the substrate; A light-shielding layer overlapping the base metal layer; A third active layer overlaps with the light-shielding layer, such that the light-shielding layer is located between the base metal layer and the third active layer; The gate overlapping the third active layer; and A third drain and a third source, wherein the third drain contacts a first portion of the third active layer, and the third source contacts a second portion of the third active layer. The light-shielding layer does not overlap with the third drain and the third source.

19. The display device according to claim 18, wherein, The light-shielding layer comprises the same material as the light-shielding layer of the at least one polysilicon switching transistor. The third active layer comprises the same material as the active layer of the at least one polysilicon switching transistor. Wherein, the gate comprises the same material as the gate of the at least one polysilicon switching transistor, and The third source electrode comprises the same material as the source electrode of the at least one polysilicon switching transistor, and the third drain electrode comprises the same material as the drain electrode of the at least one polysilicon switching transistor.

20. The display device according to claim 18, further comprising: The third connecting line is electrically connected to the light-shielding layer and the base metal layer.

21. The display device according to claim 20, wherein, The third connecting line is in the same layer as the third drain and the third source, and the third connecting line electrically connects the light-shielding layer and the base metal layer through a contact hole.

22. The display device according to claim 1, wherein, The multiple test transistors are connected in parallel.

23. The display device according to claim 22, wherein, The plurality of test transistors are connected in parallel such that the accumulated capacitance in the plurality of test transistors is in the range of 5pF to 20pF.

24. A display panel, the display panel comprising: The display area includes multiple sub-pixels; as well as A non-display area, located outside the display area, is where no image is displayed. The non-display area includes: The test area includes multiple test transistors. Specifically, the operational characteristics of the plurality of test transistors are detected, and the operational characteristics represent the operational characteristics of the plurality of transistors included in the plurality of sub-pixels.

25. The display panel according to claim 24, wherein, The test area includes: A first test area, located in the non-display area, includes at least one first transistor corresponding to at least one oxide driving transistor among the plurality of transistors included in the plurality of sub-pixels; and The second test area, located in the non-display area, includes at least one second transistor corresponding to at least one oxide switching transistor among the plurality of transistors included in the plurality of sub-pixels.

26. A display panel, the display panel comprising: A substrate, the substrate including a display area and a non-display area surrounding the display area, the non-display area including a test area; A transistor in the display area of ​​the substrate; A light-emitting element is located in the display area, and the transistor is connected to the light-emitting element; Multiple test transistors are located in the test area outside the display area, and at least one of the test transistors is on the same layer as the transistor. Wherein, the at least one test transistor includes: The base metal layer in the test area; The lower gate that overlaps with the base metal layer in the test region; The active layer overlapping the lower gate in the test region; The upper gate overlapping the active layer in the test region; and A drain and a source are provided, wherein the drain contacts a first portion of the active layer in the test region, and the source contacts a second portion of the active layer in the test region. In this test region, the lower gate does not overlap with the drain and the source.

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