Display panel and display device

Abstract

The invention relates to the technical field of display, in particular to a display panel and a display device. The display panel includes a gate drive circuit and a plurality of pixel drive circuits. The gate drive circuit includes a plurality of shift registers. A first control module of the shift register is used for controlling the potential of a first node, and a second control module is used for controlling the potential of a second node. The first output module is used for transmitting the first power signal or the first control signal to the first output end according to the potentials of the first node and the second node. And the second output module is used for transmitting the first power supply signal or the second power supply signal to a second output end according to the potential of the first node and the second node. The first output end is electrically connected with a data write-in transistor of the pixel driving circuit, and the enable pulse width of the first control signal is smaller than the line scanning duration of the display panel. The scanning signal output by the first output end of the shifting register of the display panel can meet the write-in time sequence requirement of the data write-in transistor.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] The gate drive circuit is one of the essential circuits for display panels. A gate drive circuit typically includes multiple cascaded shift registers, which are electrically connected to the sub-pixels of the display panel. The signals output by the shift registers are used to control the state of the transistors in the sub-pixels, thereby driving the sub-pixels to emit light.

[0003] Existing shift registers are unable to output short pulse signals within 1H, which makes it difficult to meet the writing timing requirements of IGZO type data writing transistors. As a result, the light emission effect of sub-pixels is affected. Therefore, how to optimize the performance of shift registers is an important problem faced by those skilled in the art. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display panel and a display device.

[0005] In a first aspect, this disclosure provides a display panel. The display panel includes a gate driving circuit and multiple pixel driving circuits arranged in an array. The gate driving circuit includes multiple cascaded shift registers. Each shift register includes a first control module, a second control module, a first output module, and a second output module. The first control module is electrically connected to a signal input terminal, a first clock signal terminal, a second clock signal terminal, and a first node, respectively. The first control module is configured to control the potential of the first node based on a first clock signal provided by the first clock signal terminal, a second clock signal provided by the second clock signal terminal, and an input signal provided by the signal input terminal. The second control module is electrically connected to the first node, a first power signal terminal, a second power signal terminal, and a second node, respectively. The second control module is configured to control the potential of the second node based on the potential of the first node, a first power signal provided by the first power signal terminal, and a second power signal provided by the second power signal terminal. The first output module is electrically connected to the first node, the second node, the first power signal terminal, a first control signal terminal, and a first output terminal, respectively. The first output module is configured to transmit a first power signal or a first control signal provided by the first control signal terminal to the first output terminal based on the potential of the first node and the potential of the second node. The second output module is electrically connected to the first node, the second node, the first power signal terminal, the second power signal terminal, and the second output terminal, respectively. The second output module is configured to transmit either a first power signal or a second power signal to the second output terminal based on the potentials of the first and second nodes. The second output terminal of the nth-stage shift register is electrically connected to the signal input terminal of the (n+1)th-stage shift register. The first output terminal of the nth-stage shift register is electrically connected to the data write transistor of the pixel driving circuit in the nth row. The enable pulse width of the first control signal is less than the row scan duration of the display panel. n is a positive integer.

[0006] Secondly, this disclosure provides a display device. The display device includes the display panel provided in any of the first aspects.

[0007] Compared with the prior art, the technical solution provided in this disclosure has the following advantages: The shift register of the gate driving circuit in the display panel provided in this disclosure has an independent first output module and a second output module. The second output terminal of the second output module is electrically connected to the signal input terminal of the next-stage shift register, so that the signal output from the second output terminal of the previous-stage shift register is used as the input signal of the next-stage shift register, thereby realizing the cascading of multiple shift registers in the gate driving circuit. In addition, the first output module is electrically connected to the first control signal terminal to construct a short pulse output line, realizing stable output of short pulses within 1 hour. Thus, the scan signal output from the first output terminal of the shift register can meet the writing timing requirements of the data writing transistor, effectively breaking through the application limitations of traditional shift register circuits in short pulse driving scenarios, and further broadening the adaptability range of shift registers in display panels. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of the structure of a display panel provided in the prior art; Figure 2 A schematic diagram of a gate drive circuit provided in the prior art; Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the structure of a shift register provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of another shift register structure provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure; Figure 7 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure; Figure 8 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure; Figure 9 A timing diagram for driving a shift register circuit provided in an embodiment of this disclosure; Figure 10 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure; Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure. Detailed Implementation

[0011] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0012] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0013] Figure 1 A schematic diagram of the structure of a display panel provided in the prior art. Figure 2 A schematic diagram of a gate drive circuit provided by the prior art.

[0014] In existing technologies, such as Figure 1 and Figure 2 As shown, the gate driving unit 01 includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, a first capacitor C10, a second capacitor C20, and a third capacitor C30.

[0015] The gate of the first transistor M1 is electrically connected to the first power supply signal terminal VGL, the first terminal of the first transistor M1 is electrically connected to the third connection node N3, and the second terminal of the first transistor M1 is electrically connected to the fourth connection node A4.

[0016] The gate of the second transistor M2 is electrically connected to the fourth connection node A4, the first terminal of the second transistor M2 is electrically connected to the fifth connection node A5, and the second terminal of the second transistor M2 is electrically connected to the second clock signal terminal XCK.

[0017] The gate of the third transistor M3 is electrically connected to the second clock signal terminal XCK, the first terminal of the third transistor M3 is electrically connected to the fifth connection node A5, and the second terminal of the third transistor M3 is electrically connected to the sixth connection node A6.

[0018] The gate of the fourth transistor M4 is electrically connected to the first clock signal terminal CK, the first terminal of the fourth transistor M4 is electrically connected to the signal input terminal IN, and the second terminal of the fourth transistor M4 is electrically connected to the first connection node A1.

[0019] The gate of the fifth transistor M5 is electrically connected to the first clock signal terminal CK, the first terminal of the fifth transistor M5 is electrically connected to the first power supply signal terminal VGL, and the second terminal of the fifth transistor M5 is electrically connected to the third connection node A3.

[0020] The gate of the sixth transistor M6 is electrically connected to the first clock signal terminal CK, the first terminal of the sixth transistor M6 is electrically connected to the signal input terminal IN, and the second terminal of the sixth transistor M6 is electrically connected to the first terminal of the fifteenth transistor M15.

[0021] The gate of the seventh transistor M7 is electrically connected to the first connection node A1, the first terminal of the seventh transistor M7 is electrically connected to the sixth connection node A6, and the second terminal of the seventh transistor M7 is electrically connected to the second power supply signal terminal VGH.

[0022] The gate of the eighth transistor M8 is electrically connected to the first connection node A1, the first terminal of the eighth transistor M8 is electrically connected to the third connection node A3, and the second terminal of the eighth transistor M8 is electrically connected to the first clock signal terminal CK.

[0023] The gate of the ninth transistor M9 is electrically connected to the sixth connection node A6, the first terminal of the ninth transistor M9 is electrically connected to the second power supply signal terminal VGH, and the second terminal of the ninth transistor M9 is electrically connected to the output terminal OUT.

[0024] The gate of the tenth transistor M10 is electrically connected to the second connection node A2, the first terminal of the tenth transistor M10 is electrically connected to the second connection node A2, and the second terminal of the tenth transistor M10 is electrically connected to the output terminal OUT.

[0025] The gate of the eleventh transistor M11 is electrically connected to the eighth connection node A8, the first terminal of the eleventh transistor M11 is electrically connected to the seventh connection node A7, and the second terminal of the eleventh transistor M11 is electrically connected to the second clock signal terminal XCK.

[0026] The gate of the twelfth transistor M12 is electrically connected to the third connection node A3, the first terminal of the twelfth transistor M12 is electrically connected to the seventh connection node A7, and the second terminal of the twelfth transistor M12 is electrically connected to the second power supply signal terminal VGH.

[0027] The gate of the thirteenth transistor M13 is electrically connected to the eighth connection node A8, the first terminal of the thirteenth transistor M13 is electrically connected to the second connection node A2, and the second terminal of the thirteenth transistor M13 is electrically connected to the eighth connection node A8.

[0028] The gate of the fourteenth transistor M14 is electrically connected to the first power supply signal terminal VGL, the first terminal of the fourteenth transistor M14 is electrically connected to the first connection node A1, and the second terminal of the fourteenth transistor M14 is electrically connected to the second connection node A2.

[0029] The gate of the fifteenth transistor M15 is electrically connected to the first power supply signal terminal VGL, the first terminal of the fifteenth transistor M15 is electrically connected to the second terminal of the sixth transistor M6, and the second terminal of the fifteenth transistor M15 is electrically connected to the eighth connection node A8.

[0030] The first plate of the first capacitor C10 is electrically connected to the sixth connection node A6, and the second plate of the first capacitor C10 is electrically connected to the second power signal terminal VGH.

[0031] The first plate of the second capacitor C20 is electrically connected to the fourth connection node A4, and the second plate of the second capacitor C20 is electrically connected to the fifth connection node A5.

[0032] The first plate of the third capacitor C30 is electrically connected to the seventh connection node A7, and the second plate of the third capacitor C30 is electrically connected to the eighth connection node A8.

[0033] The output terminal OUT of the aforementioned gate driving unit 01 can be electrically connected to the gate of the data writing transistor in the display area pixel driving circuit to control the conduction status of the data writing transistor. Generally, the data writing transistor in the display area pixel driving circuit can be an indium gallium zinc oxide (IGZO) transistor.

[0034] As described above, gate drive unit 01 and its timing control cannot generate narrow pulse signals with a width less than 1H (the horizontal scan duration of the display panel). The signal output characteristics of gate drive unit 01 directly determine the data writing efficiency and display stability of the pixel drive circuit. The high-speed switching characteristics of IGZO type data writing transistors require that the received gate drive signal have short pulse triggering capability to achieve fast data writing. However, the existing gate drive unit 01 has insufficient output timing compatibility, limiting the refresh rate adjustment and high-resolution display performance of LTPO panels.

[0035] In summary, the aforementioned defects of the existing gate driving unit 01 make it difficult to meet the requirements of LTPO OLED panels for high-speed driving, low power consumption and high stability. Therefore, there is an urgent need for a gate driving unit 01 that can achieve narrow pulse output and smooth level transition.

[0036] Based on this, some embodiments of this disclosure also provide a display panel. Figure 3This is a schematic diagram of the structure of a display panel provided in an embodiment of the present disclosure.

[0037] like Figure 3 As shown, the display panel 100 provided in this embodiment of the present disclosure may be an OLED (Organic Light Emitting Diode) display panel or a QLED (Quantum Dot Light Emitting Diodes) display panel.

[0038] The following uses an OLED display panel as an example to illustrate some embodiments of this disclosure. However, the implementation of this disclosure is not limited to this, and any other display panel can be considered as long as the same technical concept is applied.

[0039] In some examples, the display panel 100 has a display area AA and a peripheral area SA. The peripheral area SA may be located on at least one side of the display area AA (e.g., one side; or, all around, including the top and bottom sides and the left and right sides).

[0040] The display panel 100 includes a plurality of subpixels P disposed in a display area AA. The display panel 100 can display a predetermined image in the display area AA by means of light emitted from the plurality of subpixels P. The plurality of subpixels P may include multiple subpixels with different emission colors.

[0041] A sub-pixel P may include a light-emitting unit E and a pixel driving circuit M electrically connected to the light-emitting unit E.

[0042] The light-emitting unit E can be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), but is not limited to these. The embodiments of this disclosure do not limit the type of light-emitting device; that is, the light-emitting unit E can be any other light-emitting device (e.g., a light-emitting device that emits light through discharge), as long as they can emit light so that the display panel 100 can display an image.

[0043] The pixel driving circuit M may include multiple transistors and at least one (e.g., one; or multiple) capacitor. For example, the pixel driving circuit M may be a structure such as "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, such as a thin-film transistor. The number preceding "T" indicates the number of transistors. "C" represents a capacitor, and the number preceding "C" indicates the number of capacitors. The pixel driving circuit M may include a data writing transistor T among the multiple transistors. The gate of the data writing transistor T is electrically connected to the first scan signal terminal S1, the first terminal of the data writing transistor T is electrically connected to the data writing signal terminal, and the second terminal of the data writing transistor T is electrically connected to other transistors in the pixel driving circuit M. For example, the second terminal of the data writing transistor T may be electrically connected to the driving transistor.

[0044] In some examples, the display panel 100 may include a plurality of pixel driving circuits M, which are arranged in an array in the display area AA. The display panel 100 may also include a gate driver on array (GOA) G, which may be disposed in the peripheral area SA of the display panel 100. The gate driver circuit G may be electrically connected to the first scan signal terminal of the pixel driving circuit M, that is, electrically connected to the data write transistor of the pixel driving circuit, to provide a scan signal to control the conduction state of the data write transistor.

[0045] The gate drive circuit G may include multiple cascaded vertical shift registers (VSRs) G1, each of which is electrically connected to a multi-row pixel drive circuit to provide scan signals for its data writing transistors.

[0046] For example, the number of shift registers G1 can be equal to the number of rows of pixel driving circuits M in the display panel 100, so that the multi-level shift registers G1 can be connected one-to-one with the multi-row pixel driving circuits M.

[0047] For example, the first-stage shift register G1 can be electrically connected to the first scan signal terminal S1 of the pixel driving circuit M in the first row pixel driving circuit to provide a scan signal for its data writing transistor. Similarly, the a-th stage shift register G1 can be electrically connected to the first scan signal terminal S1 of the pixel driving circuit M in the a-th row pixel driving circuit to provide a scan signal for its data writing transistor. Here, a is a positive integer. Based on this, a scan signal can be provided to the data writing transistor of the pixel driving circuit M through the gate driving circuit G.

[0048] It is understood that the display panel 100 may include a first scan signal line, and the shift register G1 may be electrically connected to the first scan signal terminal S1 of the pixel driving circuit M of the corresponding row through the first scan signal line. The first scan signal line may transmit the scan signal from the shift register G1 to the first scan signal terminal S1 of the pixel driving circuit M.

[0049] Figure 4 This is a schematic diagram of the structure of a shift register provided in an embodiment of this disclosure.

[0050] like Figure 4 As shown, in some embodiments, the shift register G1 may include: a first control module 10, a second control module 20, a first output module 30, and a second output module 40.

[0051] The first control module 10 is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal XCK, and the first node N1. The first control module 10 is configured to control the potential of the first node N1 according to the first clock signal ck provided by the first clock signal terminal CK, the second clock signal xck provided by the second clock signal terminal XCK, and the input signal in provided by the signal input terminal IN.

[0052] The second control module 20 is electrically connected to the first node N1, the first power signal terminal VGL, the second power signal terminal VGH, and the second node N2. The second control module 20 is configured to control the potential of the second node N2 based on the potential of the first node N1, the first power signal vgl provided by the first power signal terminal VGL, and the second power signal vgh provided by the second power signal terminal VGH.

[0053] The first output module 30 is electrically connected to the first node N1, the second node N2, the first power signal terminal VGL, the first control signal terminal CKA, and the first output terminal OUT1. The first output module 30 is configured to transmit the first power signal VGL or the first control signal CKA provided by the first control signal terminal CKA to the first output terminal OUT1 according to the potential of the first node N1 and the potential of the second node N2.

[0054] The second output module 40 is electrically connected to the first node N1, the second node N2, the first power signal terminal VGL, the second power signal terminal VGH, and the second output terminal OUT2. The second output module 40 is configured to transmit either the first power signal VGL or the second power signal VGH to the second output terminal OUT2 based on the potential of the first node N1 and the second node N2.

[0055] The second output terminal OUT2 of the nth-stage shift register G1 is electrically connected to the signal input terminal IN of the (n+1)th-stage shift register G1. The first output terminal OUT1 of the nth-stage shift register G1 is connected to the gate of the data writing transistor T of the pixel driving circuit M in the nth row (e.g., Figure 3 (As shown) Electrical connection, the enable pulse width of the first control signal cka is less than the row scan duration of the display panel. n is a positive integer.

[0056] It should be noted that the first clock signal ck can be a pulse signal alternating between high and low level signals, and similarly, the second clock signal xck can also be a pulse signal alternating between high and low level signals. Typically, a high-level signal and a consecutive low-level signal constitute one pulse cycle. The enable levels of the second clock signal xck and the first clock signal ck do not overlap; that is, when the first clock signal ck is high, the second clock signal xck can be low, and vice versa. A low-level signal can be the enable level for both the first clock signal ck and the second clock signal xck, and a high-level signal can be the disable level for both clock signals ck and xck; alternatively, a high-level signal can be the enable level for both clock signals ck and xck, and a low-level signal can be the disable level for both clock signals ck and xck. It is understood that the enable and disable levels of the first clock signal ck and the second clock signal xck can be set as needed, and this embodiment does not specifically limit this. This article uses the example of a low-level signal being the enable level for the first clock signal ck and the second clock signal xck, and a high-level signal being the disable level for the first clock signal ck and the second clock signal xck.

[0057] In addition, the input signal in can also be a pulse signal that alternates between high-level and low-level signals.

[0058] The first power signal vgl at the first power signal terminal VGL can be a fixed signal and the second power signal vgh at the second power signal terminal VGH. For example, when the first power signal vgl at the first power signal terminal VGL is a low-level signal, the second power signal vgh at the second power signal terminal VGH can be a high-level signal; conversely, when the first power signal vgl at the first power signal terminal VGL is a high-level signal vgh, the second power signal vgh at the second power signal terminal VGH can be a low-level signal vgl. It is understood that the first power signal vgl at the first power signal terminal VGL and the second power signal vgh at the second power signal terminal VGH can be set as needed, and this embodiment does not specifically limit this.

[0059] As described above, the first control module 10, under the control of the first clock signal ck and the second clock signal xck, can transmit the input signal in to the first node N1, so that the potential of the first node N1 matches the input signal in. Alternatively, the second clock signal xck can be used to pull down the potential of the first node N1, so that the potential of the first node N1 matches the enable level of the second clock signal xck, thereby preventing the potential of the first node N1 from rising over time and ensuring that the potential of the first node N1 remains a stable low level, thus stabilizing the potential of the first node N1. Therefore, the first node N1 can provide a continuously stable low-level signal to the first output module 30 and the second output module 40.

[0060] Based on this, when the input signal in is at a low level, the first output module 30 can respond to the low level of the first node N1 by controlling the line between the first power signal terminal VGL and the first output terminal OUT1 in the first output module 30 to be open, and the first power signal vgl provided by the first power signal terminal VGL can be transmitted to the first output terminal OUT1. Similarly, the second output module 40 can respond to the low level of the first node N1 by controlling the line between the first power signal terminal VGL and the second output terminal OUT2 in the second output module 40 to be open, and the first power signal vgl provided by the first power signal terminal VGL can be transmitted to the second output terminal OUT2. Furthermore, the second control module 20 can respond to the low level of the first node N1 by controlling the transmission of the second power signal vgh from the second power signal terminal VGH to the second node N2, so that the potential of the second node N2 matches the second power signal vgh. That is, the potential of the second node N2 is high. Therefore, the first output module 30 can respond to the high level of the second node N2 and control the line between the first control signal terminal CKA and the first output terminal OUT1 in the first output module 30 to be open circuit. Similarly, the second output module 40 can respond to the high level potential of the second node N2 and control the line between the second power signal terminal VGH and the second output terminal OUT2 in the second output module 40 to be open circuit.

[0061] Correspondingly, when the input signal in is at a high level, the first output module 30 can respond to the high level of the first node N1 by controlling the line between the first power signal terminal VGL and the first output terminal OUT1 in the first output module 30 to be open-circuited. Similarly, the second output module 40 can respond to the high level of the first node N1 by controlling the line between the first power signal terminal VGL and the second output terminal OUT2 in the second output module 40 to be open-circuited. Furthermore, the second control module 20 can respond to the high level of the first node N1 by controlling the transmission of the first power signal vgl from the first power signal terminal VGL to the second node N2, so that the potential of the second node N2 matches the first power signal vgl. That is, the potential of the second node N2 is low. Therefore, the first output module 30 can respond to the low level of the second node N2 and control the line between the first control signal terminal CKA and the first output terminal OUT1 in the first output module 30 to be a closed circuit, and the first control signal cka provided by the first control signal terminal CKA can be transmitted to the first output terminal OUT1. Similarly, the second output module 40 can respond to the low level of the second node N2 and control the line between the second power signal terminal VGH and the second output terminal OUT2 in the second output module 40 to be a closed circuit, and the second power signal vgh provided by the second power signal terminal VGH can be transmitted to the second output terminal OUT2.

[0062] As described above, when the first output module 30 transmits the first power signal vgl provided by the first power signal terminal VGL to the first output terminal OUT1, the scan signal output by the shift register G1 can be considered as a non-enable signal that can control the data writing transistor T of the pixel driving circuit M of the display panel to turn off (cut off). When the first output module 30 transmits the first control signal cka (enable pulse signal) provided by the first control signal terminal CKA to the first output terminal OUT1, the scan signal (enable pulse signal) output by the shift register G1 can be considered as an enable signal that can control the data writing transistor T of the pixel driving circuit M of the display panel to turn on. In addition, since the enable pulse width of the first control signal cka provided by the first control signal terminal CKA is less than the row scan duration H of the display panel, the enable pulse width that the first output terminal OUT1 of the shift register G1 can output is less than 1H scan signal, where H is the row scan duration of the display panel.

[0063] Furthermore, since the second output terminal OUT2 of the nth-stage shift register G1 is electrically connected to the signal input terminal IN of the (n+1)th-stage shift register G1, it can be understood that the second output terminal OUT2 of the current-stage shift register G1 is electrically connected to the signal input terminal IN of the next-stage shift register G1. Therefore, when the second output module 30 of the current-stage shift register G1 transmits the first power signal vgl provided by the first power signal terminal VGL to the second output terminal OUT2, the second output terminal OUT2 can transmit the first power signal vgl to the signal input terminal IN of the next-stage shift register G1. That is, the first power signal vgl output by the second output module 30 of the current-stage shift register G1 can be used as a low-level signal of the input signal in of the signal input terminal IN of the next-stage shift register G1.

[0064] Correspondingly, when the second output module 30 of the current stage shift register G1 transmits the second power signal vgh provided by the second power signal terminal VGH to the second output terminal OUT2, the second output terminal OUT2 can transmit the second power signal vgh to the signal input terminal IN of the next stage shift register G1. That is, the second power signal vgh output by the second output module 30 of the current stage shift register G1 can be used as a high-level signal of the input signal in of the signal input terminal IN of the next stage shift register G1. Based on this, multiple shift registers G1 in the gate drive circuit G can be cascaded.

[0065] In summary, the shift register G1 of the gate drive circuit G in the display panel 100 provided in this embodiment has two independent output modules: a first output module 30 and a second output module 40. The second output terminal OUT2 of the second output module 40 is electrically connected to the signal input terminal IN of the next-stage shift register G1, so that the signal output from the second output terminal OUT2 of the previous-stage shift register G1 is used as the input signal IN of the next-stage shift register G1. The first output module 30 is electrically connected to the first control signal terminal CKA to construct a short pulse output line, realizing stable output of short pulses within 1H. The scan signal output from the first output terminal OUT of the shift register G1 can meet the writing timing requirements of the data writing transistor T (IGZO), effectively breaking through the application limitations of traditional shift register circuits in short pulse driving scenarios, and further broadening the adaptability range of the shift register G1 in the display panel 100.

[0066] like Figure 4 As shown, in some embodiments, the potential of the second node N2 is at the first level phase of the first level, covering the enable pulse phase of the first control signal cka. The first level is configured to control the second output module 40 to transmit the first control signal cka to the first output terminal OUT1.

[0067] Based on this, the potential of the second node N2 is at the first level (e.g., low level), which covers the enable pulse phase of the first control signal cka. In other words, the first output module 30 responds to the first level of the second node N2, controlling the duration of the path between the first control signal terminal CKA and the first output terminal OUT1 to be a closed path, which covers the enable pulse phase of the first control signal cka. Thus, the duration of the path between the first control signal terminal CKA and the first output terminal OUT1 controlled by the first output module 30 in response to the first level of the second node N2 can be adapted to the enable pulse period. This ensures that the complete enable pulse of the first control signal cka is transmitted to the first output terminal OUT1 without loss or distortion, and also achieves precise synchronization between path control and control signals, reducing circuit malfunctions caused by timing deviations, thereby improving the reliability of subsequent load driving and the accuracy of signal transmission.

[0068] It should be noted that, since the first control signal cka can subsequently be transmitted to the second output terminal OUT2 as a scan signal, and the second output terminal OUT2 of the shift register G1 needs to be connected to the data writing transistor T (e.g., Figure 3 The gate of the transistor (shown) is electrically connected to control the state of the data writing transistor T. The data writing transistor T is an IGZO transistor, and the enable level of the scan signal is high. Therefore, the enable pulse phase of the first control signal cka is also the enable pulse phase of the scan signal (high level phase), and the enable pulse phase of the first control signal cka is its high level phase.

[0069] In some examples, within a duty cycle (in a refresh frame), the start time of the enable pulse phase of the first control signal cka is later than the start time of the first level phase, and the end time of the enable pulse phase of the first control signal cka is earlier than the end time of the first level phase.

[0070] Thus, the first level phase covers the enable pulse phase of the first control signal cka, so that the complete enable pulse of the first control signal cka is transmitted to the first output terminal OUT1 without loss or distortion.

[0071] Figure 5 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure.

[0072] like Figure 5 As shown, in some embodiments, the first output module 30 includes: a first output transistor T13, a second output transistor T14, and a second capacitor C2.

[0073] The gate of the first output transistor T13 is electrically connected to the second node N2, the first terminal of the first output transistor T13 is electrically connected to the first control signal terminal CKA, and the second terminal of the first output transistor T13 is electrically connected to the first output terminal OUT1. The gate of the second output transistor T14 is electrically connected to the first node N1, the first terminal of the second output transistor T14 is electrically connected to the first power supply signal terminal VGL, and the second terminal of the second output transistor T14 is electrically connected to the first output terminal OUT1.

[0074] The first plate of the second capacitor C2 is electrically connected to the seventh node N7, and the second plate of the second capacitor C2 is electrically connected to the first output terminal OUT1. The seventh node N7 is also electrically connected to the gate of the first output transistor T13, and the seventh node N7 is also electrically connected to the second node N2. Alternatively, in this embodiment, the second node N2 can also be used as the seventh node N7.

[0075] Based on this, when the input signal in is at a low level, the second output transistor T14 in the first output module 30 can be turned on in response to the low level of the first node N1, connecting the first power signal terminal VGL and the first output terminal OUT1 in the first output module 30. The first power signal vgl provided by the first power signal terminal VGL can be transmitted to the first output terminal OUT1. In addition, the second control module 20 can respond to the low level of the first node N1 and control the second node N2 to be at a high level. The first output transistor T13 in the first output module 30 can be turned off in response to the high level of the second node N2. Thus, the line between the first control signal terminal CKA and the first output terminal OUT1 in the first output module 30 is disconnected.

[0076] When the input signal in is at a high level, the second output transistor T14 in the first output module 30 can turn off in response to the high level of the first node N1, thereby breaking the circuit between the first power signal terminal VGL and the first output terminal OUT1 in the first output module 30. In addition, the second control module 20 can respond to the high level of the first node N1 and control the potential of the second node N2 to be at a low level. The first output transistor T13 in the first output module 30 can respond to the low level of the second node N2 and turn on, connecting the first control signal terminal CKA and the first output terminal OUT1 in the first output module 30. The first control signal cka provided by the first control signal terminal CKA can be transmitted to the first output terminal OUT1 through the first output transistor T13.

[0077] Furthermore, when the first control signal cka transitions from a high level (enable level) to a low level (disable level), the potential of the seventh node N7 can be pulled low by the second capacitor C2, which in turn pulls down the gate potential of the first output transistor T13. This compensates for the threshold loss when the first output transistor T13 outputs a low level, reduces the probability of a step in the falling edge of the scan signal output from the first output terminal OUT1, and helps improve the accuracy of the scan signal output from the shift register G1, thereby reducing the data writing to transistor T (e.g., Figure 3 (As shown) the probability of leakage, in order to improve the stability of the pixel driving circuit.

[0078] like Figure 5 As shown, in some examples, the first output transistor T13 can be a P-type transistor. For example, the P-type transistor can be a low-temperature polysilicon (LTPS) transistor.

[0079] like Figure 5 As shown, in some examples, the second output transistor T14 can be a P-type transistor. For example, the P-type transistor can be a low-temperature polysilicon (LTPS) transistor.

[0080] Figure 6 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure.

[0081] like Figure 6 As shown, in some embodiments, the first output module 30 further includes a third protection transistor T12, the gate of the third protection transistor T12 is electrically connected to the first power supply signal terminal VGL, the first terminal of the third protection transistor T12 is electrically connected to the second node N2, and the second terminal of the third protection transistor T12 is electrically connected to the seventh node N7.

[0082] It is understandable that the third protection transistor T12 can be a P-type transistor. The first power signal terminal VGL provides a low-level first power signal vgl. The third protection transistor T12 can respond to the first power signal vgl by being in a conducting state, transmitting the potential of the second node N2 to the seventh node N7. Due to the existence of a threshold voltage for the third protection transistor T12, the third protection transistor T12 will only be in a conducting state when the potential difference between the first power signal vgl and the seventh node N7 or the second node N2 connected to the third protection transistor T12 is less than the threshold voltage of the third protection transistor T12. If this condition is not met, the third protection transistor T12 will be in a turned-off state. In this case, the third protection transistor T12 can protect the device connected to the other node when the potential of one of the nodes, N7 and N2, is abnormal. That is, the third protection transistor T12 is a normally open transistor. When other modules (e.g., the first output transistor T13) experience a momentary failure, the third protection transistor T12 can temporarily maintain the potential stability of the core node, reduce the impact of external interference or circuit noise on the output scanning signal, and improve the overall anti-interference capability and operational reliability of the shift register G1.

[0083] It should be noted that in this embodiment, the first output module 30 further includes a third protection transistor T12, which is a normally open transistor. The gate of the first output transistor T13 can be electrically connected to the second node N2 through the seventh node N7. In this case, the gate of the first output transistor T13 and the second node N2 are indirectly electrically connected.

[0084] like Figure 6 As shown, in some examples, the third protection transistor T12 can be a low-temperature polysilicon (LTPS) transistor.

[0085] like Figure 6 As shown, in some embodiments, the second output module 40 includes: a third output transistor T9, a fourth output transistor T10, a third capacitor C3, and a fourth capacitor C4.

[0086] The gate of the third output transistor T9 is electrically connected to the second node N2, the first terminal of the third output transistor T9 is electrically connected to the second power supply signal terminal VGH, and the second terminal of the third output transistor T9 is electrically connected to the second output terminal OUT2.

[0087] The first plate of the third capacitor C3 is electrically connected to the second node N2, and the second plate of the third capacitor C3 is electrically connected to the second power signal terminal VGH.

[0088] The gate of the fourth output transistor T10 is electrically connected to the first node N1, the first terminal of the fourth output transistor T10 is electrically connected to the first power supply signal terminal VGL, and the second terminal of the fourth output transistor T10 is electrically connected to the second output terminal OUT2.

[0089] The first plate of the fourth capacitor C4 is electrically connected to the first node N1, and the second plate of the fourth capacitor C4 is electrically connected to the second output terminal OUT2.

[0090] Based on this, when the input signal in is at a low level, the fourth output transistor T10 in the second output module 40 can turn on in response to the low level of the first node N1, connecting the first power signal terminal VGL and the second output terminal OUT2 in the second output module 40. The first power signal vgl provided by the first power signal terminal VGL can be transmitted to the second output terminal OUT2. Furthermore, the second control module 20 can respond to the low level of the first node N1 and control the second node N2 to be at a high level. The third output transistor T9 in the second output module 40 can turn off in response to the high level of the second node N2, thereby achieving a circuit break between the second power signal terminal VGH and the second output terminal OUT2 in the second output module 40. Additionally, the stability of the potential of the second node N2 can be improved by using the third capacitor C3.

[0091] Correspondingly, when the input signal in is at a high level, the fourth output transistor T10 in the second output module 40 can turn off in response to the high level of the first node N1. This disconnects the line between the first power signal terminal VGL and the second output terminal OUT2 in the second output module 40. Furthermore, the second control module 20 can respond to the high level of the first node N1 and control the potential of the second node N2 to be low. The third output transistor T9 in the second output module 40 can turn on in response to the low level of the second node N2, connecting the second power signal terminal VGH and the second output terminal OUT2 in the second output module 40. The second power signal vgh provided by the second power signal terminal VGH can be transmitted to the second output terminal OUT2 via the third output transistor T9. Additionally, the stability of the potential of the second node N2 can be improved by using the fourth capacitor C4.

[0092] like Figure 6 As shown, in some examples, the third output transistor T9 can be a P-type transistor. For example, the P-type transistor can be a low-temperature polysilicon (LTPS) transistor.

[0093] like Figure 6As shown, in some examples, the fourth output transistor T10 can be a P-type transistor. For example, the P-type transistor can be a low-temperature polysilicon (LTPS) transistor.

[0094] Figure 7 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure.

[0095] like Figure 7 As shown, in some embodiments, the first control module 10 includes: a first input unit 11, a second input unit 12, and a voltage regulator unit 13.

[0096] The first input unit 11 is electrically connected to the signal input terminal IN, the first clock signal terminal CK, and the first node N1, respectively. The first input unit is configured to transmit the input signal in to the first node N1 in response to the first clock signal CK being turned on.

[0097] The second input unit 12 is electrically connected to the signal input terminal IN, the first clock signal terminal CK, and the third node N3, respectively. The second input unit is configured to transmit the input signal in to the third node N3 in response to the first clock signal CK being turned on.

[0098] The voltage regulator unit 13 is electrically connected to the first node N1, the third node N3, and the second clock signal terminal XCK. The voltage regulator unit is configured to: in response to the voltage turn-on of the third node N3, write the second clock signal xck into the third node N3 and adjust the potential of the first node N1.

[0099] Based on this, when the first clock signal ck is a low-level signal, the first input unit 11 can respond to the low-level signal, the line between the control signal input terminal IN and the first node N1 is open, and the input signal in can be written to the first node N1; and the second input unit 12 can respond to the low-level signal, the line between the control signal input terminal IN and the third node N3 is open, and the input signal in can be written to the third node N3. Conversely, when the first clock signal ck is a high-level signal, the first input unit 11 can respond to the high-level signal, the line between the control signal input terminal IN and the first node N1 is open; and the second input unit 12 can respond to the high-level signal, the line between the control signal input terminal IN and the third node N3 is open.

[0100] When the input signal in is low, the potential of the first node N1 is low, and the potential of the third node N3 is also low. When the second clock signal xck transitions from high to low, it pulls down the potential of the third node N3, making its potential lower than that of the first node N1. This lowering of the third node N3 prevents the potential of the first node N1 from rising over time, ensuring a consistently stable low potential for the first node N1. Therefore, the first node N1 can provide a consistently stable low-level signal to the first output module 30 and the second output module 40.

[0101] like Figure 7 As shown, in some embodiments, the first input unit 11 includes a first input transistor T1 and a first protection transistor T2.

[0102] The gate of the first input transistor T1 is electrically connected to the first clock signal terminal CK, the first terminal of the first input transistor T1 is electrically connected to the signal input terminal IN, and the second terminal of the first input transistor T1 is electrically connected to the fifth node N5.

[0103] The gate of the first protection transistor T2 is electrically connected to the first power supply signal terminal VGL, the first terminal of the first protection transistor T2 is electrically connected to the fifth node N5, and the second terminal of the first protection transistor T2 is electrically connected to the first node N1.

[0104] Based on this, the first input transistor T1 can be a P-type transistor. When the first clock signal of the first clock signal terminal CK is a low-level signal, the first input transistor T1 can respond to the low-level signal and turn on, connecting the signal input terminal IN with the fifth node N5. The input signal in can be written to the fifth node N5 through the first input transistor T1.

[0105] The first protection transistor T2 can be a P-type transistor. The first power signal terminal VGL provides a first power signal vgl that is low-level. The first protection transistor T2 can respond to the first power signal vgl by being in the on state, and can transfer the potential of the fifth node N5 to the first node N1.

[0106] Because of the threshold voltage of the first protection transistor T2, the first protection transistor T2 will only be in the conducting state when the potential difference between the first power supply signal vgl and the fifth node N5 or the first node N1, which is electrically connected to the first protection transistor T2, is less than the threshold voltage of the first protection transistor T2. When this condition is not met, the first protection transistor T2 will be in the off state. In this case, the first protection transistor T2 can protect the devices electrically connected to the other node when the potential of one of the fifth node N5 or the first node N1 is abnormal. That is, as a normally open transistor, the first protection transistor T2 can temporarily maintain the potential stability of the core node when other modules experience transient failures, reducing the impact of external interference or circuit noise on the output scanning signal, and improving the overall anti-interference capability and operational reliability of the shift register G1.

[0107] like Figure 7 As shown, in some embodiments, the second input unit 12 includes: a second input transistor T3 and a second protection transistor T4.

[0108] The gate of the second input transistor T3 is electrically connected to the first clock signal terminal CK, the first terminal of the second input transistor T3 is electrically connected to the signal input terminal IN, and the second terminal of the second input transistor T3 is electrically connected to the sixth node N6.

[0109] The gate of the second protection transistor T4 is electrically connected to the first power supply signal terminal VGL, the first terminal of the second protection transistor T4 is electrically connected to the sixth node N6, and the second terminal of the second protection transistor T4 is electrically connected to the third node N3.

[0110] Based on this, the second input transistor T3 can be a P-type transistor. When the first clock signal of the first clock signal terminal CK is a low-level signal, the second input transistor T3 can respond to the low-level signal and turn on, connecting the signal input terminal IN with the sixth node N6. The input signal in can be written to the sixth node N6 through the second input transistor T3.

[0111] The second protection transistor T4 can be a P-type transistor. The first power signal terminal VGL provides a first power signal vgl that is low-level. The second protection transistor T4 can respond to the first power signal vgl by being in the on state, and can transfer the potential of the sixth node N6 to the third node N3.

[0112] Because of the threshold voltage of the second protection transistor T4, the second protection transistor T4 will only be in the conducting state when the potential difference between the first power supply signal vgl and the sixth node N6 or the first node N1, which is electrically connected to the second protection transistor T4, is less than the threshold voltage of the second protection transistor T4. If this condition is not met, the second protection transistor T4 will be in the off state. In this case, the second protection transistor T4 can protect the devices electrically connected to the other node when the potential of one of the sixth node N6 or the first node N1 is abnormal. That is, as a normally open transistor, the second protection transistor T4 can temporarily maintain the potential stability of the core node when other modules experience transient failures, reducing the impact of external interference or circuit noise on the output scanning signal, and improving the overall anti-interference capability and operational reliability of the shift register G1.

[0113] like Figure 7 As shown, in some embodiments, the voltage regulator unit 13 includes: a first voltage regulator transistor T11, a first capacitor C1, and a second voltage regulator transistor T8.

[0114] The first terminal of the first Zener transistor T11 is electrically connected to the first node N1, and the gate and second terminal of the first Zener transistor T11 are both electrically connected to the third node N3.

[0115] The gate of the second Zener transistor T8 is electrically connected to the third node N3, the first terminal of the second Zener transistor T8 is electrically connected to the second clock signal terminal XCK, and the second terminal of the second Zener transistor T8 is electrically connected to the fourth node N4.

[0116] The first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4.

[0117] It is understandable that the second Zener transistor T8 is also a P-type transistor. When the input signal in is a low-level signal and the first node N1 and the third node N3 are also at a low level, the second Zener transistor T8 can respond to the low-level signal and turn on, connecting the second clock signal terminal XCK with the fourth node N4, and writing the second clock signal xck to the fourth node N4.

[0118] Therefore, when the second clock signal xck transitions from a high level to a low level, the potential of the fourth node N4 is pulled low. Since the first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4, the potential of the third node N3 is pulled low to a level comparable to the transition of the second clock signal xck under the coupling effect of the first capacitor C1. Thus, the potential of the third node N3 can be lower than the potential of the first node N1, and the potential difference between the first node N1 and the third node N3 can keep the first Zener transistor T11 in a conducting state. Therefore, current will leak from the source of the first Zener transistor T11 (first node N1) to its drain (third node N3). Consequently, the potential of the first node N1 will decrease. In other words, the third node N3 can indirectly pull down the potential of the first node N1, so that the potential of the first node N1 will not rise over time, and the potential of the first node N1 can remain at a stable low level, thus stabilizing the potential of the first node N1. Therefore, the first node N1 can provide a continuously stable low-level signal to the first output module 30 and the second output module 40.

[0119] like Figure 7 As shown, in some embodiments, the first control module 10 further includes an auxiliary unit 14, which is electrically connected to the second node N2, the second power signal terminal VGH, and the fourth node N4. That is, when the first control module 10 is equipped with the auxiliary unit 14, the first control module 10 is also connected to the second node N2. The auxiliary unit 14 is configured to transmit the second power signal VGH to the fourth node N4 in response to the potential conduction of the second node N2.

[0120] Understandably, auxiliary unit 14 can respond to the low-level signal of the second node N2 by connecting the second power signal terminal VGH and the fourth node N4, thereby transmitting the second power signal VGH to the fourth node N4 and stabilizing the potential of the fourth node N4 at the high level of the second power signal VGH. That is, the potential of the second terminal of the second Zener transistor T8 can be stabilized at the high level of the second power signal VGH.

[0121] Therefore, this improves the stability of shift register G1 by addressing the issue of leakage current in the second Zener transistor T8 caused by the voltage of the fourth node N4 being pulled up when the potentials of the first node N1 and the third node N3 jump from low to high.

[0122] In some examples, the auxiliary unit 14 includes a third Zener transistor T7, the gate of which is electrically connected to the second node N2, the first terminal of which is electrically connected to the second power supply signal terminal VGH, and the second terminal of which is electrically connected to the fourth node N4.

[0123] Understandably, the third Zener transistor T7 can turn on in response to the low-level signal of the second node N2, connecting the second power supply signal terminal VGH and the fourth node N4. The second power supply signal VGH can be transmitted to the fourth node N4 via the third Zener transistor T7, thereby stabilizing the potential of the fourth node N4 at the high level of the second power supply signal VGH. That is, the potential of the second terminal of the second Zener transistor T8 can be stabilized at the high level of the second power supply signal VGH. This improves the leakage current problem caused by the unstable voltage at the second terminal of the second Zener transistor T8.

[0124] In some examples, the third Zener transistor T7 can be a P-type transistor. For example, the P-type transistor can be a low-temperature polysilicon (LTPS) transistor.

[0125] Figure 8 This is a schematic diagram of another shift register provided in an embodiment of the present disclosure.

[0126] like Figure 8 As shown, in some embodiments, the second control module 20 includes a first control transistor T5 and a second control transistor T6. The first control transistor T5 is an N-type transistor, and the second control transistor T6 is a P-type transistor.

[0127] The gate of the first control transistor T5 is electrically connected to the first node N1, the first terminal of the first control transistor T5 is electrically connected to the first power supply signal terminal VGL, and the second terminal of the first control transistor T5 is electrically connected to the second node N2.

[0128] The gate of the second control transistor T6 is electrically connected to the first node N1, the first terminal of the second control transistor T6 is electrically connected to the second power supply signal terminal VGH, and the second terminal of the second control transistor T6 is electrically connected to the second node N2.

[0129] Understandably, when the potential of the first node N1 is high, the first control transistor T5, being an N-type transistor, will turn on in response to the high-level signal, connecting the first power signal terminal VGL to the second node N2. The first power signal vgl of the first power signal terminal VGL will be transmitted to the second node N2 via the first control transistor T5, so that the potential of the second node N2 matches the potential of the first power signal vgl. That is, the potential of the second node N2 is low at this time. Meanwhile, the second control transistor T6, being a P-type transistor, will turn off in response to the high-level signal, disconnecting the line between the second power signal terminal VGH and the second node N2. The second power signal vgh of the second power signal terminal VGH will not be written to the second node N2.

[0130] Correspondingly, when the potential of the first node N1 is low, the second control transistor T6, being a P-type transistor, will turn on in response to the low-level signal, connecting the second power signal terminal VGH and the second node N2. The second power signal vgh of the second power signal terminal VGH can be written to the second node N2 via the second control transistor T6, so that the potential of the second node N2 matches the second power signal vgh. That is, the potential of the second node N2 is high at this time. Meanwhile, the first control transistor T5, being an N-type transistor, will turn off in response to the low-level signal, disconnecting the line between the first power signal terminal VGL and the second node N2. The first power signal vgl of the first power signal terminal VGL will not be transmitted to the second node N2.

[0131] Because the first control transistor T5 and the second control transistor T6 are of different types, at any given time, if one of the two transistors is in the on state, the other transistor will be in the off state. Therefore, the second control module 20 can precisely control the potential of the second node N2 based on the two transistors of different types.

[0132] It should be noted that, Figure 8 In the shift register G1 shown, since the first protection transistor T2 is a normally open transistor, the gate of the first control transistor T5 can be electrically connected to the first node N1 through the fifth node N5. In this case, the gate of the first control transistor T5 and the first node N1 are indirectly connected. However, in some other embodiments, the gate of the first control transistor T5 can also be directly electrically connected to the first node N1. This disclosure does not impose specific limitations on this.

[0133] Figure 9 This is a timing diagram of a shift register circuit provided in an embodiment of the present disclosure.

[0134] Combination Figure 8 and Figure 9 As shown, in some embodiments, one working cycle T of the shift register G1 includes a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.

[0135] In the first stage t1: the input signal in is high and the first clock signal ck is low.

[0136] The first input transistor T1 turns on in response to a low-level signal of the first clock signal ck, writing the input signal in to the fifth node N5. The first protection transistor T2 turns on in response to the first power supply signal vgl, transmitting the potential of the fifth node N5 to the first node N1. At this time, the potential of the first node N1 matches the potential of the input signal in, that is, the potential of the first node N1 is high. The second output transistor T14 turns off in response to a high-level potential of the first node N1, and the fourth output transistor T10 turns off in response to a high-level potential of the first node N1; and the first control transistor T5 turns on in response to a high-level potential of the first node N1 (fifth node N5), transmitting the first power supply signal vgl to the second node N2 via the first control transistor T5, so that the potential of the second node N2 matches the potential of the first power supply signal vgl, that is, the potential of the second node N2 is low at this time.

[0137] The first output transistor T13 can be turned on in response to the low level of the second node N2 (seventh node N7), and the first control signal cka can be transmitted to the first output terminal OUT1 via the first output transistor T13. Therefore, the pulse signal of the scan signal output from the first output terminal OUT1 of the shift register G1 can follow the first control signal cka.

[0138] The third output transistor T9 can be turned on in response to the low level of the second node N2, and the second power supply signal vgh can be transmitted to the second output terminal OUT2 via the third output transistor T9.

[0139] In the second stage t2: the first clock signal ck is high and the input signal in transitions from high to low.

[0140] The first input transistor T1 can be turned off (cut off) in response to a high-level signal of the first clock signal ck. At this time, the fourth capacitor C4 can maintain the potential of the first node N1, that is, the potential of the first node N1 is high. The second output transistor T14 and the fourth output transistor T10 remain off; and the second control transistor T6 can be turned off (cut off) in response to a high-level signal of the fifth node N5 (the first node N1), the first control transistor T5 can be turned on in response to a high-level signal of the first node N1, the potential of the second node N2 is low, and the third capacitor C3 will also maintain the potential of the second node N2 to keep the potential of the second node N2 at a stable low level.

[0141] The third output transistor T9 can be turned on in response to the low level of the second node N2, and the second power supply signal vgh can be transmitted to the second output terminal OUT2 via the third output transistor T9.

[0142] The first output transistor T13 can be turned on in response to the low level of the second node N2 (seventh node N7), and the first control signal cka can be transmitted to the first output terminal OUT1 via the first output transistor T13. Therefore, the pulse signal of the scan signal output from the first output terminal OUT1 of the shift register G1 can follow the first control signal cka.

[0143] It is understandable that during the first level phase (first stage t1 and second stage t2), when the potential of the second node N2 is low, the first control signal cka includes its enable pulse phase. That is, the enable pulse phase of the first control signal cka occurs within the first level phase (first stage t1 and second stage t2). Since the pulse signal of the scan signal output from the first output terminal OUT1 of the shift register G1 can follow the jump of the first control signal cka during the first stage t1 and second stage t2, and the enable pulse width of the first control signal cka is less than 1H, it is possible to achieve the output of a scan signal with an enable pulse width less than 1H from the first output terminal OUT1 of the shift register G1.

[0144] Furthermore, the falling edge of the first control signal cka occurs in the second stage t2, meaning that within the second stage t2, the first control signal cka will transition from a high level to a low level. At the moment the first control signal cka transitions from a high level to a low level, the potential of the seventh node N7 (second node N2) can be pulled low by the second capacitor C2, that is, the potential of the gate of the first output transistor T13 can be pulled low. This can compensate for the threshold loss when the first output transistor T13 outputs a low level, reducing the probability of a step in the falling edge of the scan signal output from the first output terminal OUT1. This is beneficial for improving the accuracy of the scan signal output from the shift register G1, thereby reducing the data write voltage to the transistor T (e.g., ...). Figure 3 (As shown) the probability of leakage, in order to improve the stability of the pixel driving circuit.

[0145] In the third stage t3: the input signal in is low and the first clock signal ck is low.

[0146] The first input transistor T1 turns on in response to a low-level signal of the first clock signal ck, writing the input signal in to the fifth node N5. The first protection transistor T2 turns on in response to the first power supply signal vgl, transmitting the potential of the fifth node N5 to the first node N1. At this time, the potential of the first node N1 matches the potential of the input signal in, that is, the potential of the first node N1 is low. The first control transistor T5 turns off (cut off) in response to a low-level signal of the first node N1, and the second control transistor T6 turns on in response to a low-level signal of the fifth node N5 (first node N1). The second power supply signal vgh is transmitted to the second node N2 via the second control transistor T6, so that the potential of the second node N2 matches the potential of the second power supply signal vgh, that is, the potential of the second node N2 is high at this time.

[0147] The third output transistor T9 can be turned off in response to a high-level potential of the second node N2, and the first output transistor T13 can be turned off in response to a high-level potential of the second node N2 (seventh node N7); and the second output transistor T14 can be turned on in response to a low-level potential of the first node N1, and the first power supply signal vgl can be transmitted to the first output terminal OUT1 via the second output transistor T14. Therefore, the first output terminal OUT1 of the shift register G1 can output a continuous low-level signal. The fourth output transistor T10 can be turned on in response to a low-level potential of the first node N1, and the first power supply signal vgl can be transmitted to the second output terminal OUT2 via the fourth output transistor T10.

[0148] In the fourth stage t4: the input signal in is low, the first clock signal ck is high, and the second clock signal xck jumps from high to low and then back to high.

[0149] The first input transistor T1 can be turned off (cut off) in response to a high-level signal of the first clock signal ck. At this time, the fourth capacitor C4 maintains the potential of the first node N1, that is, the potential of the first node N1 is low. The first control transistor T5 can be turned off (cut off) in response to a low-level signal of the first node N1, and the second control transistor T6 can be turned on in response to a low-level signal of the fifth node N5 (first node N1). The potential of the second node N2 is high, and the third capacitor C3 also maintains the potential of the second node N2 to keep it at a stable high level; the third output transistor T9 and the first output transistor T13 remain off. And... The second output transistor T14 can be turned on in response to a low level at the first node N1, and the first power supply signal vgl can be transmitted to the first output terminal OUT1 via the second output transistor T14. Therefore, the first output terminal OUT1 of the shift register G1 can continue to output a continuous low-level signal. The fourth output transistor T10 can be turned on in response to a low level at the first node N1, and the first power supply signal vgl can be transmitted to the second output terminal OUT2 via the fourth output transistor T10.

[0150] Furthermore, in the third stage t3, the potentials of the third node N3 and the first node N1 are both matched with the potential of the input signal in, i.e., a low-level signal. In the fourth stage t4, both input transistors are in the off state, and their respective capacitors maintain the potentials of the first node N1 and the third node N3, keeping them both at a low level. The second Zener transistor T8 can respond to the low level of the third node N3 and turn on, writing the second clock signal xck to the fourth node N4.

[0151] When the second clock signal xck transitions from a high level to a low level, the potential of the fourth node N4 is pulled low. Since the first plate of the first capacitor C1 is electrically connected to the third node N3, and the second plate of the first capacitor C1 is electrically connected to the fourth node N4, the coupling effect of the first capacitor C1 pulls the potential of the third node N3 down to a level comparable to the transition of the second clock signal xck. Therefore, the potential of the third node N3 becomes lower than the potential of the first node N1, and the potential difference between the first node N1 and the third node N3 keeps the first Zener transistor T11 in a conducting state. Consequently, current flows from the source of the first Zener transistor T11 (first node N1) to its drain (third node N3). This causes the potential of the first node N1 to decrease. In other words, the third node N3 can indirectly pull down the potential of the first node N1, so that the potential of the first node N1 will not rise over time, and the potential of the first node N1 can remain at a stable low level, thus stabilizing the potential of the first node N1. Therefore, the first node N1 can provide a continuously stable low-level signal to the first output module 30 and the second output module 40.

[0152] It should be noted that in the first stage of the next working cycle, similar to the first stage t1 of the previous working cycle, the potential of the first node N1 will jump from low to high. This will cause the first capacitor C1 to pull up the potential of the fourth node N4, which in turn will pull up the potential of the second terminal of the second Zener transistor T8, potentially causing leakage current in T8. However, during this stage, the third Zener transistor T7 will respond to the low level of the second node N2 and turn on, writing the second power supply signal vgh to the fourth node N4. The potential of the fourth node N4 can be adjusted by the second power supply signal vgh to stabilize it, thus stabilizing the potential of the second terminal of the second Zener transistor T8 and mitigating the leakage current problem.

[0153] Figure 10 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure.

[0154] Combination Figure 8 and Figure 10 As shown, in some embodiments, the display panel 100 further includes a first clock signal line CK1 and a second clock signal line CK2, wherein the signal transmitted by the first clock signal line CK1 is out of phase with the signal transmitted by the second clock signal line CK2.

[0155] In the odd-level shift register G11: the first clock signal terminal CK is electrically connected to the first clock signal line CK1, and the second clock signal terminal XCK is electrically connected to the second clock signal line CK2.

[0156] In the even-stage shift register G12: the first clock signal terminal CK is electrically connected to the second clock signal line CK2, and the second clock signal terminal XCK is electrically connected to the first clock signal line CK1.

[0157] Since the signal transmitted on the first clock signal line CK1 is out of phase with the signal transmitted on the second clock signal line CK2, the odd-level shift register G11 outputs an enable signal to drive the odd-row pixel driving circuit when the first clock signal line CK1 is low, and the even-level shift register G12 outputs an active signal to drive the even-row pixel driving circuit when the second clock signal line CK2 is low. Therefore, multiple shift registers G1 can be cascaded in the gate driving circuit G, and adjacent odd-level shift registers G11 and even-level shift registers G12 can be interlaced through the second output terminal OUT2.

[0158] In some examples, the display panel 100 also includes a first control signal line CKA1 and a second control signal line CKA2. The first control signal terminal CKA of the odd-level shift register G11 is electrically connected to the first control signal line CKA1, and the first control signal terminal CKA of the even-level shift register G12 is electrically connected to the second control signal line CKA2.

[0159] The enable pulse signal transmitted by the second control signal line CKA2 is later than the enable pulse signal of the first control signal line CKA1, so that the enable pulse stage of the first control signal cka received by the first control signal terminal CKA of each shift register G1 is in the first level stage where the potential of the corresponding second node N2 is the first level, so that the first output terminal OUT1 of each shift register G1 can output a complete scan signal with a pulse width of less than 1H.

[0160] In addition, in some examples, the display panel 100 also includes a first power signal line VGL1 and a second power signal line VGH1, wherein the first power signal terminal VGL of each shift register G1 is electrically connected to the first power signal line VGL1, and the second power signal terminal VGH of each shift register G1 is electrically connected to the second power signal line VGH1.

[0161] Some embodiments of this disclosure provide a display device. Figure 11 This is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure.

[0162] like Figure 11 As shown, the display device 200 is a product with image display capabilities (including still images or moving images, where moving images can be video). For example, the display device 200 can be any of the following: monitor, television set, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall display, home appliance, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), monitor, etc.

[0163] like Figure 11 As shown, the display device 200 includes the display panel 100 provided in any of the above embodiments. Therefore, the display device 200 provided in this disclosure has all the beneficial effects of the display panel 100 provided in any of the above embodiments, which will not be elaborated here.

[0164] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0165] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Pixel driving circuits with multiple arrays arranged; The gate drive circuit includes multiple cascaded shift registers; The shift register includes: a first control module, a second control module, a first output module, and a second output module; The first control module is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, and the first node, respectively. The first control module is configured to control the potential of the first node according to the first clock signal provided by the first clock signal terminal, the second clock signal provided by the second clock signal terminal, and the input signal provided by the signal input terminal. The second control module is electrically connected to the first node, the first power signal terminal, the second power signal terminal, and the second node, respectively; the second control module is configured to control the potential of the second node according to the potential of the first node, the first power signal provided by the first power signal terminal, and the second power signal provided by the second power signal terminal. The first output module is electrically connected to the first node, the second node, the first power signal terminal, the first control signal terminal, and the first output terminal, respectively. The first output module is configured to transmit the first power signal or the first control signal provided by the first control signal terminal to the first output terminal according to the potential of the first node and the potential of the second node. The second output module is electrically connected to the first node, the second node, the first power signal terminal, the second power signal terminal, and the second output terminal, respectively. The second output module is configured to transmit the first power signal or the second power signal to the second output terminal according to the potential of the first node and the potential of the second node. The second output terminal of the nth-stage shift register is electrically connected to the signal input terminal of the (n+1)th-stage shift register; the first output terminal of the nth-stage shift register is electrically connected to the data write transistor of the pixel driving circuit in the nth row; the enable pulse width of the first control signal is less than the row scanning duration of the display panel; n is a positive integer.

2. The display panel according to claim 1, characterized in that, The potential of the second node is at the first level stage of the first level, which covers the enable pulse stage of the first control signal; The first level is configured to control the second output module to transmit the first control signal to the first output terminal.

3. The display panel according to claim 1, characterized in that, The first control module includes: The first input unit is electrically connected to the signal input terminal, the first clock signal terminal, and the first node, respectively; the first input unit is configured to transmit the input signal to the first node in response to the first clock signal being turned on. The second input unit is electrically connected to the signal input terminal, the first clock signal terminal, and the third node, respectively; the second input unit is configured to transmit the input signal to the third node in response to the first clock signal being turned on. A voltage regulator unit is electrically connected to the first node, the third node, and the second clock signal terminal, respectively. The voltage regulator unit is configured to: respond to the voltage turn-on of the third node, write the second clock signal into the third node, and adjust the potential of the first node.

4. The display panel according to claim 3, characterized in that, The voltage stabilizing unit includes: A first Zener transistor, wherein the first terminal of the first Zener transistor is electrically connected to the first node, and the gate and the second terminal of the first Zener transistor are both electrically connected to the third node; A first capacitor, wherein the first plate of the first capacitor is electrically connected to the third node, and the second plate of the first capacitor is electrically connected to the fourth node; The second Zener transistor has its gate electrically connected to the third node, its first terminal electrically connected to the second clock signal terminal, and its second terminal electrically connected to the fourth node.

5. The display panel according to claim 4, characterized in that, The first control module further includes: An auxiliary unit is electrically connected to the second node, the second power signal terminal, and the fourth node, respectively; the auxiliary unit is configured to transmit the second power signal to the fourth node in response to the potential conduction of the second node.

6. The display panel according to claim 3, characterized in that, The first input unit includes: The first input transistor has its gate electrically connected to the first clock signal terminal, its first terminal electrically connected to the signal input terminal, and its second terminal electrically connected to the fifth node. The first protection transistor has its gate electrically connected to the first power supply signal terminal, its first electrode electrically connected to the fifth node, and its second electrode electrically connected to the first node.

7. The display panel according to claim 3, characterized in that, The second input unit includes: The second input transistor has its gate electrically connected to the first clock signal terminal, its first terminal electrically connected to the signal input terminal, and its second terminal electrically connected to the sixth node. The second protection transistor has its gate electrically connected to the first power signal terminal, its first terminal electrically connected to the sixth node, and its second terminal electrically connected to the third node.

8. The display panel according to claim 1, characterized in that, The second control module includes: A first control transistor, wherein the gate of the first control transistor is electrically connected to the first node, the first terminal of the first control transistor is electrically connected to the first power signal terminal, and the second terminal of the first control transistor is electrically connected to the second node; The second control transistor has its gate electrically connected to the first node, its first terminal electrically connected to the second power signal terminal, and its second terminal electrically connected to the second node. The first control transistor is an N-type transistor, and the second control transistor is a P-type transistor.

9. The display panel according to claim 1, characterized in that, The first output module includes: The first output transistor has its gate electrically connected to the second node, its first terminal electrically connected to the first control signal terminal, and its second terminal electrically connected to the first output terminal. The second capacitor has its first plate electrically connected to the gate of the first output transistor, and its second plate electrically connected to the first output terminal. The second output transistor has its gate electrically connected to the first node, its first terminal electrically connected to the first power signal terminal, and its second terminal electrically connected to the first output terminal.

10. The display panel according to claim 9, characterized in that, The first output module further includes: The third protection transistor has its gate electrically connected to the first power signal terminal, its first terminal electrically connected to the second node, and its second terminal electrically connected to the gate of the first output transistor.

11. The display panel according to claim 1, characterized in that, The second output module includes: The third output transistor has its gate electrically connected to the second node, its first terminal electrically connected to the second power signal terminal, and its second terminal electrically connected to the second output terminal. The third capacitor has its first plate electrically connected to the second node and its second plate electrically connected to the second power signal terminal. The fourth output transistor has its gate electrically connected to the first node, its first terminal electrically connected to the first power signal terminal, and its second terminal electrically connected to the second output terminal. The fourth capacitor has its first plate electrically connected to the first node and its second plate electrically connected to the second output terminal.

12. The display panel according to claim 1, characterized in that, The display panel further includes a first clock signal line and a second clock signal line, wherein the signal transmitted by the first clock signal line is out of phase with the signal transmitted by the second clock signal line. In the odd-level shift register: the first clock signal terminal is electrically connected to the first clock signal line, and the second clock signal terminal is electrically connected to the second clock signal line; In the even-numbered shift registers: the first clock signal terminal is electrically connected to the second clock signal line, and the second clock signal terminal is electrically connected to the first clock signal line.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 12.

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