Single-line chain communication system and synchronous feedback method of returned information thereof

Abstract

The invention discloses a single-wire chain type communication system which comprises a main controller and a plurality of single-wire communication links, each single-wire communication link is formed by connecting a plurality of driving chips in series, and the last driving chip at the last position in each single-wire communication link is provided with a preset synchronizing signal input port. The synchronizing signal input ports of the last driving chips of all the single-line communication links are connected to the same signal line, and the signal line is connected to the synchronizing signal output port of the main controller; the main controller controls the synchronizing signal input port to output a synchronizing signal within a time period between a previous data frame and a next data frame of driving data, and when the last driving chip of each single-line communication link receives the synchronizing signal, the synchronizing signal is output by the synchronizing signal input port. And if so, starting to transmit the return information to the main controller through the single-line communication link in a reverse direction.

Description

Technical Field

[0001] This invention relates to the field of single-bus communication technology, and in particular to a single-wire chain communication system and a synchronous feedback method for transmitting back information. Background Technology

[0002] With the development of display technology, Mini-LED, OLED, and Micro-LED displays have gradually become the three main directions of display technology development, building upon traditional LCD displays. However, OLED display technology is limited by material characteristics, and the pixel ablation problem remains difficult to solve. Micro-LED technology still needs to improve the efficiency of mass transfer technology to make it more cost-effective for large-size displays. Therefore, currently, LCD displays using direct-lit Mini-LED backlight panels are the best display solution. A direct-lit Mini-LED backlight panel refers to a high-density LED array composed of even finer Mini LED beads (smaller than 100 micrometers in size), and the entire backlight panel can be divided into multiple backlight zones, with the number of LEDs in each zone increasing from tens to hundreds or even thousands compared to traditional LEDs. Therefore, how to drive and control the large number of Mini LED beads to better match the display of the LCD panel becomes the core issue in the application of Mini-LED backlight panels.

[0003] like Figure 1 As shown, in existing single-wire bus LED driving systems, the LED driver chip has two bidirectional input / output ports. When one is set as the input port Din, the other is automatically set as the output port Dout. Chips are serially connected via the Din / Dout ports; that is, the output port Dout of the preceding chip is connected to the input port Din of the following chip. The host computer backlight controller (BCON) inputs a signal to the input port Din of the first chip and then transmits data to subsequent chips sequentially in a serial manner. Furthermore, in current mini-LED applications, due to the increasing number of backlight zones, a large number of LED driver chips are required. To simplify physical connections, the aforementioned chain structure is often used. The backlight controller (BCON) is typically a dedicated control chip or an FPGA. Each chain operates in half-duplex mode. When the BCON sends configuration frames or brightness information, all chains can send them simultaneously. However, when all chains return information, due to the inevitable differences between the chips in each chain, the chains cannot return data synchronously, resulting in delays between chains. For these reasons, the BCON cannot use a single set of control logic to synchronously sample data from all channels.

[0004] Therefore, it is evident that there is a need for a new single-line chain communication system and a synchronous feedback method for its return information in the existing technology, so that each single-line communication chain can simultaneously return information. Summary of the Invention

[0005] The technical objective of this invention is to provide a single-line chain communication system and a synchronous feedback method for its return information, so that each single-line communication chain can simultaneously feed back information, thereby enabling the backlight controller BCON to process the return information simultaneously with a simple and unified signal processing logic.

[0006] Based on the above technical objectives, the present invention provides a single-line chain communication system, which includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a first data transmission port and a second data transmission port. The single-line communication link refers to the connection between the second data transmission port of each driver chip and the first data transmission port of the next adjacent driver chip. The first data transmission port of the first driver chip in the drive link is connected to the drive data signal output port of the main controller.

[0007] Each single-line communication link has a predetermined synchronization signal input port for the last driver chip at the end of the link, and the synchronization signal input ports of all single-line communication link last driver chips are connected to the same signal line, which is connected to the synchronization signal output port of the main controller.

[0008] The main controller controls the synchronization signal input port to output a synchronization signal during the time period between the previous data frame and the next data frame of the driving data. When the last driver chip of each single-line communication link receives the synchronization signal, it starts to transmit the feedback information back to the main controller in reverse through the single-line communication link.

[0009] In one embodiment, the feedback information refers to the driver chip's operating status information, which is written into the data frame by the driver chip on the single-line communication link and needs to be fed back to the main controller during the transmission of driver data on a single-line link.

[0010] In one embodiment, the returned information is overvoltage information, undervoltage information, temperature information, or error information.

[0011] In one embodiment, the synchronization signal input port is the second data transmission port of the last bit driver chip.

[0012] Based on the above technical objectives, the present invention also provides another single-line chain communication system, which includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a first data transmission port and a second data transmission port. The single-line communication link refers to the connection between the second data transmission port of each driver chip and the first data transmission port of the next adjacent driver chip. The first data transmission port of the first driver chip in the drive link is connected to the drive data signal output port of the main controller.

[0013] The last driver chip in each single-line communication link is equipped with a predetermined synchronization signal input / output port, and the synchronization signal input / output ports of the last driver chips in all single-line communication links are connected to the same open-drain circuit control bus.

[0014] The synchronization signal input / output port of the last bit driver chip is in the first state when the last bit driver chip does not transmit back information.

[0015] When one of the last-bit driver chips needs to transmit back information, the last-bit driver chip starts a fixed-duration delay timer, and after the timer ends, the synchronization signal input / output port of the last-bit driver chip is changed to the second state.

[0016] When the open-drain circuit control bus changes to the second state, all last-bit chips simultaneously start transmitting back information.

[0017] In one embodiment, the first state is a high-impedance state or a low-level state, and the second state is a low-level state or a high-impedance state corresponding to the first state.

[0018] In one embodiment, the feedback information refers to the driver chip's operating status information, which is written into the data frame by the driver chip on the single-line communication link and needs to be fed back to the main controller during the transmission of driver data on a single-line link.

[0019] In one embodiment, the returned information is overvoltage information, undervoltage information, temperature information, or error information.

[0020] In one embodiment, the synchronization signal input port is the second data transmission port of the last bit driver chip.

[0021] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0022] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with the embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0023] Figure 1 This is a schematic diagram of a single-line chain communication system in the prior art;

[0024] Figure 2 This is a schematic diagram of the single-line chain communication system structure according to the first embodiment of the present invention;

[0025] Figure 3 This is a schematic diagram of a single-line chain communication system according to the second embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention.

[0028] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] Example 1

[0031] like Figure 2 As shown, the single-line chain communication system of this embodiment includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a first data transmission port and a second data transmission port. The single-line communication link means that the first data transmission port of each driver chip is connected to the second data transmission port of the driver chip in the preceding stage adjacent to the driver chip, and the second data transmission port of each driver chip is connected to the first data transmission port of the driver chip in the following stage adjacent to the driver chip. The first and second driver chips in the drive link are connected to the drive data signal output port of the main controller.

[0032] Each of the driver chips has multiple driver channel pins, which are used to connect to the light-emitting element to control the light-emitting element to emit light.

[0033] In this embodiment, the last driver chip in each single-line communication link is equipped with a predetermined synchronization signal input port, and the synchronization signal input ports of all the last driver chips in the single-line communication links are connected to the same signal line, which is connected to the synchronization signal output port of the main controller. The main controller, based on the timing of the drive data output from the drive data signal output port, controls the synchronization signal input port to output a synchronization signal during the time interval between the previous and next data frames. When the last driver chip in each single-line communication link receives the synchronization signal, it initiates the transmission of feedback information back to the main controller via the single-line communication link in reverse phase. That is, the single-line communication link in this invention uses a half-duplex mode for data communication. The drive data of the driver chip is transmitted from the main controller to the last driver chip, while the transmission method from the last driver chip to the main controller is used to transmit feedback information.

[0034] In this invention, the feedback information refers to the driver chip's operating status information, written into the data frame by the driver chip on the single-line communication link and required to be fed back to the main controller during the transmission of driver data via a single-line link. Examples include overvoltage / undervoltage information, temperature information, and error information.

[0035] In this invention, the drive data or feedback information is transmitted using a pass-through transmission method. This pass-through transmission means that each driver chip, upon receiving data from the previous stage, does not wait for all data frames to be received and processed before transmitting the data frame to the next stage driver chip. Instead, it synchronously transmits each data bit of the received data frame to the next driver chip through the output port in real time. That is, when the input port receives a bit of data, that bit of data is transmitted to the next driver chip through the output port in real time.

[0036] In this embodiment, the predetermined synchronization signal input port of the last driver chip in each single-line communication link can use the first or second data transmission port of the last driver chip as the synchronization signal input port.

[0037] Example 2

[0038] like Figure 3As shown, the single-line chain communication system of this embodiment includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a first data transmission port and a second data transmission port. The single-line communication link means that the first data transmission port of each driver chip is connected to the second data transmission port of the driver chip in the preceding stage adjacent to the driver chip, and the second data transmission port of each driver chip is connected to the first data transmission port of the driver chip in the following stage adjacent to the driver chip. The first and second driver chips in the drive link are connected to the drive data signal output port of the main controller.

[0039] Each of the driver chips has multiple driver channel pins, which are used to connect to the light-emitting element to control the light-emitting element to emit light.

[0040] In this embodiment, the last driver chip in each single-line communication link is equipped with a predetermined synchronization signal input / output port, and the synchronization signal input / output ports of all the last driver chips in the single-line communication links are connected to the same open-drain circuit control bus. When the last driver chip is not transmitting feedback information, its synchronization signal input / output port is in a first state, which is either a high-impedance state or a low-level state. When one of the last driver chips in the multiple single-line communication links needs to transmit feedback information, that last driver chip starts a fixed-duration delay timer, and after the timer expires, changes its synchronization signal input / output port to a second state, which is either a low-level state or a high-impedance state corresponding to the first state. That is, when the first state is high-impedance, the second state is low-level; and when the first state is low-level, the second state is high-impedance. All last driver chips start transmitting feedback information according to the second state they receive.

[0041] According to the above control logic, when the first state is high impedance and the second state is low, the synchronization signal input / output port is in a high impedance state when no feedback information is transmitted on any single-wire communication link. When the first driver chip among the multiple last-bit driver chips completes its preparation for feedback information transmission and wants to transmit it, the first driver chip starts a delay timer. When the timer expires, the first driver chip pulls the synchronization signal input / output port low. Simultaneously, the synchronization signal input / output ports of all last-bit driver chips are pulled low to the second state, and feedback information transmission is started simultaneously. That is, the last-bit driver chip triggers feedback information transmission based on the falling edge of the synchronization signal input / output port. The duration of the delay timer ensures that each last-bit driver chip is ready to begin feedback information transmission.

[0042] When the first state is low and the second state is high impedance, the synchronization signal input / output port is low when no feedback information is transmitted on any single-wire communication link. When the first driver chip among the multiple last-bit driver chips completes its preparation for feedback information transmission and wants to transmit it, it starts a delay timer. When the timer expires, the first driver chip pulls the synchronization signal input / output port high to the high impedance state. When the last last-bit driver chip pulls its synchronization signal input / output port high to the high impedance state, it triggers all last-bit driver chips to pull their synchronization signal input / output ports high to the high impedance state. Simultaneously, all last-bit driver chips start feedback information transmission. That is, the last-bit driver chip triggers feedback information transmission based on the rising edge of the synchronization signal input / output port.

[0043] That is, the single-line communication link described in this invention uses a half-duplex mode for data communication. The drive data of the drive chip is transmitted from the main controller to the last drive chip, while the transmission method from the last drive chip to the main controller is used to transmit return information.

[0044] In this invention, the feedback information refers to the driver chip's operating status information, written into the data frame by the driver chip on the single-line communication link and required to be fed back to the main controller during the transmission of driver data via a single-line link. Examples include overvoltage / undervoltage information, temperature information, and error information.

[0045] In this invention, the drive data or feedback information is transmitted using a pass-through transmission method. This pass-through transmission means that each driver chip, upon receiving data from the previous stage, does not wait for all data frames to be received and processed before transmitting the data frame to the next stage driver chip. Instead, it synchronously transmits each data bit of the received data frame to the next driver chip through the output port in real time. That is, when the input port receives a bit of data, that bit of data is transmitted to the next driver chip through the output port in real time.

[0046] In this embodiment, the predetermined synchronization signal input port of the last driver chip in each single-line communication link can use the first or second data transmission port of the last driver chip as the synchronization signal input port.

[0047] In this embodiment, the open-drain circuit can be an external open-drain circuit of the driver chip, or the open-drain circuit can be set inside the driver chip.

[0048] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A single-wire chain communication system, characterized in that: The single-line chain communication system includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a first data transmission port and a second data transmission port. The single-line communication link means that the second data transmission port of each driver chip is connected to the first data transmission port of the next adjacent driver chip. The first data transmission port of the first driver chip in the drive link is connected to the drive data signal output port of the main controller. Each single-line communication link has a predetermined synchronization signal input port for the last driver chip at the end of the link, and the synchronization signal input ports of all single-line communication link last driver chips are connected to the same signal line, which is connected to the synchronization signal output port of the main controller. The main controller controls the synchronization signal input port to output a synchronization signal during the time period between the previous data frame and the next data frame of the driving data. When the last driver chip of each single-line communication link receives the synchronization signal, it starts to transmit the feedback information back to the main controller in reverse through the single-line communication link.

2. The single-line chain communication system according to claim 1, characterized in that, The feedback information refers to the driver chip's operating status information, which is written into the data frame by the driver chip on the single-line communication link and needs to be fed back to the main controller during the transmission of driver data on the single-line link.

3. The single-line chain communication system according to claim 2, characterized in that, The returned information is overvoltage information, undervoltage information, temperature information, or error information.

4. The single-line chain communication system according to claim 1, characterized in that, The synchronization signal input port is the second data transmission port of the last bit driver chip.

5. A single-wire chain communication system, characterized in that: The single-line chain communication system includes a main controller and multiple single-line communication links. Each single-line communication link is composed of multiple driver chips connected in series. Each driver chip is provided with a first data transmission port and a second data transmission port. The single-line communication link means that the second data transmission port of each driver chip is connected to the first data transmission port of the next adjacent driver chip. The first data transmission port of the first driver chip in the drive link is connected to the drive data signal output port of the main controller. The last driver chip in each single-line communication link is equipped with a predetermined synchronization signal input / output port, and the synchronization signal input / output ports of the last driver chips in all single-line communication links are connected to the same open-drain circuit control bus. The synchronization signal input / output port of the last bit driver chip is in the first state when the last bit driver chip does not transmit back information. When one of the last-bit driver chips needs to transmit back information, the last-bit driver chip starts a fixed-duration delay timer, and after the timer ends, the synchronization signal input / output port of the last-bit driver chip is changed to the second state. When the open-drain circuit control bus changes to the second state, all last-bit chips simultaneously start transmitting back information.

6. The single-line chain communication system according to claim 5, characterized in that, The first state is a high-impedance state or a low-level state, and the second state is a low-level state or a high-impedance state corresponding to the first state.

7. The single-line chain communication system according to claim 5, characterized in that, The feedback information refers to the driver chip's operating status information, which is written into the data frame by the driver chip on the single-line communication link and needs to be fed back to the main controller during the transmission of driver data on the single-line link.

8. The single-line chain communication system according to claim 7, characterized in that, The returned information is overvoltage information, undervoltage information, temperature information, or error information.

9. The single-line chain communication system according to claim 5, characterized in that, The synchronization signal input port is the second data transmission port of the last bit driver chip.

10. An LED backlight panel, characterized in that, The LED backlight panel uses a single-wire chain communication system as described in any one of claims 1-9 to control the LED driver chip.

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