Component waveform architecture for communication signal simulation and simulation method

Abstract

The invention provides a modularized waveform architecture for communication signal simulation and a simulation method, relates to the technical field of communication countermeasure testing, and solves various limitation problems of a traditional special hardware platform in communication signal simulation. In the architecture, an information source scrambling component receives data to be modulated and performs scrambling processing on the data to be modulated; the channel coding component selects a corresponding coding mode to perform coding processing according to the parameter instruction; the group hopping frame assembly adds a synchronous code to the encoded data to realize framing, converts the framed data according to a corresponding hopping structure in a frequency hopping mode, and outputs the data; the spread spectrum component performs data expansion according to a spread spectrum multiple parameter value issued by configuration and then outputs the data; and the variable rate modulation assembly selects a corresponding modulation mode according to the parameter instruction to complete modulation mapping of symbols, and outputs obtained communication signals after rate control and filtering processing. According to the invention, advantages and effects of waveform dynamic generation and parameter real-time adjustment are smoothly realized.

Description

Technical Field

[0001] This invention relates to the field of communication countermeasures testing technology, and specifically to a componentized waveform architecture and simulation method for communication signal simulation. Background Technology

[0002] Accurate simulation technology of communication signal waveforms plays a crucial role in numerous fields, including the research and development verification of communication systems, performance testing of communication equipment, and communication countermeasures drills. These applications typically have stringent requirements for the fidelity, controllability, and response speed of analog signals. To meet these demands, traditional technical approaches primarily rely on dedicated hardware platforms. The core design concept of these hardware platforms is customized development for specific communication waveform systems, such as designing hardware circuits and signal processing flows specifically for a particular modulation method or coding standard. This dedicated approach met basic testing needs at a specific historical stage.

[0003] However, with the rapid development of modern communication technology, communication waveform systems are becoming increasingly diversified, with new modulation / desampling, encoding methods, and transmission protocols emerging one after another. Simultaneously, practical application scenarios are placing higher demands on the flexibility, adaptability, and efficiency of communication signal simulation. Against this backdrop, the inherent limitations of traditional dedicated hardware platforms are becoming increasingly apparent. Each waveform system requires a separate dedicated hardware device, leading not only to significant idle and wasted hardware resources but also to high overall system construction and maintenance costs. When testing requirements change, necessitating switching or adding waveform systems, the entire process involves multiple steps such as hardware replacement, firmware flashing, and system integration, which is time-consuming and cannot adapt to rapidly changing testing environments. Traditional fixed hardware architectures struggle to achieve dynamic waveform reconstruction or real-time online parameter adjustment during system operation, severely limiting testing flexibility and efficiency. Furthermore, a single hardware platform typically only supports a limited number of waveform systems, making it difficult to effectively support complex testing tasks involving multiple standards and scenarios. These factors collectively constrain the application effectiveness of communication signal simulation technology in broader and more complex scenarios.

[0004] Faced with these challenges, the industry has been exploring better solutions. These attempts include increasing limited software configurability on traditional hardware platforms or using general-purpose processors for software simulation. While the former can alleviate the lack of flexibility to some extent, it is still essentially within the framework of hardware customization, and its reconfiguration capabilities and multi-standard support remain weak. The latter, while possessing higher versatility, often struggles to meet the demanding requirements of communication signal simulation in terms of real-time performance, processing efficiency, and signal fidelity.

[0005] Therefore, how to break through the constraints of traditional hardware architecture and achieve efficient, flexible, and dynamic generation and adjustment of communication waveforms while maintaining or improving signal generation quality and real-time performance, and possessing strong multi-standard compatibility, has become a key issue that urgently needs to be addressed in the field of communication signal analog technology. This urgently requires a completely new technical approach that can fundamentally improve the adaptability and efficiency of communication signal analog systems. Summary of the Invention

[0006] The purpose of this invention is to address the problems of low hardware resource utilization, low waveform switching efficiency, poor parameter adjustment flexibility, and insufficient compatibility among multiple waveforms in traditional dedicated hardware platforms for communication signal simulation. Therefore, this invention proposes a component-based waveform architecture and simulation method for communication signal simulation. Based on the concept of software-defined waveforms and component-based design, this invention decomposes the core communication module into multiple functional unit components with "standardized interfaces and configurable parameters," achieving the advantages of dynamic waveform generation and real-time parameter adjustment.

[0007] The present invention employs the following technical solutions to achieve its objective: A modular waveform architecture for communication signal simulation includes multiple functional components connected in series. During communication signal simulation, configuration parameters are sent to the configuration interfaces of each functional component via waveform configuration commands, and finally, the communication signal completing the baseband modulation process is output. The functional components in this architecture are as follows: A source scrambling component is used to receive data to be modulated and scramble it. The channel coding component is used to receive scrambled data and select the corresponding coding mode for encoding processing according to the parameter instructions; The frame hopping component is used to add synchronization codes to the encoded data to achieve frame hopping, and to output the framed data according to the corresponding hopping structure in frequency hopping mode. The spread spectrum component is used to receive the data after group frame skipping processing, expand the data according to the spread spectrum multiple parameter value issued by the configuration, and then output it. The variable rate modulation component is used to receive the data after spread spectrum processing, select the corresponding modulation mode according to the parameter command to complete the modulation mapping of symbols, and then output the communication signal after rate control and filtering, thus completing the entire baseband modulation process.

[0008] Preferably, the source scrambling component generates a scrambling code internally according to the corresponding parameter configuration, and uses this scrambling code to scramble the input data it receives. The scrambling code is generated using a 15th-order polynomial, and the initial value of the register corresponding to the scrambling code and the setting of the generator polynomial are both completed after configuring the source scrambling component through the corresponding interface. When configuring the generator polynomial interface for the scrambling code for the source scrambling component, the input sequence is 1100000000000001. The source scrambling component is also used to transmit the scrambled data it outputs to the channel coding component.

[0009] Preferably, the data received by the channel coding component is a bit stream in 0 and 1 format, and is encoded according to a preset code rate; the parameter interface of the channel coding component includes clock, reset, coding mode, coding rate, coding polynomial and coding packet length, and the various encoders embedded in it are configured through the various parameter interfaces; The channel coding component is used to select the coding mode as 3Gpp Turbo coding or RS coding under the constraints of parameter instructions; wherein, the 3Gpp Turbo encoder corresponding to 3Gpp Turbo coding consists of an interleaver and two component encoders; one component encoder performs convolutional coding on the original input bit data, and the other component encoder performs convolutional coding on the interleaved bit data.

[0010] Preferably, the parameter interface of the group hopping frame component includes clock, reset, group hopping parameters, group hopping parameters, and PN code; the group hopping frame component is used to customize the hopping structure according to the changes in the group hopping parameters, and realize the group hopping processing of the input data, including: converting the power rise / fall time and frequency switching time into information length, filling random information of the corresponding information length during the power rise / fall time, filling input information of the corresponding information length during the effective signal time, and repeating the cycle until the number of group hoppings accumulates to the preset service hopping number and then ends; The framing parameters include the preset PN code length, the custom PN code, and the input data length. The PN code is obtained through local preset or custom distribution. When framing, the frame skipping component first outputs the locally preset or custom distributed PN code, and then outputs the framed information.

[0011] Preferably, the data received by the spreading component is a bit stream in 01 format. The spreading component is used to expand the input 01 bit information according to a pseudo-random sequence with a preset spreading factor and then output it. The parameter interface of the spreading component includes clock, reset, spreading factor and spreading code. The spreading code is stored in the component in a custom manner. The spread spectrum component is also used to store the input 01 bit information into the buffer, read out the information data of the preset size, read the spread spectrum code according to the spread spectrum code length, perform modulo-2 operation processing and output it until the buffer is empty; if the spread spectrum multiple parameter value received by the spread spectrum component is 1, it means that no spread spectrum processing is performed and the corresponding information data is directly transmitted.

[0012] Preferably, the parameter interface of the variable rate modulation component includes clock, reset, modulation type and modulation control parameters; the variable rate modulation component modulates and maps the data from the spread spectrum component under the corresponding modulation type, and performs rate control on the modulated information to complete the variable rate processing, and finally outputs according to the symbol rate, thereby completing the baseband modulation process; When the variable rate modulation component performs rate control processing, the modulation output information of FSK / 4FSK / 8FSK is output after the rate is mapped to the frequency control word to control the DDS, while other modulation types are output after being processed by the variable rate filter. The variable rate filter is based on a fractional shaping filter, which is used to adjust the fractional interpolation factor in real time according to the operating clock and the baseband signal data rate, so that the output data rate after shaping and filtering is consistent with the operating clock.

[0013] This invention also provides a communication signal simulation method based on the aforementioned componentized waveform architecture, the method comprising the following steps: S1. Acquire the data to be modulated and scramble it; S2. Select the corresponding encoding mode according to the parameter instructions, and encode the scrambled data. S3. Add synchronization codes to the encoded data to achieve framing, and in frequency hopping mode, output the framed data after conversion according to the corresponding hop structure; S4. After receiving the data from the frame skipping process, expand the data according to the spread spectrum multiple parameter value issued by the configuration and then output it. S5. Receive the spread spectrum processed data, select the corresponding modulation mode according to the parameter command to complete the symbol modulation mapping, and output the obtained communication signal after rate control and filtering, thus completing the entire baseband modulation process.

[0014] In summary, due to the adoption of this technical solution, the beneficial effects of this invention are as follows: This invention significantly improves the flexibility and efficiency of communication signal simulation. Through a modular waveform architecture, it enables the efficient generation of communication signals of various waveform types on a single general-purpose hardware platform, effectively overcoming the problem of traditional solutions requiring dedicated hardware for different waveform types. This not only drastically reduces the types and number of hardware devices, lowering system construction and maintenance costs, but also significantly shortens the time required for waveform switching, solving the problem of lengthy refactoring processes caused by the need to recompile hardware logic.

[0015] Thanks to the modular design of its core functional modules, this invention possesses strong dynamic parameter configuration capabilities. Users can adjust the parameters of core processing units such as source scrambling, channel coding, spreading, framing or hopping, and variable-rate modulation in real time according to actual application requirements. This flexibility supports the instant configuration and updating of key parameters such as the scrambling code generator polynomial, coding generator polynomial, synchronization code sequence, PN code sequence, and spreading pseudo-random sequence. Simultaneously, this invention can dynamically adjust the hopping structure based on parameters such as hopping rate, code rate, and duty cycle, and supports the dynamic selection of different coding and modulation modes, enabling flexible switching through a unified interface.

[0016] In terms of signal processing, this invention achieves a highly efficient and consistent processing mechanism. Regardless of the modulation method used, the modulation process can be performed within the same clock domain. By employing fractional shaping filtering technology, the system can output the mapped result according to the specified symbol rate, ensuring the quality and timing accuracy of signal generation. This design enables the generalized use of hardware resources and a lightweight development process, significantly shortening the development cycle, improving deployment efficiency, and providing an efficient, convenient, and cost-optimized solution for the testing and verification of various communication systems. Attached Figure Description

[0017] The present invention is further described in detail with reference to the following figures, which include eight figures as follows: Figure 1 This is a schematic diagram of the overall structure of the componentized waveform architecture of the present invention; Figure 2 This is a schematic diagram of the data transmission process and corresponding component interfaces of the architecture of this invention; Figure 3 This is a schematic diagram of the 3Gpp Turbo encoder in the architecture of this invention; Figure 4 This is a schematic diagram of the internal structure of the component encoder in the architecture of this invention; Figure 5 This is a schematic diagram of the jump structure applied to the group jump frame component in the architecture of this invention; Figure 6 This is a schematic diagram of the frame structure applied by the group skipping frame component in the architecture of this invention; Figure 7 This is a schematic diagram of the network structure of the fractional-multiplier shaping filter in the architecture of this invention; Figure 8 This is a schematic diagram of the overall implementation architecture of the present invention under software application control. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] Example 1 A modular waveform architecture for communication signal simulation, which employs a modular design and allows for simultaneous reference. Figure 1 This is a schematic diagram. The architecture includes multiple functional components connected in series. When simulating communication signals, various configuration parameters are sent to the configuration interfaces of each functional component via waveform configuration commands, and finally, the communication signal completing the baseband modulation process is output. In this embodiment, the functional components of the architecture are as follows: A source scrambling component is used to receive data to be modulated and scramble it. The channel coding component is used to receive scrambled data and select the corresponding coding mode for encoding processing according to the parameter instructions; The frame hopping component is used to add synchronization codes to the encoded data to achieve frame hopping, and to output the framed data according to the corresponding hopping structure in frequency hopping mode. The spread spectrum component is used to receive the data after group frame skipping processing, expand the data according to the spread spectrum multiple parameter value issued by the configuration, and then output it. The variable rate modulation component is used to receive the data after spread spectrum processing, select the corresponding modulation mode according to the parameter command to complete the modulation mapping of symbols, and then output the communication signal after rate control and filtering, thus completing the entire baseband modulation process.

[0021] This embodiment adopts the design principles of modular decomposition, standardized interfaces, and on-demand combination. It encapsulates all the key core modules of the communication system channel, namely source scrambling, channel coding, frame grouping (hopping), spread spectrum and modulation, into independent functional components, and the components are connected in series.

[0022] When a communication signal simulation is completed, various parameters are sent to the interfaces of each component via waveform configuration commands. The data to be modulated into baseband is first input to the source scrambling component for scrambling. After scrambling, the output data is connected to the channel coding component. The corresponding coding mode is selected according to the parameter command to encode the input data. If the simulated waveform does not require encoding, the data can be directly passed through. The data output by the channel coding component is framed by adding synchronization codes. In frequency hopping mode, the framed data is converted according to the corresponding hop structure and then output. The framing and hopping parameters can be defined as needed. The grouped (hopped) data is input to the spread spectrum component, which expands the data according to the spread factor parameter value sent by the configuration and then outputs it. The output data is connected to the variable rate modulation component interface. The corresponding modulation mode is selected according to the parameter command to complete the symbol modulation mapping. After rate control and filtering, the entire baseband modulation process is completed and output.

[0023] In this embodiment, the data transmission process and corresponding component interfaces of the source scrambling component, channel coding component, group frame skipping component, spreading component, and variable rate modulation component of the architecture are as follows: Figure 2 As shown, this is a complete representation of the baseband modulation process of the waveform.

[0024] Example 2 Based on Example 1, this example introduces the details and preferred design of its componentized waveform architecture.

[0025] First, the source scrambling component generates a scrambling code internally according to the corresponding parameter configuration, and uses this scrambling code to scramble the received input data. The scrambling code is generated using a 15th-order polynomial, and the initial value of the scrambling code's corresponding register and the setting of the generator polynomial are both completed after configuring the source scrambling component through the corresponding interface. The generator polynomial of the scrambling code... as follows:

[0026] In the formula, It is a delay operator, that is represent Step delay; when configuring the generator polynomial interface for scrambling codes for the source scrambling component, the input sequence is 1100000000000001; the source scrambling component is also used to pass the scrambled data it outputs to the channel coding component.

[0027] The channel coding component supports embedding mainstream channel coding modules. It receives data as a bitstream in 0 / 1 format and encodes it according to a preset code rate. The parameter interface of the channel coding component includes clock, reset, coding mode, coding rate, coding polynomial, and coding packet length. Various embedded encoders can be configured through these parameter interfaces.

[0028] In this embodiment, the channel coding component is used to select either 3GppTurbo coding or RS coding under the constraints of parameter instructions. 3GppTurbo coding supports code rates of 1 / 5, 1 / 3, 1 / 2, 2 / 5, and 1 / 4, which can be arbitrarily configured. The corresponding 3GppTurbo encoder structure is as follows... Figure 3 As shown, it consists of an interleaver and two component encoders; one component encoder performs convolutional encoding on the original input bit data, and the other component encoder performs convolutional encoding on the interleaved bit data. The internal structure of the component encoder can be found in [reference needed]. Figure 4 This is an illustration. The RS coding supported by the channel coding component is a linear block code, which can realize the corresponding error correction function.

[0029] The group-hopping frame component first buffers data in fixed / frequency-hopping modes and then outputs it after dividing it according to the frame (hop) structure. The parameter interface of the group-hopping frame component includes clock, reset, group-hopping parameters, group-hopping parameters, and PN code. The group-hopping frame component is used to adjust the data according to changes in the group-hopping parameters. Figure 5 The hop structure shown is customized to achieve group hop processing of input data, including: converting power rise / fall time and frequency switching time into information length; filling in random information of the corresponding information length during the power rise / fall time; filling in input information of the corresponding information length during the effective signal time; repeating this process until the number of group hops accumulates to the preset service hop count. The data after group hops is directly output to the subsequent spread spectrum components. It should be noted here that the hop count includes the service hop count and the synchronization hop count. The entire frequency hopping transmission includes synchronization hops and service hops, with the hop structure being consistent; however, when filling the effective signal area, synchronization information is filled first, followed by service data information.

[0030] The framing parameters include the preset PN code length, the custom PN code, and the input data length. The PN code is obtained through local preset or custom distribution. When framing, the frame skipping component first outputs the locally preset or custom distributed PN code, and then outputs the framed information.

[0031] The data received by the spread spectrum component is a bit stream in 0 and 1 format. The spread spectrum component is used to expand the input 0 and 1 bit information according to a pseudo-random sequence with a preset spreading factor and then output it. The parameter interface of the spread spectrum component includes clock, reset, spreading factor and spreading code. The spreading code is stored in the component in a custom way.

[0032] The spread spectrum component is also used to store the input 01-bit information into the buffer, read out 1 bit of information data, read the spread spectrum code according to the spread spectrum code length, perform modulo-2 operation processing and output it until the buffer is empty; if the spread spectrum multiplier parameter value sent by the configuration received by the spread spectrum component is 1, it means that no spread spectrum processing is performed and the corresponding information data is directly transmitted.

[0033] The variable rate modulation component supports the embedding of conventional modulation modules, with mainstream modulation methods including BPSK / QPSK / 8PSK, 2FSK / 4FSK / 8FSK, MSK / GMSK, and 16QAM. The parameter interfaces of the variable rate modulation component include clock, reset, modulation type, and modulation control parameters.

[0034] The variable rate modulation component modulates and maps the data from the spread spectrum component under the corresponding modulation type, and performs rate control on the modulated information to complete the variable rate processing. Finally, it outputs the data according to the symbol rate, thus completing the baseband modulation process.

[0035] When the variable rate modulation component performs rate control processing, the modulation output information of FSK / 4FSK / 8FSK is output after the rate is mapped to the frequency control word to control the DDS, while other modulation types are output after being processed by the variable rate filter.

[0036] The variable rate filter is implemented based on a fractional-multiplier shaping filter; its network structure can be found in [reference needed]. Figure 7 This is a schematic diagram. The fractional shaping filter is used to adjust the fractional interpolation factor in real time based on the operating clock and baseband signal data rate, ensuring that the output data rate after shaping and filtering is consistent with the operating clock. This processing method allows for a unified interface and data rate for modulation methods based on different principles.

[0037] Example 3 Based on the above embodiments, this embodiment provides a communication signal simulation method that can be implemented according to its componentized waveform architecture. The method includes the following steps: S1. Acquire the data to be modulated and scramble it; S2. Select the corresponding encoding mode according to the parameter instructions, and encode the scrambled data. S3. Add synchronization codes to the encoded data to achieve framing, and in frequency hopping mode, output the framed data after conversion according to the corresponding hop structure; S4. After receiving the data from the frame skipping process, expand the data according to the spread spectrum multiple parameter value issued by the configuration and then output it. S5. Receive the spread spectrum processed data, select the corresponding modulation mode according to the parameter command to complete the symbol modulation mapping, and output the obtained communication signal after rate control and filtering, thus completing the entire baseband modulation process.

[0038] In a preferred embodiment, in step S2, the encoding mode is selected as either 3GppTurbo encoding or RS encoding under the constraints of the parameter instructions. Specifically, 3GppTurbo encoding corresponds to a 3GppTurbo encoder. Composed of an interleaver and two component encoders and The system consists of one component encoder that performs convolutional encoding on the original input bit data, and another component encoder that performs convolutional encoding on the interleaved bit data.

[0039] The coding generator polynomial for 3Gpp Turbo encoding is as follows:

[0040]

[0041]

[0042] In the formula, It is a delay operator, that is represent Step delay.

[0043] Since the channel coding component in the architecture that implements this step also supports RS coding, and RS coding is a linear block code, when performing RS coding, the effective information symbols to be encoded are divided into lengths of... The code is grouped, and then each group is encoded. After processing, the codewords in each group will increase. There are 1 supervisory bit, and the codeword length is 1. Then for a definition in the Galois field RS The maximum number of errors that can be corrected is... The generator polynomial is as follows:

[0044] In the formula, ; For polynomial variables; It is a generator, that is, a primary element defined in the Galois field; It is an index variable.

[0045] In a preferred embodiment, in step S3, when the output is converted according to the corresponding hop structure, the corresponding group hop parameters include power rise / fall time, effective signal length, frequency switching time, number of hops, input data length, synchronization code length, and synchronization code; the single hop period of the hop structure. The calculation method is as follows:

[0046] In the formula, Represents the symbol rate; Represents hop count; frequency switching time Duty cycle and single jump period The product is calculated, and the duty cycle is obtained through a custom method; signal dwell time. It can be expressed as the following formula:

[0047] Similarly, changing the group jump parameters allows for customized adjustments to the jump structure. (Following...) Figure 5 The jump structure shown performs jump processing on the input data according to the jump parameters, specifically as follows: The length of the power rise / fall time and switching time conversion information is given by the following formula: During the power rise / fall time, random information of the corresponding length is filled in; during the effective signal time, input information of the corresponding length is filled in. This process is repeated until the number of group hops accumulates to the service hop count. The data after the group hop is then directly output to the next stage module. It is important to note that the hop count includes the service hop count and the synchronization hop count. The entire frequency hopping transmission includes synchronization hops and service hops, with the hop structure being consistent. However, when filling in the effective signal area, synchronization information is filled in first, followed by service data information.

[0048] During framing, the corresponding framing parameters include the preset PN code length, the custom PN code, and the input data length. During framing, the locally preset or custom PN code is output first, and then the framed information is output.

[0049] In a preferred embodiment, in step S5, the spread spectrum processed data is modulated and mapped under the corresponding modulation type, and the modulated information is rate controlled to complete the variable rate processing, and finally output according to the symbol rate.

[0050] In this embodiment, during rate control processing, the modulation output information of FSK / 4FSK / 8FSK is output after the rate is mapped to a frequency control word to control the DDS, while other modulation types are output after being processed by a variable rate filter.

[0051] The variable rate filter is implemented based on the fractional shaping filter, and its application is as follows: The fractional-multiplexed shaping filter is decomposed into a multiphase filter, and its impulse response is obtained. Group according to the preset arrangement, with the number of groups being [number missing]. The filter length is , for For integer multiples of , the filter expression is as follows:

[0052] In the formula, The Z-domain transfer function representing the filter; Represents the number of multiphase decomposition groups; Represents the filter length; Represents the phase index; Represents the delay factor; Representing the Z-domain transfer function of each sub-filter; Represents a higher-order Z variable.

[0053] Output symbol rate It is then controlled by a numerically controlled oscillator (NCO), and the calculation process is as follows: Step value of the numerically controlled oscillator NCO As shown in the following formula:

[0054] In the formula, Operating frequency; The NCO bit width is set to 28 in this embodiment; at this time, the symbol rate... The accuracy is ; Accumulated NCO value The bit width is also determined to be Then, it is represented as:

[0055] when The value is greater than or equal to At this time, the baseband data read enable is active, and the frequency of this enable signal is the symbol rate. .

[0056] Under symbol rate control, the data with completed modulation mapping in the storage area is read and placed into a shift register. The bit width of the shift register is equal to the order of a single filter. The order represents the interpolation factor; under symbol rate control, the shift register shifts according to a preset rule, through... The high-order bits are used to obtain the required filter group number, and the corresponding filter coefficients are obtained according to the group number. The filter data and filter coefficients are multiplied and summed to obtain the output signal of the variable rate filter at the current time, thus completing the entire baseband modulation process.

[0057] Figure 8 The overall implementation architecture of the method in this embodiment under software application control is shown, and its application can be understood in conjunction with the method implementation steps.

Claims

1. A modular waveform architecture for communication signal simulation, characterized in that: The architecture comprises multiple functional components connected in series. During communication signal simulation, configuration parameters are sent to the configuration interfaces of each functional component via waveform configuration commands, and finally, the communication signal completing the baseband modulation process is output. The functional components in this architecture are as follows: A source scrambling component is used to receive data to be modulated and scramble it. The channel coding component is used to receive scrambled data and select the corresponding coding mode for encoding processing according to the parameter instructions; The frame hopping component is used to add synchronization codes to the encoded data to achieve frame hopping, and to output the framed data according to the corresponding hopping structure in frequency hopping mode. The spread spectrum component is used to receive the data after group frame skipping processing, expand the data according to the spread spectrum multiple parameter value issued by the configuration, and then output it. The variable rate modulation component is used to receive the data after spread spectrum processing, select the corresponding modulation mode according to the parameter command to complete the modulation mapping of symbols, and then output the communication signal after rate control and filtering, thus completing the entire baseband modulation process.

2. The component-based waveform architecture according to claim 1, characterized in that: The source scrambling component generates a scrambling code internally according to the corresponding parameter configuration, and then uses this scrambling code to scramble the received input data. The scrambling code is generated using a 15th-order polynomial, and the initial values ​​of the scrambling code's corresponding registers and the settings of the generator polynomial are all completed after configuring the source scrambling component's interface accordingly. The generator polynomial of the scrambling code... as follows: In the formula, It is a delay operator, that is represent Step delay; when configuring the generator polynomial interface for scrambling codes for the source scrambling component, the input sequence is 1100000000000001; the source scrambling component is also used to pass the scrambled data it outputs to the channel coding component.

3. The component-based waveform architecture according to claim 1, characterized in that: The channel coding component receives data in the form of a bit stream of 0s and 1s, and encodes it according to a preset code rate. The parameter interface of the channel coding component includes clock, reset, coding mode, coding rate, coding polynomial and coding packet length, and the various encoders embedded in it can be configured through the various parameter interfaces. The channel coding component is used to select the coding mode as 3Gpp Turbo coding or RS coding under the constraints of parameter instructions; wherein, the 3Gpp Turbo encoder corresponding to 3Gpp Turbo coding consists of an interleaver and two component encoders; one component encoder performs convolutional coding on the original input bit data, and the other component encoder performs convolutional coding on the interleaved bit data.

4. The componentized waveform architecture according to claim 1, characterized in that: The parameter interface of the group framing component includes clock, reset, group framing parameters, group framing parameters, and PN code; The group hop frame component is used to customize the hop structure according to the changes in group hop parameters, and realize group hop processing of input data, including: converting power rise / fall time and frequency switching time into information length, filling random information of the corresponding information length during the power rise / fall time, filling input information of the corresponding information length during the effective signal time, and repeating until the number of group hops accumulates to the preset service hop number and then ends. The framing parameters include the preset PN code length, the custom PN code, and the input data length; The PN code is obtained through local preset or custom distribution. When framing, the frame skipping component first outputs the locally preset or custom distributed PN code, and then outputs the framed information.

5. The component-based waveform architecture according to claim 1, characterized in that: The data received by the spread spectrum component is a bit stream in 0 and 1 format. The spread spectrum component is used to expand the input 0 and 1 bit information according to a pseudo-random sequence with a preset spreading factor before outputting it. The parameter interface of the spread spectrum component includes clock, reset, spreading factor, and spreading code. The spreading code is stored in the component in a custom way. The spread spectrum component is also used to store the input 01 bit information into the buffer, read out the information data of a preset size, read the spread spectrum code according to the spread spectrum code length, perform modulo-2 operation processing and output it until the buffer is empty; If the spread spectrum component receives a spread spectrum multiple parameter value of 1 from the configuration, it means that no spread spectrum processing is performed and the corresponding information data is transmitted directly.

6. The component-based waveform architecture according to claim 1, characterized in that: The parameter interface of the variable rate modulation component includes clock, reset, modulation type and modulation control parameters; the variable rate modulation component modulates and maps the data from the spread spectrum component under the corresponding modulation type, and performs rate control on the modulated information to complete the variable rate processing, and finally outputs according to the symbol rate, thereby completing the baseband modulation process. When the variable rate modulation component performs rate control processing, the modulation output information of FSK / 4FSK / 8FSK is output after the rate is mapped to the frequency control word to control the DDS, while other modulation types are output after being processed by the variable rate filter. The variable rate filter is based on a fractional shaping filter, which is used to adjust the fractional interpolation factor in real time according to the operating clock and the baseband signal data rate, so that the output data rate after shaping and filtering is consistent with the operating clock.

7. A communication signal simulation method based on a modular waveform architecture according to any one of claims 1 to 6, characterized in that, The method includes the following steps: S1. Acquire the data to be modulated and scramble it; S2. Select the corresponding encoding mode according to the parameter instructions, and encode the scrambled data. S3. Add synchronization codes to the encoded data to achieve framing, and in frequency hopping mode, output the framed data after conversion according to the corresponding hop structure; S4. After receiving the data from the frame skipping process, expand the data according to the spread spectrum multiple parameter value issued by the configuration and then output it. S5. Receive the spread spectrum processed data, select the corresponding modulation mode according to the parameter command to complete the symbol modulation mapping, and output the obtained communication signal after rate control and filtering, thus completing the entire baseband modulation process.

8. The communication signal simulation method according to claim 7, characterized in that: In step S2, under the constraints of the parameter instructions, the encoding mode is selected as either 3Gpp Turbo encoding or RS encoding; the 3Gpp Turbo encoding corresponds to the 3Gpp Turbo encoder. Composed of an interleaver and two component encoders and The structure consists of two component encoders: one performs convolutional coding on the original input bit data, and the other performs convolutional coding on the interleaved bit data. The coding generator polynomial for 3Gpp Turbo coding is as follows: In the formula, It is a delay operator, that is represent Step delay; When performing RS encoding, the valid information symbols to be encoded are divided into lengths of... The code is grouped, and then each group is encoded. After processing, the codewords in each group will increase. One supervisory bit, codeword length is Then for a definition in the Galois field RS The maximum number of errors that can be corrected is... The generator polynomial is as follows: In the formula, ; For polynomial variables; It is a generator, that is, a primary element defined in the Galois field; It is an index variable.

9. The communication signal simulation method according to claim 7, characterized in that: In step S3, when the output is converted according to the corresponding hop structure, the corresponding group hop parameters include power rise / fall time, effective signal length, frequency switching time, number of hops, input data length, synchronization code length, and synchronization code; the single hop period of the hop structure. The calculation method is as follows: In the formula, Represents the symbol rate; Represents hop count; frequency switching time Duty cycle and single jump period The product is calculated, and the duty cycle is obtained through a custom method; signal dwell time. It can be expressed as the following formula: During framing, the corresponding framing parameters include the preset PN code length, the custom PN code, and the input data length. During framing, the locally preset or custom PN code is output first, and then the framed information is output.

10. The communication signal simulation method according to claim 9, characterized in that: In step S5, the spread spectrum processed data is modulated and mapped under the corresponding modulation type, and the modulated information is rate controlled to complete the variable rate processing, and finally output according to the symbol rate. During rate control processing, the modulation output information of FSK / 4FSK / 8FSK is output after the rate is mapped to a frequency control word to control the DDS. Other modulation types are output after being processed by a variable rate filter. The variable rate filter is based on a fractional shaping filter, and its application is as follows: The fractional-multiplexed shaping filter is decomposed into a multiphase filter, and its impulse response is obtained. Group according to the preset arrangement, with the number of groups being [number missing]. The filter length is , for For integer multiples of , the filter expression is as follows: In the formula, The Z-domain transfer function representing the filter; Represents the number of multiphase decomposition groups; Represents the filter length; Represents the phase index; Represents the delay factor; Representing the Z-domain transfer function of each sub-filter; Represents a higher-order Z variable; Output symbol rate It is then controlled by a numerically controlled oscillator (NCO), and the calculation process is as follows: Step value of the numerically controlled oscillator NCO As shown in the following formula: In the formula, Operating frequency; Define the NCO bit width; accumulate the NCO value. The bit width is also determined to be Then, it is represented as: when The value is greater than or equal to At this time, the baseband data read enable is active, and the frequency of this enable signal is the symbol rate. ; Under symbol rate control, the data with completed modulation mapping in the storage area is read and placed into a shift register. The bit width of the shift register is equal to the order of a single filter. The order represents the interpolation factor; under symbol rate control, the shift register shifts according to a preset rule, through... The high-order bits are used to obtain the required filter group number, and the corresponding filter coefficients are obtained according to the group number. The filter data and filter coefficients are multiplied and summed to obtain the output signal of the variable rate filter at the current time, thus completing the entire baseband modulation process.

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