Quantum hash function resisting software and hardware collaboration system oriented to computer monitoring system

Abstract

The invention relates to the technical field of cryptography, and belongs to a computer monitoring system-oriented anti-quantum hash function software and hardware collaboration system, the architecture design adopted by the invention only operates a single vector register at a time, and compared with a multi-vector parallel processing mode in the paper, the occupied hardware resources are obviously reduced. Under a 64-bit architecture, a single round of Keccak operation in the scheme only needs 75 cycles; under a 32-bit architecture, the single-round operation period of the scheme is 147, the efficiency is improved, and meanwhile, the resource consumption is reduced. Standard instructions of an RISC-V vector instruction extension set are fully utilized, and comprehensive support for 32-bit and 64-bit architectures is realized through well-designed custom extension instructions. Compared with a scheme only aiming at specific bit width optimization, the platform adaptability and transportability of the design are higher. In addition, according to the scheme, through software and hardware collaborative design, different parameter setting and application scenes can be flexibly adapted, and meanwhile excellent performance is kept.

Description

Technical Field

[0001] This invention relates to the field of cryptography technology and belongs to a quantum-resistant hash function hardware and software co-operation system for computer monitoring systems. Background Technology

[0002] With the rapid development of quantum algorithms and quantum computers, traditional cryptographic algorithms face unprecedented challenges, especially RSA and elliptic curve cryptography, which rely on large factorization and discrete logarithm security. Against this backdrop, post-quantum cryptography has emerged, aiming to develop novel encryption algorithms resistant to quantum computer attacks. Post-quantum protocols based on lattice cryptography, with their superior performance and security, have been widely adopted in various application scenarios and formally adopted by international standardization organizations as next-generation standard algorithms. Among them, the lattice cryptography-based key encapsulation mechanism KYBER and the digital signature algorithm Dilithium, benefiting from their relatively small key length and flexibility, have significant advantages in IoT devices and resource-constrained mobile platforms.

[0003] In lattice-based cryptography algorithms, the hash function is one of the core algorithms. The resource consumption and computational latency of this module have a decisive impact on the overall algorithm performance, accounting for approximately 40% of the computation time. In 2012, NIST adopted the Keccak-f algorithm based on a sponge structure as the standard for secure hash functions. This algorithm achieves obfuscation by padding the information to be encrypted and rearranging it into a matrix array, then performing a series of permutations, XOR operations, and mapping transformations on the rows and columns of the matrix, thus providing security for the output. After 24 rounds of the five-step algorithm (θ, ρ, π, χ, ι), the encryption result is compressed into a hash value with a length much smaller than the input length. Although hash algorithms theoretically provide reliable security, the computation time and resources consumed in their calculation process cannot be ignored, especially when processing large amounts of data, where hash algorithms often become the bottleneck of system performance.

[0004] To address the demands of applications such as the Internet of Things (IoT) and resource-constrained mobile platforms, the RISC-V kernel architecture, based on a reduced instruction set architecture, has become a key choice for overcoming performance bottlenecks. By leveraging scalable Single Instruction Multiple Data (SIMD) technology, processors can access large amounts of data to be processed in parallel, significantly optimizing the efficiency of hash functions and meeting the growing demands for high-performance and high-speed computing. However, due to the data dependencies in the encryption process, a single instruction cannot efficiently implement the entire five-step algorithm. Furthermore, hash functions typically use a single-channel 64-bit encoding with 25 channels, making them difficult to be effectively compatible with processors of different bit widths (such as 32-bit or 64-bit), posing a significant challenge to the portability of hash functions. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a quantum-resistant hash function hardware and software co-operation system for computer monitoring systems.

[0006] To achieve the above objectives, the present invention provides the following technical solution: This invention provides a quantum-resistant hash function hardware and software co-system for computer monitoring systems, including a RISC-V processor core configured to execute SIMD custom vector extension instructions and process data; The vector register unit connects to the RISC-V processor core via a register file interface, supports RISC-V vector instruction set extensions, and is configured with Keccak state data to provide access space. It runs a vector register allocation strategy for Keccak state data, optimizes the register allocation of Keccak state data, and receives decoded vector operation instructions and data address information. A vector processing unit group, connected to the vector register unit, performs parallel processing on the data in the vector register unit, runs a SIMD parallel computation method for the five steps of the Keccak algorithm, and performs single instruction multiple data stream parallel computation on the five steps of the Keccak algorithm. The read / write storage unit is connected to the RISC-V processor core and is used to store and read data. It divides the data in a single Keccak state into blocks and stores them in the vector register unit. After processing, it stores the data in the external storage unit according to the address correspondence.

[0007] Preferably, the RISC-V processor core adopts a five-stage pipeline architecture, including instruction fetch, decode, execute, write-back, and memory access pipeline architecture.

[0008] Preferably, the RISC-V processor core includes an instruction control unit and a prefetch buffer. The instruction control unit is used to parse and schedule instructions, and the prefetch buffer is used to temporarily store fetched instructions.

[0009] Preferably, the vector register unit includes register groups numbered v0 to v31.

[0010] Preferably, in the vector register unit, the vector register allocation strategy for Keccak state data is as follows: for a 64-bit architecture, the data of a single Keccak state is allocated to the vector registers v0 to v4 along the x-direction; for a 32-bit architecture, the vector register unit uses bit truncation technology to store the data of a single Keccak state in v0-v15 and v16-v31 in terms of the lower 32 bits and the higher 32 bits, respectively.

[0011] Preferably, the vector processing unit group includes five parallel processing units, PE0 to PE4. Each PE unit has multiple built-in arithmetic units, including a 64-bit converter, a shifter, a multiplier, an XOR unit, and a carry-store adder.

[0012] Preferably, in the SIMD parallel computation method for the five steps of the Keccak algorithm, the calculation of the theta function, rho function, chi function and iota function is completed collaboratively by calling the XOR, shifter, 64-bit slew in the vector processing unit group and accessing a pre-stored lookup table, which is stored in the processor core.

[0013] Preferably, the read / write storage unit has a configurable data bus width, which can be configured as 64 bits or 128 bits.

[0014] Preferably, the processor core pre-stores a mapping lookup table for the rho function and a round constant lookup table for the iota function.

[0015] Compared with existing technologies, this invention provides a quantum-resistant hash function-based hardware and software co-operation system for computer monitoring systems, which has the following advantages: 1. The architecture design adopted in this invention operates on only a single vector register at a time, significantly reducing hardware resources compared to the multi-vector parallel processing method in the aforementioned papers. In a 64-bit architecture, this scheme requires only 75 cycles for a single round of Keccak computation; in a 32-bit architecture, the single-round computation cycle is 147, improving efficiency while reducing resource consumption.

[0016] 2. This invention fully utilizes the standard instructions of the RISC-V Vector Instruction Set Extension (RVV 1.0) and achieves comprehensive support for both 32-bit and 64-bit architectures through carefully designed custom extension instructions. Compared to solutions that are optimized only for specific bit widths, this design offers greater platform adaptability and portability. Furthermore, through hardware and software co-design, this solution can flexibly adapt to different parameter settings and application scenarios while maintaining excellent performance.

[0017] The features and advantages of the present invention will be described in detail through embodiments and in conjunction with the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is an architecture diagram of a quantum-resistant hash function hardware and software co-operation system for computer monitoring systems according to the present invention; Figure 2 The allocation of Keccak states in the vector register in this invention; Figure 3This is a diagram of the processing core architecture supporting RISC-CV vector instructions based on SIMD, as described in this invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. However, it should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0020] See Figures 1-3 A quantum-resistant hash function hardware and software co-system for computer monitoring systems includes a RISC-V processor core configured to execute SIMD custom vector extension instructions and process data; The vector register unit connects to the RISC-V processor core via a register file interface, supports RISC-V vector instruction set extensions, and is configured with Keccak state data to provide access space. It runs a vector register allocation strategy for Keccak state data, optimizes the register allocation of Keccak state data, and receives decoded vector operation instructions and data address information. A vector processing unit group, connected to the vector register unit, performs parallel processing on the data in the vector register unit, runs a SIMD parallel computation method for the five steps of the Keccak algorithm, and performs single instruction multiple data stream parallel computation on the five steps of the Keccak algorithm. The read / write storage unit is connected to the RISC-V processor core and is used to store and read data. It divides the data in a single Keccak state into blocks and stores them in the vector register unit. After processing, it stores the data in the external storage unit according to the address correspondence.

[0021] Preferably, the RISC-V processor core adopts a five-stage pipeline architecture, including instruction fetch, decode, execute, write-back, and memory access pipeline architecture.

[0022] Preferably, the RISC-V processor core includes an instruction control unit and a prefetch buffer. The instruction control unit is used to parse and schedule instructions, and the prefetch buffer is used to temporarily store fetched instructions.

[0023] Preferably, the vector register unit includes register groups numbered v0 to v31.

[0024] Preferably, in the vector register unit, the vector register allocation strategy for Keccak state data is as follows: for a 64-bit architecture, the data of a single Keccak state is allocated to the vector registers v0 to v4 along the x-direction; for a 32-bit architecture, the vector register unit uses bit truncation technology to store the data of a single Keccak state in v0-v15 and v16-v31 in terms of the lower 32 bits and the higher 32 bits, respectively.

[0025] Preferably, the vector processing unit group includes five parallel processing units, PE0 to PE4. Each PE unit has multiple built-in arithmetic units, including a 64-bit converter, a shifter, a multiplier, an XOR unit, and a carry-store adder.

[0026] Preferably, in the SIMD parallel computation method for the five steps of the Keccak algorithm, the calculation of the theta function, rho function, chi function and iota function is completed collaboratively by calling the XOR, shifter, 64-bit slew in the vector processing unit group and accessing a pre-stored lookup table, which is stored in the processor core.

[0027] Preferably, the read / write storage unit has a configurable data bus width, which can be configured as 64 bits or 128 bits.

[0028] Preferably, the processor core pre-stores a mapping lookup table for the rho function and a round constant lookup table for the iota function.

[0029] The following detailed description of the system architecture and operation process will further explain the design concept and implementation method of the present invention.

[0030] like Figure 1 The RISC-V pipeline architecture supporting SIMD shown mainly includes the following core modules and their collaborative working mechanisms.

[0031] (1) Overall system architecture This invention constructs a hardware-software co-engineering architecture optimized for the Keccak hash function. It uses a RISC-V processor core as the control center, coordinating instruction parsing and execution scheduling. A dedicated vector register unit serves as the data cache center, supporting the extended functions of the RISC-V vector instruction set and providing storage space for Keccak state data. A vector processing unit cluster is deployed as the computing module, achieving efficient Keccak algorithm computation through parallel design. A read / write memory unit is set up as a data bridge, establishing a communication link between the system and external memory. The entire system transmits control information via an instruction bus, carries the computational data flow via a data bus, and coordinates the states of each module via a control bus, forming a complete processing pipeline from instruction parsing, data preparation, parallel computation to result output.

[0032] The RISC-V processor core, serving as the system control center, employs a five-stage pipeline architecture (IF-ID-EX-WB-LSU), such as... Figure 1 As shown, the processor is responsible for instruction parsing, scheduling, and execution control. Instructions are fetched through the instruction interface, managed by the prefetch buffer and instruction control unit, and then parsed by the decoder using custom vector extension instructions.

[0033] Vector Register Unit (VecRegfile): A dedicated register set supporting RISC-V vector instruction set extensions, numbered v0 to v31, such as... Figure 2 The Keccak state allocation scheme is shown. This unit is connected to the processor core via a register file interface, receiving decoded vector operation instructions and data address information.

[0034] Vector processing unit group: such as Figure 3 The SIMD-based processing core shown contains five parallel processing units, PE0-PE4. Each PE unit has a built-in dedicated arithmetic unit, including a 64-bit converter, shifter, multiplier, XOR, and carry-save adder.

[0035] Read / Write Memory Unit (LSU): Responsible for data loading and storage operations. It communicates with external memory through a data interface, and the bus width can be configured to 64 bits or 128 bits.

[0036] (2) SIMD custom instruction implementation mechanism Instruction parsing and data rearrangement: The SIMD unit optimizes parallel data processing during the instruction parsing stage. A single vector instruction can simultaneously read 5×64 bits (64-bit architecture) or 10×32 bits (32-bit architecture) of Keccak state data. The decoder rearranges the input data according to the instruction type and the Keccak algorithm requirements, allocating the 5×5 matrix states to the corresponding vector registers in the row or column direction. The instruction control unit simultaneously distributes the rearranged data to multiple PE processing units, achieving true single-instruction multiple-data parallel processing.

[0037] (3) Detailed design of the vector register unit (VecRegfile) Parameter configuration mechanism: VLEN defines the total bit width of a single vector register, supporting flexible configuration to adapt to different processor architectures. ELEN is automatically set according to the processor architecture: 32-bit for 32-bit architectures and 64-bit for 64-bit architectures. VEMax is automatically calculated by VLEN / ELEN to determine the maximum number of data elements that a single register can hold. VL, as the dynamically configurable number of active elements, is adjusted at runtime using the vsetvl instruction.

[0038] Data allocation strategy: such as Figure 2 As shown, optimized data layouts are employed for different architectures. In a 64-bit architecture, the 5×5×64-bit data in a single Keccak state is allocated along the x-axis to registers v0-v4, with each register storing five 64-bit elements. The 32-bit architecture uses a hierarchical storage strategy, with the lower 32 bits stored in v0-v15 and the higher 32 bits stored in v16-v31, with data concatenation achieved through address offsets.

[0039] (4) Read / Write Memory Unit (LSU) Cooperative Control Mechanism Data transfer control: The LSU unit plays a crucial role in the EX and WB pipeline stages. During the load stage, Keccak status data is read from external memory according to the vlw instruction and transferred to the vector register unit via the data bus. During the computation stage, it coordinates with the vector processing unit to ensure data consistency during computation. During the write-back stage, the vsw instruction is used to write the processing results back to external memory, ensuring data alignment and integrity.

[0040] Bus configuration optimization: The 64-bit bus mode is suitable for low-power scenarios, transmitting one 64-bit data element per cycle. The 128-bit bus mode is suitable for high-performance scenarios, transmitting two 64-bit data elements per cycle, further improving data throughput.

[0041] (5) Inter-module collaborative workflow Instruction execution flow: In the IF stage, the instruction interface retrieves the vector instruction, which is then temporarily stored in the prefetch buffer and scheduled by the instruction control unit. In the ID stage, the decoder identifies the custom vector instruction, generates control signals, and the vector register prepares data. In the EX stage, the vector processing units execute the Keccak algorithm steps in parallel, and the LSU coordinates the data flow. In the WB stage, the LSU writes the calculation results back to external storage and updates the vector register state.

[0042] Data flow control: The entire system achieves efficient data flow management through a carefully designed data path. The modules communicate with each other through the standard RISC-V vector interface protocol, ensuring the system's scalability and standard compatibility.

[0043] The hardware and software design of the hash function in this invention is as follows: Step 1: Adjust the hardware architecture to adapt to the input data structure (1) Preset SIMD vector instruction extension hardware parameters: The RISC-V processor core parses configuration instructions through the instruction control unit, passing the element bit width parameter ELEN (32 or 64 bits) according to the processor's bit width, with the default element count VL being VEMax. For example... Figure 2 The vector register allocation scheme shown occupies 5 elements for 5 groups of 64-bit data (single-plane data) in a single Keccak state in a 64-bit architecture. The processor bit width is perfectly aligned with the single-channel 64-bit data, achieving optimal utilization of hardware resources. For a 32-bit architecture, a single state occupies 10 elements. The vector register unit uses bit truncation technology to store the 64-bit data in v0-v15 and v16-v31, respectively, breaking through the limitation of traditional 32-bit processors being unable to efficiently process 64-bit Keccak data. Through hardware-level data segmentation and reassembly, the 32-bit architecture can also fully utilize vector parallelism. The vector processing unit group performs concatenation operations during processing, achieving seamless reassembly of separated data at the hardware level and avoiding frequent data merging operations at the software level. After the operation, the LSU unit is stored in blocks at the corresponding addresses. Address mapping optimization reduces storage conflicts, thereby improving storage bandwidth utilization. The number of Keccak states that a single vector register can operate on in parallel is defined as N, which is equal to ⌊VL / 5⌋, while VRegMax defines the upper limit on the number of vector registers used per instruction. Related configurations are accomplished through the `vconfig imm` and `vsetvl rd, rs1` instructions. This parameterized configuration mechanism allows the system to flexibly adapt to different processor architectures and application requirements, achieving adaptive support for processors with different bit widths using the same hardware architecture.

[0044] (2) Vector data read / store operations: Operation description: The LSU unit is responsible for storing the 5x5x64 (1600) bit data of a single Keccak state into blocks in the vector register unit. After processing, it is stored in the external memory unit according to the address correspondence.

[0045] Specifically: For 64-bit systems, data is arranged sequentially along the VL direction (x-direction) and the v0-v31 direction (y-direction). A single Keccak state occupies vector registers v0 to v4, with each register using 5 elements. The parser uses the vector load instruction `vlw vd, 0(%[data_addr])` to load VL elements of data from the LSU unit into the target vector register. The write-back operation uses a similar instruction `vsw vd, 0(%[data_addr])` to write the calculation result to the data memory. For 32-bit systems, 64-bit data is stored in blocks in v0-v15 and v16-v31. Read and write operations are performed in two steps using address offsets: `vlw vd, 0(%[data_addr])` and `vlw vd, 80(%[data_addr])`. Storage operations also require writing data to the target address in two steps. This preprocessing method allows the raw data to be distributed in an ordered manner in the register units, shifting the traditional runtime data rearrangement to the hardware initialization stage. This transforms the data access mode during the execution of the Keccak algorithm from random access to sequential access, while creating optimal data layout conditions for subsequent vector parallel computation and significantly reducing computational complexity.

[0046] Step 2: Perform matrix array calculations. The algorithm and corresponding calculations for a single Keccak state are as follows.

[0047] (1) theta function: Input size: 5×5×64 or 2×5×5×32; Output size: 5×64 or 2×5×32. Operation Description: First, XOR the five groups of data in the same column bit by bit to obtain a one-dimensional vector A[x] containing only the x-direction. Then, flip the data on the right by 1 bit, and XOR the data on the left with the flipped data to obtain the intermediate value B[x].

[0048] Calculation content: This design uses a custom vector instruction to implement the hardware of theta function. For example... Figure 3In the vector processing unit group shown, the XOR and shifter built into each PE unit work together to complete the hardware implementation of the theta function. After the decoder of the RISC-V processor core recognizes the theta operation instruction, the vector processing unit group uses existing RVV 1.0 instructions such as vxor.vv vd, v0, v1 to complete the XOR processing of the source vector. For the single-plane input, a bit-shifting operation is performed. vmovi.vi vd, v0, simm receives the source vector register and the instantaneous value to perform the bit-shifting operation. simm is a signed number, where a positive number represents a rightward bit-shift and a negative number represents a leftward bit-shift, and the absolute value is the offset. The bit-flipping instruction vroti64.vivd, v0, simm is defined in the single-channel instruction group, while the 32-bit architecture requires the definition of vroti32h.vi and vroti32l.vi instructions to write back the high 32 bits and low 32 bits of data, respectively. Finally, the processed A[x] is XORed with the original data to obtain the output B[x] of the theta function.

[0049] (2) rho function: Input size: 5×64 or 2×5×32; Output size: 5×64 or 2×5×32. Operation description: Based on the mapping lookup table, perform a single-channel rotation flip on [x,y], and store the flipped bits in rot_table[x,y] to obtain the intermediate value C[x,y].

[0050] Calculation Content: The 64-bit Rotator (64-bit ROT) in the vector processing unit group is specifically optimized for the rho function. For the 64-bit architecture, only one vector extension instruction, rho64.vi vd, v0, imm, is needed to perform a 64-bit rotation and flipping operation within a single element. `imm` represents the index used to look up the corresponding data in the mapping table to read the `rot_table[x mod 5, imm]` data for correct flipping. For the 32-bit architecture, such as the flipping operation after the theta function, two instructions are needed to complete the bit truncation after flipping: rho32h.vi, vd, v0, v16, imm and rho32l.vi, vd, v0, v16, imm. The high-order bits are stored in v16-v31, and the low-order bits are stored in v0-v15. The rho function mapping lookup table shown in Table 1 is pre-stored inside the processor, avoiding external memory access overhead and improving the efficiency of rho function operations.

[0051] Table 1. Rho function mapping lookup table (3) The pi function: Input size: 1×5×64 or 1×5×32; Output size: 5×1×64 or 5×1×32. Operation Description: The vector register unit supports the transpose operation of the pi function through a dedicated address remapping mechanism. The instructions `pi.vi vd, v0, imm` are used, where `vd` does not represent the destination register but rather the starting address to write the transposed value. The input is a 1×5 row vector, and the output is a 5×1 column vector, requiring writing from `vd` to the `vd+5` vector register. `imm` represents the y-value, used to calculate (2x+3y) mod 5. Repeating this five times completes the single-Keccak state pi transformation; this hardware-level transpose operation avoids the overhead of data rearrangement at the software level.

[0052] (1) chi function: Input size: 5×5×64 or 5×5×32; Output size: 5×5×64 or 5×5×32. Operation description: In the same row vector, first invert the data on the right, then AND it with the data offset 2 bits to the right, and finally XOR it with the original data to obtain the intermediate value E[x,y].

[0053] Calculation content: The XORers and shifters of each PE unit in the vector processing unit group work together to complete the chi operation. Inter-element operations can reuse the aforementioned instructions to complete the chi operation. The offset data is obtained by using vmovi.vi vd, v0, simm with an appropriate simm value. The inversion operation is implemented using vxor.v vd.s, v0, s1, and the corresponding AND and XOR operations are performed by the vand.vv and vxor.vv instructions. The simm value in vmovi.vi vd, v0, simm is assigned -1, resulting in D[(x+1) mod 5, y]. Since there is no inversion instruction in RVV 1.0, the system only needs to XOR with 1 to obtain the inverted result. This operation is implemented using vxor.v vd.s, v0, s1, where s1 stores 32'1b or 64'1b for the XOR operation. Then, executing `vmovi.vivd, v0, simm` assigns -2 to `simm`, resulting in `D[(x+2) mod 5, y]`. ANDing these two results with the original data and then XORing them yields `E[x,y]`. This parallelization design significantly reduces the computational complexity of the `chi` function.

[0054] (5) iota function: Input size: 1×64 or 2×32; Output size: 1×64 or 2×32. Operation description: Perform an XOR operation on E[0,0] to eliminate the symmetry effect and obtain the final result F[0,0]. The calculation involves using a lookup table of iota function round constants, as shown in Table 2, pre-stored within the processor core to avoid external memory access. For a 64-bit architecture, we design a vector instruction `iota64.vx vd, v0, s2` to implement the operation, where `s2` stores the round number used to look up the value of `RC[s2]`. Only `D00` in `v0` needs to be XORed, while the remaining elements remain unchanged. For a 32-bit architecture, as before, two instructions, `iota32h.vx vd, v0, v16, s2` and `iota32l.vxvd, v0, v16, s2`, are needed to process the high and low bits respectively. Before the calculation, the two 32-bit values ​​need to be concatenated into a 64-bit value before XORing. This hardware-level lookup table mechanism reduces the latency of the iota function operation to a single cycle.

[0055] Table 2. Lookup table for iota function round constants (6) Output: After a single round of computation, the LSU unit writes the computation result to the external storage unit through a configurable 64-bit or 128-bit data bus, completing the hardware acceleration processing of the entire Keccak round function. The five-step algorithm of Step 2 significantly improves the performance of a single round of Keccak compared to traditional software implementations through the parallel design of the vector processing unit group and dedicated hardware optimization.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions or improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A quantum-resistant hash function hardware and software co-operation system for computer monitoring systems, characterized in that: Includes a RISC-V processor core configured to execute SIMD custom vector extension instructions and process data; The vector register unit connects to the RISC-V processor core via a register file interface, supports RISC-V vector instruction set extensions, and is configured with Keccak state data to provide access space. It runs a vector register allocation strategy for Keccak state data, optimizes the register allocation of Keccak state data, and receives decoded vector operation instructions and data address information. A vector processing unit group, connected to the vector register unit, performs parallel processing on the data in the vector register unit, runs a SIMD parallel computation method for the five steps of the Keccak algorithm, and performs single instruction multiple data stream parallel computation on the five steps of the Keccak algorithm. The read / write storage unit is connected to the RISC-V processor core and is used to store and read data. It divides the data in a single Keccak state into blocks and stores them in the vector register unit. After processing, it stores the data in the external storage unit according to the address correspondence.

2. The quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 1, characterized in that: The RISC-V processor core adopts a five-stage pipeline architecture, including instruction fetch, decode, execute, write-back, and memory access pipelines.

3. The quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 1, characterized in that: The RISC-V processor core includes an instruction control unit and a prefetch buffer. The instruction control unit is used to parse and schedule instructions, and the prefetch buffer is used to temporarily store fetched instructions.

4. The quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 1, characterized in that: The vector register unit contains register groups numbered v0 to v31.

5. A quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 4, characterized in that: In the vector register unit, the vector register allocation strategy for Keccak state data is specifically as follows: For a 64-bit architecture, the data for a single Keccak state is distributed along the x-direction into vector registers v0 through v4; For the 32-bit architecture, the vector register unit uses bit truncation to store the data of a single Keccak state in v0-v15 and v16-v31 in terms of the lower 32 bits and the higher 32 bits, respectively.

6. The quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 1, characterized in that: The vector processing unit group includes five parallel processing units, PE0 to PE4. Each PE unit has multiple built-in arithmetic units, including a 64-bit converter, a shifter, a multiplier, an XOR unit, and a carry-store adder.

7. A quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 6, characterized in that: In the SIMD parallel computation method for the five steps of the Keccak algorithm, the calculation of the theta function, rho function, chi function and iota function is completed collaboratively by calling the XOR, shifter, 64-bit slew in the vector processing unit group and accessing the pre-stored lookup table, which is stored in the processor core.

8. A quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 1, characterized in that: The read / write storage unit has a configurable data bus width, which can be configured as 64 bits or 128 bits.

9. A quantum-resistant hash function hardware and software co-operation system for computer monitoring systems as described in claim 1, characterized in that: The processor core has a pre-stored mapping lookup table for the rho function and a round constant lookup table for the iota function.

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