Synchronous equalization-decoding circuit for PAM4 receiver

Abstract

The invention discloses a synchronous equalization-decoding circuit for a PAM4 receiver, and the circuit comprises a two-stage cascaded continuous time linear equalizer which is used for achieving the preliminary equalization of channel loss; the two-stage cascaded broadband amplifier is used for increasing the signal amplitude; the four current mode logic-based adders are used for inputting level superposition; the four double-tail decision devices are used for comparing differential signals and realizing decision and decoding of PAM4 signals; and the two high-speed differential sampling and holding units with bootstrapped grid voltage are used for delaying the input signal so as to realize LSB decoding of the PAM4 signal. The synchronous equalization-decoding circuit is used for realizing high energy efficiency and good output jitter performance, and the synchronous equalization-decoding circuit is expected to be applied to next-generation 200G / 400G Ethernet communication.

Description

Technical Field

[0001] This invention relates to the field of high-speed serial transceiver communication systems, and more particularly to a synchronous equalization-decoding circuit for a PAM4 receiver. Background Technology

[0002] With the rapid development of emerging technologies such as big data, cloud computing, and artificial intelligence, data generation is exploding, and the demand for data communication bandwidth is growing rapidly. Currently, backplane Ethernet is widely used in data centers, and communication speeds have improved rapidly in recent years. According to the latest 100G / 200G / 400G Ethernet standards, the data transmission rate of a single backplane channel needs to reach 50 Gb / s or higher. However, in high-speed backplane interconnects of ≥50 Gb / s, channel bandwidth is approaching its physical limit, and the cost of multi-path parallel processing remains high. Therefore, new solutions must be sought to improve the data throughput of communication systems.

[0003] Pulse Amplitude Modulation (PAM4) uses four different signal levels for data transmission, with each symbol period representing 2 bits of logic information. When transmitting signals at the same bit rate, PAM4 requires only half the bandwidth of non-return-to-zero (NRZ) signals. Therefore, PAM4 modulation is widely recognized as one of the most suitable data formats for ultra-high-speed optical interconnect systems, and PAM4-based transceiver circuit design has become a current research hotspot. In the new high-speed backplane Ethernet standard proposed by IEEE, PAM4 coding modulation is the preferred choice for serializer / deserializer (SerDes) communication mode when the single-channel data rate reaches 50 Gb / s or higher. Therefore, the development of PAM4 modulation is crucial for improving computing speed in future data centers and for the successful implementation of 200G / 400G Ethernet. However, PAM4 is a four-level transmission code, and receivers cannot directly use traditional NRZ receiver architectures.

[0004] To address this problem, extensive research has been conducted both domestically and internationally, resulting in significant progress in PAM4 serializer / deserializer (SerDes) receivers. For example, Liu Xuena et al. [1] A 112 Gb / s PAM4 receiver equalization scheme was designed, but only algorithm simulation was performed using Matlab; no circuit was built for verification. (Xu Peng et al.) [2] A 40Gb / s PAM4 serial signal receiver equalizer was designed, but different feedback loops were required for each thermometer code after the decision, which greatly increased the circuit complexity. Furthermore, Jung W et al. [3] A 48 Gb / s PAM4 receiver equalization circuit was implemented, but the designed circuit could only equalize 4 dB of channel loss; Sim J et al. [4]A 40 Gb / s PAM4 receiver equalizer was implemented, but its decision feedback loop requires multiple taps, making circuit implementation difficult. Currently, although domestic patents related to PAM4 high-speed SerDes receivers have been published... [5] However, it did not achieve synchronous equalization and decoding, and its circuit architecture was relatively complex. In conclusion, given the demands of high-speed network switching, there is still significant room for development in improving the transmission rate of PAM4 serializer / deserializer (SerDes) receivers with limited circuit complexity.

[0005] References: [1] Liu Xuena, Li Zhensong, Wen Hao, et al. An adaptive equalization design scheme for 112 Gb / s PAM4 receiver [J]. Telecommunications Technology, 2024, 64(06):960-966. [2] Xu Peng, Shi Juan, Wei Xueming, et al. A 40 Gbit / s PAM4 serial signal receiver equalizer [J]. Journal of Guilin University of Electronic Technology, 2024, 44(04):365-371. [3]Jung W, Lee K, Park K, et al. A 48 Gb / s PAM-4 Receiver With Pre-Cursor Adjustable Baud-Rate Phase Detector in 40 nm CMOS[J]. IEEE Journal ofSolid-State Circuits, 2023, 58(5): 1414-1424. [4]Sim J, Park H, Choi Y, et al. PAM-4 Receiver With 1-Tap DFE UsingClocked Comparator Offset Instead of Threshold Voltages for Improved LSB BERPerformance[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(5): 1907-1916. [5] Yu Jie, Zhang Chongyun. A PAM4 signal receiver and its adaptive equalization control method: CN115499024A [P]. 2022-12-20. Summary of the Invention

[0006] This invention proposes a synchronous equalization-decoding circuit for a PAM4 receiver used in high-speed, short-range backplane communication based on CMOS standard technology. This circuit achieves high energy efficiency and good output jitter performance. The synchronous equalization-decoding circuit is expected to be applied to next-generation 200G / 400G Ethernet communication. See the description below for details. A synchronous equalization-decoding circuit for a PAM4 receiver, the circuit comprising: A two-stage cascaded continuous-time linear equalizer is used to achieve initial equalization of channel loss. A two-stage cascaded broadband amplifier is used to increase the signal amplitude; Four current-mode logic adders are used to superimpose input levels; Four dual-tailed decision units are used to compare differential signals to realize the decision and decoding of PAM4 signals; Two gate-voltage bootstrap high-speed differential sample-and-hold units are used to delay the input signal to achieve LSB decoding of PAM4 signals; The input signal passes through a continuous-time linear equalizer and a broadband amplifier in sequence for preliminary equalization and processing; at the output of the broadband amplifier, the signal is divided into two half-rate equalization and decoding paths with the same circuit architecture. In one path, the output signal of the broadband amplifier is input into the adder. After equalization, one path is decoded by the decision unit to obtain the MSB signal and output. The other path is input to the next stage adder after a delay through the sample-and-hold unit. After equalization and level shifting, the decision unit decodes the LSB signal and outputs it. Both the MSB signal and the LSB signal are fed back to the taps of the adder to participate in signal equalization.

[0007] The four current-mode logic-based adders are: The two adders in the MSB feedback loop contain a branch for eliminating backward inter-symbol interference; The two adders in the Least Significant Bit (LSB) feedback loop contain two branches: one branch is used to eliminate backward intersymbol interference (ISI), and the other branch is used to eliminate the Most Significant Bit (MSB) component of the signal, enabling the decision unit to directly decode the LSB.

[0008] The adder includes two signal paths: an odd path and an even path. These two signals are driven by a pair of half-rate inverted clocks. The input signal DISI[k] is represented as:

[0009] DISI[k] is decomposed into: .

[0010] In the odd-path signal path, the input of the adder for the most significant bit (MSB) is connected to a wideband amplifier, and the output is connected to the MSB decision unit and the sample-and-hold unit. The MSB decision unit completes the MSB decoding, outputs the odd-path MSB decoding signal DMSB1, and inputs it to the taps of the odd-path LSB adder and the even-path MSB adder.

[0011] The even-path MSB decision unit outputs the even-path MSB decoding signal DMSB2, which is then input to the taps of the even-path LSB adder and the odd-path MSB adder; when the tap coefficient is set to... At that time, the MSB adder eliminates the MSB component of intersymbol interference by feeding back the MSB signal. This reduces the overall inter-symbol interference to one-third of its original value; the two MSB adders and MSB decision units together form an MSB decision-feedback loop.

[0012] The LSB adder, after level shifting and inter-symbol interference cancellation, outputs the signal to the LSB decision unit to complete LSB decoding, outputting the odd-path LSB decoded signal DLSB1, which is then input to the tap of the even-path LSB adder. The LSB adder consists of two taps; one tap is connected to the MSB signal obtained from the decision, and level shifting is performed to eliminate the MSB component in the PAM4 signal. The PAM4 signal is converted to an NRZ signal; another tap is connected to the feedback LSB signal to eliminate the LSB component of intersymbol interference. .

[0013] The beneficial effects of the technical solution provided by this invention are: 1. Simple circuit structure and small chip area: The decision feedback equalization (DFE) and decoding circuit fusion technology proposed in this invention simplifies the overall circuit structure, thus significantly reducing the chip area of ​​the equalization-decoding circuit, improving the integration of the receiver monolithic integration, and reducing the influence of interconnect parasitic parameters. 2. Synchronous implementation of equalization and decoding functions: The decision device in the traditional decision feedback equalization (DFE) needs to independently set the reference threshold voltage and convert the four levels of the PAM4 signal into thermometer code before performing the decoding operation. However, the decision device used in this invention can directly compare the input differential signal and can synchronously realize the equalization-decoding function. 3. Low output signal jitter: Because the circuit structure used in this invention avoids the output jitter problems caused by reference threshold voltage jitter, signal common mode level and amplitude changes, a low jitter output signal can be obtained, effectively reducing the overall bit error rate of the receiver.

[0014] In summary, the synchronous equalization-decoding circuit for the PAM4 receiver proposed in this invention has good application prospects in practical applications. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the step equalization and decoding circuit of a traditional PAM4 receiver; Figure 2 This is a schematic diagram of a synchronous equalization-decoding circuit used in a PAM4 receiver. Figure 3 This is a schematic diagram of the least significant bit (LSB) adder level shifting process; Figure 4 The eye diagram of a simulated 56Gb / s PAM4 signal after equalization by a continuous-time linear equalizer (CTLE). Figure 5 Inter-symbol interference of a simulated 56Gb / s PAM4 signal after CTLE equalization; Figure 6 The eye diagram of the most significant bit (MSB) signal after synchronous equalization and decoding of a simulated 56Gb / s PAM4 signal; Figure 7 The image shows the eye diagram of the LSB signal after synchronous equalization and decoding of a simulated 56Gb / s PAM4 signal. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below.

[0017] This invention provides a synchronous equalization-decoding circuit. Compared to the step equalization and decoding circuits of traditional PAM4 receivers, this synchronous equalization-decoding circuit eliminates the need to convert the PAM4 signal into thermometer code, thus simplifying the signal processing flow. Furthermore, since the decision unit used in this invention implements thresholdless decision-making, the matching problem between the threshold voltage and the signal is avoided, reducing the output jitter of the decision unit.

[0018] A synchronous equalization-decoding circuit, comprising: A two-stage cascaded continuous-time linear equalizer (CTLE) is used to achieve initial equalization of channel loss. A two-stage cascaded broadband amplifier is used to increase the signal amplitude and improve the response speed of the decision circuit. Four current-mode logic (CML) based adders are used. The two adders in the most significant bit (MSB) feedback loop contain one branch for eliminating backward inter-symbol interference (ISI). The two adders in the least significant bit (LSB) feedback loop contain two branches, one for eliminating ISI and the other for eliminating the MSB component of the signal, so that the decision unit can directly decode the least significant bit (LSB). Four double-tailed decision units are used to compare differential signals to realize the decision and decoding of PAM4 signals; Two gate-voltage bootstrap high-speed differential sample-and-hold units are used to delay the input signal to achieve LSB decoding of the PAM4 signal.

[0019] The input signal passes through a continuous-time linear equalizer and a broadband amplifier in sequence for preliminary equalization and processing. At the output of the broadband amplifier, the signal is divided into two half-rate equalization and decoding paths with the same circuit architecture. In one path, the output signal of the broadband amplifier is input into the adder. After equalization, one path is decoded by the decision unit to obtain the MSB signal and output. The other path is input to the next stage adder after a delay through the sample-and-hold unit. After equalization and level shifting, the decision unit decodes the LSB signal and outputs it. Both the MSB signal and the LSB signal are fed back to the taps of the adder to participate in signal equalization.

[0020] Example 1 The synchronous equalization-decoding circuit provided by the present invention will be further described below with reference to the accompanying drawings and embodiments, as detailed in the following description: Figure 1 This is a schematic diagram of the step equalization and decoding circuit of a traditional PAM4 receiver. Decision Feedback Equalization (DFE) converts the PAM4 signal into three thermometer codes (DL, DM, and DH) using three decision circuits with different reference threshold voltages. Since the PAM4 code DPAM4 is a linear combination of the three thermometer codes, delaying and feeding back the thermometer codes achieves the equalization purpose of eliminating backward inter-symbol interference. During decoding, the MSB decoding signal DMSB is the same as DM and can be directly output; however, the LSB decoding signal DLSB is an XOR operation of the three thermometer codes, requiring a three-input XOR gate to complete the decoding.

[0021] In traditional PAM4 receiver architectures, each decision feedback loop requires three thermometer codes, and the adder needs three branches for feedback. Therefore, an additional load capacitor is introduced at the adder's output in each branch, thus reducing the adder's output bandwidth. Furthermore, maintaining signal path consistency across the three thermometer codes places stringent requirements on circuit design and layout. In actual layout design, differences in the signal paths of the three thermometer codes can introduce phase differences, thereby increasing the timing jitter of the LSB decoded signal.

[0022] Figure 2This is a schematic diagram of the synchronous equalization-decoding circuit for a PAM4 receiver proposed in an embodiment of the present invention. The differential PAM4 signal, after backplane channel loss, is input to a continuous-time equalizer (CTLE) for initial equalization in the frequency domain. Subsequently, two stages of broadband amplifiers adjust the amplitude and common-mode level of the received signal. Finally, a half-rate decision feedback equalizer-decoder (DFE-DE) completes the equalization and decoding operations. In short-range backplane communication, channel loss is generally small, and the continuous-time equalizer (CTLE) can suppress most inter-symbol interference (ISI). The residual ISI at a specific symbol in its output signal is mainly backward ISI from the previous symbol. Therefore, a single-tap architecture can be used to eliminate residual ISI.

[0023] Example 2 The circuit architecture of the equalizer-decoder (DFE-DE) is explained in detail below with reference to the workflow.

[0024] The half-rate decision feedback equalizer-decoder (DFE-DE) consists of two signal paths: an odd path and an even path, both driven by a pair of half-rate inverted clocks. If only the main residual inter-symbol interference is considered, the input signal DISI[k] can be expressed as:

[0025] Since the PAM4 signal is a linear combination of the MSB and LSB signals, DISI[k] can be decomposed as:

[0026] In the odd-path signal path, the input of the adder for the most significant bit (MSB) is connected to a wideband amplifier, and the output is connected to the MSB decision unit and a sample-and-hold unit. The MSB decision unit performs MSB decoding, outputting the odd-path MSB decoded signal DMSB1, which is then input to the taps of the odd-path LSB adder and the even-path MSB adder. Similarly, the even-path MSB decision unit outputs the even-path MSB decoded signal DMSB2, which is also input to the taps of the even-path LSB adder and the odd-path MSB adder. When the tap coefficient is set to... At that time, the MSB adder eliminates the MSB component of intersymbol interference by feeding back the MSB signal. This reduces overall inter-symbol interference to one-third of its original level. With sufficient eye opening, the MSB decision unit can achieve accurate decision-making. The two MSB adders and the MSB decision unit together form the MSB decision-feedback loop.

[0027] In the odd-path signal path, the sample-and-hold unit delays the output signal of the MSB adder by one signal cycle before inputting it into the LSB adder. After level shifting and inter-symbol interference (ISI) cancellation, the LSB adder outputs the signal to the LSB decision unit to complete LSB decoding, outputting the odd-path LSB decoded signal DLSB1, which is then input to the tap of the even-path LSB adder. The LSB adder consists of two taps, one of which is connected to the MSB signal obtained from the decision, and then... Figure 3 The level shift shown eliminates the MSB component in the PAM4 signal, i.e. The PAM4 signal is converted to an NRZ signal; another tap is connected to the feedback LSB signal to eliminate the LSB component of intersymbol interference. Similarly, the even-path LSB decision unit outputs the even-path LSB decoding signal DLSB2, which is then input to the tap of the odd-path LSB adder. The two LSB adders and the LSB decision unit together form the LSB decision feedback loop.

[0028] The circuit simulation selected a short-range backplane channel model with a channel loss of 12.5 dB at 14 GHz. The 56 Gb / s PAM4 signal was passed through this channel loss and used as the input signal Din of this embodiment of the invention. A pair of inverted clocks with a frequency of 14 GHz were connected to verify the function of the synchronous equalization-decoding circuit described in this embodiment of the invention.

[0029] Figure 4 This is the simulated signal eye diagram after CTLE equalization. After CTLE equalization, the originally closed signal eye diagram is opened to some extent, but the eye width is only 0.42 UI. Figure 5 The pulse response results show that the forward inter-symbol interference (ISI) is almost completely eliminated. The backward ISI at one symbol is 0.11, and the backward ISI at two symbols is 0.03. Therefore, the ISI is mainly the backward ISI at the first symbol. Figure 2 After the synchronous equalization-decoding circuit proposed in the embodiment of the present invention (where the DFE-DE tap coefficient is set to 0.07), the decoded MSB and LSB eye diagrams are as follows. Figure 6 and Figure 7 As shown in the figure, the decoded eye widths all reach over 0.94 UI, achieving low-jitter output.

[0030] In summary, the synchronous equalization-decoding circuit for the PAM4 receiver proposed in this invention is expected to achieve high-speed PAM4 signal reception with a single-channel rate exceeding 50 Gb / s. Compared with the step-equalization and decoding circuits of traditional PAM4 receivers, the synchronous equalization-decoding circuit proposed in this invention has advantages such as simple circuit structure, small chip area, synchronous equalization and decoding without the need for a reference threshold voltage, and low output signal jitter. Therefore, this invention provides a new solution to address the rate limitations of high-speed backplane Ethernet.

[0031] Unless otherwise specified, the model numbers of the various devices in this embodiment of the invention are not limited, and any device that can perform the above functions is acceptable.

[0032] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of a preferred embodiment, and the sequence numbers of the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0033] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A synchronous equalization-decoding circuit for a PAM4 receiver, characterized in that, The circuit includes: A two-stage cascaded continuous-time linear equalizer is used to achieve initial equalization of channel loss. A two-stage cascaded broadband amplifier is used to increase the signal amplitude; Four current-mode logic adders are used to superimpose input levels; Four dual-tailed decision units are used to compare differential signals to realize the decision and decoding of PAM4 signals; Two gate-voltage bootstrap high-speed differential sample-and-hold units are used to delay the input signal to achieve LSB decoding of PAM4 signals; The input signal passes through a continuous-time linear equalizer and a broadband amplifier in sequence for preliminary equalization and processing; at the output of the broadband amplifier, the signal is divided into two half-rate equalization and decoding paths with the same circuit architecture. In one path, the output signal of the broadband amplifier is input into the adder. After equalization, one path is decoded by the decision unit to obtain the MSB signal and output. The other path is input to the next stage adder after a delay through the sample-and-hold unit. After equalization and level shifting, the decision unit decodes the LSB signal and outputs it. Both the MSB signal and the LSB signal are fed back to the taps of the adder to participate in signal equalization.

2. The synchronous equalization-decoding circuit for a PAM4 receiver according to claim 1, characterized in that, The four current-mode logic-based adders are: The two adders in the MSB feedback loop contain a branch for eliminating backward inter-symbol interference; The two adders in the Least Significant Bit (LSB) feedback loop contain two branches: one branch is used to eliminate backward intersymbol interference (ISI), and the other branch is used to eliminate the Most Significant Bit (MSB) component of the signal, enabling the decision unit to directly decode the LSB.

3. The synchronous equalization-decoding circuit for a PAM4 receiver according to claim 2, characterized in that, The adder includes two signal paths: an odd path and an even path. Both paths are driven by a pair of half-rate inverted clocks. The input signal DISI[k] is represented as: ； DISI[k] is decomposed into: 。 4. The synchronous equalization-decoding circuit for a PAM4 receiver according to claim 3, characterized in that, In the odd-path signal path, the input of the adder for the most significant bit (MSB) is connected to a wideband amplifier, and the output is connected to the MSB decision unit and the sample-and-hold unit. The MSB decision unit completes the MSB decoding, outputs the odd-path MSB decoded signal DMSB1, and inputs it to the taps of the odd-path LSB adder and the even-path MSB adder.

5. A synchronous equalization-decoding circuit for a PAM4 receiver according to claim 3, characterized in that, The even-path MSB decision unit outputs the even-path MSB decoding signal DMSB2, and inputs it to the taps of the even-path LSB adder and the odd-path MSB adder. When the tap factor is set to At that time, the MSB adder eliminates the MSB component of intersymbol interference by feeding back the MSB signal. This reduces the overall inter-symbol interference to one-third of its original value; the two MSB adders and MSB decision units together form an MSB decision-feedback loop.

6. A synchronous equalization-decoding circuit for a PAM4 receiver according to claim 3, characterized in that, After level shifting and inter-symbol interference cancellation, the LSB adder outputs the signal to the LSB decision unit to complete LSB decoding, outputting the odd-path LSB decoding signal DLSB1, and inputting it to the tap of the even-path LSB adder. The LSB adder consists of two taps. One tap is connected to the MSB signal obtained from the decision, and the level is shifted to eliminate the MSB component in the PAM4 signal. The PAM4 signal is converted to an NRZ signal; another tap is connected to the feedback LSB signal to eliminate the LSB component of intersymbol interference. .

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