Image decoding device and method

Abstract

The invention relates to an image decoding device and method. An image decoding method includes: determining an occurrence of an error block for an Nth image picture generated according to an inter-image coding technique; enabling the image encoding device to receive error return information when the image decoding device receives the corresponding block of the (N + P-1) th image picture, and encoding the (N + Pth) th image picture according to an inter-image encoding technology; capturing motion vector information and residual value information of a block before the error block occurs in the Nth image picture, and decoding according to an inter-image coding technology; setting the motion vector information and the residual value information to be zero, and decoding a block from the error block to the last block of the (N + P-1) th image picture according to an inter-image coding technology; and capturing motion vector information and residual value information corresponding to blocks of the (N + P) th image picture, and decoding the blocks according to an inter-image coding technology.

Description

Technical Field

[0001] This invention relates to image decoding technology, and more particularly to an image decoding apparatus and method. Background Technology

[0002] As consumers demand more multimedia entertainment and higher display quality, the requirements for resources related to video content processing, transmission, and storage, such as memory size and bandwidth, are also increasing. Many standards have been established to ensure the display quality of video content, while significant progress has also been made in compression and decompression efficiency.

[0003] However, data loss is inevitable during video streaming. When data is lost, the video decoding device will be unable to decode based on the information transmitted by the video encoding device, such as motion vector information and residual information. Without a corresponding mechanism, the video decoding device will be unable to decode normally in such a situation, let alone generate a decoded video image. Summary of the Invention

[0004] In view of the problems of the prior art, one object of the present invention is to provide an image decoding apparatus and method to improve the prior art.

[0005] This invention includes an image decoding method applied in an image decoding device, comprising: determining the occurrence of an error block in an Nth image frame generated by inter-image coding technology from an image stream from an image encoding device, where N is an integer greater than 1; transmitting error reporting information to the image encoding device, so that the image encoding device receives the error reporting information when the image decoding device receives the corresponding block of the N+P-1th image frame in the image stream, and the image encoding device encodes the N+Pth image frame in the image stream according to the inter-image coding technology with reference to a reference image frame before the Nth image frame where no error occurred, where P is an integer greater than or equal to 1; extracting motion vector information and residual information of multiple first blocks in the corresponding Nth image frame before the occurrence of the error block from the image stream, so as to perform a decoding procedure on the first blocks according to the inter-image coding technology to generate a first decoding result; setting the motion vector information as a zero vector. The vector is set to zero, and the residual information is used to perform a decoding procedure on multiple second blocks from the error block to the last block of the N+P-1th image frame according to the inter-image coding technique to generate a second decoding result; and the motion vector information and residual information of multiple inter-image reference blocks corresponding to the N+Pth image frame are extracted from the image stream to perform a decoding procedure on the inter-image reference blocks according to the inter-image coding technique to generate an inter-image reference decoding result.

[0006] The present invention further includes an image decoding apparatus, comprising: a front-end decoding circuit and a back-end decoding circuit. The front-end decoding circuit is configured to: determine the occurrence of an error block in the Nth image frame generated by inter-image coding technology from the image stream from the image encoding device, where N is an integer greater than 1; and transmit error reporting information to the image encoding device, so that the image encoding device receives the error reporting information when the image decoding device receives the corresponding block of the N+P-1th image frame in the image stream, and enables the image encoding device to encode the N+Pth image frame in the image stream according to the inter-image coding technology with reference to a reference image frame before the Nth image frame where no error occurred, where P is an integer greater than or equal to 1. The back-end decoding circuit is configured to: when the front-end decoding circuit extracts motion vector information and residual value information of multiple first blocks before the occurrence of the error block in the corresponding Nth image frame from the image stream, perform a decoding procedure on the first block according to the inter-image coding technique to generate a first decoding result; when the front-end decoding circuit sets the motion vector information to a zero vector and sets the residual value information to a zero value, perform a decoding procedure on multiple second blocks from the error block to the last block of the N+P-1th image frame according to the inter-image coding technique to generate a second decoding result; and when the front-end decoding circuit extracts motion vector information and residual value information of multiple inter-image reference blocks in the corresponding N+Pth image frame from the image stream, perform a decoding procedure on the inter-image reference blocks according to the inter-image coding technique to generate an inter-image reference decoding result.

[0007] Regarding the features, implementation, and effects of this case, the preferred embodiments are described in detail below with reference to the drawings. Attached Figure Description

[0008] Figure 1 This shows a block diagram of an image encoding device and an image decoding device according to one embodiment of the present invention;

[0009] Figure 2A This diagram illustrates a plurality of image frames transmitted by an image stream in one embodiment of the present invention.

[0010] Figure 2B This diagram illustrates a plurality of image frames transmitted by an image stream in one embodiment of the present invention; and

[0011] Figure 3 This diagram shows a flowchart of an image decoding method according to one embodiment of the present invention. Detailed Implementation

[0012] One objective of this invention is to provide an image decoding apparatus and method. When an erroneous block is determined to occur in the Nth image frame, the motion vector information is set to a zero vector and the residual value information is set to a zero value. Decoding is performed on the image blocks from the erroneous block up to the last block of the N+P-1th image frame where the corresponding block for which the image encoding device receives the error report information. Furthermore, the inter-image reference block of the N+Pth image frame is decoded by referencing the decoded image frame of a previous reference image frame that did not experience an error, using inter-image coding techniques. This approach allows the decoding process to continue while preventing the decoding program from referencing erroneous image data, thus improving the accuracy of the decoded image frames.

[0013] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of an image encoding device 100 and an image decoding device 110 according to one embodiment of the present invention.

[0014] The image encoding device 100 is configured to perform FM on multiple image frames according to an inter-image encoding technique, for example... Figure 1 The exemplary N-1th image frame FM N-1 The Nth video frame FM N ..., the N+Pth video frame FM N+P Encode the video stream IS. Here, N is an integer greater than 1, and P is an integer greater than or equal to 1.

[0015] To be more specific, FM using the Nth video frame N Taking the image frame to be encoded as an example, the image encoding device 100 encodes it according to the corresponding reference image data. The image encoding device 100 can use inter-frame encoding technology to enable FM encoding of the Nth image frame. N At least one previous image frame is used as reference image data. For example, when the reference image data is the previous image frame, the image encoding device 100 will make the (N-1)th image frame FM. N-1 FM for the Nth image frame as reference image data N Encoding is performed. However, in other embodiments, the image encoding device 100 may also FM the Nth image frame. N The first K images (not shown in the figure) are used as reference image data, or the Nth image is FM. N Multiple preceding images are used as reference image data. This invention is not limited thereto.

[0016] On the other hand, the image encoding device 100 can also use intra-frame encoding technology to enable the Nth image frame to be encoded to FM. NUse its own internal image content as reference image data.

[0017] In accordance with the inter-image coding technique, the image coding device 100 performs motion compensation on the motion vector information of the current image relative to the reference image data to obtain residual information, and performs processing such as, but not limited to, discrete cosine transform (DCT), quantization, and entropy coding to generate an image stream IS.

[0018] On the other hand, in accordance with the intra-image coding technology, the image coding device 100 performs processing on the current image frame, such as, but not limited to, discrete cosine transformation, quantization and entropy coding, to generate an image stream IS.

[0019] The image decoding device 110 is configured to receive and decode the image stream IS to generate multiple decoded image frames FD, for example... Figure 1 The (N-1)th decoded image frame FD shown N-1 The Nth decoded image frame FD N ..., the N+Pth decoded image frame FD N+P The image decoding device 110 includes a front-end decoding circuit 120 and a back-end decoding circuit 130.

[0020] The front-end decoding circuit 120 is configured to perform processing on the video stream IS, such as, but not limited to, entropy decoding, inverse quantization (IQ), and inverse discrete cosine transform (IT), to extract motion vector information MV and residual information RES corresponding to different video frames.

[0021] The back-end decoding circuit 130 is configured to perform a decoding process. In one embodiment, the back-end decoding circuit 130 includes an estimation circuit 140, an image reconstruction circuit 150, and a deblocking operation circuit 160.

[0022] Corresponding to the inter-image coding technique, the estimation circuit 140 calculates and generates multiple estimated pixels EP based on the reference image data RD and motion vector information MV during the decoding process. The image reconstruction circuit 150 calculates and generates multiple reconstructed pixels RP based on the estimated pixels EP and residual information RES. The deblocking circuit 160 performs deblocking operations based on the reconstructed pixels RP to generate a decoding result, and then outputs the decoded image frame FD based on the decoding result. The decoded image frame FD can be fed back to the estimation circuit 140 as the reference image data RD.

[0023] In the corresponding intra-image coding technique, since motion compensation is not required, the front-end decoding circuit 120 does not need to extract the corresponding motion vector information MV, but only the corresponding residual information RES. The estimation circuit 140 can calculate and generate estimated pixels EP based on the decoded portion of the same image frame as reference image data RD. The image reconstruction circuit 150 calculates and generates reconstructed pixels RP based on the estimated pixels EP and the residual information RES. The reconstructed pixels RP can be fed back to the estimation circuit 140 as the reference image data RD as the decoded portion of the same image frame. The deblocking circuit 160 performs deblocking operations based on the reconstructed pixels RP to generate a decoding result, and then outputs the decoded image frame FD based on the decoding result.

[0024] In some usage scenarios, data loss may occur in the video stream IS, causing the video decoding device 110 to detect an error. The following will use the (N-1)th video frame FM of the video stream IS as an example. N-1 The Nth video frame FM N ..., the N+Pth video frame FM N+P The Nth video frame in FM N Using the detection of errors as an example, the processing mechanism of the image decoding device 110 will be explained.

[0025] Please refer to Figure 2A . Figure 2A This diagram illustrates multiple image frames transmitted by an image stream IS in one embodiment of the present invention. More specifically, in Figure 2A The image in the middle is the (N-1)th image frame (FM) transmitted by the video stream IS. N-1 The Nth video frame FM N And the N+1th video frame FM N+1 .

[0026] In one embodiment, each image frame in the image stream IS is like the Nth image frame FM. N The image shown comprises multiple image processing blocks separated by solid lines. These image processing blocks have a size that can be read and processed by the front-end decoding circuit 120, for example, a size of 32×32. Figure 2A In the image, only one image processing block 200 is represented. Each image processing block contains multiple coding unit blocks separated by dashed lines. These coding unit blocks are the block size for one encoding operation by the image coding device 100, for example, 16×16. Figure 2AIn this example, only one coding unit block 210 is marked in the image processing block 200. It should be noted that the size of the image processing block and the coding unit block, as well as the number of coding unit blocks contained in the image processing block, are merely examples. The present invention is not limited thereto.

[0027] The front-end decoding circuit 120 generates the Nth image frame FM from the image stream IS from the image encoding device 100 according to the inter-image coding technique. N The occurrence of an erroneous block EB is determined. In one embodiment, the front-end decoding circuit 120 determines the size of the layer of the aforementioned coding unit block. Therefore, the erroneous block EB has the same size as the coding unit block.

[0028] Once the front-end decoding circuit 120 determines that an error block EB has occurred, the front-end decoding circuit 120 transmits error report information ER to the video encoding device 100, so that the video encoding device 100 can receive the N+P-1th video frame FM in the video stream from the video decoding device 110. N+P-1 When the corresponding block CB is reached, an error report message ER is received. In this embodiment, P is 1. In other words, in Figure 2A In the image, the corresponding block CB is located in the Nth image frame FM. N middle.

[0029] The image encoding device 100 will view the N+Pth image frame in FM mode. N+P (In this embodiment, the N+1th image frame is FM) N+1 () is a new image slice, referencing the Nth image frame FM according to inter-image coding techniques. N Previously error-free reference image frames are used to encode image frames in the image stream IS. In one embodiment, the reference image frame is the Nth image frame FM. N The previous video frame, that is, the (N-1)th video frame FM N-1 .

[0030] The front-end decoding circuit 120 captures the corresponding Nth video frame (FM) from the video stream IS. N The movement vector information MV and residual information RES of multiple first blocks 220 prior to the occurrence of the erroneous block EB. Figure 2A In the diagram, the first block 220 before the occurrence of error block EB is depicted as a block with a forward slash.

[0031] The back-end decoding circuit 130 performs a decoding procedure on the first block 200 according to the image inter-coding technology to generate the first decoding result DR1.

[0032] More specifically, for the Nth image frame FM NThe back-end decoding circuit 130 captures previously decoded image frames according to inter-image coding techniques (e.g., the estimation circuit 140 receives the decoded image frame FD fed back from the deblocking operation circuit 160). N-1 The first block 220 is decoded using the reference image data RD. In the decoding process, the estimation circuit 140 calculates and generates the estimated pixel EP based on the reference image data RD and the motion vector information MV. The image reconstruction circuit 150 calculates and generates the reconstructed pixel RP based on the estimated pixel EP and the residual information RES. The deblocking operation circuit 160 performs deblocking operation based on the reconstructed pixel RP to generate the first decoding result DR1.

[0033] On the other hand, the front-end decoding circuit 120 sets the movement vector information MV to a zero vector and sets the residual information RES to a zero value.

[0034] The back-end decoding circuit 130 uses inter-image coding technology to FM the image from the error block EB to the N+P-1th image frame. N+P-1 (In this embodiment, the Nth image frame is FM) N The final block of the last block of the ) is decoded by multiple second blocks 230 to produce a second decoding result DR2. Figure 2A In the middle, the error block EB to the Nth image frame FM N The second block 230 of the last block is drawn as a dotted block.

[0035] More specifically, the back-end decoding circuit 130 still uses FM corresponding to the (N-1)th image frame. N-1 Previous decoded video footage FD N-1 As reference image data RD, the second block 230 undergoes a decoding process. The estimation circuit 140 calculates an estimated pixel EP based on the reference image data RD and the zero-valued motion vector information MV. The image reconstruction circuit 150 calculates a reconstructed pixel RP based on the estimated pixel EP and the zero-valued residual information RES. Finally, the deblocking circuit 160 performs a deblocking operation based on the reconstructed pixel RP to generate a second decoding result DR2. Since the motion vector information MV is a zero vector and the residual information RES is zero, the second decoding result DR2 is equivalent to copying the content of the reference image data RD.

[0036] The back-end decoding circuit 130 outputs the first decoding result DR1 and the second decoding result DR2 as the Nth decoded image frame FD. N More specifically, after generating the first decoding result DR1 and the second decoding result DR2, the deblocking circuit 160 of the back-end decoding circuit 130 merges the first decoding result DR1 and the second decoding result DR2 to output the Nth decoded image frame FD.N .

[0037] Therefore, in this embodiment, the Nth image frame FM N The first block 220 in the reference is the (N-1)th image frame FM. N-1 Multiple blocks 240 in the image are generated based on the motion vector information MV and residual information RES transmitted from the image encoding device 100. Figure 2A In the middle, block 240 is drawn as a blank block. On the other hand, the Nth image frame FM N The second block 230 is equivalent to copying the (N-1)th image frame FM. N-1 Multiple blocks 250 within. Figure 2A In the diagram, block 250 is depicted as a gray block.

[0038] In this embodiment, the N+Pth image frame FM N+P (In this embodiment, the N+1th image frame is FM) N+1 It contains only multiple inter-image reference blocks 260. Figure 2A In the image reference block 260, the area between images is drawn as a reverse diagonal block.

[0039] The front-end decoding circuit 120 captures the corresponding (N+1)th video frame (FM) from the video stream IS. N+1 The image reference block 260 contains the motion vector information MV and residual information RES.

[0040] The back-end decoding circuit 130 performs a decoding procedure on the inter-image reference block 260 according to the inter-image coding technology to generate the inter-image reference decoding result ITE.

[0041] More specifically, due to the Nth image frame FM N The decoding result of the second block 230 is a copy of the N-1th video frame FM. N Block 250 is derived from this and has no reference value. Therefore, the back-end decoding circuit 130 extracts previously decoded image frames as reference image data RD according to the inter-image coding technique to perform the decoding process on the inter-image reference block 260. Among them, the previously decoded image frame is the Nth image frame FM. N The decoded video frame corresponding to the previous video frame where no error occurred, such as the previous video frame, i.e., the (N-1)th video frame FM. N-1 The corresponding decoded image screen. The estimation circuit 140, the image reconstruction circuit 150, and the deblocking operation circuit 160 sequentially perform the decoding process to generate the inter-image reference decoding result ITE.

[0042] The back-end decoding circuit 130 further outputs the inter-image reference decoding result ITE as the (N+1)th decoded image frame FD. N+1 More specifically, after generating the inter-image reference decoding result ITE, the deblocking operation circuit 160 of the back-end decoding circuit 130 will output the inter-image reference decoding result ITE as the (N+1)th decoded image frame FD. N+1 .

[0043] Figure 2B This diagram illustrates multiple image frames transmitted by an image stream IS in one embodiment of the present invention. More specifically, in Figure 2B The image in the middle is the (N-1)th image frame (FM) transmitted by the video stream IS. N-1 The Nth video frame FM N The N+1th video frame FM N+1 And the N+2nd video frame FM N+2 .

[0044] The aforementioned image frame includes content such as image processing blocks and, more specifically, encoding unit blocks within those image processing blocks. Figure 2A The same applies, so I won't repeat it here.

[0045] Similar to correspondence Figure 2A The operation mode of the front-end decoding circuit is 120 pairs of the Nth image frame FM. N The system determines the occurrence of an erroneous block EB and transmits an error report message ER to the image encoding device 100, so that the image encoding device 100 can receive the N+P-1th image frame FM from the image stream in the image decoding device 110. N+P-1 When the corresponding block CB is reached, an error report message ER is received. In this embodiment, the value of P is greater than 1, and in Figure 2B This is illustrated using a value of P equal to 2. In other words, in Figure 2B In the image, the corresponding block CB is located in the (N+1)th image frame FM. N+1 middle.

[0046] The image encoding device 100 will view the N+Pth image frame in FM mode. N+P (In this example, the N+2th video frame is FM) N+2 () is a new image slice, referencing the Nth image frame FM according to inter-image coding techniques. N The reference image frame that did not previously cause an error is compared to the N+Pth image frame FM in the video stream IS. N+P Encoding. Similarly, in one embodiment, this reference image frame is the image frame preceding the Nth image frame, i.e., the (N-1)th image frame FM. N-1 .

[0047] The front-end decoding circuit 120 and the back-end decoding circuit 130 FM the Nth image frame. N The processing method performed on the first block 220 before the occurrence of the erroneous block EB is the same as Figure 2A The same applies, and the first decoding result DR1 is generated by the back-end decoding circuit 130, which will not be described in detail here.

[0048] On the other hand, the front-end decoding circuit 120 sets the movement vector information MV to a zero vector and sets the residual information RES to a zero value.

[0049] The back-end decoding circuit 130 uses inter-image coding technology to FM the image from the error block EB to the N+P-1th image frame. N+P-1 (In this example, the N+1th video frame is FM) N+1 The final block of the last block of the ) is decoded by multiple second blocks 230 to produce a second decoding result DR2. Figure 2B In the middle, the error block EB to the N+1th image frame FM N+1 The second block 230 of the last block is drawn as a dotted block.

[0050] More specifically, the back-end decoding circuit 130 corresponds to the (N-1)th video frame in FM mode. N-1 Previous decoded video footage FD N-1 As reference image data RD, for the Nth image frame FM N The second block 230 is subjected to a decoding process, which is sequentially processed by the estimation circuit 140, the image reconstruction circuit 150 and the deblocking operation circuit 160 to produce the first part of the second decoding result DR2.

[0051] The back-end decoding circuit 130 outputs the first decoding result DR1 and the first part of the second decoding result DR2 as the Nth decoded image frame FD. N More specifically, after generating the first decoding result DR1 and the first part of the second decoding result DR2, the deblocking circuit 160 of the back-end decoding circuit 130 merges the first decoding result DR1 and the first part of the second decoding result DR2 to output the Nth decoded image frame FD. N .

[0052] Furthermore, the back-end decoding circuit 130 corresponds to the Nth image frame in FM mode. N Previous decoded video footage FD N As reference image data RD, for the N+1th image frame FM N+1The second block 230 is subjected to a decoding process, which is sequentially processed by the estimation circuit 140, the image reconstruction circuit 150 and the deblocking operation circuit 160 to produce the second part of the second decoding result DR2.

[0053] The back-end decoding circuit 130 outputs the second part of the second decoding result DR2 as the (N+1)th decoded image frame FD. N+1 More specifically, after generating the second part of the second decoding result DR2, the deblocking operation circuit 160 of the back-end decoding circuit 130 will output the second part of the second decoding result DR2 as the (N+1)th decoded image frame FD. N+1 .

[0054] Since the motion vector information MV is a zero vector and the residual information RES is zero, the first part of the second decoding result DR2 (i.e., the Nth decoded image frame FD) N The portion corresponding to the second block 230 is equivalent to the content of the corresponding reference image data RD, that is, the (N-1)th decoded image frame FD. N-1 The portion corresponding to block 250 is copied over. The second part of the second decoding result DR2 (i.e., the N+1th decoded image frame FD) is also copied over. N+1 This is equivalent to referencing the content of the image data RD, which is the Nth decoded image frame FD. N Copy it over.

[0055] It should be noted that when P is any integer greater than 2, the back-end decoding circuit 130 can output the second part of the second decoding result DR2 as the (N+1)th to (N+P-1)th decoded image frames in the manner described above. Furthermore, when P is any integer greater than 2, the (N+1)th to (N+P-1)th decoded image frames are equivalent to being copied sequentially from one another.

[0056] In this embodiment, the N+Pth image frame FM N+P (In this embodiment, the N+2th image frame is FM) N+2 It contains only multiple inter-image reference blocks 260. Figure 2A In the image reference block 260, the area between images is drawn as a reverse diagonal block.

[0057] The front-end decoding circuit 120 captures the corresponding (N+2)th video frame (FM) from the video stream IS. N+2 The image reference block 260 contains the motion vector information MV and residual information RES.

[0058] The back-end decoding circuit 130 performs a decoding procedure on the inter-image reference block 260 according to the inter-image coding technique to generate an inter-image reference decoding result ITE, and the decoding procedure performed by the back-end decoding circuit 130 is consistent with the corresponding... Figure 2A The decoding procedure is the same and will not be repeated here.

[0059] The back-end decoding circuit 130 further outputs the inter-image reference decoding result ITE as the N+Pth decoded image frame FD. N+P (In this example, the N+2nd decoded image frame is FD) N+2 More specifically, after generating the inter-image reference decoding result ITE, the deblocking operation circuit 160 of the back-end decoding circuit 130 will output the inter-image reference decoding result ITE as the N+2th decoded image frame FD. N+2 .

[0060] In one embodiment, in both of the above embodiments, the image encoding device 100 can, without receiving the image decoding device 110's FM image related to the (N+P)th image frame... N+P When checking the error report, determine the N+Pth video frame FM. N+P No error block occurred, and the next (N+P+1) video frame is referenced to the previously preset video frame using inter-video coding technology (e.g., the previous video frame, i.e., the N+Pth video frame FM). N+P The image decoding device 110 uses the corresponding motion vector information and residual information based on the inter-image coding technique to perform the decoding process, instead of referring to the decoded image corresponding to the reference image that did not have an error before the Nth image. However, the present invention is not limited thereto.

[0061] In some technologies, when data loss occurs in the received video stream, the image decoding device will be unable to extract the motion vector information and residual information of the image, and thus will be unable to correctly generate the decoded image.

[0062] The image decoding apparatus of this invention, when determining that an erroneous block has occurred in the Nth image frame, sets the motion vector information to a zero vector and the residual value information to a zero value. It then decodes the image blocks from the erroneous block up to the last block of the N+P-1th image frame containing the corresponding block where the image encoding apparatus receives the error report. Furthermore, it decodes the inter-image reference block of the N+Pth image frame by referencing the decoded image frame of a previous reference image frame that did not experience an error, using inter-image coding techniques. This approach allows the decoding process to continue while preventing the decoding program from referencing erroneous image data, thus improving the accuracy of the decoded image frames.

[0063] Please refer to Figure 3 . Figure 3 This diagram shows a flowchart of an image decoding method 300 according to one embodiment of the present invention.

[0064] In addition to the aforementioned apparatus, the present invention also discloses an image decoding method 300, applicable to, for example, but not limited to, [other applications]. Figure 1 In the image decoding apparatus 110. One of the image decoding methods 300 is implemented, for example. Figure 3 As shown, it includes the following steps.

[0065] In step S310, the Nth image frame FM generated from the image stream IS from the image encoding device 100 according to the inter-image coding technique is... N Determine if an erroneous block EB has occurred, where N is an integer greater than 1.

[0066] In step S320, error reporting information ER is transmitted to the image encoding device 100, so that the image encoding device 100 receives the N+P-1th image frame FM in the image stream from the image decoding device 110. N+P-1 When the corresponding block CB receives the error report information ER, the image encoding device 100 encodes the (N+P)th image in the image stream IS using inter-image encoding techniques, referencing a reference image that did not experience an error before the Nth image. N+P , where P is an integer greater than or equal to 1.

[0067] In step S330, the corresponding Nth image frame FM is captured from the image stream IS. N The motion vector information MV and residual information RES of the first block 220 before the occurrence of the error block are used to generate the first decoding result DR1 by decoding the first block 220 according to the inter-image coding technique.

[0068] In step S340, the motion vector information MV is set to zero and the residual information RES is set to zero, so as to process the FM from the error block to the N+P-1th image frame according to the inter-image coding technique. N+P-1 The second block 230 of the last block is decoded to produce the second decoding result DR2.

[0069] In step S350, the corresponding N+P-th image frame FM is captured from the image stream IS. N+P The motion vector information MV and residual information RES of the inter-image reference block 260 are used to generate the inter-image reference decoding result ITE by decoding the inter-image reference block 260 according to the inter-image coding technique.

[0070] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0071] In summary, the image decoding apparatus and method of the present invention, when determining that an erroneous block has occurred in the Nth image frame, sets the motion vector information to a zero vector and the residual value information to a zero value, and decodes these image blocks from the erroneous block up to the last block of the N+P-1th image frame where the corresponding block of the image encoding device receives the error report information. Furthermore, the inter-image reference block of the N+Pth image frame is decoded by referencing the decoded image frame of the previous reference image frame that did not experience an error, using inter-image coding techniques. This approach allows the decoding process to continue while preventing the decoding program from referencing erroneous image data, thus improving the accuracy of the decoded image frames.

[0072] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

[0073] Symbol Explanation

[0074] 100: Image encoding device

[0075] 110: Image decoding device

[0076] 120: Front-end decoding circuit

[0077] 130: Back-end decoding circuit

[0078] 140: Estimation Circuit

[0079] 150: Image Reconstruction Circuit

[0080] 160: Deblocking circuit

[0081] 200: Image Processing Block

[0082] 210: Coding unit block

[0083] 220: Block 1

[0084] 230: Second Block

[0085] 240, 250: Blocks

[0086] 260: Inter-image reference block

[0087] 300: Image Decoding Methods

[0088] S310~S350: Steps

[0089] CB: Corresponding block

[0090] DR1: First Decoding Result

[0091] DR2: Second Decoding Result

[0092] EB: Error Block

[0093] EP: Estimated Pixels

[0094] ER: Error Reporting Information

[0095] FD: Decoded video footage

[0096] FD N-1 The (N-1)th decoded image frame

[0097] FD N The Nth decoded image frame

[0098] FD N+1 The (N+1)th decoded image frame

[0099] FD N+2 The (N+2)th decoded image frame

[0100] FD N+P The N+Pth decoded image frame

[0101] FM: Video feed

[0102] FM N-1 The (N-1)th image frame

[0103] FM N The Nth image frame

[0104] FM N+1 The (N+1)th image frame

[0105] FM N+2 The N+2th image frame

[0106] FM N+P The N+Pth image frame

[0107] IS: Video Streaming

[0108] ITE: Inter-image reference decoding results

[0109] MV: Movement Vector Information

[0110] RD: Reference Image Data

[0111] RES: Residual Value Information

[0112] RP: Reconstructed Pixels

Claims

1. An image decoding method, applied in an image decoding device, comprising: For the video stream from the video encoding device, the occurrence of an error block is determined based on the Nth video frame generated by the inter-video encoding technique, where N is an integer greater than 1; Error reporting information is transmitted to the image encoding device so that the image encoding device receives the error reporting information when the image decoding device receives the corresponding block of the N+P-1th image frame in the image stream, and the image encoding device encodes the N+Pth image frame in the image stream with reference to the reference image frame before the Nth image frame that did not have an error, according to the inter-image coding technique, where P is an integer greater than or equal to 1; The motion vector information and residual information of multiple first blocks before the occurrence of the error block in the Nth image frame are extracted from the image stream, so as to generate a first decoding result by decoding the first blocks according to the inter-image coding technology. The motion vector information is set to a zero vector and the residual information is set to a zero value, so that the decoding procedure is performed on multiple second blocks from the error block to the last block of the N+P-1th image frame according to the image coding technique to generate a second decoding result. as well as The motion vector information and residual information of multiple inter-image reference blocks corresponding to the N+Pth image frame are extracted from the image stream, and the inter-image reference blocks are decoded according to the inter-image coding technology to generate inter-image reference decoding results.

2. The image decoding method according to claim 1, further comprising: The decoding process uses previously decoded image frames as reference image data, based on the inter-image coding technique; and The decoded portion of the N+Pth image frame is set as the reference image data for the decoding process based on the image coding technology.

3. The image decoding method according to claim 2, wherein the reference image frame is the (N-1)th image frame, and the image decoding method further comprises: For the N+Pth image frame, the previously decoded image frame corresponding to the N-1th image frame is extracted as the reference image data for the decoding process according to the inter-image coding technique.

4. An image decoding device, comprising: The front-end decoding circuit is configured as follows: In the video stream from the video encoding device, the occurrence of an error block is determined based on the Nth video frame generated by inter-video coding technology, where N is an integer greater than 1; and Error reporting information is transmitted to the image encoding device so that the image encoding device receives the error reporting information when the image decoding device receives the corresponding block of the N+P-1th image frame in the image stream, and the image encoding device encodes the N+Pth image frame in the image stream according to the inter-image coding technique, referring to a reference image frame that did not occur before the Nth image frame, where P is an integer greater than or equal to 1; the back-end decoding circuit is configured to: When the front-end decoding circuit extracts the motion vector information and residual information of multiple first blocks corresponding to the Nth image frame before the occurrence of the error block from the image stream, it performs a decoding procedure on the first blocks according to the inter-image coding technology to generate a first decoding result. When the front-end decoding circuit sets the motion vector information to a zero vector and the residual information to a zero value, it performs the decoding procedure on multiple second blocks from the error block to the last block of the N+P-1th image frame according to the image coding technique to generate a second decoding result. as well as When the front-end decoding circuit extracts the motion vector information and residual information of multiple inter-image reference blocks corresponding to the N+Pth image frame from the image stream, it performs the decoding procedure on these inter-image reference blocks according to the inter-image coding technology to generate inter-image reference decoding results.

5. The image decoding apparatus according to claim 4, wherein when P is 1, the back-end decoding circuit is configured as follows: The first decoding result and the second decoding result are output as the Nth decoded image frame; and The reference decoding result between the images is output as the N+1th decoded image frame.

6. The image decoding apparatus according to claim 4, wherein when P is greater than 1, the back-end decoding circuit is further configured to: The first decoding result and the first part of the second decoding result are output as the Nth decoded image frame; The second part of the second decoding result is output as the N+1th decoded image frame to the N+P-1th decoded image frame; and The reference decoding result between the images is output as the N+Pth decoded image frame.

7. The image decoding apparatus according to claim 4, wherein the back-end decoding circuit is configured to: The decoding process uses previously decoded image frames as reference image data, based on the inter-image coding technique; and The decoded portion of the N+Pth image frame is set as the reference image data for the decoding process based on the image coding technology.

8. The image decoding apparatus according to claim 7, wherein the reference image frame is the (N-1)th image frame, and the back-end decoding circuit is configured to: For the N+Pth image frame, the previously decoded image frame corresponding to the N-1th image frame is extracted as the reference image data for the decoding process according to the inter-image coding technique.

9. The image decoding apparatus according to claim 7, wherein the back-end decoding circuit comprises: An estimation circuit is configured to calculate and generate multiple estimated pixels in the decoding process based on the reference image data and the motion vector information, according to the inter-image coding technique. An image reconstruction circuit is configured to calculate and generate a plurality of reconstructed pixels in the decoding process based on the estimated pixels and the residual information. as well as The deblocking circuit is configured to perform deblocking operations on the reconstructed pixels in the decoding process to generate the first decoding result for the first block and the second decoding result for the second block.

10. The image decoding apparatus of claim 7, wherein the back-end decoding circuit comprises: An estimation circuit is configured to calculate and generate multiple estimated pixels based on the reference image data in the decoding process, according to the inter-image coding technique. Image reconstruction circuitry, configured to calculate and generate a plurality of reconstructed pixels in the decoding process based on the estimated pixels and the residual information; and The deblocking circuit is configured to perform deblocking operations on the reconstructed pixels in the decoding process to generate an inter-image reference decoding result corresponding to the inter-image reference blocks.

Images