Image sensor, camera and pixel signal conversion method

Abstract

The invention provides an image sensor, a camera and a pixel signal conversion method, and relates to the technical field of image sensors, first analog pixel signals of first pixel units in each odd-numbered line in a pixel unit column are converted into first digital pixel signals through a first analog-to-digital converter group corresponding to the pixel unit column, and the first digital pixel signals are converted into second digital pixel signals through a second analog-to-digital converter group corresponding to the first analog-to-digital converter group. And through a second analog-to-digital converter group corresponding to the pixel unit column, a second analog pixel signal of a second pixel unit in each even-numbered row in the pixel unit column is converted into a second digital pixel signal, so that analog pixel signals of two rows of pixel units in the pixel unit array can be processed in each period of the image sensor; compared with the prior art in which the image sensor processes the analog pixel signals of one row of pixel units in the pixel unit array in each period, the processing efficiency is improved.

Description

Technical Field

[0001] This application belongs to the field of image sensor technology, specifically relating to an image sensor, a camera, and a method for converting pixel signals. Background Technology

[0002] In prior art, image sensors process the analog pixel signals of a row of pixel units in a pixel unit array in each cycle, that is, read out the analog pixel signals of a column of pixel units row by row and convert them into digital pixel signals.

[0003] In the process of developing this application, the inventors discovered that the prior art has at least the following problem: because the image sensor processes the analog pixel signal of a row of pixel units in the pixel unit array in each cycle, the processing efficiency is low. Summary of the Invention

[0004] This application aims to provide an image sensor, a camera, and a method for converting pixel signals, which at least solves the problem of low processing efficiency in the prior art due to the image sensor processing the analog pixel signals of a row of pixel units in a pixel unit array in each cycle.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows:

[0006] In a first aspect, embodiments of this application provide an image sensor, including a pixel unit array, a plurality of first analog-to-digital converter groups and a plurality of second analog-to-digital converter groups, wherein each pixel unit column in the pixel unit array has a corresponding first analog-to-digital converter group and a corresponding second analog-to-digital converter group, and each pixel unit column has a corresponding first column line and a second column line;

[0007] The first pixel unit in each odd-numbered row of the pixel unit column is electrically connected to the first analog-to-digital converter group corresponding to the pixel unit column through the first column line; the second pixel unit in each even-numbered row of the pixel unit column is electrically connected to the second analog-to-digital converter group corresponding to the pixel unit column through the second column line.

[0008] Optionally, the image sensor further includes a first wafer and a second wafer, the pixel unit array is disposed on the first wafer, and the first analog-to-digital converter group and the second analog-to-digital converter group are both disposed on the second wafer.

[0009] Optionally, the first analog-to-digital converter group and the second analog-to-digital converter group are respectively disposed on the peripheral side of the second wafer.

[0010] Optionally, the first analog-to-digital converter group is disposed on the first side of the second wafer, and the second analog-to-digital converter group is disposed on the second side of the second wafer, with the first side and the second side being disposed opposite to each other.

[0011] Optionally, the pixel unit array is disposed in the central region of the first wafer.

[0012] Optionally, the plane of the first wafer is parallel to the plane of the second wafer.

[0013] Optionally, each of the first column lines has a first connection point disposed on the first wafer, each of the second column lines has a second connection point disposed on the first wafer, each of the first analog-to-digital converter groups has a third connection point disposed on the second wafer, and each of the second analog-to-digital converter groups has a fourth connection point disposed on the second wafer; the first connection point of the first column line is electrically connected to the third connection point of the first analog-to-digital converter group corresponding to the first column line; and the second connection point of the second column line is electrically connected to the fourth connection point of the second analog-to-digital converter group corresponding to the second column line.

[0014] Optionally, the first connection point is located at the first boundary of the region where the pixel unit array is located, the second connection point is located at the second boundary of the region where the pixel unit array is located, and the first boundary and the second boundary are opposite to each other; the third connection point is located at the geometric center of the region where the first analog-to-digital converter group is located, and the fourth connection point is located at the geometric center of the region where the second analog-to-digital converter group is located.

[0015] Optionally, the first analog-to-digital converter group includes two first analog-to-digital converters, and the image sensor further includes two first switches, each of which corresponds to one of the first analog-to-digital converters; the first analog-to-digital converter is electrically connected to each first pixel unit in the pixel unit column corresponding to the first analog-to-digital converter through the first switch corresponding to the first analog-to-digital converter.

[0016] Optionally, the second analog-to-digital converter group includes two second analog-to-digital converters, and the image sensor further includes two second switches, each of which corresponds to one of the second analog-to-digital converters; the second analog-to-digital converters are electrically connected to each second pixel unit in the pixel unit column corresponding to the second analog-to-digital converter through the second switches corresponding to the second analog-to-digital converters.

[0017] Optionally, the first analog-to-digital converter group and the second analog-to-digital converter group corresponding to the pixel unit column operate in parallel.

[0018] Optionally, each pixel unit in the pixel unit array includes four photodiodes.

[0019] Optionally, the image sensor further includes a ramp generator, which is electrically connected to each of the first analog-to-digital converter groups and each of the second analog-to-digital converter groups.

[0020] Optionally, the image sensor is provided with an optical coating for controlling the light attenuation of small pixels.

[0021] Secondly, embodiments of this application also provide a pixel signal conversion method, applied to the aforementioned image sensor, the method comprising:

[0022] Obtain the first analog pixel signal of the first pixel unit and the second analog pixel signal of the second pixel unit in the pixel unit column;

[0023] The first analog pixel signal is converted into a first digital pixel signal by the first analog-to-digital converter group corresponding to the pixel unit column, and the second analog pixel signal is converted into a second digital pixel signal by the second analog-to-digital converter group corresponding to the pixel unit column.

[0024] Optionally, obtaining the first analog pixel signal of the first pixel unit and the second analog pixel signal of the second pixel unit in the pixel unit column includes: obtaining the first analog large pixel signal and the first analog small pixel signal of the first pixel unit, and obtaining the second analog large pixel signal and the second analog small pixel signal of the second pixel unit.

[0025] Optionally, the step of converting the first analog pixel signal into a first digital pixel signal through the first analog-to-digital converter group corresponding to the pixel unit column, and converting the second analog pixel signal into a second digital pixel signal through the second analog-to-digital converter group corresponding to the pixel unit column, includes: converting the first analog large pixel signal into a first digital large pixel signal and the first analog small pixel signal into a first digital small pixel signal through the first analog-to-digital converter group, and converting the second analog large pixel signal into a second digital large pixel signal and the second analog small pixel signal into a second digital small pixel signal through the second analog-to-digital converter group.

[0026] Optionally, the method further includes: generating a ramp signal using a ramp generator; the step of converting the first analog pixel signal into a first digital pixel signal using a first analog-to-digital converter group corresponding to the pixel unit column, and converting the second analog pixel signal into a second digital pixel signal using a second analog-to-digital converter group corresponding to the pixel unit column, includes: generating the first digital pixel signal using the first analog-to-digital converter group based on the first analog pixel signal and the ramp signal, and generating the second digital pixel signal using the second analog-to-digital converter group based on the second analog pixel signal and the ramp signal.

[0027] Thirdly, embodiments of this application also provide a camera, including an image sensor as described in the first aspect, or a pixel signal conversion method as described in the second aspect.

[0028] In this embodiment, the first analog pixel signal of the first pixel unit in each odd-numbered row of the pixel unit column is converted into a first digital pixel signal by the first analog-to-digital converter group corresponding to the pixel unit column, and the second analog pixel signal of the second pixel unit in each even-numbered row of the pixel unit column is converted into a second digital pixel signal by the second analog-to-digital converter group corresponding to the pixel unit column. This enables the processing of analog pixel signals of two rows of pixel units in the pixel unit array in each cycle of the image sensor, which improves processing efficiency compared to the prior art where the image sensor processes analog pixel signals of one row of pixel units in the pixel unit array in each cycle. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0030] Figure 1 This is a schematic diagram of the structure of an image sensor provided in an embodiment of this application;

[0031] Figure 2 This is another structural schematic diagram of the image sensor provided in the embodiments of this application;

[0032] Figure 3 This is a schematic diagram of the structure of the first pixel unit and the first analog-to-digital converter group provided in the embodiments of this application;

[0033] Figure 4 This is a schematic diagram of the structure of the second pixel unit and the second analog-to-digital converter group provided in the embodiments of this application;

[0034] Figure 5 This is a schematic diagram of the specific structure of the analog-to-digital converter provided in the embodiments of this application;

[0035] Figure 6This is a flowchart of the steps of a pixel signal conversion method provided in an embodiment of this application.

[0036] Figure label:

[0037] 10 - Pixel unit array; 11 - Pixel unit column; 111 - First column line; 112 - Second column line; 113 - First pixel unit; 114 - Second pixel unit; 20 - First analog-to-digital converter group; 30 - Second analog-to-digital converter group; 40 - First wafer; 41 - Central region; 42 - Second connection point; 43 - First connection point; 43 - First connection point; 50 - Second wafer; 51 - Third connection point; 52 - Fourth connection point; 60 - Row control circuit; 61 - Row control line; 80 - Column readout and control circuit; 81 - Column control line. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0040] Reference Figure 1This application provides an image sensor, including a pixel unit array 10, a plurality of first analog-to-digital converter (ADC) groups 20, and a plurality of second analog-to-digital converter (ADC) groups 30. Each pixel unit column 11 in the pixel unit array 10 has a corresponding first ADC group 20 and a corresponding second ADC group 30. Each pixel unit column 11 has a corresponding first column line 111 and a second column line 112. The first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is electrically connected to the first ADC group 20 corresponding to the pixel unit column 11 through the first column line 111. The second pixel unit 114 in each even-numbered row of the pixel unit column 11 is electrically connected to the second ADC group 30 corresponding to the pixel unit column 11 through the second column line 112.

[0041] It should be noted that the image sensor may include one or more pixel unit arrays 10. Image pixels (i.e., pixel units) can be formed in a semiconductor substrate using Complementary Metal Oxide Semiconductor (CMOS) technology, Charge-Coupled Device (CCD) technology, or any other suitable photosensitive device technology. Image pixels can be front-side illumination (FSI) or back-side illumination (BSI) image pixels. A given image pixel may include one or more photosensitive regions; for example, an image pixel may consist of a photodiode or a pair of split photodiodes, and all photosensitive regions in an image pixel share the same microlens.

[0042] The pixel unit array 10 is an array composed of one or more pixel units, including one or more pixel unit columns 11 and one or more pixel unit rows.

[0043] Pixel units are used to collect light signals and convert them into electrical signals, which are analog pixel signals.

[0044] The first analog-to-digital converter group 20 includes one or more first analog-to-digital converters, and the second analog-to-digital converter group 30 includes one or more second analog-to-digital converters. Both the first and second analog-to-digital converters are analog-to-digital converters.

[0045] The first column line 111 is electrically connected to the first pixel unit 113 of each odd-numbered row in the pixel unit column 11 corresponding to the first column line 111. The first column line 111 is also electrically connected to the first analog-to-digital converter group 20 of the pixel unit column 11 corresponding to the first column line 111. The second column line 112 is electrically connected to the second pixel unit 114 of each even-numbered row in the pixel unit column 11 corresponding to the second column line 112. The second column line 112 is also electrically connected to the second analog-to-digital converter group 30 of the pixel unit column 11 corresponding to the second column line 112.

[0046] For example, a pixel unit array includes n pixel unit columns and m pixel unit rows, where n is a positive integer and m is a positive even number. The n pixel unit columns are A1, A2, A3, ..., A(n-1), An, and the m pixel unit rows are B1, B2, B3, ..., B(m-1), Bm. Column A1 has a corresponding first analog-to-digital converter group C1 and a corresponding second analog-to-digital converter group D1, and a corresponding first column line E1 and a second column line F1. Column A2 has a corresponding first analog-to-digital converter group C2 and a corresponding second analog-to-digital converter group D2, and a corresponding... The first column line E2 and the second column line F2, column A3 has a corresponding first analog-to-digital converter group C3 and a corresponding second analog-to-digital converter group D3, column A3 has a corresponding first column line E3 and a second column line F3, and so on, ..., column A(n-1) has a corresponding first analog-to-digital converter group C(n-1) and a corresponding second analog-to-digital converter group D(n-1), column A(n-1) has a corresponding first column line E(n-1) and a second column line F(n-1), column An has a corresponding first analog-to-digital converter group Cn and a corresponding second analog-to-digital converter group Dn, column An has a corresponding first column line En and a second column line Fn.

[0047] The first pixel unit of each odd-numbered row in column A1 is electrically connected to the first analog-to-digital converter group C1 corresponding to column A1 via the first column line E1. The second pixel unit of each even-numbered row in column A1 is electrically connected to the second analog-to-digital converter group D1 corresponding to column A1 via the second column line F1. The first pixel unit of each odd-numbered row in column A2 is electrically connected to the first analog-to-digital converter group C2 corresponding to column A2 via the first column line E2. The second pixel unit of each even-numbered row in column A2 is electrically connected to the second analog-to-digital converter group D2 corresponding to column A2 via the second column line F2, and so on, ..., each odd-numbered row in column A(n-1) The first pixel unit of each row is electrically connected to the first analog-to-digital converter group C(n-1) corresponding to column A(n-1) via the first column line E(n-1). The second pixel unit of each even row in column A(n-1) is electrically connected to the second analog-to-digital converter group D(n-1) corresponding to column A(n-1) via the second column line F(n-1). The first pixel unit of each odd row in column An is electrically connected to the first analog-to-digital converter group Cn corresponding to column An via the first column line En. The second pixel unit of each even row in column An is electrically connected to the second analog-to-digital converter group Dn corresponding to column An via the second column line Fn.

[0048] In some embodiments, refer to Figure 2 The row control circuit 60 (i.e., the row decoding and driving circuit, row decoder, RDEC, Row Address Decoder) can provide corresponding row control signals to the pixel units via the row control line 61, such as reset, row selection, charge transfer, double conversion gain, and readout control signals. The column readout and control circuit 80 reads the analog image signals in the pixel units via the column control line 81. The column control line 81 (column line) can couple one or more conductive lines to each column of pixel units in the pixel unit array 10. At some stages, such as during pixel readout, the row control circuit 60 can be used to select a pixel row in the pixel array and read the image signal generated by the pixel unit in that pixel row along the column line. The image readout circuit can receive the image signal transmitted by the column line, such as the analog pixel signal generated by the pixel unit. The image readout circuit may include a sample-and-hold circuit, an ADC, a bias circuit, a column counter, a latch circuit, and other circuits. The sampling and holding circuit is used to temporarily store the image signal read from the pixel unit array 10. The ADC can convert the analog pixel signal received from the pixel array unit into the corresponding digital pixel signal. The latch circuit is used to selectively enable or disable the column circuit. Other circuits can generally be coupled to one or more columns to control the image pixels and read the image signal from the pixel unit.

[0049] In this embodiment, the first analog pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is converted into a first digital pixel signal by the first analog-to-digital converter group 20 corresponding to the pixel unit column 11, and the second analog pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 is converted into a second digital pixel signal by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11. This allows the analog pixel signals of two rows of pixel units in the pixel unit array 10 to be processed in each cycle of the image sensor, which improves processing efficiency compared to the prior art where the image sensor processes the analog pixel signal of one row of pixel units in the pixel unit array in each cycle.

[0050] Optionally, the image sensor further includes a first wafer 40 and a second wafer 50, the pixel unit array 10 is disposed on the first wafer 40, and the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 are both disposed on the second wafer 50.

[0051] It should be noted that the first wafer 40 is the pixel wafer, and the second wafer 50 is the logic wafer.

[0052] In some embodiments, the image sensor employs a back-illuminated three-dimensional stacked structure, with the first wafer 40 and the second wafer 50 directly connected via a hybrid bonding method using four vertical contacts (including a first connection point 43, a second connection point 42, a third connection point 51, a fourth connection point 52, etc.). The second wafer 50 also includes a row control circuit 60, an image readout circuit, and other related control and processing circuits. The image readout circuit can provide the control and processing circuits with digital pixel signals obtained from one or more columns of pixel units.

[0053] In this embodiment, by placing the pixel unit array 10 on the first wafer 40 and placing the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 on the second wafer 50, the layout area of ​​the pixel unit array 10 can be isolated from the layout areas of the first analog-to-digital converter group and the second analog-to-digital converter group 30, thus avoiding mutual interference between the first analog-to-digital converter group 20, the second analog-to-digital converter group 30 and the pixel unit array 10.

[0054] Optionally, the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 are respectively disposed on the peripheral side of the second wafer 50.

[0055] In this embodiment, by placing the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 on the peripheral side of the second wafer 50, it is beneficial to achieve a symmetrical layout of the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30.

[0056] Optionally, the first analog-to-digital converter group 20 is disposed on the first side of the second wafer 50, and the second analog-to-digital converter group 30 is disposed on the second side of the second wafer 50, with the first side and the second side being disposed opposite to each other.

[0057] In this embodiment, the first analog-to-digital converter group 20 is disposed on the first side of the second wafer 50, and the second analog-to-digital converter group 30 is disposed on the second side of the second wafer 50. Since the first side and the second side are disposed opposite to each other, it is beneficial to the symmetrical layout of the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30.

[0058] Optionally, the pixel unit array 10 is disposed in the central region 41 of the first wafer 40.

[0059] In this embodiment, by placing the pixel unit array 10 in the central region 41 of the first wafer 40, it is beneficial to arrange the pixel unit array 10 symmetrically on the first wafer 40.

[0060] Optionally, the plane of the first wafer 40 is parallel to the plane of the second wafer 50.

[0061] It should be noted that the projection of the plane of the first wafer 40 onto the horizontal plane coincides with the projection of the plane of the second wafer 50 onto the horizontal plane.

[0062] In this embodiment, since the plane of the first wafer 40 is parallel to the plane of the second wafer 50, it is beneficial to the regular arrangement of the first wafer 40 and the second wafer 50.

[0063] Optionally, each of the first column lines 111 has a first connection point 43 disposed on the first wafer 40, each of the second column lines 112 has a second connection point 42 disposed on the first wafer 40, each of the first analog-to-digital converter groups 20 has a third connection point 51 disposed on the second wafer 50, and each of the second analog-to-digital converter groups 30 has a fourth connection point 52 disposed on the second wafer 50; the first connection point 43 of the first column line 111 is electrically connected to the third connection point 51 of the first analog-to-digital converter group 20 corresponding to the first column line 111; the second connection point 42 of the second column line 112 is electrically connected to the fourth connection point 52 of the second analog-to-digital converter group 30 corresponding to the second column line 112.

[0064] It should be noted that the wire connecting the first connection point 43 and the third connection point 51 is perpendicular to the plane of the first wafer 40 and the plane of the second wafer 50; the wire connecting the second connection point 42 and the fourth connection point 52 is perpendicular to the plane of the first wafer 40 and the plane of the second wafer 50.

[0065] In this embodiment, by electrically connecting the first connection point 43 of the first column line 111 to the third connection point 51 of the first analog-to-digital converter group 20 corresponding to the first column line 111, the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 on the first wafer 40 can be electrically connected to the first analog-to-digital converter group 20 corresponding to the pixel unit column 11 on the second wafer 50; by electrically connecting the second connection point 42 of the second column line 112 to the fourth connection point 52 of the second analog-to-digital converter group 30 corresponding to the second column line 112, the second pixel unit 114 in each even-numbered row of the pixel unit column 11 on the first wafer 40 can be electrically connected to the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 on the second wafer 50.

[0066] Optionally, the first connection point 43 is located at the first boundary of the area where the pixel unit array 10 is located, the second connection point 42 is located at the second boundary of the area where the pixel unit array 10 is located, and the first boundary and the second boundary are opposite to each other; the third connection point 51 is located at the geometric center of the area where the first analog-to-digital converter group 20 is located, and the fourth connection point 52 is located at the geometric center of the area where the second analog-to-digital converter group 30 is located.

[0067] In this embodiment, by setting the first connection point 43 at the first boundary of the area where the pixel unit array 10 is located, setting the second connection point 42 at the second boundary of the area where the pixel unit array 10 is located, setting the third connection point 51 at the geometric center of the area where the first analog-to-digital converter group 20 is located, and setting the fourth connection point 52 at the geometric center of the area where the second analog-to-digital converter group 30 is located, it is beneficial to arrange the wires connecting the first connection point 43 and the third connection point 51, and the wires connecting the second connection point 42 and the fourth connection point 52 in an orderly manner.

[0068] Optionally, the first analog-to-digital converter group 20 includes two first analog-to-digital converters, and the image sensor further includes two first switches, each of which corresponds to one of the first analog-to-digital converters; the first analog-to-digital converters are electrically connected to each of the first pixel units 113 in the pixel unit column 11 corresponding to the first analog-to-digital converter through the first switches corresponding to the first analog-to-digital converters.

[0069] Specifically, the first analog-to-digital converter is electrically connected to the first switch corresponding to the first analog-to-digital converter, and the first switch corresponding to the first analog-to-digital converter is electrically connected to each first pixel unit 113 in the pixel unit column 11 corresponding to the first analog-to-digital converter through the first column line 111.

[0070] In this embodiment of the application, the first switch of the first analog-to-digital converter can control the conduction or disconnection of the first analog-to-digital converter and each first pixel unit 113 in the pixel unit column 11 corresponding to the first analog-to-digital converter.

[0071] Optionally, the second analog-to-digital converter group 30 includes two second analog-to-digital converters, and the image sensor further includes two second switches, each of which corresponds to one of the second analog-to-digital converters; the second analog-to-digital converters are electrically connected to each of the second pixel units 114 in the pixel unit column 11 corresponding to the second analog-to-digital converters through the second switches corresponding to the second analog-to-digital converters.

[0072] Specifically, the second analog-to-digital converter is electrically connected to the second switch corresponding to the second analog-to-digital converter, and the second switch corresponding to the second analog-to-digital converter is electrically connected to each second pixel unit 114 in the pixel unit column 11 corresponding to the second analog-to-digital converter through the second column line 112.

[0073] In this embodiment of the application, the second switch of the second analog-to-digital converter can control the second analog-to-digital converter and the second pixel unit 114 in the pixel unit column 11 corresponding to the second analog-to-digital converter to be turned on or off.

[0074] Optionally, the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 operate in parallel.

[0075] It should be noted that the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 work in parallel. That is, the first analog-to-digital converter group 20 and the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 simultaneously convert analog pixel signals into digital pixel signals. Specifically, while the first analog pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is converted into a first digital pixel signal by the first analog-to-digital converter group 20, the second analog pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 is converted into a second digital pixel signal by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11.

[0076] For example, a pixel unit array includes n pixel unit columns and m pixel unit rows, where n is a positive integer and m is a positive even number. The n pixel unit columns are A1, A2, A3, ..., A(n-1), An, and the m pixel unit rows are B1, B2, B3, ..., B(m-1), Bm. Column A1 has a corresponding first analog-to-digital converter (ADC) group C1 and a corresponding second ADC group D1, column A2 has a corresponding first ADC group C2 and a corresponding second ADC group D2, column A3 has a corresponding first ADC group C3 and a corresponding second ADC group D3, and so on, ..., column A(n-1) has a corresponding first ADC group C(n-1) and a corresponding second ADC group D(n-1), and column An has a corresponding first ADC group Cn and a corresponding second ADC group Dn.

[0077] In the first cycle of the image sensor, when the analog-to-digital converter (ADC) groups corresponding to all pixel unit columns simultaneously convert and quantize the analog pixel signals, the first ADC group C1 corresponding to column A1 converts the first analog pixel signal of the first pixel unit in row B1 of column A1 into a first digital pixel signal; the second ADC group D1 corresponding to column A1 converts the second analog pixel signal of the second pixel unit in row B2 of column A1 into a second digital pixel signal; and the first ADC group C2 corresponding to column A2 converts the first analog pixel signal of the first pixel unit in row B1 of column A2 into a first digital pixel signal. The second ADC group D2 corresponding to column A2 converts the second analog pixel signal of the second pixel unit in row B2 of column A2 into a second digital pixel signal. Digital pixel signals, and so on, ..., the first analog-to-digital converter group C(n-1) corresponding to column A(n-1) converts the first analog pixel signal of the first pixel unit in row B1 of column A(n-1) into a first digital pixel signal; the second analog-to-digital converter group D(n-1) corresponding to column A(n-1) converts the second analog pixel signal of the second pixel unit in row B2 of column A(n-1) into a second digital pixel signal; the first analog-to-digital converter group Cn corresponding to column An converts the first analog pixel signal of the first pixel unit in row B1 of column An into a first digital pixel signal; the second analog-to-digital converter group Dn corresponding to column An converts the second analog pixel signal of the second pixel unit in row B2 of column An into a second digital pixel signal;

[0078] In the second cycle of the image sensor, when the analog-to-digital converter (ADC) groups corresponding to all pixel unit columns simultaneously convert and quantize the analog pixel signals, the first ADC group C1 corresponding to column A1 converts the first analog pixel signal of the first pixel unit in row B3 of column A1 into a first digital pixel signal; the second ADC group D1 corresponding to column A1 converts the second analog pixel signal of the second pixel unit in row B4 of column A1 into a second digital pixel signal; and the first ADC group C2 corresponding to column A2 converts the first analog pixel signal of the first pixel unit in row B3 of column A2 into a first digital pixel signal. The second ADC group D2 corresponding to column A2 converts the second analog pixel signal of the second pixel unit in row B4 of column A2 into a second digital pixel signal. Digital pixel signals, and so on, ..., the first analog-to-digital converter group C(n-1) corresponding to column A(n-1) converts the first analog pixel signal of the first pixel unit in row B3 of column A(n-1) into a first digital pixel signal; the second analog-to-digital converter group D(n-1) corresponding to column A(n-1) converts the second analog pixel signal of the second pixel unit in row B4 of column A(n-1) into a second digital pixel signal; the first analog-to-digital converter group Cn corresponding to column An converts the first analog pixel signal of the first pixel unit in row B3 of column An into a first digital pixel signal; the second analog-to-digital converter group Dn corresponding to column An converts the second analog pixel signal of the second pixel unit in row B4 of column An into a second digital pixel signal;

[0079] And so on, ...

[0080] In the m / 2th cycle of the image sensor, when the analog-to-digital converter (ADC) groups corresponding to all pixel unit columns simultaneously convert and quantize the analog pixel signals, the first ADC group C1 corresponding to column A1 converts the first analog pixel signal of the first pixel unit in row B(m-1) of column A1 into a first digital pixel signal; the second ADC group D1 corresponding to column A1 converts the second analog pixel signal of the second pixel unit in row Bm of column A1 into a second digital pixel signal; the first ADC group C2 corresponding to column A2 converts the first analog pixel signal of the first pixel unit in row B(m-1) of column A2 into a first digital pixel signal; and the second ADC group D2 corresponding to column A2 converts the second analog pixel signal of the second pixel unit in row Bm of column A2 into a second digital pixel signal. The two digital pixel signals, and so on, ..., the first analog-to-digital converter group C(n-1) corresponding to column A(n-1) converts the first analog pixel signal of the first pixel unit in row B(m-1) of column A(n-1) into a first digital pixel signal. The second analog-to-digital converter group D(n-1) corresponding to column A(n-1) converts the second analog pixel signal of the second pixel unit in row Bm of column A(n-1) into a second digital pixel signal. The first analog-to-digital converter group Cn corresponding to column An converts the first analog pixel signal of the first pixel unit in row B(m-1) of column An into a first digital pixel signal. The second analog-to-digital converter group Dn corresponding to column An converts the second analog pixel signal of the second pixel unit in row Bm of column An into a second digital pixel signal.

[0081] In this embodiment, the first analog pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is converted into a first digital pixel signal by the first analog-to-digital converter group 20 corresponding to the pixel unit column 11, and the second analog pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 is converted into a second digital pixel signal by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11. This allows the analog pixel signals of two rows of pixel units in the pixel unit array 10 to be processed in each cycle of the image sensor.

[0082] Optionally, each pixel unit in the pixel unit array 10 includes four photodiodes.

[0083] Specifically, in some embodiments, each pixel unit includes four photodiodes, namely a first photodiode, a second photodiode, a third photodiode, and a fourth photodiode. The analog pixel signal of the pixel unit includes an analog large pixel signal and an analog small pixel signal. The first photodiode, the second photodiode, and the third photodiode in the pixel unit work together to synthesize the analog large pixel signal, and the fourth photodiode in the pixel unit collects the light signal to generate the analog small pixel signal.

[0084] The first analog large pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is converted into a first digital large pixel signal by one of the first analog-to-digital converters in the first analog-to-digital converter group 20 corresponding to the pixel unit column 11. The first analog small pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is converted into a first digital small pixel signal by another of the first analog-to-digital converters in the first analog-to-digital converter group 20 corresponding to the pixel unit column 11. The second analog large pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 is converted into a second digital large pixel signal by one of the second analog-to-digital converters in the second analog-to-digital converter group 30 corresponding to the pixel unit column 11. The second analog small pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 is converted into a second digital small pixel signal by another of the second analog-to-digital converters in the second analog-to-digital converter group 30 corresponding to the pixel unit column 11.

[0085] In this embodiment of the application, analog large pixel signals and analog small pixel signals can be generated through the four photodiodes of the pixel unit.

[0086] Optionally, the image sensor is provided with an optical coating for controlling the light attenuation of small pixels.

[0087] It should be noted that in the relevant technologies, titanium nitride is used to reduce the sensitivity of photodiodes to light sources and read image information under high illumination conditions. However, the production process is complex and not conducive to mass production.

[0088] In this embodiment, the image sensor has an optical coating on the small pixels. The optical coating in the internal structure of the pixel unit controls the light attenuation of the small pixels. During the manufacturing process, the optical coating of the small pixels controls the light attenuation, which not only facilitates the parameter adjustment of the photodiode and makes the photodiode's light response consistent, but also has low cost, simple process and easy control, and greatly improves the yield of finished products.

[0089] Optionally, the image sensor further includes a ramp generator, which is electrically connected to each of the first analog-to-digital converter group 20 and each of the second analog-to-digital converter group 30.

[0090] In this embodiment, a ramp generator provides a ramp signal so that the first analog-to-digital converter group 20 corresponding to the pixel unit column 11 can generate a first digital pixel signal based on the first analog pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 and the ramp signal. The ramp generator also provides a ramp signal so that the second analog-to-digital converter group 30 corresponding to the pixel unit column 11 can generate a second digital pixel signal based on the second analog pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 and the ramp signal.

[0091] In some embodiments, refer to Figure 3 The first pixel unit 113 in a pixel unit column 11 includes a first photodiode D1a, a second photodiode D2a, a third photodiode D3a, a fourth photodiode D4a, a first switch Q1a, a second switch Q2a, a third switch Q3a, a fourth switch Q4a, a fifth switch Q5a, a sixth switch Q6a, a seventh switch Q7a, an eighth switch Q8a, a first capacitor FD1a, and a second capacitor FD2a. The positive terminal of the first photodiode D1a is grounded, and the negative terminal of the first photodiode D1a is connected to the first terminal circuit of the first switch Q1a. The positive terminal of the second photodiode D2a is grounded, and the negative terminal of the second photodiode D2a is connected to the first terminal circuit of the second switch Q2a. The positive terminal of the third photodiode D3a is grounded, and the negative terminal of the third photodiode D3a is connected to the first terminal of the third switching device Q3a. The positive terminal of the fourth photodiode D4a is grounded, and the negative terminal of the fourth photodiode D4a is connected to the first terminal of the fourth switching device Q4a. The second terminals of the first switching device Q1a, the second switching device Q2a, the third switching device Q3a, and the fourth switching device Q4a are electrically connected to the control terminal of the seventh switching device Q7a. The second terminals of the first switching device Q1a, the second switching device Q2a, the third switching device Q3a, and the fourth switching device Q4a are electrically connected to the first terminal of the first capacitor FD1a. The second terminal of the first capacitor FD1a is grounded.

[0092] The first terminal of the fifth switching device Q5a is electrically connected to the power supply. The second terminal of the fifth switching device Q5a is electrically connected to the first terminal of the sixth switching device Q6a and the first terminal of the second capacitor FD2a. The second terminal of the second capacitor FD2a is grounded. The second terminal of the sixth switching device Q6a is electrically connected to the first terminal of the first capacitor FD1a and the control terminal of the seventh switching device Q7a. The first terminal of the seventh switching device Q7a is electrically connected to the power supply. The second terminal of the seventh switching device Q7a is electrically connected to the first terminal of the eighth switching device Q8a. The second terminal of the eighth switching device Q8a is electrically connected to the first terminal of the first switch SW1a and the first terminal of the first switch SW2a through the first column line 111. The second terminal of the first switch SW1a is electrically connected to the first input terminal of the first analog-to-digital converter 21a. The second terminal of the first switch SW2a is electrically connected to the first input terminal of the first analog-to-digital converter 22a. The first analog-to-digital converter group 20 corresponding to a pixel unit column 11 includes the first analog-to-digital converter 21a and the first analog-to-digital converter 22a.

[0093] The second input terminal of the first analog-to-digital converter 21a is electrically connected to the first terminal of the third switch SW3a, and the second terminal of the third switch SW3a is electrically connected to the ramp signal receiver X1. The second input terminal of the first analog-to-digital converter 22a is electrically connected to the first terminal of the third switch SW4a, and the second terminal of the third switch SW4a is electrically connected to the ramp signal receiver X1. The ramp signal receiver X1 is used to receive the ramp signal generated by the ramp generator.

[0094] It should be noted that the control terminal TX1a of the first switching device Q1a is used to receive the pulse control signal of the first switching device Q1a, the control terminal TX2a of the second switching device Q2a is used to receive the pulse control signal of the second switching device Q2a, the control terminal TX3a of the third switching device Q3a is used to receive the pulse control signal of the third switching device Q3a, the control terminal TX4a of the fourth switching device Q4a is used to receive the pulse control signal of the fourth switching device Q4a, the control terminal RSTa of the fifth switching device Q5a is used to receive the reset signal, the control terminal DCGa of the sixth switching device Q6a is used to receive the switching pulse signal, and the control terminal Q8a of the eighth switching device Q8a is used to receive the row selection signal.

[0095] The first pixel unit 113 in another pixel unit column 11 includes a first photodiode D1b, a second photodiode D2b, a third photodiode D3b, a fourth photodiode D4b, a first switch Q1b, a second switch Q2b, a third switch Q3b, a fourth switch Q4b, a fifth switch Q5b, a sixth switch Q6b, a seventh switch Q7b, an eighth switch Q8b, a first capacitor FD1b, and a second capacitor FD2b. The positive terminal of the first photodiode D1b is grounded, and the negative terminal of the first photodiode D1b is connected to the first terminal circuit of the first switch Q1b. The positive terminal of the second photodiode D2b is grounded, and the negative terminal of the second photodiode D2b is connected to the first terminal circuit of the second switch Q2b. The positive terminal of the third photodiode D3b is grounded, and the negative terminal of the third photodiode D3b is connected to the first terminal of the third switching device Q3b. The positive terminal of the fourth photodiode D4b is grounded, and the negative terminal of the fourth photodiode D4b is connected to the first terminal of the fourth switching device Q4b. The second terminals of the first switching device Q1b, the second switching device Q2b, the third switching device Q3b, and the fourth switching device Q4b are electrically connected to the control terminal of the seventh switching device Q7b. The second terminals of the first switching device Q1b, the second switching device Q2b, the third switching device Q3b, and the fourth switching device Q4b are electrically connected to the first terminal of the first capacitor FD1b. The second terminal of the first capacitor FD1b is grounded.

[0096] The first terminal of the fifth switching device Q5b is electrically connected to the power supply. The second terminal of the fifth switching device Q5b is electrically connected to the first terminal of the sixth switching device Q6b and the first terminal of the second capacitor FD2b. The second terminal of the second capacitor FD2b is grounded. The second terminal of the sixth switching device Q6b is electrically connected to the first terminal of the first capacitor FD1b and the control terminal of the seventh switching device Q7b. The first terminal of the seventh switching device Q7b is electrically connected to the power supply. The second terminal of the seventh switching device Q7b is electrically connected to the first terminal of the eighth switching device Q8b. The second terminal of the eighth switching device Q8b is electrically connected to the first terminal of the first switch SW1b and the first terminal of the first switch SW2b through the first column line 111. The second terminal of the first switch SW1b is electrically connected to the first input terminal of the first analog-to-digital converter 21b. The second terminal of the first switch SW2b is electrically connected to the first input terminal of the first analog-to-digital converter 22b. The first analog-to-digital converter group 20 corresponding to another pixel unit column 11 includes the first analog-to-digital converter 21b and the first analog-to-digital converter 22b.

[0097] The second input terminal of the first analog-to-digital converter 21b is electrically connected to the first terminal of the third switch SW3b, the second terminal of the third switch SW3b is electrically connected to the ramp signal receiver X1, the second input terminal of the first analog-to-digital converter 22b is electrically connected to the first terminal of the third switch SW4b, and the second terminal of the third switch SW4b is electrically connected to the ramp signal receiver X1.

[0098] It should be noted that the control terminal TX1b of the first switching device Q1b is used to receive the pulse control signal of the first switching device Q1b, the control terminal TX2b of the second switching device Q2b is used to receive the pulse control signal of the second switching device Q2b, the control terminal TX3b of the third switching device Q3b is used to receive the pulse control signal of the third switching device Q3b, the control terminal TX4b of the fourth switching device Q4b is used to receive the pulse control signal of the fourth switching device Q4b, the control terminal RSTb of the fifth switching device Q5b is used to receive the reset signal, the control terminal DCGb of the sixth switching device Q6b is used to receive the switching pulse signal, and the control terminal Q8b of the eighth switching device is used to receive the row selection signal.

[0099] Reference Figure 4 The second pixel unit 114 in a pixel unit column 11 includes a first photodiode D1c, a second photodiode D2c, a third photodiode D3c, a fourth photodiode D4c, a first switch Q1c, a second switch Q2c, a third switch Q3c, a fourth switch Q4c, a fifth switch Q5c, a sixth switch Q6c, a seventh switch Q7c, an eighth switch Q8c, a first capacitor FD1c, and a second capacitor FD2c. The positive terminal of the first photodiode D1c is grounded, and the negative terminal of the first photodiode D1c is connected to the first terminal circuit of the first switch Q1c. The positive terminal of the second photodiode D2c is grounded, and the negative terminal of the second photodiode D2c is connected to the first terminal circuit of the second switch Q2c. The positive terminal of the third photodiode D3c is grounded, and the negative terminal of the third photodiode D3c is connected to the first terminal of the third switching device Q3c. The positive terminal of the fourth photodiode D4c is grounded, and the negative terminal of the fourth photodiode D4c is connected to the first terminal of the fourth switching device Q4c. The second terminals of the first switching device Q1c, the second switching device Q2c, the third switching device Q3c, and the fourth switching device Q4c are electrically connected to the control terminal of the seventh switching device Q7c. The second terminals of the first switching device Q1c, the second switching device Q2c, the third switching device Q3c, and the fourth switching device Q4c are electrically connected to the first terminal of the first capacitor FD1c. The second terminal of the first capacitor FD1c is grounded.

[0100] The first terminal of the fifth switching device Q5c is electrically connected to the power supply. The second terminal of the fifth switching device Q5c is electrically connected to the first terminal of the sixth switching device Q6c and the first terminal of the second capacitor FD2c. The second terminal of the second capacitor FD2c is grounded. The second terminal of the sixth switching device Q6c is electrically connected to the first terminal of the first capacitor FD1c and the control terminal of the seventh switching device Q7c. The first terminal of the seventh switching device Q7c is electrically connected to the power supply. The second terminal of the seventh switching device Q7c is electrically connected to the first terminal of the eighth switching device Q8c. The second terminal of the eighth switching device Q8c is electrically connected to the first terminal of the second switch SW1c and the first terminal of the second switch SW2c through the second column line 112. The second terminal of the second switch SW1c is electrically connected to the first input terminal of the second analog-to-digital converter 31c. The second terminal of the second switch SW2c is electrically connected to the first input terminal of the second analog-to-digital converter 32c. The second analog-to-digital converter group 30 corresponding to a pixel unit column 11 includes the second analog-to-digital converter 31c and the second analog-to-digital converter 32c.

[0101] The second input terminal of the second analog-to-digital converter 31c is electrically connected to the first terminal of the fourth switch SW3c, the second terminal of the fourth switch SW3c is electrically connected to the ramp signal receiver X1, the second input terminal of the second analog-to-digital converter 32c is electrically connected to the first terminal of the fourth switch SW4c, and the second terminal of the fourth switch SW4c is electrically connected to the ramp signal receiver X1. The ramp signal receiver X1 is used to receive the ramp signal generated by the ramp generator.

[0102] It should be noted that the control terminal TX1c of the first switching device Q1c is used to receive the pulse control signal of the first switching device Q1c, the control terminal TX2c of the second switching device Q2c is used to receive the pulse control signal of the second switching device Q2c, the control terminal TX3c of the third switching device Q3c is used to receive the pulse control signal of the third switching device Q3c, the control terminal TX4c of the fourth switching device Q4c is used to receive the pulse control signal of the fourth switching device Q4c, the control terminal RSTc of the fifth switching device Q5c is used to receive the reset signal, the control terminal DCGc of the sixth switching device Q6c is used to receive the switching pulse signal, and the control terminal Q8c of the eighth switching device Q8c is used to receive the row selection signal.

[0103] The second pixel unit 114 in another pixel unit column 11 includes a first photodiode D1d, a second photodiode D2d, a third photodiode D3d, a fourth photodiode D4d, a first switch Q1d, a second switch Q2d, a third switch Q3d, a fourth switch Q4d, a fifth switch Q5d, a sixth switch Q6d, a seventh switch Q7d, an eighth switch Q8d, a first capacitor FD1d, and a second capacitor FD2d. The positive terminal of the first photodiode D1d is grounded, and the negative terminal of the first photodiode D1d is connected to the first terminal circuit of the first switch Q1d. The positive terminal of the second photodiode D2d is grounded, and the negative terminal of the second photodiode D2d is connected to the first terminal circuit of the second switch Q2d. The positive terminal of the third photodiode D3d is grounded, and the negative terminal of the third photodiode D3d is connected to the first terminal of the third switching device Q3d. The positive terminal of the fourth photodiode D4d is grounded, and the negative terminal of the fourth photodiode D4d is connected to the first terminal of the fourth switching device Q4d. The second terminals of the first switching device Q1d, the second switching device Q2d, the third switching device Q3d, and the fourth switching device Q4d are electrically connected to the control terminal of the seventh switching device Q7d. The second terminals of the first switching device Q1d, the second switching device Q2d, the third switching device Q3d, and the fourth switching device Q4d are electrically connected to the first terminal of the first capacitor FD1d. The second terminal of the first capacitor FD1d is grounded.

[0104] The first terminal of the fifth switching device Q5d is electrically connected to the power supply. The second terminal of the fifth switching device Q5d is electrically connected to the first terminal of the sixth switching device Q6d and the first terminal of the second capacitor FD2d. The second terminal of the second capacitor FD2d is grounded. The second terminal of the sixth switching device Q6d is electrically connected to the first terminal of the first capacitor FD1d and the control terminal of the seventh switching device Q7d. The first terminal of the seventh switching device Q7d is electrically connected to the power supply. The second terminal of the seventh switching device Q7d is electrically connected to the first terminal of the eighth switching device Q8d. The second terminal of the eighth switching device Q8d is electrically connected to the first terminal of the second switch SW1d and the first terminal of the second switch SW2d through the second column line 112. The second terminal of the second switch SW1d is electrically connected to the first input terminal of the second analog-to-digital converter 31d. The second terminal of the second switch SW2d is electrically connected to the first input terminal of the second analog-to-digital converter 32d. The second analog-to-digital converter group 30 corresponding to another pixel unit column 11 includes the second analog-to-digital converter 31d and the second analog-to-digital converter 32d.

[0105] The second input terminal of the second analog-to-digital converter 31d is electrically connected to the first terminal of the fourth switch SW3d, the second terminal of the fourth switch SW3d is electrically connected to the ramp signal receiver X1, the second input terminal of the second analog-to-digital converter 32d is electrically connected to the first terminal of the fourth switch SW4d, and the second terminal of the fourth switch SW4d is electrically connected to the ramp signal receiver X1.

[0106] It should be noted that the control terminal TX1d of the first switching device Q1d is used to receive the pulse control signal of the first switching device Q1d, the control terminal TX2d of the second switching device Q2d is used to receive the pulse control signal of the second switching device Q2d, the control terminal TX3d of the third switching device Q3d is used to receive the pulse control signal of the third switching device Q3d, the control terminal TX4d of the fourth switching device Q4d is used to receive the pulse control signal of the fourth switching device Q4d, the control terminal RSTd of the fifth switching device Q5d is used to receive the reset signal, the control terminal DCGd of the sixth switching device Q6d is used to receive the switching pulse signal, and the control terminal Q8d of the eighth switching device is used to receive the row selection signal.

[0107] In some embodiments, refer to Figure 5 The analog-to-digital converter (ADC) includes a first operational amplifier 91, a second operational amplifier 92, a counter 93, a first sampling capacitor Cr1, a second sampling capacitor Cr2, a first reset switch S1, a second reset switch S2, and a third reset switch S3. The first input terminal 91a of the ADC is electrically connected to a pixel unit to receive analog pixel signals from the pixel unit. The second input terminal 91b of the ADC is electrically connected to a ramp signal receiver X1 to receive ramp signals. The first sampling capacitor Cr1 is electrically connected to the first input terminal 91a of the ADC to acquire analog pixel signals from the pixel unit. The second sampling capacitor Cr2 is electrically connected to the second input terminal 91b of the ADC to acquire ramp signals. The first input terminal of the first operational amplifier 91 is electrically connected to the first sampling capacitor Cr1, the second input terminal of the first operational amplifier 91 is electrically connected to the second sampling capacitor Cr2, and the output terminal of the first operational amplifier 91 is electrically connected to the first input terminal of the second operational amplifier 92.

[0108] The second input terminal of the second operational amplifier 92 is used to receive a reference voltage signal, and the output terminal of the second operational amplifier 92 is electrically connected to the input terminal of the counter 93. The reset terminal 93a of the counter 93 is used to receive a counter reset signal, the clock signal terminal 93b of the counter 93 is used to receive a clock signal, and the output terminal of the counter 93 is used to output a digital pixel signal. The first terminal of the first reset switch S1 is electrically connected to the first input terminal of the first operational amplifier 91, and the second terminal of the first reset switch S1 is electrically connected to the output terminal of the first operational amplifier 91. The first terminal of the second reset switch S2 is electrically connected to the second input terminal of the first operational amplifier 91, and the second terminal of the second reset switch S2 is electrically connected to the output terminal of the first operational amplifier 91. The first reset switch S1 and the second reset switch S2 are used to reset the first operational amplifier 91. The first terminal of the third reset switch S3 is electrically connected to the first input terminal of the second operational amplifier 92, and the second terminal of the third reset switch S3 is electrically connected to the output terminal of the second operational amplifier 92. The third reset switch S3 is used to reset the second operational amplifier 92.

[0109] The horizontal control signals are generated by the horizontal decoding and driving circuits and include a reset signal, a switch pulse signal, a horizontal selection signal, and pulse control signals for the switching devices. These horizontal control signals work together to control the on / off state of the switching devices (transistors) within the pixel unit, completing the pixel unit's reset, exposure, and readout processes. The transistor controlled by the reset signal resets the voltage of the second capacitor to the power supply voltage. The switch pulse signal enables the pixel unit to operate in low-gain or high-gain mode. The horizontal selection signal controls the signal output of one row of the pixel unit array 10. The pulse control signal controls the image signal transmission of the photodiode.

[0110] This application embodiment increases the number of analog-to-digital conversion circuits, allowing simultaneous conversion of analog pixel signals in odd and even rows. The conversion time for analog pixel signals is halved, meaning that under the same operating frequency, this application embodiment can process more pixel signals and perform more complex calculations, thus increasing the frame rate of image processing and reducing the conversion time of the column ADC. Compared with related technologies, this application embodiment achieves a higher frame rate and has superior operating characteristics.

[0111] The four ADCs double the operating efficiency of the circuitry compared to related technologies. This means that, at the same operating frequency, the present invention can process more pixel signals and perform more complex calculations, thus increasing the frame rate of image processing. The internal structure of the pixel unit uses the same four photodiodes, simplifying the pixel structure and increasing image resolution four times that of a pixel structure using a single photodiode, and twice that of a pixel structure using two photodiodes.

[0112] Reference Figure 6 This application also provides a pixel signal conversion method applied to the aforementioned image sensor, the method comprising:

[0113] Step 101: Obtain the first analog pixel signal of the first pixel unit and the second analog pixel signal of the second pixel unit in the pixel unit column.

[0114] The implementation of this step is similar to the specific implementation process of the image sensor mentioned above, and will not be repeated here.

[0115] Step 102: Convert the first analog pixel signal into a first digital pixel signal using the first analog-to-digital converter group corresponding to the pixel unit column, and convert the second analog pixel signal into a second digital pixel signal using the second analog-to-digital converter group corresponding to the pixel unit column.

[0116] The implementation of this step is similar to the specific implementation process of the image sensor mentioned above, and will not be repeated here.

[0117] Optionally, step 101 includes the following sub-steps:

[0118] Step 1011: Obtain the first analog large pixel signal and the first analog small pixel signal of the first pixel unit, and obtain the second analog large pixel signal and the second analog small pixel signal of the second pixel unit.

[0119] The implementation of this step is similar to the specific implementation process of the image sensor mentioned above, and will not be repeated here.

[0120] Optionally, step 102 includes the following sub-steps:

[0121] Step 1021: Using the first analog-to-digital converter group, the first analog large pixel signal is converted into a first digital large pixel signal and the first analog small pixel signal is converted into a first digital small pixel signal. Using the second analog-to-digital converter group, the second analog large pixel signal is converted into a second digital large pixel signal and the second analog small pixel signal is converted into a second digital small pixel signal.

[0122] The implementation of this step is similar to the specific implementation process of the image sensor mentioned above, and will not be repeated here.

[0123] Optionally, the method further includes the following steps:

[0124] Step 103: Generate a ramp signal using a ramp generator.

[0125] The implementation of this step is similar to the specific implementation process of the image sensor mentioned above, and will not be repeated here.

[0126] Step 102 includes the following sub-steps:

[0127] Step 1022: Generate the first digital pixel signal using the first analog-to-digital converter group based on the first analog pixel signal and the ramp signal, and generate the second digital pixel signal using the second analog-to-digital converter group based on the second analog pixel signal and the ramp signal.

[0128] The implementation of this step is similar to the specific implementation process of the image sensor mentioned above, and will not be repeated here.

[0129] This application also provides a camera, including the aforementioned image sensor, or a pixel signal conversion method as described above.

[0130] The specific implementation process of the image sensor in the camera provided in this application embodiment is similar to the specific implementation process of the image sensor described above. The specific implementation process of the pixel signal conversion method running in the camera is similar to the specific implementation process of the pixel signal conversion method described above, and will not be repeated here.

[0131] In summary, in this embodiment, the first analog pixel signal of the first pixel unit 113 in each odd-numbered row of the pixel unit column 11 is converted into a first digital pixel signal by the first analog-to-digital converter group 20 corresponding to the pixel unit column 11, and the second analog pixel signal of the second pixel unit 114 in each even-numbered row of the pixel unit column 11 is converted into a second digital pixel signal by the second analog-to-digital converter group 30 corresponding to the pixel unit column 11. This allows the analog pixel signals of two rows of pixel units in the pixel unit array 10 to be processed in each cycle of the image sensor, which improves processing efficiency compared to the prior art where the image sensor processes the analog pixel signal of one row of pixel units in the pixel unit array in each cycle.

[0132] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited. Functions may be performed in the order shown or discussed, or may be performed substantially simultaneously or in reverse order depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0133] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. An image sensor, characterized in that, It includes a pixel unit array (10), a plurality of first analog-to-digital converter groups (20) and a plurality of second analog-to-digital converter groups (30). Each pixel unit column (11) in the pixel unit array (10) has a corresponding first analog-to-digital converter group (20) and a corresponding second analog-to-digital converter group (30). Each pixel unit column (11) has a corresponding first column line (111) and a second column line (112). The first pixel unit (113) of each odd-numbered row in the pixel unit column (11) is electrically connected to the first analog-to-digital converter group (20) corresponding to the pixel unit column (11) through the first column line (111); the second pixel unit (114) of each even-numbered row in the pixel unit column (11) is electrically connected to the second analog-to-digital converter group (30) corresponding to the pixel unit column (11) through the second column line (112).

2. The image sensor according to claim 1, characterized in that, The image sensor also includes a first wafer (40) and a second wafer (50), the pixel unit array (10) is disposed on the first wafer (40), and the first analog-to-digital converter group (20) and the second analog-to-digital converter group (30) are both disposed on the second wafer (50).

3. The image sensor according to claim 2, characterized in that, The first analog-to-digital converter group (20) and the second analog-to-digital converter group (30) are respectively disposed on the peripheral side of the second wafer (50).

4. The image sensor according to claim 3, characterized in that, The first analog-to-digital converter group (20) is disposed on the first side of the second wafer (50), and the second analog-to-digital converter group (30) is disposed on the second side of the second wafer (50), with the first side and the second side being disposed opposite to each other.

5. The image sensor according to claim 2, characterized in that, The pixel unit array (10) is disposed in the central region (41) of the first wafer (40).

6. The image sensor according to claim 2, characterized in that, The plane of the first wafer (40) is parallel to the plane of the second wafer (50).

7. The image sensor according to claim 2, characterized in that, Each of the first column lines (111) has a first connection point (43) disposed on the first wafer (40), each of the second column lines (112) has a second connection point (42) disposed on the first wafer (40), each of the first analog-to-digital converter groups (20) has a third connection point (51) disposed on the second wafer (50), and each of the second analog-to-digital converter groups (30) has a fourth connection point (52) disposed on the second wafer (50). The first connection point (43) of the first column line (111) is electrically connected to the third connection point (51) of the first analog-to-digital converter group (20) corresponding to the first column line (111); The second connection point (42) of the second column line (112) is electrically connected to the fourth connection point (52) of the second analog-to-digital converter group (30) corresponding to the second column line (112).

8. The image sensor according to claim 7, characterized in that, The first connection point (43) is located at the first boundary of the area where the pixel unit array (10) is located, and the second connection point (42) is located at the second boundary of the area where the pixel unit array (10) is located. The first boundary and the second boundary are opposite to each other. The third connection point (51) is located at the geometric center of the area where the first analog-to-digital converter group (20) is located, and the fourth connection point (52) is located at the geometric center of the area where the second analog-to-digital converter group (30) is located.

9. The image sensor according to claim 1, characterized in that, The first analog-to-digital converter group (20) includes two first analog-to-digital converters, and the image sensor also includes two first switches, each of which corresponds to one of the first analog-to-digital converters. The first analog-to-digital converter is electrically connected to each of the first pixel units (113) in the pixel unit column (11) corresponding to the first analog-to-digital converter through the first switch corresponding to the first analog-to-digital converter.

10. The image sensor according to claim 1, characterized in that, The second analog-to-digital converter group (30) includes two second analog-to-digital converters, and the image sensor also includes two second switches, each of which corresponds to one of the second analog-to-digital converters; The second analog-to-digital converter is electrically connected to each of the second pixel units (114) in the pixel unit column (11) corresponding to the second analog-to-digital converter via the second switch corresponding to the second analog-to-digital converter.

11. The image sensor according to claim 1, characterized in that, The first analog-to-digital converter group (20) and the second analog-to-digital converter group (30) corresponding to the pixel unit column (11) work in parallel.

12. The image sensor according to claim 1, characterized in that, Each pixel unit in the pixel unit array (10) includes four photodiodes.

13. The image sensor according to claim 1, characterized in that, The image sensor also includes a ramp generator, which is electrically connected to each of the first analog-to-digital converter group and each of the second analog-to-digital converter group.

14. The image sensor according to claim 1, characterized in that, The image sensor is equipped with an optical coating, which is used to control the light attenuation of small pixels.

15. A method for converting pixel signals, characterized in that, Applied to an image sensor as described in any one of claims 1 to 14, the method comprises: Obtain the first analog pixel signal of the first pixel unit and the second analog pixel signal of the second pixel unit in the pixel unit column; The first analog pixel signal is converted into a first digital pixel signal by the first analog-to-digital converter group corresponding to the pixel unit column, and the second analog pixel signal is converted into a second digital pixel signal by the second analog-to-digital converter group corresponding to the pixel unit column.

16. The method according to claim 15, characterized in that, The step of obtaining the first analog pixel signal of the first pixel unit and the second analog pixel signal of the second pixel unit in the pixel unit column includes: Acquire the first analog large pixel signal and the first analog small pixel signal of the first pixel unit, and acquire the second analog large pixel signal and the second analog small pixel signal of the second pixel unit.

17. The method according to claim 16, characterized in that, The step of converting the first analog pixel signal into a first digital pixel signal using the first analog-to-digital converter group corresponding to the pixel unit column, and converting the second analog pixel signal into a second digital pixel signal using the second analog-to-digital converter group corresponding to the pixel unit column, includes: The first analog-to-digital converter group converts the first analog large pixel signal into a first digital large pixel signal and the first analog small pixel signal into a first digital small pixel signal. The second analog-to-digital converter group converts the second analog large pixel signal into a second digital large pixel signal and the second analog small pixel signal into a second digital small pixel signal.

18. The method according to claim 15, characterized in that, The method further includes: A ramp signal is generated using a ramp generator; The step of converting the first analog pixel signal into a first digital pixel signal using the first analog-to-digital converter group corresponding to the pixel unit column, and converting the second analog pixel signal into a second digital pixel signal using the second analog-to-digital converter group corresponding to the pixel unit column, includes: The first analog-to-digital converter group generates the first digital pixel signal based on the first analog pixel signal and the ramp signal, and the second analog-to-digital converter group generates the second digital pixel signal based on the second analog pixel signal and the ramp signal.

19. A camera, characterized in that, Includes an image sensor as described in any one of claims 1 to 14, or a pixel signal conversion method as described in claims 15 to 18.

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