Field effect transistor and method of manufacturing the same

Abstract

The application relates to a field effect transistor and a manufacturing method thereof, the method comprising: obtaining a wafer formed with a drift region, a source region, a drain region and a gate; forming a metal silicide barrier layer, including an oxidation layer and an etching stop layer on the oxidation layer; forming an interlayer dielectric layer; using a contact hole photoetching plate to perform photoetching on the interlayer dielectric layer to form a contact hole etching window and a plurality of hole field plate etching windows above the metal silicide barrier layer between the gate and the drain region, the width of each hole field plate etching window gradually increases in a first direction; through etching, a contact hole penetrating through the interlayer dielectric layer is formed below the contact hole etching window, and a plurality of corresponding recesses are formed below the plurality of hole field plate etching windows; in the first direction, different recesses have different bottom depths. The micro load effect of the hole field plate in the etching process is utilized to form a stepped multi-stage field plate with gradually increasing interlayer dielectric layer thickness.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a field-effect transistor, and also to a method for manufacturing a field-effect transistor. Background Technology

[0002] LDMOS (Lateral Double-Diffused MOSFET) is a lateral power device that is easily integrated monolithically with low-voltage signal and other devices. It offers advantages such as high voltage withstand capability, high gain, and low distortion, and is widely used in power integrated circuits. The structural performance of LDMOS directly affects the performance of power integrated circuits. Two important parameters for evaluating LDMOS performance are on-resistance and breakdown voltage; generally, a lower on-resistance and a higher breakdown voltage indicate better LDMOS performance.

[0003] In related technologies, STI (Shallow Trench Isolation) technology is typically used to improve breakdown voltage, or LOCOS (Local Oxidation of Silicon) process is used to provide isolation over the drift region. However, the inventors discovered that both STI and LOCOS technologies lead to an increase in the on-resistance of the device. Summary of the Invention

[0004] Therefore, it is necessary to provide a field-effect transistor and its manufacturing method that can further optimize the on-resistance relative to the structure of setting LOCOS / STI on the drift region.

[0005] A method for manufacturing a field-effect transistor includes: obtaining a wafer having a drift region, a source region, a drain region, and a gate; wherein the drift region is at least partially located between the source region and the drain region, and the gate is located between the source region and the drain region; forming a metal silicide barrier layer, wherein the metal silicide barrier layer is at least partially located between the gate and the drain region, and the metal silicide barrier layer includes an oxide layer and an etch stop layer on the oxide layer; forming an interlayer dielectric layer covering the source region, the drain region, the gate, and the metal silicide barrier layer; and performing photolithography using a contact hole photomask to form contact hole etching windows and a region located between the gate and the drain region on the interlayer dielectric layer. A plurality of field-plate etching windows are formed above the metal silicide barrier layer. The width of each of the field-plate etching windows gradually increases in a first direction, which is the direction from the source region to the drain region. Through etching, contact holes penetrating the interlayer dielectric layer are formed below the contact hole etching windows, and a plurality of corresponding recesses are formed below the plurality of field-plate etching windows. In the first direction, different recesses have different bottom depths, that is, the bottom depth gradually decreases in the first direction, and the width of the recesses gradually increases in the first direction, which is the first direction. Conductive material is filled into the contact holes and each of the recesses.

[0006] In the aforementioned method for manufacturing field-effect transistors, the photolithography and etching of the orifice field plate can be performed simultaneously with the contact holes, eliminating the need for additional photolithography layers and process steps. Utilizing the micro-load effect of the orifice field plate during etching, a stepped, multi-level field plate can be formed, with the interlayer dielectric layer thickness gradually increasing from the source region to the drain region and below the recess. This design is compatible with high-voltage operating ranges and exhibits good ductility. Furthermore, STI and LOCOS structures, which serve as field oxides, can be omitted in the drift region, avoiding the reduction in on-resistance caused by using STI or LOCOS structures as field oxides.

[0007] In one embodiment, the drift region is not provided with STI and LOCOS structures serving as field oxygen.

[0008] In one embodiment, the etch stop layer includes a nitride layer.

[0009] In one embodiment, the etch stop layer includes a silicon nitride layer and a silicon oxynitride layer on the silicon nitride layer.

[0010] In one embodiment, the pattern in the contact hole photomask corresponding to the etching window of the hole field plate is striped, and different stripes have different widths.

[0011] In one embodiment, the contact hole includes a source contact hole leading out the source region; the manufacturing method further includes the step of forming a metal layer on the interlayer dielectric layer, the metal layer including a first metal wire electrically connecting the conductive material in each of the recesses to the conductive material in the source contact hole.

[0012] In one embodiment, the oxide layer extends a certain distance from the side near the drain region into the bottom of the gate, and only the gate dielectric layer is formed above the channel region of the field-effect transistor without the oxide layer; the oxide layer forms a fault region, and the fault region is not provided with the oxide layer but only with an etch stop layer, and the oxide layer is provided on both sides of the fault region; the one closest to the gate among the recesses is provided above the fault region, and the bottom of the recess extends to the etch stop layer in the fault region.

[0013] A field-effect transistor (FET) includes: a source region; a drain region; a drift region at least partially located between the source region and the drain region; a gate located between the source region and the drain region; a metal silicide barrier layer at least partially located between the gate region and the drain region, the metal silicide barrier layer including an oxide layer and an etch stop layer on the oxide layer; an interlayer dielectric layer covering the source region, drain region, gate region, and metal silicide barrier layer; and a via plate located between the gate region and the drain region, including a plurality of recesses filled with conductive material, each recess extending downward into the interlayer dielectric layer and having its bottom located on the metal silicide barrier layer; in a first direction, different recesses have different bottom depths, i.e., the bottom depth gradually decreases in the first direction, and the width of the recesses gradually increases in the first direction, the width direction being the first direction, which is the direction from the source region to the drain region.

[0014] The aforementioned field-effect transistor utilizes the micro-load effect of the aperture field plate during the etching process to form a stepped multi-level field plate with progressively increasing thickness of the interlayer dielectric layer from the source region to the drain region and below the recess. It is compatible with high-voltage operating range and has good ductility.

[0015] In one embodiment, the aperture plate is photolithographically formed using a contact hole photolithography plate, which includes patterns corresponding to each of the recesses and patterns corresponding to each contact hole of the field-effect transistor. Each of the recesses is formed by etching simultaneously with each of the contact holes.

[0016] In one embodiment, the pattern corresponding to each recess in the contact hole photomask is a stripe, and the different stripes have different widths.

[0017] In one embodiment, the drift region is not provided with STI and LOCOS structures serving as field oxygen. Attached Figure Description

[0018] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0019] Figure 1 This is a flowchart of a method for manufacturing a field-effect transistor according to one embodiment of this application.

[0020] Figure 2 This is a schematic diagram of the structure of a field-effect transistor in one embodiment of this application.

[0021] Figure 3 This is a top view of grooves 162, 164, and 166 of the perforated plate 160 in one embodiment of this application.

[0022] Figure 4 This is a schematic diagram of the structure of a field-effect transistor in another embodiment of this application. Detailed Implementation

[0023] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0026] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0028] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0029] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0030] In traditional field plate processes, using STI (Shallow Trench Isolation) offers advantages such as simplicity and strong compatibility. However, this process has drawbacks. The STI structure creates shallow trenches in the current paths between the source and drain of the device, lengthening the current flow distance. Furthermore, the presence of silicon dioxide in these shallow trenches prevents optimal impurity distribution in the N-wells (for NLDMOS), thus hindering the optimization of the LDMOS's on-resistance. In contrast, using LOCOS (Local Oxidation Coefficient) allows for thickness adjustment based on different voltage withstand requirements. The relatively flat voltage withstand region also results in shorter current paths between the source and drain, facilitating optimized on-resistance. However, this approach has disadvantages. Localized thermal oxidation (TOO) involves the reaction of oxygen with silicon to grow silicon dioxide, which can affect wafer surface planarization, stress, and the impurity distribution in the formed N-wells and P-wells. The bird's beak effect inherent in LOCOS further limits the reduction of the device's lateral critical dimensions, and the presence of stress can easily lead to lattice defects at the LOCOS edges, increasing on-resistance.

[0031] This application proposes a field-effect transistor with a novel field plate structure and its manufacturing method. Without adding additional photolithography layers and process steps, a stepped contact field plate (CFP) structure is formed above the drift region, resulting in a more uniform electric field distribution at the front and rear of the drift region. Furthermore, by eliminating the use of STI and LOCOS structures as field oxides on the drift region, the application avoids the reduced on-resistance caused by using STI or LOCOS structures as field oxides.

[0032] Figure 1 This is a flowchart of a method for manufacturing a field-effect transistor according to an embodiment of this application, including the following steps:

[0033] S110, to obtain a wafer with a drift region, source region, drain region and gate formed.

[0034] In one embodiment of this application, the field-effect transistor to be fabricated is an LDMOS. In one embodiment of this application, the front-end process can be performed using LDMOS fabrication methods known in the art to form structures such as a substrate 110, a drift region 120, a source region 132, a drain region 134, and a gate 136, up to the step of forming a metal silicide barrier layer.

[0035] Drift region 120, source region 132 and drain region 134 have the same conductivity type.

[0036] The gate 136 material can be polycrystalline silicon.

[0037] S120 forms a metal silicide barrier layer.

[0038] Self-aligned metallicide (salicide) is a relatively simple and convenient contact metallization process. During the fabrication of semiconductor devices, some areas require a salicide process, while others require a non-salicide process. For devices requiring a non-salicide process, the properties of salicide are utilized by covering the areas requiring non-salicide with a material that does not react with the metal. This material used to cover non-salicide devices is called a self-aligned silicide area block (SAB), which is the metallicide barrier layer 140 in this application.

[0039] A metal silicide barrier layer 140 is at least partially located between the gate 136 and the drain region 134. The metal silicide barrier layer 140 includes an oxide layer 142 and an etch stop layer 144 on the oxide layer 142. The etch stop layer 144 is used to prevent further etching when etching silicon oxide (i.e., when the interlayer dielectric layer above the etch stop layer 144 is etched through). The thickness of the oxide layer 142 is set according to the voltage withstand requirements of the device.

[0040] S130 forms an interlayer dielectric layer.

[0041] An interlayer dielectric (ILD) layer 150 is formed, covering the source region 132, drain region 134, gate 136 and metal silicide barrier layer 140.

[0042] The interlayer dielectric layer 150 can be a silicon oxide layer, such as a doped or undoped silicon oxide material layer formed using thermal chemical vapor deposition (TCVD) or high-density plasma chemical vapor deposition (HDPCVD) processes. Specifically, it can be undoped silicon glass (USG), silicon phosphosilicate glass (PSG), or borosilicate phosphosilicate glass (BPSG). Alternatively, the interlayer dielectric layer 150 can also be a boron-doped or phosphorus-doped spin-on-glass (SOG), a phosphorus-doped tetraethoxysilane (PTEOS), or a boron-doped tetraethoxysilane (BTEOS), etc.

[0043] In one embodiment of this application, before forming the interlayer dielectric layer 150, a metal silicide is further formed on the surfaces of the source region 132, the drain region 134, and the gate region 136 that are not covered by the metal silicide barrier layer 140. Figure 2 (not shown in the figure) Step. In order to reduce contact resistance, metal silicides may be formed on the surface of source region 132, drain region 134 and gate 136, wherein the metal silicides may include materials such as CoSix, NiSix and PtSix or combinations thereof.

[0044] S140 uses a contact hole photomask for photolithography to form contact hole etching windows and hole field plate etching windows.

[0045] In one embodiment of this application, photoresist is coated on the interlayer dielectric layer 150, and then exposure is performed using a contact hole photomask. The contact hole photomask includes contact hole patterns corresponding to each contact hole and field plate patterns corresponding to each recess of the field plate. After development, the contact hole patterns form contact hole etching windows, and a plurality of field plate etching windows corresponding to the field plate patterns are formed above the metal silicide barrier layer 140 between the gate 136 and the drain region 134. The width of each field plate etching window gradually increases in a first direction, which is the direction from the source region 132 to the drain region 134. In one embodiment of this application, each field plate etching window is rectangular, and the width of the rectangle gradually increases along the first direction. The field plate patterns on the photomask are also multiple corresponding rectangles, and the width of the rectangles gradually increases.

[0046] S150, etching to form contact holes and recesses.

[0047] The interlayer dielectric layer 150 is etched, and a contact hole penetrating the interlayer dielectric layer 150 is formed below the contact hole etching window. A corresponding recess is formed below each hole field plate etching window. Since the widths of the different hole field plate etching windows are different, the different recesses have different bottom depths; that is, the bottom depth gradually decreases in the first direction of the device, and the width of the recess gradually increases. In other words, due to the micro-loading effect of etching, the depth of the recess formed by etching decreases from deep to shallow in the first direction.

[0048] S160, fill the contact hole and recess with conductive material.

[0049] The conductive material can be a metal or an alloy, for example, tungsten plugs formed in the contact holes and recesses. After the recesses are filled with conductive material, a perforated field plate 160 is formed, i.e., the aforementioned CFP.

[0050] In the above-described method for manufacturing field-effect transistors, the photolithography and etching of the via field plate 160 can be performed simultaneously with the contact holes, eliminating the need for additional photolithography layers and process steps. Utilizing the micro-load effect of the via field plate 160 during etching, a stepped multi-level field plate can be formed, with the thickness gradually increasing from the source region 132 towards the drain region 134 and below the recessed portion. This allows for compatibility with high-voltage operating ranges and exhibits good ductility. Furthermore, STI and LOCOS structures, which serve as field oxides, can be omitted from the drift region 120, avoiding the reduction in on-resistance caused by using STI or LOCOS structures as field oxides.

[0051] In one embodiment of this application, after step S160, a step of forming a metal layer on the interlayer dielectric layer 150 is further included. The metal layer includes a first metal interconnect 172 that electrically connects the conductive material in the orifice field plate 160 to the conductive material in the source contact hole 171. (Refer to...) Figure 2 It is important to note that although in Figure 2 It is not shown in the figure, but the first metal connection 172 above the orifice plate 160 and the first metal connection 172 above the source contact hole 171 are connected as one.

[0052] Figure 2 In the embodiment shown, STI and LOCOS structures serving as field oxygen are not provided in the drift region 120 to avoid reducing the on-resistance.

[0053] In one embodiment of this application, the hole field pattern in the contact hole photomask is strip-shaped, and different stripes have different widths. Figure 3 This is a top view of grooves 162, 164, and 166 of the perforated plate 160 in one embodiment of this application. The shape of the perforated plate pattern is similar to... Figure 3 same. Figure 3 The three slots in the perforated plate 160 are merely an example; in other embodiments, the perforated plate 160 may also have four or more slots.

[0054] In one embodiment of this application, the etch stop layer 144 includes a nitride layer. Further, the etch stop layer 144 includes a silicon nitride layer and a silicon oxynitride layer on the silicon nitride layer.

[0055] exist Figure 2 In the illustrated embodiment, the oxide layer 142 extends a certain distance from the side near the drain region 134 into the bottom of the gate 136. Only a gate dielectric layer (e.g., gate oxide layer) is formed directly above the channel region of the field-effect transistor, without the oxide layer 142. A break region is formed in the middle of the oxide layer 142. The break region does not have the oxide layer 142 but only an etch stop layer 144. Oxide layers 142 are formed on both sides of the break region. A recess in the interlayer dielectric layer 150 closest to the gate 136 is located above the break region. Figure 2 In the illustrated embodiment, trench 162 is positioned above the fault region. Thus, gate 136 and its underlying oxide layer 142 constitute a first-level field plate, trench 162 constitutes a second-level field plate, trench 164 constitutes a third-level field plate, and trench 166 constitutes a fourth-level field plate. Specifically, trench 162 has only an etch stop layer 144 below it, without an oxide layer 142; trench 164 has an oxide layer 142 and an etch stop layer 144 below it, with the bottom of trench 164 contacting the etch stop layer 144; trench 166 has an interlayer dielectric layer 150 of a certain thickness below it, in addition to the oxide layer 142 and the etch stop layer 144.

[0056] In one embodiment of this application, the wafer obtained in step S110 further has a body region 122, and a source region 132 is formed in the body region 122. In one embodiment of this application, the drift region 120, the source region 132, and the drain region 134 have a first conductivity type, and the substrate 110 and the body region 122 have a second conductivity type.

[0057] This application correspondingly provides a field-effect transistor, which can be manufactured according to the manufacturing method of a field-effect transistor described in any of the foregoing embodiments. (Refer to...) Figure 2 In one embodiment of this application, the field-effect transistor includes a source region 132, a drain region 134, a drift region 120, a gate 136, a metal silicide barrier layer 140, an interlayer dielectric layer 150, and a via field plate 160. The drift region 120, source region 132, and drain region 134 have the same conductivity type. The drift region 120 is at least partially located between the source region 132 and the drain region 134. The gate 136 is located between the source region 132 and the drain region 134. The metal silicide barrier layer 140 is at least partially located between the gate 136 and the drain region 134, and the metal silicide barrier layer 140 includes an oxide layer 142 and an etch stop layer 144 on the oxide layer 142. The interlayer dielectric layer 150 covers the source region 132, the drain region 134, the gate 136, and the metal silicide barrier layer 140. The aperture plate 160 is located between the gate region 136 and the drain region 134, and includes a plurality of recesses filled with conductive material. Each recess extends downward into the interlayer dielectric layer 150, and the bottom of each recess is located on the metal silicide barrier layer 140. In the direction from the source region 132 to the drain region 134, the different recesses have different bottom depths, that is, the bottom depth gradually decreases in this direction; and the width of the recesses gradually increases in this direction, the width direction being the direction from the source region 132 to the drain region 134.

[0058] The aforementioned field-effect transistor utilizes the micro-load effect of the aperture field plate during the etching process to form a stepped multi-level field plate with progressively increasing thickness of the interlayer dielectric layer from the source region to the drain region and below the recess. It is compatible with high-voltage operating range and has good ductility.

[0059] Figure 2 In the embodiment shown, STI and LOCOS structures serving as field oxygen are not provided in the drift region 120 to avoid reducing the on-resistance.

[0060] In one embodiment of this application, the aperture field plate 160 is photolithographically formed using a contact hole photomask. The contact hole photomask includes aperture field plate patterns corresponding to each recess and contact hole patterns corresponding to each contact hole of the field-effect transistor. Each recess is formed simultaneously with each contact hole through etching. Figure 2In the illustrated embodiment, the perforated plate 160 includes three recesses, namely grooves 162, 164, and 166; in other embodiments, the perforated plate 160 may also have four or more grooves.

[0061] In one embodiment of this application, the field-effect transistor further includes a metal layer located on the interlayer dielectric layer 150. The metal layer includes a first metal interconnect 172 electrically connecting the conductive material in the via field plate 160 to the conductive material in the source contact via 171, as shown below. Figure 2 Although in Figure 2 It is not shown in the figure, but the first metal connection 172 above the orifice plate 160 and the first metal connection 172 above the source contact hole 171 are connected as one.

[0062] In one embodiment of this application, the etch stop layer 144 includes a nitride layer. Further, the etch stop layer 144 includes a silicon nitride layer and a silicon oxynitride layer on the silicon nitride layer.

[0063] In one embodiment of this application, the wafer obtained in step S110 further has a body region 122, and a source region 132 is formed in the body region 122. In one embodiment of this application, the drift region 120, the source region 132, and the drain region 134 have a first conductivity type, and the substrate 110 and the body region 122 have a second conductivity type.

[0064] In one embodiment of this application, Figure 2 The field-effect transistor shown is an NLDMOS, with N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments, the first conductivity type may be P-type and the second conductivity type may be N-type.

[0065] Figure 4 This is a schematic diagram of the structure of a field-effect transistor in another embodiment of this application. It is in... Figure 2 The substrate further includes a first conductivity type buried layer 112 located in the substrate 110. The first conductivity type buried layer 112 is located below the drift region 120 and is separated from the drift region 120 by a portion of the substrate 110.

[0066] Figure 4The field-effect transistor in the illustrated embodiment further includes an isolation well 123, a second conductivity type region 124 located within the isolation well 123, and an isolation lead-out region 125 located within the second conductivity type region 124. The isolation well 123 is located on the side of the drift region 120 away from the source region 132, and the bottom of the isolation well 123 extends to the first conductivity type buried layer 112. The isolation well 123 and the isolation lead-out region 125 have a second conductivity type. The doping concentration of the second conductivity type region 124 is greater than the doping concentration of the isolation well 123, and the doping concentration of the isolation lead-out region 125 is greater than the doping concentration of the second conductivity type region 124.

[0067] Figure 4 The field-effect transistor in the illustrated embodiment further includes a first conductivity type well region 126 and a buried lead-out region 127 located within the first conductivity type well region 126. The first conductivity type well region 126 is located on the side of the isolation well 123 away from the drift region 120, and the bottom of the first conductivity type well region 126 extends to a first conductivity type buried layer 112. The buried lead-out region 127 has a first conductivity type. The doping concentration of the buried lead-out region 127 is greater than the doping concentration of the first conductivity type well region 126.

[0068] Figure 4 The field-effect transistor in the illustrated embodiment further includes a second conductivity type well region 128 and a substrate lead-out region 129 located within the second conductivity type well region 128. The second conductivity type well region 128 is located on the side of the first conductivity type well region 126 away from the isolation well 123. The substrate lead-out region 129 has a second conductivity type. The doping concentration of the substrate lead-out region 129 is greater than the doping concentration of the second conductivity type well region 128.

[0069] Figure 4 The field-effect transistor in the illustrated embodiment also includes an STI 152. STI 152 is provided between the drain region 134 and the isolation lead-out region 125, between the isolation lead-out region 125 and the buried layer lead-out region 127, and between the buried layer lead-out region 127 and the substrate lead-out region 129.

[0070] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0071] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for manufacturing a field-effect transistor, comprising: Obtain a wafer with a drift region, source region, drain region and gate formed; The drift region is at least partially located between the source region and the drain region, and the gate is located between the source region and the drain region; A metal silicide barrier layer is formed, the metal silicide barrier layer being at least partially located between the gate and the drain region, the metal silicide barrier layer comprising an oxide layer and an etch stop layer on the oxide layer; An interlayer dielectric layer is formed covering the source region, drain region, gate, and metal silicide barrier layer; Photolithography is performed using a contact hole photomask to form contact hole etching windows and a plurality of aperture field plate etching windows above the metal silicide barrier layer between the gate and the drain regions on the interlayer dielectric layer. The width of each aperture field plate etching window gradually increases in a first direction, and the width direction is the first direction, which is the direction from the source region to the drain region. Through etching, a contact hole penetrating the interlayer dielectric layer is formed below the contact hole etching window, and a number of corresponding recesses are formed below the number of hole field plate etching windows; in the first direction, different recesses have different bottom depths, that is, the bottom depth gradually becomes shallower in the first direction, and the width of the recess gradually becomes wider in the first direction, with the width direction being the first direction. The contact holes and each of the recesses are filled with conductive material.

2. The method for manufacturing a field-effect transistor according to claim 1, characterized in that, No STI and LOCOS structures serving as field oxygen are provided on the drift region.

3. The method for manufacturing a field-effect transistor according to claim 1 or 2, characterized in that, The etching stop layer includes a nitrided layer.

4. The method for manufacturing a field-effect transistor according to claim 3, characterized in that, The etching stop layer includes a silicon nitride layer and a silicon oxynitride layer on the silicon nitride layer.

5. The method for manufacturing a field-effect transistor according to claim 1 or 2, characterized in that, The pattern in the contact hole photomask corresponding to the etching window of the hole field plate is strip-shaped, and different stripes have different widths.

6. The method for manufacturing a field-effect transistor according to claim 1 or 2, characterized in that, The contact hole includes a source contact hole that leads out the source region; The manufacturing method further includes the step of forming a metal layer on the interlayer dielectric layer, the metal layer including a first metal wire electrically connecting the conductive material in each of the recesses to the conductive material in the source contact hole.

7. The method for manufacturing a field-effect transistor according to claim 1 or 2, characterized in that, The oxide layer extends from the side near the drain region into the bottom of the gate by a certain distance. Only the gate dielectric layer is formed directly above the channel region of the field-effect transistor, and the oxide layer is not formed therein. The oxide layer forms a fault region, and the fault region is not provided with the oxide layer but only with an etch stop layer. The oxide layer is provided on both sides of the fault region. The one of the recesses closest to the gate is provided above the fault region, and the bottom of the recess extends to the etch stop layer in the fault region.

8. A field-effect transistor, characterized in that, include: Source region; Drain region; The drift region is at least partially located between the source region and the drain region; The gate is located between the source region and the drain region; A metal silicide barrier layer, at least partially located between the gate and the drain region, the metal silicide barrier layer comprising an oxide layer and an etch stop layer on the oxide layer; An interlayer dielectric layer covers the source region, drain region, gate, and metal silicide barrier layer; The aperture plate, located between the gate and the drain region, includes several recesses filled with conductive material. Each recess extends downward into the interlayer dielectric layer and its bottom is located on the metal silicide barrier layer. In a first direction, different recesses have different bottom depths, that is, the bottom depth gradually becomes shallower in the first direction, and the width of the recess gradually becomes wider in the first direction. The width direction is the first direction, which is the direction from the source region to the drain region.

9. The field-effect transistor according to claim 8, characterized in that, The aperture plate is photolithographically formed using a contact hole photolithography plate. The contact hole photolithography plate includes patterns corresponding to each of the recesses and patterns corresponding to each contact hole of the field-effect transistor. Each of the recesses is formed by etching simultaneously with each of the contact holes.

10. The field-effect transistor according to claim 9, characterized in that, The pattern corresponding to each recess in the contact hole photomask is a strip, and different stripes have different widths.

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