Grid-control junction field effect transistor

Abstract

The invention provides a grid-controlled junction field effect transistor, which comprises a substrate and an epitaxial layer formed on the substrate, the drain electrode is formed on the back side of the substrate; the channel region of the second doping type is formed at a downward position of the top surface of the epitaxial layer; the second doping type source electrode contact region is formed at the downward position of the top surface of the epitaxial layer and is connected to the outer edge of the channel region; the well region of the first doping type is positioned below the source contact region of the second doping type and the channel region; the gate region of the first doping type is formed on the channel region in the vertical direction; the tunneling connection layer is formed on the gate region; and a gate electrode for connecting a gate voltage formed on the tunneling connection layer in the vertical direction. The technical problem that the gate leakage current Igss of a traditional gate-controlled junction field effect transistor is large is solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a gate-controlled junction field-effect transistor. Background Technology

[0002] Silicon carbide (SiC) devices offer advantages such as high voltage withstand capability, low on-resistance, faster switching speed, higher operating temperature, better heat dissipation, and good radiation resistance, leading to their widespread application in power electronic circuits. SiC devices include MOSFETs and JFETs.

[0003] JFET (Junction Field-Effect Transistor) devices are three-port devices that operate by using voltage applied to the gate region to control the reverse and forward bias of the PN junction, thereby controlling the channel to turn on and off. They have advantages such as low noise, small size, and high-frequency response. JFET devices made of silicon carbide can also be used in high-power applications, such as new energy vehicles and high-voltage power transmission.

[0004] Figure 1 This is a schematic diagram of a gate-controlled junction field-effect transistor (GFET) according to patent application CN119947202A. Figure 1 The gate-controlled junction field-effect transistor shown has no gate dielectric layer. A PN junction exists between the gate region 4 and the source, making it an enhancement-mode device with a positive threshold voltage Vth. When the device is forward-biased, a positive voltage is applied to the gate region, resulting in a large gate leakage current Igss, sometimes reaching 100mA. This increases the difficulty of driving the transistor and also leads to higher power consumption.

[0005] Therefore, the gate leakage current Igss of traditional gate-controlled junction field-effect transistors is relatively large, which is a technical problem that urgently needs to be solved by those skilled in the art.

[0006] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0007] This application provides a gate-controlled junction field-effect transistor to solve the technical problem of large gate leakage current Igss in traditional gate-controlled junction field-effect transistors.

[0008] This application provides a gate-controlled junction field-effect transistor, comprising:

[0009] Substrate, epitaxial layer formed on the substrate;

[0010] A drain electrode is formed on the back side of the substrate;

[0011] The second type of doped channel region is formed at a position facing downwards from the top surface of the epitaxial layer;

[0012] The second doped source contact region is formed at a position facing downwards from the top surface of the epitaxial layer and is connected to the outer edge of the channel region;

[0013] The well region of the first doping type is located below the source contact region of the second doping type and the channel region;

[0014] A gate region of the first doped type is formed on the channel region in the vertical direction;

[0015] A tunneling connection layer is formed above the gate region;

[0016] A gate electrode for connecting the gate voltage is formed vertically on the tunneling connection layer.

[0017] This application, by adopting the above technical solution, has the following technical effects:

[0018] The gate-controlled junction field-effect transistor (GJFET) of this application has a tunneling connection layer between the gate region and the gate electrode. When the GJFET is turned on, the tunneling current generated by the electron tunneling effect in the tunneling connection layer is very small. Therefore, the gate leakage current Igss of the GJFET of this application is very small when it is turned on, typically in the range of a few mA. At the same time, the breakdown voltage BV of the GJFET of this application can also be relatively large. Attached Figure Description

[0019] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0020] Figure 1 This is a schematic diagram of the gate-controlled junction field-effect transistor (GFET) according to patent application CN119947202A.

[0021] Figure 2 This is a schematic diagram of the gate-controlled junction field-effect transistor of this application;

[0022] Figure 3 The thickness of the gate dielectric layer in the prior art is Simulation diagram of the gate-controlled junction field-effect transistor structure;

[0023] Figure 4 The thickness of the gate dielectric layer serving as the tunneling connection layer in this application is [missing information]. Simulation diagram of the gate-controlled junction field-effect transistor structure;

[0024] Figure 5 For existing technology Figure 1 The thickness of the gate dielectric layer is Simulation diagram of the structure of a gate-controlled junction field-effect transistor;

[0025] Figure 6 for Figures 3 to 5 A comparison of the conduction curves of a gate-controlled junction field-effect transistor when it is turned on at a gate-source voltage of Vgs = 2.8V;

[0026] Figure 7 The thickness of the gate dielectric layer in the prior art is Simulation diagram of the source-drain current distribution Ids of a gate-controlled junction field-effect transistor with Ids = 0.001A as the blocking current when the gate-source voltage Vgs = 0V is 0V.

[0027] Figure 8 The thickness of the gate dielectric layer serving as the tunneling connection layer in this application is [missing information]. Simulation diagram of the source-drain current distribution Ids of a gate-controlled junction field-effect transistor with Ids = 0.001A as the blocking current when the gate-source voltage Vgs = 0V is 0V.

[0028] Figure 9 For existing technology Figure 1 The thickness of the gate dielectric layer is Simulation diagram of the source-drain current distribution Ids of a gate-controlled junction field-effect transistor with Ids = 0.001A as the blocking current when the gate-source voltage Vgs = 0V is 0V.

[0029] Figure 10 for Figures 7 to 9 A comparison of the blocking states of a gate-controlled junction field-effect transistor when the gate-source voltage Vgs = 0V.

[0030] Figure 11 The thickness of the gate dielectric layer in the prior art is Simulation diagram of the gate current Igs distribution of a gate-controlled junction field-effect transistor when the gate-source voltage Vgs = 3V;

[0031] Figure 12 The thickness of the gate dielectric layer, which serves as the tunneling connection layer 15 in this application, is [missing information]. Simulation diagram of gate current Igs distribution of gate-controlled junction field-effect transistor when gate-source voltage Vgs = 3V;

[0032] Figure 13 For existing technology Figure 1 The thickness of the gate dielectric layer is Simulation diagram of the gate current Igs distribution of a gate-controlled junction field-effect transistor when the gate-source voltage Vgs = 3V;

[0033] Figure 14 for Figures 11 to 13A comparison of the gate current Igs curves of gate-controlled junction field-effect transistors when the gate-source voltage Vgs = 0V to 3V and Vds = 0V.

[0034] Figure label:

[0035] Well region 1, first-doped source contact region 2, second-doped source contact region 3,

[0036] Gate region 4, channel region 5, source electrode 6, gate electrode 7, dielectric layer 9, current guiding layer 10, epitaxial layer 11, buffer layer 12, substrate 13, drain electrode 14, tunneling connection layer 15. Detailed Implementation

[0037] To make the technical solutions and advantages of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0038] This application aims to solve the technical problem of high input capacitance and gate leakage current, which leads to high switching losses.

[0039] Example 1

[0040] like Figure 2 As shown, the gate-controlled junction field-effect transistor of this application includes:

[0041] Substrate 13, epitaxial layer formed on said substrate 13;

[0042] Drain electrode 14 is formed on the back side of the substrate 13;

[0043] The second type of doped channel region 5 is formed at a position facing downwards from the top surface of the epitaxial layer;

[0044] The second doped source contact region 3 is formed at a position facing downwards from the top surface of the epitaxial layer and is connected to the outer edge of the channel region 5;

[0045] The first doped type well region 1 is located below the second doped type source contact region 3 and the channel region 5;

[0046] A gate region 4 of the first doped type is formed on the channel region 5 in the vertical direction;

[0047] A tunneling connection layer 15 is formed on the grid region 4;

[0048] The gate electrode 7, used to connect the gate voltage, is formed vertically on the tunneling connection layer 15.

[0049] In practice, when the voltage between the gate electrode 7 and the gate region 4 does not reach the preset voltage and the tunneling connection layer 15 does not experience electron tunneling effect, the tunneling connection layer 15 electrically isolates the gate electrode 7 and the gate region 4, and the gate region 4 is in a floating state.

[0050] When a voltage is formed between the gate electrode 7 and the gate region 4 to a preset voltage, causing the tunneling connection layer 15 to undergo an electron tunneling effect, the tunneling current generated by the tunneling connection layer 15 will weakly connect the gate electrode 7 and the gate region 4, so that the potential of the gate region 4 is determined by the gate electrode 7.

[0051] Specifically, the preset voltage is the minimum voltage between the gate electrode 7 and the gate region 4 when the tunneling connection layer 15 experiences electron tunneling. The value of the preset voltage is related to the material and thickness of the tunneling connection layer 15.

[0052] In a gate-controlled junction field-effect transistor (JFET), the gate leakage current should theoretically be very small, ideally close to zero, when the device is in the forward conduction state. This is because the PN junction between the gate and channel regions is reverse-biased under normal operating conditions, and a reverse-biased PN junction theoretically does not allow current to flow. However, in practical applications, due to factors such as material defects, surface states, and temperature, a small gate leakage current, Igss, still exists. A key reason for the existence of gate leakage current Igss in practical applications is the reverse saturation current of the PN junction between the gate and channel regions.

[0053] The reverse saturation current of a PN junction is formed for the following reasons:

[0054] When a PN junction is reverse biased, the direction of the applied electric field is the same as that of the built-in electric field, which enhances the effect of the depletion layer and prevents the flow of majority carriers, but allows minority carriers (i.e., electrons in the P region and holes in the N region) to pass through the depletion layer and form a reverse current, i.e., the reverse saturation current of the PN junction.

[0055] like Figure 1 As shown in the background art, in Figure 1 The P-type heavily doped gate region 4 and gate electrode 7 of the gate-controlled junction field-effect transistor are directly connected, that is, there is always a strong electrical connection between the gate region 4 and the gate electrode 7.

[0056] When the background technology Figure 1When the gate-controlled junction field-effect transistor (GJFET) is turned on, the PN junction formed by the P-type gate region 4 and the N-type channel region 5 is forward biased, resulting in a forward turn-on current in the PN junction. Due to the strong electrical connection between the gate region 4 and the gate electrode 7, the forward turn-on current flows out through the gate region 4 and the gate electrode 7, leading to a large gate leakage current Igss, sometimes reaching 100mA. This is described in the background section. Figure 1 When the gate-controlled junction field-effect transistor is turned on, the strong electrical connection between the gate region 4 and the gate electrode 7 results in a large gate leakage current Igss, which can even reach 100mA.

[0057] For ease of description, the following explanation will use P-type as the first doping type and N-type as the second doping type. Figure 2 As shown, the gate-controlled junction field-effect transistor of this application has a tunneling connection layer 15 between the gate region 4 and the gate electrode 7.

[0058] In this application, the source electrode and drain electrode 14 of the gate-controlled junction field-effect transistor are connected to the main circuit (the source is grounded, that is, the source contact region 3 corresponding to the second doping type is grounded; the drain electrode 14 is connected to the drain voltage), and the gate electrode 7 is connected to the control circuit.

[0059] In this application, when a forward bias voltage (e.g., 3V) is applied to the gate electrode 7, the tunneling current generated by the tunneling connection layer 15 weakly connects the gate electrode 7 and the gate region 4, changing the potential of the gate region 4 so that its potential is close to that of the gate electrode 7. That is, the potential of the gate region 4 is determined by the potential of the gate electrode 7, ensuring that the gate region 4 is not in a floating state. At this time, the depletion layers of the PN junction formed by the gate region 4 and the channel region 5, and the PN junction formed by the well region 1 and the channel region 5, shrink, and the device turns on.

[0060] The tunneling current generated by the electron tunneling effect in the tunneling connection layer 15 is very small. Therefore, the gate-source-drain current Igss of the gate-controlled junction field-effect transistor of this application is very small when it is turned on, typically in the range of a few mA. This is far less than that in the prior art. Figure 1 The gate leakage current Igss of the gate-controlled junction field-effect transistor is 100mA when it is turned on.

[0061] When the drain voltage of the gate-controlled junction field-effect transistor (GMT-J) of this application is applied and the gate electrode 7 is reverse biased or biased to zero, the drain voltage causes a coupling voltage to the gate region 4, increasing the potential of the gate region 4. The voltage between the gate region 4 and the gate electrode 7 reaches a preset voltage, causing electron tunneling in the tunneling connection layer 15. The tunneling current generated by the tunneling connection layer 15 weakly connects the gate electrode 7 and the gate region 4, making the potential of the gate region 4 close to that of the gate electrode 7. That is, the potential of the gate region 4 is still determined by the potential of the gate electrode 7. At this time, the PN junction formed by the gate region 4 and the channel region 5, and the PN junction formed by the well region 1 and the channel region 5, are depleted, and the device is turned off.

[0062] Existing technologies include gate-controlled junction field-effect transistors (GJFETs) with a gate dielectric layer, where a gate dielectric layer is placed between the gate region and the gate electrode. This gate dielectric layer primarily serves an isolation function. A problem with GJFETs with a gate dielectric layer is that the breakdown voltage (BV) cannot be achieved at a high level. The reasons are as follows:

[0063] In existing gate-controlled junction field-effect transistors (GJFETs) with a gate dielectric layer, when a drain voltage is applied to the drain electrode (i.e., a voltage is applied between the drain and source electrodes) and a zero-bias voltage is applied to the gate electrode, the drain voltage causes a coupling voltage to the gate region, increasing the potential of the gate region. This results in the PN junction between the gate and channel regions being forward biased, and the device turning on. In other words, GJFETs with a gate dielectric layer can also turn on even with a zero-bias voltage. Therefore, GJFETs with a gate dielectric layer have the drawback of not being able to achieve a high breakdown voltage.

[0064] In practice, the thickness of the tunneling connection layer is limited to the point that electron tunneling can occur when the gate electrode 7 is connected to both forward and reverse bias voltages and the drain electrode 14 is connected to the drain voltage.

[0065] In practice, the material of the tunneling connection layer 15 is silicon dioxide, aluminum oxide, hafnium dioxide, or magnesium oxide.

[0066] In practice, the thickness of the tunnel connection layer 15 is greater than or equal to [value missing]. and less than or equal to

[0067] Specifically, the well region 1, the second doped source contact region 3, the gate region 4, and the channel region 5 form a JFET structure.

[0068] In the gate-controlled junction field-effect transistor of this application, since the gate region 4 is formed vertically above the channel region 5, and the outer edge of the gate region 4 is located within the outer edge of the channel region 5 in the lateral direction (i.e., the gate region 4 is smaller than the channel region 5), the gate region 4 and the second-doped source contact region 3 maintain a predetermined distance in the lateral direction. This ensures that the first-doped gate region 4 and the second-doped source contact region 3 are completely non-contacting and do not form a PN junction. Therefore, during the turn-on and turn-off processes of the gate-controlled junction field-effect transistor of this application, the first-doped gate region 4 and the second-doped source contact region 3 do not form a PN junction. The absence of a PN junction between the first-doped gate region 4 and the second-doped source contact region 3 has at least the following advantages:

[0069] The gate region 4 of the first doping type and the source contact region 3 of the second doping type doping type do not have a PN junction, which makes the input capacitance of the gate-controlled junction field-effect transistor of this application very small; the small input capacitance makes the gate-controlled junction field-effect transistor have a fast switching speed and a low switching loss.

[0070] If the first-doped gate region 4 and the second-doped source contact region 3 directly form a PN junction, then the PN junction between them will have leakage current, leading to gate leakage. In the gate-controlled junction field-effect transistor of this application, the first-doped gate region 4 and the second-doped source contact region 3 do not form a PN junction, thus preventing gate leakage.

[0071] In addition, because the gate region 4 is separated from the second doped source contact region 3, this can adjust the forward and reverse leakage current between the gate and source, thereby improving the reliability of device operation and reducing drive losses.

[0072] The current path of the gate-controlled junction field-effect transistor in this application during conduction is used as follows: Figure 2 The dashed line with an arrow in the middle is an illustration.

[0073] The reason why the input capacitance of the gate-controlled junction field-effect transistor in this application is very small will be explained in detail:

[0074] If gate region 4 and the second doped source contact region 3 are in contact, a PN junction will be formed between gate region 4 and the second doped source contact region 3, resulting in a PN junction capacitance between them. The input capacitance is primarily formed by the PN junction capacitance between gate region 4 and the second doped source contact region 3.

[0075] In this application, the gate region 4 of the first doped type and the source contact region 3 of the second doped type are completely non-contacting, and they do not form a PN junction, nor do they have a corresponding capacitance. Therefore, the input capacitance of the gate-controlled junction field-effect transistor of this application is very small.

[0076] The gate-controlled junction field-effect transistor of this application also retains the advantages of traditional gate-controlled junction field-effect transistors, such as reliability and electrical performance.

[0077] Specifically, such as Figure 2 and Figure 3 As shown, the well region 1, the second doped source contact region 3, the gate region 4, and the channel region 5 form a JFET structure, which is controlled by a single gate (i.e. by the gate region 4) and the channel is turned on and off by the change of the PN junction depletion region formed by the first doped gate region 4 and the second doped channel region 5.

[0078] Specifically, as an optional approach, the first doping type is P-type and the second doping type is N-type. The accompanying drawings in this application all depict P-type as the first doping type and N-type as the second doping type.

[0079] Specifically, as an alternative approach, the first doping type is N-type and the second doping type is P-type.

[0080] During implementation, such as Figure 2 and Figure 3 As shown, the preset spacing between the gate region 4 and the second doped source contact region 3 in the lateral direction is greater than 0 μm and less than or equal to 0.3 μm.

[0081] The preset spacing between the first doped gate region 4 and the second doped source contact region 3 ensures that the first doped gate region 4 and the second doped source contact region 3 will not make contact at all and will not form a PN junction.

[0082] The preset distance between the gate region 4 and the second doped source contact region 3 in the lateral direction should not be too large. If the preset distance between the gate region 4 and the second doped source contact region 3 in the lateral direction is too large, the on-resistance will increase.

[0083] During implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field-effect transistor of this application further includes:

[0084] The source electrode 6 is formed on the second doped source contact region 3, and the distance between the source electrode 6 and the gate region 4 is greater than the distance between the second doped source contact region 3 and the gate region 4.

[0085] A dielectric layer 9 is filled between the source electrode 6, the gate electrode 7, and the gate region 4.

[0086] The dielectric layer 9 fills the space between the source electrode 6, the gate electrode 7, and the gate region 4, and is located above the portion of the second-doped source contact region 3 and the channel region 5 exposed between the source electrode 6 and the gate region 4. In this way, the dielectric layer 9 completely separates the second-doped source contact region 3 and the gate region 4, ensuring they do not contact each other.

[0087] During implementation, such as Figure 2 and Figure 3 As shown, the doping concentration of the gate region 4 ranges from greater than or equal to 1 × 10⁻⁶. 18 cm -3 ;

[0088] The doping concentration of the second doped source contact region 3 is greater than or equal to 1 × 10⁻⁶. 18 cm -3 .

[0089] Gate electrode 7 and source electrode 6 are typically made of metallic materials. The high doping concentration of gate region 4 results in a lower connection resistance between gate electrodes 7 and 6. Similarly, the high doping concentration of the second-doped source contact region 3 results in a lower connection resistance between the second-doped source contact region 3 and source electrode 6.

[0090] The high doping concentration of gate region 4 results in a wider depletion range between gate region 4 and channel region 5, leading to a higher breakdown voltage BV and a lower gate-source voltage Vgs.

[0091] During implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field-effect transistor also includes:

[0092] The first doped source contact region 2 is formed downward from the top surface of the epitaxial layer, and the first doped source contact region 2 is connected to the side of the second doped source contact region 3 away from the channel region 5.

[0093] A second doped buffer layer 12 is formed between the substrate 13 and the epitaxial layer 11;

[0094] A second doped current guiding layer 10 is formed beneath the channel region 5 and the well region 1.

[0095] Specifically, the doping concentration of the current guiding layer 10 is greater than that of the epitaxial layer 11.

[0096] During implementation, such as Figure 2 and Figure 3 As shown, the gate-controlled junction field-effect transistor has a symmetrical structure, and there are two of each of the following: well region 1, first-doped source contact region 2, second-doped source contact region 3, source electrode 6, and dielectric layer 9.

[0097] During implementation, such as Figure 2 and Figure 3 As shown, the doping concentration of well region 1 ranges from greater than or equal to 1 × 10⁻⁶. 17 cm -3 Less than or equal to 1×10 18 cm -3 ;

[0098] The doping concentration of the first doped source contact region 2 is greater than or equal to 1 × 10⁻⁶. 18 cm -3 .

[0099] Figure 3 The thickness of the gate dielectric layer in the prior art is Simulation diagram of the gate-controlled junction field-effect transistor structure;

[0100] Figure 4 The thickness of the gate dielectric layer serving as the tunneling connection layer in this application is [missing information]. Simulation diagram of the gate-controlled junction field-effect transistor structure;

[0101] Figure 5 For existing technology Figure 1 The thickness of the gate dielectric layer is Simulation diagram of the structure of a gate-controlled junction field-effect transistor;

[0102] Figure 6 for Figures 3 to 5 A comparison of the conduction curves of a gate-controlled junction field-effect transistor when it is turned on at a gate-source voltage of Vgs = 2.8V.

[0103] like Figure 3 , Figure 4 , Figure 5 and Figure 6 As shown, with a gate-source voltage Vgs = 2.8V, the conduction curves of the three gate-controlled junction field-effect transistors are very similar when they are turned on.

[0104] Figure 7 The thickness of the gate dielectric layer in the prior art is Simulation diagram of the source-drain current distribution Ids of a gate-controlled junction field-effect transistor with Ids = 0.001A as the blocking current when the gate-source voltage Vgs = 0V is 0V.

[0105] Figure 8 The thickness of the gate dielectric layer serving as the tunneling connection layer in this application is [missing information]. Simulation diagram of the source-drain current distribution Ids of a gate-controlled junction field-effect transistor with Ids = 0.001A as the blocking current when the gate-source voltage Vgs = 0V is 0V.

[0106] Figure 9 For existing technology Figure 1 The thickness of the gate dielectric layer is Simulation diagram of the source-drain current distribution Ids of a gate-controlled junction field-effect transistor with Ids = 0.001A as the blocking current when the gate-source voltage Vgs = 0V is 0V.

[0107] Figure 10 for Figures 7 to 9 A comparison of the blocking states of a gate-controlled junction field-effect transistor when the gate-source voltage Vgs = 0V.

[0108] like Figure 7 , Figure 8 , Figure 9 and Figure 10 As shown, when the gate-source voltage Vgs = 0V, the gate-controlled junction field-effect transistor is blocked:

[0109] The thickness of the gate dielectric layer is When the source-drain voltage Vds is very small, the blocking current of the gate-controlled junction field-effect transistor increases rapidly, indicating that the thickness of the gate dielectric layer is [missing information]. The gate-controlled junction field-effect transistor has a relatively low breakdown voltage, meaning it has poor voltage withstand capability.

[0110] The thickness of the gate dielectric layer is In a gate-controlled junction field-effect transistor, the blocking current only increases rapidly when the source-drain voltage Vds is very large, indicating that the thickness of the gate dielectric layer is... The gate-controlled junction field-effect transistor has the highest breakdown voltage, that is, the best withstand voltage.

[0111] The thickness of the gate dielectric layer in this application is The gate-controlled junction field-effect transistor (GFET) only experiences a rapid increase in blocking current when the source-drain voltage Vds is relatively large, indicating that the thickness of the gate dielectric layer is... The gate-controlled junction field-effect transistor has a larger breakdown voltage, that is, better withstand voltage.

[0112] Figure 11 The thickness of the gate dielectric layer in the prior art is Simulation diagram of the gate current Igs distribution of a gate-controlled junction field-effect transistor when the gate-source voltage Vgs = 3V;

[0113] Figure 12 The thickness of the gate dielectric layer, which serves as the tunneling connection layer 15 in this application, is [missing information]. Simulation diagram of gate current Igs distribution of gate-controlled junction field-effect transistor when gate-source voltage Vgs = 3V;

[0114] Figure 13 For existing technology Figure 1 The thickness of the gate dielectric layer is Simulation diagram of the gate current Igs distribution of a gate-controlled junction field-effect transistor when the gate-source voltage Vgs = 3V;

[0115] Figure 14 for Figures 11 to 13 A comparison of the gate current Igs curves of gate-controlled junction field-effect transistors when the gate-source voltage Vgs = 0V to 3V and Vds = 0V.

[0116] like Figure 11 , Figure 12 , Figure 13 and Figure 14 As shown, when the gate-source voltage Vgs = 3V, the PN junction of the gate region 4 and the channel region 5 of the gate-controlled junction field-effect transistor is forward biased:

[0117] The thickness of the gate dielectric layer is In a gate-controlled junction field-effect transistor, the gate electrode and the gate region are in direct contact. When the PN junction of the gate region 4 and the channel region 5 is forward biased, as shown in the curve, the gate source voltage Vgs = 2.5V, the gate current Igs increases rapidly, which leads to an increase in the gate source drain current Igss after the device is turned on, resulting in a large drive power consumption.

[0118] The thickness of the gate dielectric layer is The thickness of the gate dielectric layer between the gate electrode and the gate region of the gate-controlled junction field-effect transistor is When the PN junction of gate region 4 and channel region 5 is forward biased, as shown in the curve Vgs = 3V, the gate current Igs begins to increase, resulting in a smaller gate-source-drain current Igss after the device is turned on, and lower drive power consumption.

[0119] The thickness of the gate dielectric layer is The thickness of the gate dielectric layer between the gate electrode and the gate region of the gate-controlled junction field-effect transistor is . When the PN junction of gate region 4 and channel region 5 is forward biased, if the gate current Igs in the curve does not show an increasing trend, the gate-source-drain current Igss will be minimized after the device is turned on, resulting in very low drive power consumption.

[0120] In summary, the thickness of the gate dielectric layer in the prior art is The gate-controlled junction field-effect transistor has the lowest breakdown voltage and very low drive power consumption;

[0121] The thickness of the gate dielectric layer in the prior art is The gate-controlled junction field-effect transistor has the highest breakdown voltage and the highest drive power consumption.

[0122] The thickness of the gate dielectric layer is The gate-controlled junction field-effect transistor of this application has a large breakdown voltage and low drive power consumption, making it a gate-controlled junction field-effect transistor with good overall performance.

[0123] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0124] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0125] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0126] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0127] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0128] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A gate-controlled junction field-effect transistor, characterized in that, include: Substrate (13), epitaxial layer formed on said substrate (13); A drain electrode (14) is formed on the back side of the substrate (13); The second doped type of channel region (5) is formed at a position facing downwards from the top surface of the epitaxial layer; The second doped source contact region (3) is formed at a position facing downwards from the top surface of the epitaxial layer and is connected to the outer edge of the channel region (5); The first doped type well region (1) is located below the second doped type source contact region (3) and the channel region (5); A gate region (4) of the first doped type is formed on the channel region (5) in the vertical direction; A tunneling connection layer (15) is formed on the gate region (4); A gate electrode (7) for connecting the gate voltage is formed vertically on the tunneling connection layer (15).

2. The gate-controlled junction field-effect transistor according to claim 1, characterized in that, When the voltage between the gate electrode (7) and the gate region (4) does not reach the preset voltage and the tunneling connection layer (15) does not have an electron tunneling effect, the tunneling connection layer (15) electrically isolates the gate electrode (7) and the gate region (4), and the gate region (4) is in a floating state. When the voltage between the gate electrode (7) and the gate region (4) reaches a preset voltage, causing the tunneling connection layer (15) to undergo an electron tunneling effect, the tunneling current generated by the tunneling connection layer (15) will make a weak electrical connection between the gate electrode (7) and the gate region (4), so that the potential of the gate region (4) is determined by the gate electrode (7). The preset voltage is the minimum voltage between the gate electrode (7) and the gate region (4) when the tunneling connection layer (15) undergoes electron tunneling effect.

3. The gate-controlled junction field-effect transistor according to claim 2, characterized in that, When the gate electrode (7) is connected to a forward bias voltage, the drain electrode (14) is connected to a drain voltage, and the second doped source contact region (3) is grounded, the voltage between the gate electrode (7) and the gate region (4) reaches a preset voltage, causing the tunneling connection layer (15) to undergo an electron tunneling effect, making the gate electrode (7) and the gate region (4) electrically weakly connected, causing the depletion layer of the PN junction formed by the gate region (4) and the channel region (5) and the PN junction formed by the well region (1) and the channel region (5) to shrink, and the device turns on.

4. The gate-controlled junction field-effect transistor according to claim 3, characterized in that, When the gate electrode (7) is connected to a reverse bias voltage or is biased to zero, the drain electrode (14) is connected to a drain voltage, and the second doped source contact region (3) is grounded, the voltage between the gate electrode (7) and the gate region (4) reaches a preset voltage, causing the tunneling connection layer (15) to undergo an electron tunneling effect, which weakly connects the gate electrode (7) and the gate region (4). The PN junction formed by the gate region (4) and the channel region (5) and the PN junction formed by the well region (1) and the channel region (5) are depleted, and the device is turned off.

5. The gate-controlled junction field-effect transistor according to claim 4, characterized in that, The thickness of the tunneling connection layer is limited to the point that electron tunneling can occur when the gate electrode (7) is connected to both forward and reverse bias voltages and the drain electrode (14) is connected to the drain voltage.

6. The gate-controlled junction field-effect transistor according to claim 4, characterized in that, The thickness of the tunnel connection layer (15) is greater than or equal to the value of the specified value. and less than or equal to 7. The gate-controlled junction field-effect transistor according to any one of claims 1 to 6, characterized in that, The material of the tunneling connection layer (15) is silicon dioxide, aluminum oxide, hafnium dioxide, or magnesium oxide.

8. The gate-controlled junction field-effect transistor according to claim 7, characterized in that, In the lateral direction, the outer edge of the gate region (4) is located within the outer edge of the channel region (5), so that the gate region (4) and the second doped source contact region (3) maintain a preset distance in the lateral direction; The preset spacing between the gate region (4) and the second doped source contact region (3) in the lateral direction is greater than or equal to 0.1 μm and less than or equal to 0.3 μm.

9. The gate-controlled junction field-effect transistor according to claim 8, characterized in that, Also includes: A source electrode (6) is formed on the second doped source contact region (3), and the distance between the source electrode (6) and the gate region (4) is greater than the distance between the second doped source contact region (3) and the gate region (4); A dielectric layer (9) is filled between the source electrode (6), the gate electrode (7), and the gate region (4).

10. The gate-controlled junction field-effect transistor according to claim 9, characterized in that, Also includes: A first doped source contact region (2) is formed at a position facing downwards from the top surface of the epitaxial layer, and the first doped source contact region (2) is connected to the side of the second doped source contact region (3) away from the channel region (5). A second doped buffer layer (12) is formed between the substrate (13) and the epitaxial layer (11); A second doped current guiding layer (10) is formed beneath the channel region (5) and the well region (1).

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