An ESD-resistant enhanced power semiconductor device based on trench structure

Abstract

An ESD-enhanced power semiconductor device based on a trench structure is disclosed. To improve the device's ESD resistance, the device includes a gate metal layer and a gate bus. A field-limiting ring is provided inside the device. Multiple sets of parallel-arranged first trench gates are connected between the gate metal layer and the gate bus. A second trench gate is provided within the gate metal layer. The gate bus side is equivalent to an input capacitor. C iss The first trench gate and the field limiting ring form a capacitor. C G_pad The gate metal layer and the gate bus are connected through the first trench gate to form an equivalent resistance. R g_int The second trench gate and the field limiting ring form an equivalent capacitance. C G_tre , C G_tre and C G_pad in parallel. C G_tre It can provide an additional discharge path for ESD current, thereby reducing the current flowing through R g_int The current helps to share the instantaneous high voltage caused by ESD and improve the device's ESD resistance.

Description

Technical Field

[0001] This invention relates to power semiconductor devices, and more particularly to an ESD-enhanced power semiconductor device based on a trench structure. Background Technology

[0002] Power semiconductor devices, as the core of power conversion and control in power electronic systems, directly determine the stability and lifespan of the entire system. With the rapid development of industries such as new energy vehicles, photovoltaic inverters, and energy storage, the application demands and performance requirements of power semiconductor devices have significantly increased. To address this trend, semiconductor manufacturing processes have continuously improved, and device feature sizes have been constantly reduced in pursuit of lower conduction losses and faster switching speeds. However, the reduction in device size has also brought more severe challenges to the reliability of power semiconductor devices.

[0003] Electrostatic discharge (ESD) is the process by which charge rapidly transfers between two objects with different electrostatic potentials due to direct contact or electrostatic induction. For power semiconductor devices, the instantaneous high voltage and large current generated by ESD can cause irreversible damage. The specific damage mechanisms are mainly twofold: first, ESD current burn-out, which is essentially caused by the instantaneous large current released during ESD, creating localized high temperatures inside the device, leading to metal melting, dielectric carbonization, or burn-out of the semiconductor junction; second, overvoltage breakdown damage caused by ESD, where the insulating dielectric (oxide layer, silicon nitride layer) inside the device fails due to the electric field strength exceeding its breakdown field strength when the device is in a strong electrostatic field. Therefore, to improve the reliability of power semiconductor devices, it is necessary to optimize the device structure to enhance ESD resistance.

[0004] like Figure 1 The image shows a top view of a prior art power semiconductor device 100. The prior art device structure includes a gate metal layer and a gate bus. Multiple parallel trench gates are provided between the gate metal layer and the gate bus. The trench gates are filled with a polysilicon layer. An oxide layer is provided between the polysilicon layer and the field limiting ring. One end of the polysilicon layer is connected to the gate metal layer through a metal contact hole, and the other end is connected to the gate bus, effectively forming a built-in gate resistor. R g_int . Figure 2 This is a cross-sectional view along the Y direction of section AA'. The gate metal layer and gate bus are isolated from the field limiting ring by an insulating layer. To achieve parallel current sharing between power device chips, internal components are typically required within the device. R g_int On the other hand, built-in R g_intIt can balance switching speed and electromagnetic compatibility, suppress switching oscillations, simplifying circuit design for users and solving interference problems at the application end. With advancements in semiconductor manufacturing processes, the most advanced power semiconductor devices today typically employ contact-on-trench technology to save on polysilicon film layers and photomasks. R g_int This is typically achieved through a trench structure. By adjusting the doping concentration of the polysilicon, the thickness of the gate oxide layer at the bottom of the trench, and the number of polysilicon trenches, a suitable resistance value can be selected to match different application requirements.

[0005] However, Figure 1 The drawback of the device shown is its poor ESD protection. Because... Figure 1 The gate oxide layer of the device is relatively thin, and the instantaneous high voltage generated by ESD far exceeds the inherent breakdown electric field strength of the gate oxide layer, leading to gate oxide breakdown. Increasing the gate oxide layer thickness to improve the device's ESD resistance would increase the equivalent resistance of the gate circuit. R g_int This will increase accordingly, thus affecting the device's switching speed. Furthermore, the ESD discharge current flows through the internal gate resistor. R g_int At this time, a high amount of heat will accumulate in its local area; especially for ESD modes with extremely short charge discharge times, such as Charged Device Model (CDM) and Machine Model (MM) ESD, etc., through R g_int The energy released transiently is higher. If the current is too large, it may lead to... R g_int The oxide layer on the sidewall of the trench burned through, leading to device failure. Summary of the Invention

[0006] To address the problems existing in current power semiconductor devices, a structural design is needed to improve the device's ESD resistance without changing the gate resistance. The device includes a gate metal layer and a gate bus located on top of the device. A field-limiting ring is provided inside the device. Multiple sets of parallel-arranged first trench gates are connected between the gate metal layer and the gate bus. Each first trench gate includes a first polysilicon layer, a first oxide layer below the first polysilicon layer and between it and the field-limiting ring, and a metal contact hole above the first polysilicon layer. One end of the metal contact hole is connected to the gate metal layer, and the other end is connected to the gate bus. Both the gate metal layer and the gate bus are isolated from the field-limiting ring by an insulating layer. A second trench gate is also provided within the gate metal layer. The second trench gate includes a second polysilicon layer filled within the trench, a second oxide layer between the second polysilicon layer and the field-limiting ring, and one or more metal contact holes above the second polysilicon layer connecting to the gate metal layer. The gate bus side is equivalent to an input capacitor.C iss The first trench gate and the field limiting ring form a capacitor. C G_pad The gate metal layer and the gate bus are connected through the first trench gate to form an equivalent resistance. R g_int The second trench gate and the field limiting ring form an equivalent capacitance. C G_tre The equivalent capacitance C G_tre With capacitor C G_pad in parallel.

[0007] Furthermore, the effective facing area of ​​the second trench gate accounts for no more than 10% of the total area of ​​the device.

[0008] Furthermore, the second groove grid is a combination of a square, a circle, a rectangle, a rhombus, or a square with concave and convex edges, wherein the concave and convex edges are the edges close to the first groove grid.

[0009] Furthermore, the first grooved grid is partially surrounded by concave and convex edges.

[0010] Furthermore, by adjusting the width of the second trench gate, the effective facing area is adjusted, thereby obtaining a suitable equivalent capacitance. C G_tre .

[0011] Furthermore, the second trench gate is strip-shaped, with one or more strip-shaped trench gates evenly arranged within the gate metal layer.

[0012] Furthermore, the device is a gate-controlled device, which can be an insulated-gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor.

[0013] The innovation of this invention lies in the design of a trench layout structure beneath the gate metal layer. This trench, together with the underlying field limiting ring, effectively forms an additional capacitor, providing an extra discharge path for ESD current and thus reducing the current flowing through it. R g_int The added capacitor helps to distribute the instantaneous high voltage caused by ESD, further enhancing the device's ESD immunity.

[0014] The device design proposed in this invention has two advantages: First, by adjusting the width of the second trench gate, the equivalent capacitance value can be flexibly adjusted, thereby effectively improving the device's ESD resistance. Second, the effective facing area of ​​the second trench gate structure accounts for only 10% of the total device area, and the introduced equivalent capacitance has minimal impact on the switching speed. Furthermore, the new structure requires no additional mask and does not increase manufacturing costs, exhibiting good process compatibility.

[0015] In summary, compared with the prior art, the device proposed in this invention can significantly improve ESD resistance without additional adjustment of the gate resistance, while basically not affecting the switching speed, thus achieving simultaneous improvement in performance and reliability. Attached Figure Description

[0016] Figure 1 A top view of a prior art power device 100;

[0017] Figure 2 yes Figure 1 A schematic diagram of the structure along the Y direction at section AA';

[0018] Figure 3 This is a top view of device 200 according to Embodiment 1 of the present invention;

[0019] Figure 4 for Figure 3 A schematic diagram of the structure along the Y direction at section BB';

[0020] Figure 5 The circuit schematic for device 200;

[0021] Figure 6 This is a top view of device 300 according to Embodiment 2 of the present invention. Detailed Implementation

[0022] The following will provide specific examples illustrating embodiments of the device and its manufacturing method according to the present invention. It should be noted that the positional terms used in this document, such as "upper," "lower," and "parallel," correspond to their relative positions in the reference figures. In the following description, the insulating layer material of the device may be silicon oxide (SiO2). x It is composed of ) but other dielectric materials can also be used, such as silicon nitride (Si). x N y ), aluminum oxide (Al x O y ) and silicon oxynitride (Si x N y O zIn the following description, a semiconductor region of n-type polycrystalline silicon can also be formed by doping the original semiconductor region with one or more impurities, which can be, but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H), etc. + Furthermore, it should be noted that this invention is also applicable to other gate-controlled devices.

[0023] Example 1

[0024] Figure 3 The image shown is a top view of a device 200 according to a first embodiment of the present invention. The device 200 includes a gate metal layer 201 and a gate bus 202. Multiple sets of parallel-arranged first trench gates 203 are connected between the gate metal layer 201 and the gate bus 202. Each first trench gate 203 includes a first polysilicon layer 204 with n-type doping. A first oxide layer 206 is disposed below the first polysilicon layer 204 and between it and a field confinement ring 205. A metal contact hole 207 is disposed above the first trench gate 203, with one end connected to the gate metal layer 201 and the other end connected to the gate bus 202. Below the gate metal layer 201, a second trench gate 208 with a combined "U" and "wavy" layout is also provided. The second trench gate 208 includes a second polysilicon layer 209 with n-type doping. A second oxide layer 210 is disposed below the second polysilicon layer 209 and between it and the field confinement ring 205. Multiple metal contact holes 207 are disposed above the second polysilicon layer 209 and connected to the gate metal layer 201. Figure 4 This is a cross-sectional view of device 200 along the Y direction of section BB'. The gate metal layer 201 and gate bus 202 are isolated from the field limiting ring 205 through insulating layer 211.

[0025] The working principle of device 200 to enhance ESD capability is explained as follows: The circuit principle of the newly added trench gate device 200 with a combination of square and wavy layout is as follows: Figure 5 As shown. On the gate metal layer 201 side, the second trench gate 208 and the field limiting ring 205 form an equivalent capacitance. C G_tre The parallel first trench gate 203 and the field limiting ring 205 form a capacitor. C G_pad The gate bus 202 side is equivalent to the input capacitor. C iss The gate metal layer 201 and the gate bus 202 are connected through the first trench gate 203 to form an equivalent resistance. R g_int Due to the addition of capacitors C G_tre With the introduction of this technology, when ESD generates a discharge current, part of the current can be diverted through... C G_tre This creates new discharge paths, thereby reducing the flow throughR g_int The current, reducing its in R g_int The heat generated by the loss is effectively protected. R g_int To avoid damage. At the same time, C G_tre and C G_pad By forming a parallel structure, the total equivalent capacitance increases. According to the relationship V=Q / C, under the condition that the ESD discharge charge Q is constant, increasing the capacitance C will significantly reduce the voltage V that the device can withstand, thereby improving its ability to withstand high ESD voltages.

[0026] like Figure 3 As shown, the second groove grid 208 is a combination of a square and a wave shape. The wave-shaped edge is the edge of the square that is closest to the first groove grid 203. Multiple parallel first groove grids 203 are partially surrounded by the wave-shaped edge of the second groove grid, meaning that the first groove grid 203 is deep inside the position surrounded by the wave-shaped groove grid.

[0027] The second groove grid pattern can also be a circle, cross, rectangle, rhombus, square or other shapes or combinations thereof. Preferably, the lower edge of the pattern (the edge closest to the first groove grid 203) is preferably a wave or convex shape, and the first groove grid 203 can penetrate into the semi-enclosed area of ​​the wave or convex groove grid.

[0028] Based on the above working principle analysis, the device design proposed in this invention has two advantages: First, the second trench gate 208 and the lower field limiting ring can be equivalent to a parallel plate capacitor, according to the parallel plate capacitor formula... C G_tre = ε0 εᵣ A / d (ε0 is the vacuum permittivity, εᵣ is the relative permittivity of the dielectric material, A represents the effective area of ​​the electrode, and d is the thickness of the dielectric layer). The trench width directly affects the effective area A. When the trench width of the second trench gate increases, the effective area A between the trench and the field limiting ring increases accordingly, resulting in an increase in capacitance; conversely, when the trench width of the second trench gate decreases, A decreases accordingly, and the capacitance decreases accordingly. By adjusting the width of the second trench gate 208, the equivalent capacitance can be flexibly adjusted. C G_tre The capacitance value effectively improves the device's ESD resistance. Secondly, the effective facing area of ​​this second trench gate structure accounts for only ten percent of the total device area, introducing an equivalent capacitance of... C G_tre It has minimal impact on switching speed.

[0029] The power devices of the present invention can be gate-controlled devices such as insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0030] Example 2

[0031] Figure 6 The diagram shown is a top view of the device 300 according to the second embodiment of the present invention. Unlike the device 200 described in Embodiment 1, in the device 300 of this embodiment, the second trench gate does not adopt the combined groove layout of the square and wave-shaped trenches, but adopts a second rectangular trench gate 308 with multiple parallel rectangular trenches. The rectangular distribution also helps to enhance the device's ESD resistance.

Claims

1. An ESD-enhanced power semiconductor device based on a trench structure, wherein a gate metal layer and a gate bus are disposed on the top of the device, a field limiting ring is disposed inside the device, and multiple sets of parallel-arranged first trench gates are connected between the gate metal layer and the gate bus. Each first trench gate includes a first polysilicon layer, a first oxide layer is disposed below the first polysilicon layer and between it and the field limiting ring, and a metal contact hole is disposed above the first polysilicon layer, one end of which is connected to the gate metal layer and the other end of which is connected to the gate bus. Both the gate metal layer and the gate bus are isolated from the field limiting ring by an insulating layer, and the gate bus side is equivalent to an input capacitor. C iss The first trench gate and the field limiting ring form a capacitor. C G_pad The gate metal layer and the gate bus are connected through the first trench gate to form an equivalent resistance. R g_int Its characteristics are, A second trench gate is further provided below the gate metal layer. The second trench gate includes a second polysilicon layer filled in the trench. A second oxide layer is provided between the second polysilicon layer and the field limiting ring. One or more metal contact holes are provided above the second polysilicon layer to connect with the gate metal layer. The second trench gate and the field limiting ring form an equivalent capacitance. C G_tre The equivalent capacitance C G_tre With capacitor C G_pad in parallel.

2. The trench-structure-based ESD-enhanced power semiconductor device as described in claim 1, characterized in that, The effective facing area of ​​the second trench gate accounts for no more than 10% of the total area of ​​the device.

3. The trench-structure-based ESD-enhanced power semiconductor device as described in claim 1, characterized in that, The second groove grid has a shape that is a combination of a square, a circle, a rectangle, a rhombus, or a square with concave and convex edges, wherein the concave and convex edges are the edges that are close to the first groove grid.

4. The trench-structure-based ESD-enhanced power semiconductor device as described in claim 3, characterized in that, The first grooved grid is partially surrounded by concave and convex edges.

5. The ESD-enhanced power semiconductor device based on a trench structure as described in claim 1, characterized in that, The effective facing area is adjusted by regulating the width of the second trench gate, thereby obtaining a suitable equivalent capacitance. C G_tre .

6. The ESD-enhanced power semiconductor device based on a trench structure as described in claim 1, characterized in that, The second trench gate is strip-shaped, with one or more strip-shaped trench gates evenly arranged within the gate metal layer.

7. The trench-structure-based ESD-enhanced power semiconductor device according to any one of claims 1-6, characterized in that, The device in question is a gate-controlled device.

8. The trench-structure-based ESD-enhanced power semiconductor device as described in claim 7, characterized in that, The gate control device is an insulated gate bipolar transistor or a metal-oxide-semiconductor field-effect transistor.

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