Controlling resource set # 0 puncturing control

Abstract

Embodiments of the present disclosure relate to an apparatus, a method, and a computer readable storage medium for controlling a control resource set (CORESET) # 0 puncturing. The method includes determining, at a first device, whether a particular type of CORESET is punctured based on detecting a synchronization signal block received from a second device at least on a particular frequency location, where a punctured resource portion in the particular type of CORESET cannot carry downlink control information; according to the fact that the CORESET of the specific type is punched, a CORESET punching pattern is obtained; and determining a punctured resource portion in the CORESET based at least on the CORESET puncturing pattern. Further, the method includes indicating from the second device to the first device that the particular type of CORESET is punctured by transmitting a synchronization signal block on the particular frequency location.

Description

Cross-reference to related applications

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 518380, filed August 9, 2023. The entire contents of the above application are incorporated herein by reference. Technical Field

[0002] Various exemplary embodiments of this disclosure generally relate to the telecommunications field, and particularly to methods, apparatus, devices, and computer-readable storage media for controlling the punching of control resource set (CORESET) #0, especially in a scenario with a 5MHz channel bandwidth and 20 resource blocks (RBs). Background Technology

[0003] In Release 18, a work item has been approved regarding dedicated spectrum of less than 5 MHz in Frequency Range 1 (FR1) for New Radio (NR). This work item addresses dedicated networks designed to provide mission-critical communications for vertical industries such as smart energy and infrastructure, public safety, and rail communications, and to provide 3 MHz CBW for any scenario. These networks will benefit not only from the high spectral efficiency of 5G NR but also from its other features such as ultra-reliability and low latency. Summary of the Invention

[0004] In a first aspect of this disclosure, a first apparatus is provided. The first apparatus includes at least one processor and at least one memory storing instructions, which, when executed by the at least one processor, cause the first apparatus to at least: determine whether a specific type of CORESET has been punctured based on detecting a synchronization signal block received from a second apparatus at least at a specific frequency location, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information; acquire a CORESET punctured pattern based on determining that the specific type of CORESET has been punctured; and determine the punctured resource portion of the CORESET based at least on the CORESET punctured pattern.

[0005] In a second aspect of this disclosure, a second apparatus is provided. The second apparatus includes at least one processor and at least one memory storing instructions, which, when executed by the at least one processor, cause the second apparatus to at least: indicate to a first apparatus that a specific type of CORESET is punctured by transmitting a synchronization signal block at a specific frequency location; and transmit downlink control information to the first apparatus based at least on the resource portion of the unpunctured CORESET.

[0006] In a third aspect of this disclosure, a method is provided. The method includes: determining whether a specific type of CORESET has been punctured based on detecting a synchronization signal block received from a second device at least at a specific frequency location, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information; obtaining a CORESET puncturing pattern based on determining that the specific type of CORESET has been punctured; and determining the punctured resource portion of the CORESET based at least on the CORESET puncturing pattern.

[0007] In a fourth aspect of this disclosure, a method is provided. The method includes: instructing a first device that a specific type of CORESET is punctured by transmitting a synchronization signal block at a specific frequency location; and transmitting downlink control information to the first device based at least on the resource portion of an unpunctured CORESET.

[0008] In a fifth aspect of this disclosure, a first apparatus is provided. The first apparatus includes: means for determining whether a specific type of CORESET has been punctured based on a synchronization signal block received from a second means at least at a specific frequency position, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information; means for acquiring a CORESET puncturing pattern based on determining that the specific type of CORESET has been punctured; and means for determining the punctured resource portion of the CORESET at least based on the CORESET puncturing pattern.

[0009] In a sixth aspect of this disclosure, a second apparatus is provided. The second apparatus includes: means for instructing a first apparatus that a particular type of CORESET has been punctured by transmitting a synchronization signal block at a specific frequency location; and means for transmitting downlink control information to the first apparatus based at least on the resource portion of an unpunctured CORESET.

[0010] In a seventh aspect of this disclosure, a computer-readable medium is provided. The computer-readable medium includes instructions stored thereon for causing a device to perform at least the method according to the third aspect.

[0011] In an eighth aspect of this disclosure, a computer-readable medium is provided. The computer-readable medium includes instructions stored thereon for causing a device to perform at least the method according to the fourth aspect.

[0012] It should be understood that the summary portion is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0013] Some exemplary embodiments will now be described with reference to the accompanying drawings, in which:

[0014] Figure 1 The illustration shows an example communication environment in which example embodiments of the present disclosure may be implemented;

[0015] Figure 2 The illustration shows an example of CORESET#0 frequency domain resource allocation according to some exemplary embodiments of the present disclosure;

[0016] Figure 3 A signaling diagram 300 for communication is illustrated according to some example embodiments of the present disclosure;

[0017] Figures 4A-4F The illustration shows an example of CORESET punching according to some exemplary embodiments of the present disclosure;

[0018] Figure 5 The illustration shows a flowchart of an example method 500 for CORESET#0 punch control according to some example embodiments of the present disclosure;

[0019] Figure 6 The illustration shows a flowchart of an example method 600 for CORESET#0 punch control according to some example embodiments of the present disclosure;

[0020] Figure 7 A simplified block diagram of a device 700 suitable for implementing an example embodiment of the present disclosure is illustrated;

[0021] Figure 8 A block diagram of an example computer-readable medium according to some example embodiments of the present disclosure is illustrated.

[0022] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar elements. Detailed Implementation

[0023] The principles of this disclosure will now be described with reference to some exemplary embodiments. It should be understood that these embodiments are described for illustrative purposes only and to assist those skilled in the art in understanding and implementing this disclosure, and do not constitute any limitation on the scope of this disclosure. The embodiments described herein can be implemented in various other ways besides those described below.

[0024] In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains.

[0025] In this disclosure, references to "an embodiment," "embodiment," and "example embodiment," etc., indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment must include that particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, those skilled in the art will understand that, whether explicitly described or not, combining it with other embodiments to affect such a feature, structure, or characteristic is within the knowledge of those skilled in the art.

[0026] It should be understood that although the terms "first," "second," etc., preceding nouns in this document may be used to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another and do not restrict the order of the nouns. For example, without departing from the scope of the exemplary embodiments, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the listed terms.

[0027] As used herein, “at least one of the following: ” and “at least one of the following: ” and similar wording (where the list of two or more elements is connected by “and” or “or”) means at least any one of these elements, or at least any two or more of these elements, or at least all of these elements.

[0028] As used herein, unless explicitly stated otherwise, “responding to A” does not mean that the step is performed immediately after “A” occurs, but may include one or more intermediate steps.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. The singular forms “a,” “an,” and “the” used herein also include the plural forms unless the context clearly indicates otherwise. Further understanding, the terms “comprises,” “comprising,” “has,” “having,” “includes,” and / or “including” as used herein specify the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or combinations thereof.

[0030] As used in this application, the term "circuit system" may refer to one or more or all of the following: (a) Pure hardware circuit implementation (such as implementation using only analog and / or digital circuit systems), and (b) A combination of hardware circuitry and software, such as (if applicable): (i) A combination of (multiple) analog and / or digital hardware circuits and software / firmware, and (ii) Any part of a hardware processor (including multiple digital signal processors), software, and memory (multiple processors) having software, which work together to enable a device (such as a mobile phone or server) to perform various functions, and (c) (Multiple) hardware circuits and / or (multiple) processors, such as (multiple) microprocessors or a portion thereof, which require software (e.g., firmware) to operate, but may be absent when operation is not required.

[0031] The definition of "circuit system" applies to all uses of the term in this application, including in any claim. As another example, as used in this application, the term "circuit system" also covers only hardware circuitry or a processor (or processors) or a portion of hardware circuitry or a processor and its accompanying software and / or firmware. For example, if applicable to a particular claim element, the term "circuit system" also covers baseband integrated circuits or processor integrated circuits for mobile devices, or similar integrated circuits in servers, cellular network devices, or other computing or network devices.

[0032] As used herein, the term "communication network" refers to a network that conforms to any suitable communication standard, such as New Radio (NR), Long Term Evolution (LTE), LTE-A Advanced (LTE-A), Wideband Code Division Multiplexing (WCDMA), High-Speed ​​Packet Access (HSPA), Narrowband Internet of Things (NB-IoT), etc. Furthermore, communication between terminal devices and network devices in a communication network can be performed according to any suitable generation of communication protocol, including but not limited to first-generation (1G), second-generation (2G), 2.5G, 2.75G, third-generation (3G), fourth-generation (4G), 4.5G, fifth-generation (5G), 5G Advanced, sixth-generation (6G) communication protocols and / or any other currently known or to be developed in the future. Embodiments of this disclosure can be applied to various communication systems. Given the rapid development of communications, there will naturally be communication technologies and systems that can be used to embody future types of communication technologies and systems. This should not be construed as limiting the scope of this disclosure to the systems described above.

[0033] As used herein, the term "network device" refers to a node in a communication network through which terminal devices access the network and receive services. A network device can refer to a base station (BS) or access point (AP), such as a Node B (NodeB or NB), an evolved Node B (eNodeB or eNB), an NR NB (also known as a gNB), a Remote Radio Unit (RRU), a Radio Header (RH), a Remote Radio Header (RRH), a relay, an Integrated Access and Backhaul (IAB) node, a low-power node (such as a femtosecond or picosecond), a non-terrestrial network (NTN) or non-terrestrial network device (such as satellite network equipment, low Earth orbit (LEO) satellites, and geostationary orbit (GEO) satellites), an aircraft network device, etc., depending on the terminology and technology applied. In some example embodiments, the Radio Access Network (RAN) split architecture includes a centralized unit (CU) and a distributed unit (DU) at the IAB donor node. An IAB node includes a mobile terminal (IAB-MT) portion that behaves as a UE to its parent node, and the DU portion of the IAB node behaves as a base station to the next-hop IAB node.

[0034] The term "terminal device" refers to any terminal device capable of wireless communication. As an example and not a limitation, a terminal device may also be referred to as a communication device, user equipment (UE), subscriber station (SS), portable subscriber station, mobile station (MS), or access terminal (AT). Terminal devices can include, but are not limited to, mobile phones, cellular phones, smartphones, Voice over IP (VoIP) phones, wireless local loop phones, tablets, wearable terminal devices, personal digital assistants (PDAs), portable computers, desktop computers, image capture terminal devices (such as digital cameras), gaming terminal devices, music storage and playback devices, in-vehicle wireless terminal devices, wireless endpoints, mobile stations, laptop embedded devices (LEE), laptop mounted devices (LME), USB dongles, smart devices, wireless customer premises equipment (CPE), Internet of Things (IoT) devices, watches or other wearable devices, head-mounted displays (HMDs), vehicles, drones, medical devices and applications (e.g., remote surgery), industrial devices and applications (e.g., robots and / or other wireless devices operating in industrial and / or automated processing chain environments), consumer electronics devices, devices operating on commercial and / or industrial wireless networks, etc. The terminal device may also correspond to the mobile terminal (MT) portion of an IAB node (e.g., a relay node). In the following description, the terms "terminal device," "communication device," "terminal," "user equipment," and "UE" are used interchangeably.

[0035] As used herein, the terms “resource,” “transmission resource,” “resource block,” “physical resource block” (PRB), “uplink resource,” or “downlink resource” can refer to any resource used to perform communication, such as communication between a terminal device and a network device, including time-domain resources, frequency-domain resources, spatial-domain resources, code-domain resources, or any other combination of time-domain resources, frequency-domain resources, spatial-domain resources, and / or code-domain resources used to implement communication. In the following, unless explicitly stated otherwise, resources in the frequency and time domains will be used as examples of transmission resources to describe some exemplary embodiments of this disclosure. It should be noted that the exemplary embodiments of this disclosure are equally applicable to other resources in other domains. In some embodiments, frequency-domain resources may cover one or more resource blocks, each resource block having 12 subcarriers, while time-domain resources may cover one or more OFDM symbols.

[0036] Figure 1 An example communication network 100 in which embodiments of the present disclosure may be implemented is shown. Figure 1 As shown, the communication network 100 may include a first device 110. In the following text, the first device 110 may also be referred to as a UE or terminal device.

[0037] The communication network 100 may also include a second device 120. Hereinafter, the second device 120 may also be referred to as a gNB or network device. The first device 110 may communicate with the second device 120.

[0038] It should be understood that Figure 1 The number of network devices and terminal devices shown is for illustrative purposes and does not imply any limitation. Communication network 100 may include any suitable number of network devices and terminal devices.

[0039] In some example embodiments, the link from the second device 120 to the first device 110 may be referred to as a downlink (DL), and the link from the first device 110 to the second device 120 may be referred to as an uplink (UL). In the DL, the second device 120 is a transmitting (TX) device (or transmitter), and the first device 110 is a receiving (RX) device (or receiver). In the UL, the first device 110 is a TX device (or transmitter), and the second device 120 is an RX device (or receiver).

[0040] Communication in communication environment 100 can be implemented according to any suitable communication protocol(s), including but not limited to cellular communication protocols such as first-generation (1G), second-generation (2G), third-generation (3G), fourth-generation (4G), fifth-generation (5G), and sixth-generation (6G), wireless local area network communication protocols such as IEEE 802.11, and / or any other protocols currently known or to be developed in the future. Furthermore, communication can utilize any suitable wireless communication technology, including but not limited to: Code Division Multiple Access (CDMA), Frequency Division Multiple Access (FDMA), Time Division Multiple Access (TDMA), Frequency Division Duplex (FDD), Time Division Duplex (TDD), Multiple-Input Multiple-Output (MIMO), Orthogonal Frequency Division Multiplexing (OFDM), Discrete Fourier Transform Spread Spectrum OFDM (DFT-s-OFDM), and / or any other technologies currently known or to be developed in the future.

[0041] As mentioned above, research on NR support for dedicated spectrum of less than 5 MHz in frequency range 1 (FR1) has been discussed.

[0042] For example, the dedicated FDD spectrum in FR1 should include the following objectives: • Identify and specify the necessary changes to the NR physical layer with minimal scalar impact to operate in spectrum allocations from approximately 3MHz to below 5MHz: ○ The subcarrier spacing (SCS) is limited to 15 kHz, and a normal cyclic prefix is ​​used. ○ For Synchronization Signal / Physical Broadcast Channel Block (SSB): • Reuses PSS / SSS specifications, no punching required. • Based on the current design of PBCH. ○ Identify and specify the minimum necessary changes to the Physical Downlink Control Channel (PDCCH), Channel State Information Reference Signal (CSI-RS) / Tracking Reference Signal (TRS), Physical Uplink Control Channel (PUCCH), and Physical Random Access Channel (PRACH) to provide functional support based on existing designs without optimization.

[0043] In addition, the following are some relevant aspects: • For the 3MHz channel bandwidth in band n100 (i.e., the band for the Future Railway Mobile Communication System (FRMCS)) (the maximum channel utilization already agreed upon in RAN1 / RAN4 is 15 Physical Resource Blocks (PRBs)): ○ The Physical Broadcast Channel (PBCH) has a transmission bandwidth of 12 PRBs. ○ The transmission bandwidth of CORESET#0 is determined by RAN1. • RAN1 needs to consider whether the above also applies to other frequency bands with a channel bandwidth of 3MHz, or whether the PBCH transmission bandwidth of such frequency bands is 15 PRBs. • For a 5MHz channel bandwidth: ○ The PBCH transmission bandwidth is 20 PRBs. ○ The transmission bandwidth of CORESET#0 is determined by RAN1. • Other details (including synchronization raster details) will be worked out in the working group.

[0044] Based on the current protocol, for a 3MHz channel bandwidth, 12 & 15 PRB CORESET operation is supported. Specifically, • For all frequency bands with a 3MHz channel bandwidth (the maximum channel utilization already agreed upon in RAN1 / RAN4 is 15 PRB): ○ The PBCH transmission bandwidth is 12 PRBs. ○ For CORESET#0 transmission bandwidth, 12 PRBs and 15 PRBs are supported. • In the case of 12 PRBs, using conventional interleaving (R=2) CORESET CCE to REG mapping, N RB CORESET =12, meaning 12PRB is marked as no punch. • In the case of 15 PRBs N RB CORESET =24 CORESET #0 holes were punched. • Supports both interleaved (traditional interleaver size R=2) and non-interleaved mappings. • Some entries in the table relate to interleaved mappings, while others are non-interleaved mappings. • A single table with up to 16 entries to accommodate two scenarios: • The maximum number of CORESET#0 symbols is 3. The minimum number of CORESET#0 symbols is 2. • Use SSB and CORESET#0 to reuse pattern 1 (pattern 1 indicates that SSB and CORESET#0 are time-multiplexed). • REG bundle size = 6.

[0045] As mentioned above, one of the objectives of the work item could be to "identify and specify the minimum changes required to functionally support the PDCCH based on the existing design without optimization." During system information acquisition, the UE monitors the PDCCH on resources of at least 4.32 MHz (i.e., 24 RBs), which exceeds the target transmission bandwidth of 20, 15, and 12 RBs, respectively. Therefore, the PDCCH changes required to support NR in narrow spectrum allocations should focus on these PDCCH resources. Another aspect of the PDCCH that needs attention is its frequency domain location relative to the SSB.

[0046] PDCCH can be mapped to a physical resource set called CORESET, which is composed of control channel elements (CCE). A control channel element consists of 6 resource element groups (REG), where a resource element group equals a resource block during one OFDM symbol.

[0047] After initial access, CORESET can be flexibly configured for the UE. However, the configuration options available for CORESET#0 are limited, such as the PDCCH used to schedule the transmission of System Information Block 1 (SIB1), which is called Type 0-PDCCH.

[0048] First, we can consider the CORESET#0 frequency domain position relative to the SSB. Figure 2 An example of CORESET#0 frequency domain resource allocation is shown.

[0049] like Figure 2 As shown, after the UE detects the primary synchronization signal (PSS) 201 and the secondary synchronization signal (SSS) 203 and demodulates PBCH 202, the UE acquires the main information block (MIB) on PBCH 202. Next, the UE needs to acquire the remaining minimum system information carried by SIB1. The UE reads the CORESET#0 configuration index from the MIB on PBCH 202, which indicates the time and frequency resource allocation parameters of CORESET 205. One of these parameters defines the frequency domain offset 204 between the first RB where the SSB is located and the first RB of CORESET#0.

[0050] Similar to PBCH transmissions, puncturing may be required to confine CORESET#0 to the available spectrum. This could result in a constrained CORESET#0 containing some partial CCEs. For example, there will be at least one partial CCE when the available spectrum is not an integer multiple of the CCE size and is less than 24 RBs (20 RBs in our specific case).

[0051] However, if PBCH puncturing is not considered in the CORESET#0 frequency domain allocation, two CCEs will be unnecessarily punctured. Since CCEs are used as the basic resource unit in channel estimation, partial CCEs will degrade the quality of channel estimation.

[0052] While the use of partial CCEs is unavoidable, minimizing the number of partial CCEs is meaningful. Therefore, the frequency domain allocation of CORESET#0 may need to be reconsidered to keep CORESET=0 aligned with the unpunctured RBs of the SSB at the CCE level, or, in the case of 20 RBs, to keep the unpunctured portion of CORESET#0 aligned with the RBs of the SSB at the CCE level.

[0053] In this case, it may be necessary to further discuss how to configure a narrower bandwidth for CORESET#0 (specifically Type0_PDCCH) with a 20RB CORESET#0 design when operating with a 5MHz channel bandwidth (specifically band n100) to minimize additional complexity while providing sufficient flexibility.

[0054] According to some example embodiments of this disclosure, a solution for controlling CORESET#0 puncturing is provided. In this solution, a first device 110 detects a synchronization signal block received from a second device at a specific frequency position and determines, based on the detection, whether a specific type of CORESET has been punctured. If the first device 110 determines that a specific type of CORESET has been punctured, the first device 110 determines the punctured resource portion of the CORESET based at least on the CORESET puncturing pattern.

[0055] Based on this solution, users can flexibly choose between the punched and unpunched CORESET#0 and the corresponding punching options.

[0056] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0057] Now for reference Figure 3 This illustrates signaling diagram 300 for communication according to some example embodiments of the present disclosure. For example... Figure 3 As shown, signaling diagram 300 relates to first device 110 and second device 120. For discussion purposes, reference is made to... Figure 1 To describe signaling diagram 300. It should be understood that, Figure 3 The process shown can also be Figure 1 The other terminal devices and network devices shown are adopted.

[0058] The first device 110 can perform initial access to a channel associated with a specific bandwidth (e.g., n100, 5MHz channel bandwidth (CBW)). Figure 1 As shown, the second device 120 can transmit (305) SSB. It should be understood that the SSB used herein may include a 'synchronization signal' (SS) block and a PBCH block, and the SS block may be replaced by a synchronization signal, a primary synchronization signal, or a secondary synchronization signal.

[0059] Based on the SSB detection, the first device 110 determines the CORESET#0 parameters, such as the CORESET multiplexing pattern, number of RBs, number of symbols, and offset (RB) of entries 0-5 in Table 1. Table 1: Resource block set and slot symbol set for CORESET when the SCS of {SS / PBCH block, PDCCH} is {15, 15} kHz, for a Type 0-PDCCH search space set with a minimum channel bandwidth of 5 MHz or 10 MHz, or a minimum channel bandwidth of 3 MHz and a channel bandwidth greater than 3 MHz.

[0060] If the first device 110 detects an SSB at a specific frequency location, the first device 110 can determine (315) that a specific type of CORESET has been punched. The term “specific type of CORESET” as used herein may be referred to as CORESET#0, which, for example, is the PDCCH used to schedule the transmission of SIB1, referred to as Type0-PDCCH.

[0061] The term "specific frequency location" used in this document can be referred to as the location of the synchronization grid point in the frequency domain, for example, 921.45 MHz. This synchronization grid point can be set based on the n100 low-frequency band edge of 919.4 MHz. This means that the lowest channel grid point with a channel BW within the band is located at 919.4 MHz + 2.5 MHz = 921.9 MHz. A 5 MHz CBW represents 25 RBs, so the lowest RB edge is 12.5 RBs below the channel grid point. The synchronization grid point (common grid) whose lowest RB is aligned with the lowest RB of the channel is located 12.5 - 10 = 2.5 RBs (= 450 kHz) below the channel grid point, i.e., 921.9 - 0.45 = 921.45 MHz. In short, 921.45 is the synchronization grid point that allows the SSB to be placed as low as possible within the 5 MHz CBW band, but is limited to a transmission bandwidth of 20 PRBs. It is also a synchronization grid point, not part of the regular / traditional synchronization grid, which would otherwise be used on the n100 with a 5MHz CBW having a regular 25 PRB transmission bandwidth.

[0062] For example, if the first device 110 determines that the primary synchronization signal or the secondary synchronization signal is detected at a specific frequency position, the first device 110 can determine that a specific type of CORESET has been punched.

[0063] For 5MHz CBW, CORESET#0 operates without punching the remaining sync grid points.

[0064] In addition, the first device can obtain additional confirmation of CORESET punching through another means (e.g., from MIB).

[0065] The first device 110 can acquire / determine various punching patterns. For example, the punching pattern can be configured by the second device 120 and sent to the first device 110, or it can be pre-configured / predefined in a specification.

[0066] After determining that a specific type of CORESET is being punched, the first device 110 can determine the corresponding punching pattern for the CORESET punching. The following is about references. Figures 4A-4F Detailed description of various drilling patterns.

[0067] As an option (hereinafter referred to as Option 1), the RBs below the lowest RB (i.e., RB#0) of the PBCH are perforated. In some embodiments, the lowest subcarrier of the PBCH (i.e., RB#0) can be considered as puncturing_threshold_low .

[0068] Figure 4A An example of CORESET punching when using MIB notification in Table 1 according to some exemplary embodiments of this disclosure is shown. As shown, for indices 0 or 3, 1 or 4, and 2 or 5 of Table 1, the RBs below RB#0 of PBCH will be punched.

[0069] In another option (hereinafter referred to as Option 2), RBs above the highest RB (i.e., RB#19) of the PBCH are perforated. In some embodiments, the highest subcarrier of the PBCH (i.e., RB#19) can be considered as puncturing_threshold_high .

[0070] In another option (hereinafter referred to as Option 3), RBs below the lowest RB (i.e., RB#0) and above the highest RB (i.e., RB#19) of the PBCH are punched to align the transmission bandwidth with the PBCH.

[0071] Figure 4B Examples of CORESET punching when using MIB notification table 1 according to some example embodiments of this disclosure are shown. As shown based on option 3, for indices 0 or 3, 1 or 4, and 2 or 5 of table 1, RBs below RB#0 and above RB#19 of PBCH will be punched.

[0072] Furthermore, based on options 1-3 above, only indexes containing up to 20 RBs after the punching operation can be considered valid indexes. The first device 110 may also not expect to receive invalid indexes. Alternatively or optionally, punching can be applied at the granularity of the entire CCE (not just RBs). In other words, if at least one RB of a CCE needs to be punched, the entire CCE (i.e., all RB portions of the CCE) will be punched (hereinafter referred to as option 4). In this option, unpunished resources include multiples of 6 REGs.

[0073] Figure 4C Examples of CORESET punching when using Table 1 of the MIB notification according to some exemplary embodiments of this disclosure are shown. Based on option 1, i.e., RBs below the lowest RB of PBCH (i.e., RB#0) are punched. Figure 4C The punch pattern according to option 4 (index 1 or 4) is shown, where only a complete CCE is sent. Figure 4C In the diagram, the Option 1 pattern is shown as a reference (index 1 or 4) to the Option 4 pattern derived from the Option 1 pattern (one for index 4 with 3 OFDM symbols (OS), and the other for index 1 with 2 OS, shown below the Option 1 pattern).

[0074] Figure 4D Examples of CORESET punching when using Table 1 with MIB notification according to some exemplary embodiments of this disclosure are shown. Based on option 3, i.e., RBs below the lowest RB (i.e., RB#0) and above the highest RB (i.e., RB#19) of PBCH are punched, Figure 4D The punch pattern according to option 4 (for indices 0-5 of Table 1) is shown, in which only a complete CCE is sent.

[0075] In some variants, there is a threshold for the share of the RBs of the CCE, based on which it is determined whether the entire CCE will be punched. For example, if the threshold is 0.5 (50%), then the entire CCE will be punched if at least half of the RBs of the CCE need to be punched.

[0076] Figure 4E Examples of CORESET punching when using Table 1 with MIB notification according to some exemplary embodiments of this disclosure are shown. Based on option 3, i.e., RBs below the lowest RB (i.e., RB#0) and above the highest RB (i.e., RB#19) of PBCH are punched, Figure 4E The punch pattern according to option 4 is shown, i.e., in the case where more than 50% of the PRB in the CCE is sent, only the PRB is sent.

[0077] In addition, based on options 1-4 above, IE puncturing_threshold_low and / or puncturing_ threshold_high It can be determined with a predefined offset relative to the lowest RB (i.e., RB#0) and the highest RB (i.e., RB#19) of PBCH (hereinafter referred to as Option 5).

[0078] In some embodiments, the predefined offset is [offset_low, offset_high] = [x, y] subcarriers (x and y are positive or negative integers). In some other embodiments, the predefined offset is [offset_low, offset_high] = [x, y] RBs (x and y are positive or negative integers).

[0079] In another option, it is assumed that CORESET#0 and PBCH are in subcarrier offset relative to each other. This option (hereinafter referred to as Option 6) is a variation of Options 1-3, where puncturing is applied at the subcarrier granularity. In this case, a portion of the RB (for CORESET#0) is considered a punctured RB. A portion of the RB can be considered as a symbol or part of a subcarrier within an RB (hereinafter referred to as Option 6). A portion of the RB can also be referred to as a punctured RB, where the portion of the RB has punctured subcarriers, and the number of punctured subcarriers of the portion of the RB is greater than 0 and less than 12.

[0080] Furthermore, based on options 1-5 above, puncturing may require additional implicit or explicit signaling or acknowledgment (otherwise the UE interprets the error in the MIB content and continues searching for other PSS / SSS, or alternatively, the UE does not apply puncturing without additional acknowledgment). Additional acknowledgment can be, for example, a specific value in k_SSB (an indication gap between subcarrier 0 of the SS / PBCH block and the common resource block), such as 0, or a k_SSB value predefined corresponding to the indicated CORESET table index (hereinafter referred to as Option 7). k_SSB can indicate the frequency domain offset between the SSB and the common resource block in terms of the number of subcarriers. k_SSB is indicated by the MIB.

[0081] In another option, when the detected synchronization grid point is associated with n100, 5MHz CBW, certain indices (e.g., index 0 and / or index 3) are considered the only valid option (hereinafter referred to as option 8).

[0082] Figure 4FExamples of CORESET puncturing using Table 1 with MIB notification according to some exemplary embodiments of this disclosure are shown. As shown based on option 8, in the case of a predefined synchronization grid point of 921.45MHz, in some embodiments, RB 20-23 are punctured for index 0 or index 3 (Alternative 1). In some other embodiments, represented by Alternative 2, RB 18-23 are punctured for index 0 (using 2OS CORESET) and RB 20-23 are punctured for index 3 (using 3OS CORESET), thus limiting the puncturing to the granularity of the entire CCE.

[0083] As described above, using the CORESET punch pattern, the first device 110 can determine the resource portion of the punch in the CORESET. Now return to Figure 3 The first device 110 can decode (320) PBCH and monitor PDCCH based on the punched resource portion in the determined CORESET.

[0084] In another scenario, if a PSS / SSS is found from another synchronization grid point defined for a 5MHz CBW on a specific channel, and it is determined that the CORESET has not been punctured, the first device 110 can decode the PBCH and obtain information from the PBCH / MIB to determine the index of row (0-5) in addressing table 1. Then, assuming that reception does not involve puncturing, the first device 110 can perform Type0_PDCCH detection.

[0085] In this way, the original table of CORESET#0 (i.e., Table 1) can be reused. Furthermore, it allows for flexible selection between punched and unpunched CORESET#0 and their corresponding punching options.

[0086] Figure 5 A flowchart illustrating an example method 500 for CORESET#0 punch control according to some example embodiments of the present disclosure is shown. Figure 1 As shown, method 500 can be implemented at the first device 110 (which can be implemented as a terminal device). For the purposes of discussion, reference will be made to... Figure 1 Description method 500.

[0087] At block 510, the first device 110 determines whether a specific type of CORESET has been punctured based on detecting a synchronization signal block received from the second device at least at a specific frequency location, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information.

[0088] If the first device 110 determines that a specific type of CORESET is punched, then at frame 520, the first device 110 acquires the CORESET punch pattern.

[0089] At frame 530, the first device 110 determines the resource portion of the CORESET with holes based at least on the CORESET hole pattern.

[0090] In some example embodiments, a particular type of CORESET is CORESET#0.

[0091] In some example embodiments, method 500 further includes determining that a particular type of CORESET has been punched based on at least one of the following: a primary or secondary synchronization signal is detected at a specific frequency position, or an additional confirmation of the CORESET punching is obtained from the primary information block.

[0092] In some example embodiments, a specific frequency location is associated with the location of a synchronization grid point in the frequency domain.

[0093] In some example embodiments, obtaining the CORESET punch pattern includes: determining at least one punch threshold associated with the location of the broadcast channel resource block set; and determining that the resource portion is punched based on the determination that the resource portion in the CORESET does not meet at least one punch threshold.

[0094] In some example embodiments, a resource portion in a CORESET not meeting at least one punch threshold includes at least one of the following: one or more resource blocks of the CORESET are below the lowest broadcast channel resource block; or one or more resource blocks of the CORESET are above the highest broadcast channel resource block.

[0095] In some example embodiments, at least one punching threshold is determined based on an offset relative to at least one of the following: the lowest broadcast channel resource block or the highest broadcast channel resource block.

[0096] In some example embodiments, method 500 further includes determining that the punctured resource portion in CORESET comprises at least one partial resource block, based on the determination of the puncturing threshold being determined based on an offset relative to the location of the broadcast channel resource block set, and the offset having a subcarrier granularity.

[0097] In some example embodiments, method 500 further includes: determining that a second portion of another resource block in the CCE is punched, based on the determination that the CORESET punching pattern requires the CORESET to be punched at the granularity of the control channel element CCE and that at least one resource block in the CCE is punched.

[0098] In some example implementations, whether additional resource blocks in the CCE are punched is determined based on a threshold.

[0099] In some example embodiments, method 500 further includes: determining that only at least one specific index associated with a specific type of CORESET is valid based on determining that the synchronization grid point is associated with at least one of a specific bandwidth or a specific frequency band; and determining that one or more specific resource blocks associated with at least one specific index are punched, wherein the at least one specific index is indicated by a master information block.

[0100] In some example embodiments, method 500 further includes determining that at least one particular index associated with a particular type of CORESET is valid when the associated CORESET contains up to 20RBs after the punching operation.

[0101] In some example embodiments, the first device includes a terminal device, and the second device includes a network device.

[0102] Figure 6 A flowchart illustrating an example method 600 for CORESET punch control according to some example embodiments of the present disclosure is shown. Figure 1 As shown, method 600 can be implemented at the second device 120 (which can be implemented as a network device). For the purposes of discussion, reference will be made to... Figure 1 Description method 600.

[0103] At frame 610, a synchronization signal block is sent at a specific frequency position to indicate to the first device that a specific type of CORESET has been punched; and

[0104] At frame 620, downlink control information is sent to the first device based at least on the resource portion of the un-punched CORESET.

[0105] In some example embodiments, a particular type of CORESET is CORESET#0.

[0106] In some example embodiments, the device is configured to indicate that a particular type of CORESET is punched with additional information in the main information block.

[0107] In some example embodiments, a specific frequency location is associated with the location of a synchronization grid point in the frequency domain.

[0108] In some example embodiments, the first device includes a terminal device, and the second device includes a network device.

[0109] In some example embodiments, a first device capable of performing any of method 500 (e.g., Figure 1The first device 110 may include components for performing the corresponding operations of method 500. These components may be implemented in any suitable form. For example, the components may be implemented in a circuit system or a software module. The first device may be implemented as or included therein.

[0110] In some example embodiments, the first device includes components for determining whether a particular type of CORESET has been punctured based on a synchronization signal block received from the second device at least at a specific frequency location, wherein the punctured resource portion of the particular type of CORESET cannot carry downlink control information; components for acquiring a CORESET puncturing pattern based on determining that the particular type of CORESET has been punctured; and components for determining the punctured resource portion of the CORESET based at least on the CORESET puncturing pattern.

[0111] In some example embodiments, a particular type of CORESET is CORESET#0.

[0112] In some example embodiments, the first device further includes: a component for determining that a particular type of CORESET has been punched based on at least one of the following: a primary or secondary synchronization signal is detected at a specific frequency position, or an additional confirmation of the CORESET punching is obtained from the primary information block.

[0113] In some example embodiments, a specific frequency location is associated with the location of a synchronization grid point in the frequency domain.

[0114] In some example embodiments, the components for obtaining the CORESET punch pattern include: components for determining at least one punch threshold associated with the location of the broadcast channel resource block set; and components for determining that a resource portion is punched based on the determination that a resource portion in the CORESET does not meet at least one punch threshold.

[0115] In some example embodiments, a resource portion in a CORESET not meeting at least one punch threshold includes at least one of the following: one or more resource blocks of the CORESET are below the lowest broadcast channel resource block; or one or more resource blocks of the CORESET are above the highest broadcast channel resource block.

[0116] In some example embodiments, at least one punching threshold is determined based on an offset relative to at least one of the following: the lowest broadcast channel resource block or the highest broadcast channel resource block.

[0117] In some example embodiments, the first apparatus further includes a component for determining that the punctured resource portion in the CORESET comprises at least one partial resource block, based on an offset of the location relative to the broadcast channel resource block set, wherein the puncturing threshold is determined based on the offset having a subcarrier granularity.

[0118] In some example embodiments, the first apparatus further includes a component for determining that a second portion of a further resource block in the CCE is punched based on the determination that the CORESET punching pattern requires the CORESET to punch at the granularity of the control channel element CCE, and that at least one resource block in the CCE is punched.

[0119] In some example implementations, whether additional resource blocks in the CCE are punched is determined based on a threshold.

[0120] In some example embodiments, the first apparatus further includes: components for determining that only at least one specific index associated with a specific type of CORESET is valid based on determining that the synchronization grid point is associated with at least one of a specific bandwidth or a specific frequency band; and components for determining that one or more specific resource blocks associated with at least one specific index are punched, wherein the at least one specific index is indicated by a master information block.

[0121] In some example embodiments, the first device further includes a component for determining that at least one particular index associated with a particular type of CORESET is valid when the associated CORESET contains up to 20RBs after the punching operation.

[0122] In some example embodiments, the first device includes a terminal device, and the second device includes a network device.

[0123] In some example embodiments, the first device further includes components for performing additional operations in some example implementations of method 500 or the first device 110. In some example embodiments, the components include at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the execution of the first device.

[0124] In some example embodiments, a second means capable of performing any of method 600 (e.g., Figure 1 The second device 120 may include a component for performing the corresponding operation of method 600. This component may be implemented in any suitable form. For example, the component may be implemented in a circuit system or a software module. The second device may be implemented as... Figure 1 The second device 120 may be included therein.

[0125] In some example embodiments, the second device includes components for instructing the first device that a particular type of CORESET has been punctured by transmitting a synchronization signal block at a specific frequency location; and components for transmitting downlink control information to the first device based at least on the resource portion of the unpunctured CORESET.

[0126] In some example embodiments, a particular type of CORESET is CORESET#0.

[0127] In some example embodiments, the second device also includes a component for indicating that a particular type of CORESET is punched by additional information in the main information block.

[0128] In some example embodiments, a specific frequency location is associated with the location of a synchronization grid point in the frequency domain.

[0129] In some example embodiments, the first device includes a terminal device, and the second device includes a network device.

[0130] In some example embodiments, the second means further includes components for performing additional operations in some example implementations of method 600 or second means 120. In some example embodiments, the components include at least one processor; and at least one memory storing instructions that, when executed by the at least one processor, cause the execution of the second means.

[0131] Figure 7 This is a simplified block diagram of a device 700 suitable for implementing exemplary embodiments of the present disclosure. The device 700 can be provided to implement a communication device, for example, such as... Figure 1 The first device 110 or the second device 120 shown. As shown, the device 700 includes one or more processors 710, one or more memories 720 coupled to the processors 710, and one or more communication modules 740 coupled to the processors 710.

[0132] Communication module 740 is used for bidirectional communication. Communication module 740 has one or more communication interfaces to facilitate communication with one or more other modules or devices. The communication interface can represent any interface required for communication with other network elements. In some example embodiments, communication module 740 may include at least one antenna.

[0133] Processor 710 can be of any type suitable for a local technology network, and by way of non-limiting example, can include one or more of the following: general-purpose computer, special-purpose computer, microprocessor, digital signal processor (DSP), and processor based on a multi-core processor architecture. Device 700 can have multiple processors, such as application-specific integrated circuit chips that are time-dependent on a clock synchronized with the main processor.

[0134] Memory 720 may include one or more non-volatile memories and one or more volatile memories. Examples of non-volatile memories include, but are not limited to, read-only memory (ROM) 724, electrically programmable read-only memory (EPROM), flash memory, hard disk, compact disc (CD), digital video disc (DVD), optical disc, laser disc, and other magnetic and / or optical storage devices. Examples of volatile memories include, but are not limited to, random access memory (RAM) 722 and other volatile memories that do not persist during power outages.

[0135] Computer program 730 includes computer-executable instructions that are executed by an associated processor 710. The instructions of program 730 may include instructions for performing operations / actions of some example embodiments of this disclosure. Program 730 may be stored in memory (e.g., ROM 724). Processor 710 can perform any suitable actions and processes by loading program 730 into RAM 722.

[0136] Example embodiments of this disclosure can be implemented via program 730, enabling device 700 to execute reference... Figures 2 to 6 Any process discussed in this disclosure. Exemplary embodiments of this disclosure may also be implemented in hardware or a combination of software and hardware.

[0137] In some example embodiments, program 730 may be tangibly contained in a computer-readable medium, which may be included in device 700 (such as memory 720) or other storage devices accessible to device 700. Device 700 may load program 730 from the computer-readable medium into RAM 722 for execution. In some example embodiments, the computer-readable medium may include any type of non-transitory storage medium, such as ROM, EPROM, flash memory, hard disk, CD, DVD, etc. The term "non-transitory" as used herein refers to a limitation on the medium itself (i.e., tangible, not tactile), rather than a limitation on the persistence of data storage (e.g., RAM and ROM).

[0138] Figure 8 An example of a computer-readable medium 800, which may be in the form of a CD, DVD, or other optical storage disc, is shown. A program 730 is stored on the computer-readable medium 800.

[0139] Generally, the various embodiments of this disclosure can be implemented using hardware or dedicated circuitry, software, logic, or any combination thereof. Some aspects can be implemented using hardware, while others can be implemented using firmware or software that can be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of this disclosure are illustrated and described as block diagrams, flowcharts, or using some other graphical representation, it should be understood that, as non-limiting examples, the blocks, apparatuses, systems, techniques, or methods described herein can be implemented using hardware, software, firmware, dedicated circuitry or logic, general-purpose hardware or controllers or other computing devices, or some combination thereof.

[0140] Some exemplary embodiments of this disclosure also provide at least one computer program product tangibly stored on a computer-readable medium, such as a non-transitory computer-readable medium. The computer program product includes computer-executable instructions, such as instructions included in a program module, that execute in a device on a target physical or virtual processor to perform any of the methods described above. Typically, a program module includes routines, programs, libraries, objects, classes, components, data structures, etc., that perform a particular task or implement a particular abstract data type. In various embodiments, the functionality of a program module can be combined or split among program modules as needed. The machine-executable instructions of a program module can execute within a local or distributed device. In a distributed device, a program module can reside on both local and remote storage media.

[0141] Program code used to perform the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a stand-alone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0142] In the context of this disclosure, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, etc.

[0143] Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable media can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any suitable combination of the foregoing. More specific examples of computer-readable storage media will include electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable optical disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0144] Furthermore, although operations are described in a specific order, this should not be construed as requiring the operations to be performed in the specific order shown or sequentially, or to perform all of the shown operations to obtain the desired result. In some cases, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the foregoing discussion, these should not be construed as limiting the scope of this disclosure, but rather as descriptions of features that may be specific to particular embodiments. Unless explicitly stated otherwise, certain features described in the context of a single embodiment may also be implemented in combination in a single embodiment. Conversely, unless explicitly stated otherwise, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0145] Although this disclosure has been described in language specific to structural features and / or methodological actions, it should be understood that the disclosure as defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features or actions described above are disclosed as exemplary forms of implementing the claims.

Claims

1. A first device, comprising: At least one processor; as well as At least one memory storing instructions, which, when executed by the at least one processor, cause the first device to at least: Based on the detection of a synchronization signal block received from a second device at least at a specific frequency location, it is determined whether a specific type of control resource set CORESET is punctured, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information; Based on the determination that the specific type of CORESET is punched, obtain the CORESET punch pattern; as well as The portion of the resource in the CORESET that is punched is determined at least based on the CORESET punch pattern.

2. The first apparatus according to claim 1, wherein the particular type of CORESET is CORESET#0.

3. The first device according to claim 1 or 2, wherein the device is configured to: Based on determining at least one of the following: The primary synchronization signal or the secondary synchronization signal is detected at the specific frequency position, or Additional confirmation for CORESET punching is obtained from the main information block. It is determined that the CORESET of the specific type is punched.

4. The first device according to any one of claims 1 to 3, wherein the specific frequency position is associated with the position of a synchronization grid point in the frequency domain.

5. The first apparatus according to any one of claims 1 to 4, wherein obtaining the CORESET punch pattern comprises: Determine at least one punching threshold associated with the location of the broadcast channel resource block set; The resource portion is determined to be punched based on the determination that the resource portion in the CORESET does not meet the at least one punching threshold.

6. The first apparatus of claim 5, wherein the resource portion in the CORESET that does not satisfy the at least one punch threshold includes at least one of the following: One or more resource blocks of the CORESET are located below the lowest broadcast channel resource block; or One or more resource blocks of the CORESET are located above the highest broadcast channel resource block.

7. The first apparatus of claim 5, wherein the at least one punching threshold is determined based on an offset relative to at least one of: Minimum broadcast channel resource block, or Highest broadcast channel resource block.

8. The first apparatus according to claim 7, wherein the apparatus is configured to: Based on the determination that the puncturing threshold is determined based on an offset relative to the location of the broadcast channel resource block set, and that the offset has a subcarrier granularity, it is determined that the punctured resource portion in the CORESET includes at least one partial resource block.

9. The first device according to any one of claims 1 to 4, wherein the device is configured to: Based on the determination of the CORESET punching pattern, the CORESET is punched at the granularity of the control channel element (CCE), and at least one resource block in the CCE is punched, it is determined that a second portion of another resource block in the CCE is punched.

10. The first apparatus of claim 8, wherein whether the additional resource block in the CCE is punched is determined based on a threshold.

11. The first device according to claim 4, wherein the device is configured to: Based on the determination that the synchronization grid point is associated with at least one of the following: Specific bandwidth, or For a specific frequency band, it is determined that only at least one specific index associated with the CORESET of the specific type is valid; and It is determined that one or more specific resource blocks associated with the at least one specific index are punched, wherein the at least one specific index is indicated by the master information block.

12. The first device according to claim 11, wherein the first device is configured to: When the associated CORESET contains up to 20RB after a punching operation, the at least one specific index associated with the CORESET of the specific type is determined to be valid.

13. The first apparatus according to claims 1 to 11, wherein the first apparatus includes a terminal device and the second apparatus includes a network device.

14. A second device, comprising: At least one processor; as well as At least one memory storing instructions, which, when executed by the at least one processor, cause the second means to at least: By sending a synchronization signal block at a specific frequency position, a specific type of control resource set CORESET is indicated to the first device to be punched; as well as Downlink control information is sent to the first device based at least on the un-punched resource portion of the CORESET.

15. The second apparatus of claim 14, wherein the particular type of CORESET is CORESET#0.

16. The second device according to claim 14 or 15, wherein the device is configured to: The CORESET of the specified type is punched by additional information in the main information block.

17. The second device according to any one of claims 14 to 16, wherein the specific frequency position is associated with the position of a synchronization grid point in the frequency domain.

18. The second apparatus according to any one of claims 14 to 17, wherein the first apparatus includes a terminal device and the second apparatus includes a network device.

19. A method comprising: At the first device, based on the detection of a synchronization signal block received from the second device at least at a specific frequency location, it is determined whether a specific type of control resource set CORESET is punctured, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information; Based on the determination that the specific type of CORESET is punched, obtain the CORESET punch pattern; as well as The portion of the resource in the CORESET that is punched is determined at least based on the CORESET punch pattern.

20. A method comprising: By sending a synchronization signal block at a specific frequency position, the second device indicates to the first device that a specific type of control resource set CORESET has been punched; as well as Downlink control information is sent to the first device based at least on the un-punched resource portion of the CORESET.

21. A first device, comprising: A component for determining whether a specific type of control resource set CORESET is punctured based on the detection of a synchronization signal block received from a second device at least at a specific frequency location, wherein the punctured resource portion of the specific type of CORESET cannot carry downlink control information; A component for obtaining a CORESET punch pattern based on determining that the CORESET of a specific type has been punched; as well as A component for determining the portion of the resource that has been punched in the CORESET, at least based on the CORESET punch pattern.

22. A second device, comprising: A component used to indicate to a first device that a specific type of control resource set CORESET has been punched by sending a synchronization signal block at a specific frequency position; as well as A component for sending downlink control information to the first device based at least on the un-punched resource portion of the CORESET.

23. A computer-readable medium comprising instructions stored thereon, the instructions being configured to cause a device to perform at least the method of claim 19 or the method of claim 20.

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