Miniaturized GPU (Graphics Processing Unit) encoding and decoding device and data encoding acceleration processing method

Abstract

According to the miniaturized GPU coding and decoding device and the data coding acceleration processing method, an advanced algorithm and a reliable hardware architecture are adopted, a GPU, a special coding module, a high-capacity video memory and a PCIe Switch form coding equipment, and a video processing acceleration platform which is highly integrated, clear in division of labor and huge in throughput is formed. The processing core performance, the data interaction capability and the physical form are broken through, and the functions of efficiently encoding and decoding and displaying and outputting various image video information are achieved. According to the invention, multi-format video coding and decoding, real-time processing and high-quality display output are supported, and the coding efficiency is obviously improved; according to the invention, a high-bandwidth reconfigurable interconnected PCIe Switch architecture is adopted, the I / O transmission bottleneck is eliminated, and a dynamic bandwidth allocation function is realized; on the premise that high performance is guaranteed, a high-performance miniaturized structural design is adopted, the application requirement of a compact space scene is met, and the application potential is expanded.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of computer coding and decoding, and particularly relates to a miniaturized GPU coding and decoding device and a data coding and acceleration processing method. BACKGROUND

[0002] In the era of digital information explosion, video data is generated, spread and applied on an unprecedented scale. From the popularization of high-definition video to ultra-high-definition and even 8K and 16K video, from online video platforms to real-time video communication, from film and television production to intelligent security monitoring, video has penetrated into every corner of people's life, work and social operation. With the deep expansion of video applications, extremely strict requirements are put forward for video coding and decoding technology. The video resolution gradually rises from standard definition to 4K, 8K and even higher, the frame rate is continuously improved, and the dynamic range is also significantly expanded, which makes the video data volume grow exponentially. At the same time, in order to pursue higher compression ratio and better picture quality, the complexity of video compression algorithm is also increasing, such as evolving from H.264 / AVC to H.265 / HEVC, the coding and decoding complexity is greatly improved.

[0003] Traditionally, video coding and decoding mainly rely on central processing units (CPUs) to complete. However, when facing modern video processing requirements, CPUs expose many limitations that are difficult to overcome. On the one hand, the number of CPU cores is relatively small, and the architecture design focuses on complex logic control and serial task processing. When processing a large number of same type of data-intensive operations in video coding and decoding, the efficiency is extremely low, and it is difficult to meet the high speed requirement of real-time coding and decoding. On the other hand, when traditional video processing software runs on a CPU, it often occupies a large amount of system resources, causing the overall performance of the system to decline, and the running of other application programs to be seriously affected. Especially when processing high-definition and ultra-high-definition video, the performance bottleneck of the CPU will cause coding and decoding delay, and real-time performance cannot be guaranteed, which is unacceptable in video communication, live broadcast and other scenarios with extremely high real-time requirements.

[0004] The emergence and development of the graphics processing unit (GPU) bring new hope to solve the video coding problem. The GPU is originally mainly used for graphics rendering, and its hardware architecture has a unique design, with a large number of computing cores suitable for large-scale parallel computing. Many operations in video coding, such as motion estimation, motion compensation, intra-frame prediction, etc., have the characteristics of large numerical operation, small logical operation, and independent operation of each pixel, which is highly consistent with the parallel computing advantage of the GPU. By offloading these operation tasks to the GPU for execution, the powerful parallel processing capability of the GPU can be fully utilized, and the coding speed and efficiency can be significantly improved. At the same time, with the development of general computing platforms such as CUDA (Compute Unified Device Architecture) launched by NVIDIA and industry general standards such as OpenCL (Open Computing Language) initiated by the Khronos Group, the GPU has gradually broken the limitation of being used only for graphics rendering, and its application in the field of general computing is becoming more and more widespread, providing strong support for its deep application in the field of video coding. Using the GPU to accelerate video coding has become a hot topic of common concern in the academic and industrial circles, and provides a practical solution to the bottleneck problem of the development of high-definition video services.

[0005] In the prior art, the GPU is usually not integrated with a dedicated encoding module, resulting in that the encoding task needs to rely on the general computing unit of the GPU or the CPU to complete. Since the general computing unit is not optimized for the encoding algorithm, it directly causes low encoding efficiency, and it is difficult to support real-time processing of complex formats such as H.265 and AV1, especially in the 4K / 8K high-resolution scenario, which is prone to problems such as insufficient frame rate and picture lag.

[0006] In the prior art, the communication between the GPU, the CPU and the encoding-related components relies on the traditional PCIe interface and does not use a multi-channel dynamic scheduling mechanism. This results in limited data transmission bandwidth (usually less than 20 GB / s), and the inability to allocate resources according to task priority, which is prone to data congestion when multiple devices are transmitting in parallel, further increasing the system response delay.

[0007] Since the encoding function is scattered in multiple independent modules, and the communication interface is large in size, the existing device is difficult to realize miniaturized design, resulting in large occupied space and being unable to adapt to application scenarios sensitive to volume such as edge computing and mobile devices. SUMMARY

[0008] The technical problem to be solved by the present application is to provide a miniaturized GPU coding device and a data coding acceleration processing method for efficient coding and display output of various image and video information.

[0009] The technical scheme adopted by the present application to solve the above technical problems is: a miniaturized GPU encoding and decoding device, comprising a plurality of video memory modules, an encoding module, a GPU, a PCIe switch and a velcro connector; the plurality of video memory modules are respectively connected to the encoding module and the GPU; the PCIe switch is respectively connected to the encoding module and the GPU; the velcro connector is connected to the PCIe switch, and forms an external interface module through an elastic contact structure, which is used to connect a CPU; further comprising a heat dissipation assembly; the device adopts a stacked design, and integrates the video memory module, the encoding module, the GPU and the heat dissipation assembly in layers.

[0010] According to the above scheme, the video memory module is used to provide temporary data storage for parallel computing and encoding of the GPU, and to provide bandwidth and load isolation.

[0011] According to the above scheme, the encoding module adopts a special hardware acceleration architecture, which is used to efficiently compress and format convert image data, reduce file size under the premise of ensuring image quality, and facilitate storage and network transmission.

[0012] According to the above scheme, the GPU is used for image acquisition, processing, compression and encoding, format conversion and data transmission, including basic operations such as image enhancement, geometric transformation and feature extraction, and advanced processing such as filter effects, image stitching and 3D rendering, to improve image quality or achieve specific visual effects.

[0013] According to the above scheme, the PCIe switch is used to establish a high-speed data transmission channel between the encoding module, the GPU and the CPU, support multiple devices working in parallel and point-to-point transmission; it is also used for direct data transmission between the GPU and the encoding module; the PCIe switch also intelligently adjusts the data transmission rate according to the priority of the encoding task through the dynamic bandwidth allocation function.

[0014] According to the above scheme, the velcro connector is used to transmit the signals of the encoding module and the GPU externally through the differential signal transmission mode; the signal types transmitted by the velcro connector also include power signals, PCIe signals, display signals and video data.

[0015] According to the above scheme, it further comprises a power module for inputting external voltage through the velcro connector, and supplying power to each module of the device through voltage reduction and voltage division.

[0016] According to the above scheme, the GPU further comprises an intelligent temperature control module for monitoring the temperature of each module in real time and adjusting the heat dissipation power to stabilize the operating temperature of the whole machine.

[0017] A data encoding acceleration processing method, comprising the following specific steps: S1: CPU connects a miniaturized GPU codec device through a button connector, and the CPU reads a compressed source video file into system memory; S2: The CPU sends the source video data to the GPU through a PCIe switch; S3: The GPU pre-processes the decoded original video frame; S4: The pre-processed data is transmitted from the GPU-connected video memory module to the video memory module connected to the encoding module through the PCIe switch; S5: The encoding module receives data and performs efficient hardware encoding; S6: The encoded code stream is transmitted back to the system memory of the CPU through the PCIe switch; S7: The CPU encapsulates the code stream back to the external device format.

[0018] A computer memory has a computer program stored therein, which can be executed by a computer processor, and the computer program executes a data encoding acceleration processing method.

[0019] The beneficial effects of the present application are: 1. The miniaturized GPU codec device and data encoding acceleration processing method of the present application adopts advanced algorithms and reliable hardware architecture, forms a highly integrated, clear division of labor, and high-throughput video processing acceleration platform by using GPU, special encoding module, large-capacity video memory and PCIe switch, and reduces the bottlenecks of each link of calculation, encoding, storage and transmission to the minimum, breaks through from three key dimensions of processing core performance, data interaction ability and physical form, and realizes the functions of efficient encoding and decoding and display output of multiple image and video information.

[0020] 2. The present application supports multi-format video encoding and decoding, real-time processing and high-quality display output by integrating a special hardware encoding and decoding module, significantly improves the encoding efficiency, and breakthroughly supports real-time processing of complex format video or data stream, solves the problems of low encoding efficiency and not supporting real-time processing of complex format in the prior art, and is an irreplaceable solution for traditional methods when processing large-scale, low-latency, high-specification video applications.

[0021] 3. The present application adopts a high-bandwidth reconfigurable interconnection PCIe switch architecture, improves the system data transmission bandwidth to more than 32 GB / s, completely eliminates the I / O transmission bottleneck, realizes the dynamic bandwidth allocation function, can flexibly allocate resources according to task requirements, and ensures the stability and efficiency of data transmission when multiple tasks are concurrent.

[0022] 4. The overall structure is deeply optimized, and high-performance miniaturized structure design is adopted under the premise of ensuring high performance; application requirements of compact space scenarios are met, and application potential in embedded, mobile or high-density deployment environments is expanded.

[0023] Of course, implementing any product of the present application does not necessarily require achieving all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0025] Figure 1 is a principle block diagram of an embodiment of the present application.

[0026] Figure 2 is a data encoding acceleration processing flowchart of an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the present application more clear, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.

[0028] Embodiment 1 Referring to Figure 1 A miniaturized GPU codec device includes a GPU, an encoding module, a power module, a Velcro connector, a video memory and a PCIe switch.

[0029] The GPU (Graphics Processing Module) is the core component of the GPU codec device, which is used for image acquisition, processing, compression encoding, format conversion and data transmission. In terms of graphics processing, the module uses GPU to realize basic operations such as image enhancement (such as contrast adjustment, noise reduction), geometric transformation (scaling, rotation), feature extraction (edge detection, texture analysis) and other basic operations, and can also perform advanced processing such as filter effects, image stitching, 3D rendering, etc., to improve image quality or achieve specific visual effects. Thousands of cores of GPU can process tasks before and after encoding in parallel, prepare data for the dedicated encoding module, and greatly improve the overall pipeline efficiency.

[0030] The encoding module uses a dedicated encoding chip for efficient compression and format conversion of image data. Through mainstream encoding standards such as JPEG, PNG, H.264, etc., the file size is reduced under the premise of ensuring image quality, which is convenient for storage and network transmission.

[0031] The dedicated video memory provides temporary data storage for the GPU's massive parallel computing and encoding, easily handling the real-time processing and data exchange demands of 8K / 60fps or even higher-resolution video. It offers extreme bandwidth, delivering data to the GPU core at speeds far exceeding system memory speeds through specialized GDDR or HBM technologies. It isolates the load, preventing the GPU's high-speed data stream from competing with the encoding module for system memory bandwidth, thereby improving overall system efficiency and stability.

[0032] PCIe switches provide high-speed data transfer channels, connecting all components for data transmission. They allow multiple devices to work in parallel and enable point-to-point transmission, allowing direct data exchange between the GPU and encoding modules without the need for CPU-memory intermediaries, significantly reducing latency and bandwidth consumption.

[0033] The button connector enables the external signal path of the entire miniaturized encoding module, and is used for external signal transmission of the GPU, encoding module and power module. The signal types include: power signals, PCIe signals, display signals and video data to be processed.

[0034] The power module supplies power to the entire miniaturized encoding module. The encoding device has a total power input of 12V, and external power is supplied to the power module via a button connector. The power module supplies power to various modules such as the GPU, encoding module, video memory, and PCIe switch through voltage reduction and division.

[0035] This embodiment specifically addresses the technical deficiency of existing GPUs lacking independent encoding capabilities. The newly added encoding module adopts a dedicated hardware acceleration architecture, supports mainstream encoding formats such as H.265 and AV1, and can meet the real-time processing requirements of 4K / 8K video.

[0036] To achieve efficient data interaction, the encoding module establishes a high-speed communication link with the GPU and CPU through a PCIe switch. This architecture supports parallel data transmission across multiple devices, with a single-channel bandwidth of up to 32GB / s, more than 50% higher than traditional PCIe interfaces, effectively eliminating data transmission bottlenecks. Simultaneously, the PCIe switch's dynamic bandwidth allocation function intelligently adjusts the data transmission rate based on the priority of encoding tasks, further improving system response speed.

[0037] Multiple technical breakthroughs have been achieved in the design of the GPU codec device, and the application of the button connector has become a core highlight. This connector, with its unique elastic contact structure, not only ensures stable signal transmission, but also significantly reduces the size of the interface module, laying the foundation for the miniaturization of the device. On this basis, the device adopts a stacked design, integrating GPU, encoding module, memory module, and cooling components in layers, not only saving more than 60% of the installation space, but also achieving rational allocation of resources through optimized internal layout - the operation core can dynamically adjust the computing power output according to the load, and the storage module adopts a distributed architecture to reduce data access delay.

[0038] To solve the heat dissipation problem caused by high-density integration, the GPU has an intelligent temperature control module built-in, which monitors the temperature of each unit in real time and adjusts the cooling power, keeping the operating temperature of the whole machine below 55°C. At the same time, the low-loss characteristics of the button connector combined with differential signal transmission technology effectively reduce signal attenuation and crosstalk in high-speed data transmission, with signal integrity improved by more than 30%. The synergy of these designs ensures the long-term stable operation of the device in all aspects from space utilization, resource scheduling, heat dissipation efficiency to signal quality, significantly improving its reliability in complex working conditions.

[0039] The embodiment has the following advantages: 1) High performance and efficiency: Through the combination of "dedicated hardware codec" and "high-speed PCIe interconnection", the codec throughput and processing efficiency far exceed traditional solutions, perfectly supporting real-time processing of complex formats.

[0040] 2) High bandwidth and low latency: The PCIe Switch architecture provides a data path of more than 32GB / s and supports dynamic allocation, completely eliminating transmission bottlenecks and ensuring high smoothness and low latency throughout the processing and display chain.

[0041] 3) Strong flexibility and scalability: The dynamic bandwidth allocation mechanism enables the device to intelligently adapt to changing workloads, making system configuration more flexible and leaving room for future functional upgrades.

[0042] 4) Compactness and high integration: While pursuing extreme performance, the device has been successfully miniaturized, making it applicable to fields with stringent space requirements and solving the industry's difficult problem of balancing high performance and miniaturization.

[0043] 5) High reliability and practicality: Optimized miniaturized structure and selected connectors (such as button connectors) not only reduce failure points, but also improve stability in harsh environments such as vibration and movement, making it highly practical.

[0044] Embodiment 2 Reference Figure 2Taking video transcoding as an example, the embodiment based on the above-mentioned device embodiment implements a data encoding acceleration processing method, including the following steps: S1: The CPU connects the miniaturized GPU coding and decoding device through the molex connector, and reads the compressed source video file to the system memory.

[0045] S2: The CPU sends the source video data to the GPU through the PCIe Switch.

[0046] S3: The GPU pre-processes the decoded original video frame.

[0047] S4: The pre-processed data is transmitted from the GPU's video memory to the video memory of the encoding module through the PCIe Switch.

[0048] S5: The encoding module receives the data and performs efficient hardware encoding.

[0049] S6: The encoded bitstream is directly transmitted back to the system memory of the CPU through the PCIe Switch.

[0050] S7: The CPU encapsulates the bitstream into a container format such as MP4.

[0051] It should be understood that the size of the serial number of each step in the above-mentioned embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiment of the present application.

[0052] It should be noted that according to the needs of implementation, each step / component described in the present application can be split into more steps / components, or two or more steps / components or part of the operation of the steps / components can be combined into a new step / component to achieve the purpose of the present application.

[0053] The embodiment also includes a processor, a communication interface, a memory and a communication bus; wherein the processor, the communication interface and the memory complete the communication among each other through the communication bus; the memory stores a computer program, and when the program is executed by the processor, the processor executes the steps of a data encoding acceleration processing method.

[0054] The embodiment also provides a computer readable storage medium having executable instructions stored thereon, which, when executed by a processor, causes the processor to implement a data encoding acceleration processing method.

[0055] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.

[0056] Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0057] This application is described with reference to a block diagram of an apparatus (system) according to Embodiment 1 and a flowchart of a method and computer program product according to Embodiment 2. It should be understood that each step or block in the flowchart or block diagram, as well as combinations of steps or blocks in the flowchart or block diagram, can be implemented by computer program instructions.

[0058] These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which are executable by the processor of the computer or other programmable data processing device, produce instructions for implementing the process. Figure 1 One or more processes or boxes Figure 1 A data encoding acceleration processing system that specifies functions within one or more boxes.

[0059] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes or boxes Figure 1 The steps of a data encoding acceleration processing method are specified in one or more boxes.

[0061] The above embodiments are only used to illustrate the design concept and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, all equivalent changes or modifications made based on the principles and design ideas disclosed in the present invention are within the protection scope of the present invention.

Claims

1. A miniaturized GPU codec apparatus, characterized by: The GPU coding and decoding device comprises a plurality of video memory modules, a plurality of coding modules, a plurality of GPUs, a plurality of PCIe switches and a plurality of velcro connectors. The plurality of video memory modules are connected to the plurality of coding modules and the plurality of GPUs respectively. The plurality of PCIe switches are connected to the plurality of coding modules and the plurality of GPUs respectively. The plurality of velcro connectors are connected to the plurality of PCIe switches, and form an external interface module through elastic contact structures, and are used for connecting a CPU. The GPU coding and decoding device further comprises a plurality of heat dissipation components; the device adopts a stacked design, and integrates the plurality of video memory modules, the plurality of coding modules, the plurality of GPUs and the plurality of heat dissipation components in layers.

2. The GPU coding and decoding device according to claim 1, wherein: The video memory module is used for providing temporary data storage for parallel computing and coding of the GPU, and providing bandwidth and load isolation.

3. The GPU coding and decoding device according to claim 1, wherein: The coding module adopts a special hardware acceleration architecture, is used for efficiently compressing and converting the format of image data, reduces the file size under the premise of ensuring the image quality, and is convenient for storage and network transmission.

4. The GPU coding and decoding device according to claim 1, wherein: The GPU is used for image acquisition, processing, compression coding, format conversion and data transmission, and comprises basic operations such as image enhancement, geometric transformation and feature extraction, and high-level processing such as filter special effects, image stitching and 3D rendering, so as to improve the image quality or realize specific visual effects.

5. The GPU coding and decoding device according to claim 1, wherein: The PCIe switch is used for establishing a high-speed data transmission channel between the coding module, the GPU and the CPU, supports multi-device parallel work and point-to-point transmission, and is also used for directly transmitting data between the GPU and the coding module; The PCIe switch is also used for intelligently adjusting the data transmission rate according to the coding task priority through a dynamic bandwidth allocation function.

6. The GPU coding and decoding device according to claim 1, wherein: The velcro connector is used for transmitting the signals of the coding module and the GPU to the outside through the differential signal transmission mode; the signal types transmitted by the velcro connector further comprise power signals, PCIe signals, display signals and video data.

7. The GPU coding and decoding device according to claim 1, further comprising a power module, which is used for inputting external voltage through the velcro connector, and supplying power to each module of the device through voltage reduction and voltage division.

8. The GPU coding and decoding device according to claim 1, wherein: The GPU further comprises an intelligent temperature control module, which is used for monitoring the temperature of each module in real time and adjusting the heat dissipation power, so as to stabilize the operating temperature of the whole machine. The specific steps comprise:

9. A method for accelerating data encoding processing, the method comprising: S1: The CPU connects the GPU coding and decoding device through the velcro connector, and the CPU reads the compressed source video file to the system memory; S2: The CPU sends the source video data to the GPU through the PCIe switch; S3: The GPU pre-processes the decoded original video frame; ​ S4: The pre-processed data is transmitted from the GPU-connected memory module to the encoding module-connected memory module through the PCIe Switch; S5: The encoding module receives the data and performs efficient hardware encoding; S6: The encoded code stream is directly transmitted back to the system memory of the CPU through the PCIe Switch; S7: The CPU encapsulates the code stream back into the external device format.

10. A computer memory, characterized by: The computer program stored therein can be executed by a computer processor, and the computer program performs a data encoding acceleration processing method as claimed in any one of claims 1 to 8.

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