Dual-line cascade-based line-scan synchronization display method and system

Abstract

The application provides a line scanning synchronous display method and system based on double-line cascade. The method comprises the following steps: sending a clock signal and an address configuration instruction to a first constant current chip by a controller; after the i-th constant current chip receives the clock signal and the address configuration instruction, generating an IC address for the i-th constant current chip according to the address configuration information, and forwarding the clock signal and the address configuration instruction to the (i+1)-th constant current chip after processing; generating a frame synchronization signal according to the IC address in the instruction synchronization period; and correcting the frame synchronization signal by the i-th constant current chip by using the IC address to generate a line synchronization signal. The application realizes cascade through two lines of DCLK and SDI, makes the cascade chip automatically configure the address by sending a specific instruction by the controller, and delays the synchronization of the chip according to the configured address. Meanwhile, the cascade chip adopts a serial reverse output strategy to realize stable sampling of cascade data, and solves the attenuation problem of the DCLK parallel mode.

Description

A method and system for synchronous line scanning based on dual-line cascading Technical Field

[0001] This invention relates to the field of LED display technology, and more particularly to a method and system for synchronous row scanning display based on dual-line cascading. Background Technology

[0002] Direct LED display technology uses a constant current driver chip (IC) to provide a stable current to each LED pixel. Its high brightness, high contrast, and long lifespan make it widely used in indoor and outdoor high-definition display applications. Constant current driver solutions supporting horizontal scanning synchronization mainly include four-wire and three-wire drivers.

[0003] Figure 1 shows a traditional four-wire drive scheme: DCLK, LE, and RCLK in parallel, and SDI in serial. DCLK is the synchronous clock, which attenuates significantly when multiple wires are cascaded; LE is used to send control commands, achieving frame synchronization without delay; RCLK is used to display line feeds, achieving line synchronization without delay; and SDI is the data line, used for register configuration and grayscale data writing in the constant current chip.

[0004] Figure 2 shows a traditional three-wire drive scheme. Compared to a four-wire drive scheme, the three-wire mode reduces the number of RCLK signal lines. While frame synchronization is achieved through LE, line synchronization is directly achieved by generating RCLK internally within the constant current chip. When a frame change signal arrives, the line synchronization signal needs to be restored to its initial state to avoid accumulated errors during line synchronization.

[0005] In scenarios such as holographic displays, both of the above driving schemes suffer from problems such as tight wiring resources, clock attenuation affecting cascading, and high cost due to the presence of parallel signals and a large number of data signals. To completely solve these problems, a better driving strategy is needed. Summary of the Invention

[0006] To address the challenges of complex wiring, limited cascading capacity, and high cost associated with traditional LED constant current driving in applications such as holographic displays, this invention provides a display method and system based on dual-line cascading line scanning synchronization.

[0007] According to one aspect of the present invention, a method for synchronous horizontal scanning display based on dual-line cascading is provided for a display system including a controller and M cascaded constant current chips. The clock input and data input terminals of the first constant current chip are connected to the clock output and data output terminals of the controller, and the clock input and data input terminals of the kth constant current chip are connected to the clock output and data output terminals of the (k-1)th constant current chip, wherein M is a positive integer ≥ 1, 2 ≤ k ≤ M, and the method includes the following steps:

[0008] The controller sends a clock signal and an address configuration instruction to the first constant current chip. The address configuration instruction includes instruction identification information, address configuration information, and instruction synchronization period.

[0009] After receiving the clock signal and address configuration instruction, the i-th constant current chip generates an IC address for the i-th constant current chip according to the address configuration information, and processes the clock signal and address configuration instruction before forwarding it to the (i+1)-th constant current chip, where 1≤i≤M;

[0010] The i-th constant current chip generates a frame synchronization signal based on the IC address during the instruction synchronization period;

[0011] The i-th constant current chip uses the IC address to correct the frame synchronization signal and generate a line synchronization signal.

[0012] In the horizontal scanning synchronous display method based on dual-line cascading of the present invention, the i-th constant current chip generates an IC address for the i-th constant current chip according to the number of pulse signals or the number of levels of the address configuration information.

[0013] In the horizontal scanning synchronous display method based on dual-line cascading of the present invention, the i-th constant current chip inverts the clock signal and forwards it to the (i+1)-th constant current chip; the i-th constant current chip shields the first pulse or level of the received address configuration information and forwards it to the (i+1)-th constant current chip.

[0014] In the line scan synchronization display method based on dual-line cascading of the present invention, the step of the i-th constant current chip generating a frame synchronization signal according to the IC address during the instruction synchronization period includes:

[0015] The i-th constant current chip generates a delay clock number based on the IC address;

[0016] After entering the instruction synchronization period, a delay is performed according to the number of delay clocks to generate a frame synchronization signal.

[0017] In the horizontal scanning synchronization display method based on dual-line cascading of the present invention, the step of generating a horizontal synchronization signal by using the IC address to correct the frame synchronization signal by the i-th constant current chip includes:

[0018] Using the frame synchronization signal and the configured line spacing parameters, a first delay signal is generated, and a second delay signal is generated by delaying the first delay signal by half a clock cycle. The start of the first delay signal corresponds to the rising edge of the clock, and the start of the second delay signal corresponds to the falling edge of the clock.

[0019] Determine whether the IC address of the i-th constant current chip is odd or even. If the IC address is odd, select the second delay signal as the horizontal synchronization signal of the i-th constant current chip. If the IC address is even, select the first delay signal as the horizontal synchronization signal of the i-th constant current chip.

[0020] According to another aspect of the present invention, a line scan synchronous display system based on dual-line cascade is also provided, comprising a controller and M constant current chips, wherein the clock input and data input terminals of the first constant current chip are connected to the clock output and data output terminals of the controller, and the clock input and data input terminals of the kth constant current chip are connected to the clock output and data output terminals of the (k-1)th constant current chip, wherein M is a positive integer ≥ 1, 2 ≤ k ≤ M,

[0021] The controller is configured to send a clock signal and an address configuration instruction to the first constant current chip. The address configuration instruction includes instruction identification information, address configuration information, and instruction synchronization period.

[0022] Each constant current chip includes:

[0023] The decoding module is used to generate the IC address based on the address configuration information after receiving the clock signal and the address configuration instruction;

[0024] The forwarding module is used to process the clock signal and address configuration instructions and forward them to the next cascaded constant current chip;

[0025] A frame synchronization signal generation module is used to generate a frame synchronization signal based on the IC address during the instruction synchronization period.

[0026] A line synchronization signal generation module is used to correct the frame synchronization signal using the IC address to generate a line synchronization signal.

[0027] In the dual-line cascaded row scan synchronous display system of the present invention, the address configuration information is composed of continuous pulse or level signals, and the decoding module generates the IC address according to the number of pulse signals or level signals of the address configuration information.

[0028] In the line scan synchronization display system based on dual-line cascading of the present invention, the forwarding module includes:

[0029] The clock signal processing unit is used to invert the clock signal and forward it to the next cascaded constant current chip.

[0030] The address configuration instruction processing module is used to shield the first pulse or level of the received address configuration information and then forward the address configuration instruction to the next cascaded constant current chip.

[0031] In the line scan synchronization display system based on dual-line cascade of the present invention, the frame synchronization signal generation module includes:

[0032] A calculation unit is used to generate a number of delay clocks based on the IC address;

[0033] The frame synchronization signal generation unit is used to generate a frame synchronization signal after entering the instruction synchronization period and delaying according to the number of delay clocks.

[0034] In the line scan synchronization display system based on dual-line cascade of the present invention, the line synchronization signal generation module includes:

[0035] The delay unit is used to generate a first delay signal using the frame synchronization signal and the configured line spacing parameters, and to generate a second delay signal by delaying the first delay signal by half a clock cycle. The start of the first delay signal corresponds to the rising edge of the clock, and the start of the second delay signal corresponds to the falling edge of the clock.

[0036] The selection module is used to select the second delay signal as the line synchronization signal of the constant current chip for the constant current chip with an odd IC address, and to select the first delay signal as the line synchronization signal of the constant current chip for the constant current chip with an even IC address.

[0037] The method and system for synchronous row scanning based on dual-line cascading of the present invention have the following advantages: The present invention achieves cascading through serial connection of two lines, DCLK and SDI. The controller sends specific instructions to enable the cascaded chips to automatically configure their addresses. The chips perform delay synchronization on the received instructions according to the configured addresses. At the same time, the sampling clock of the cascaded chips adopts a serial inverse output strategy to achieve stable sampling of cascaded data, which solves the attenuation problem of DCLK parallel mode and supports cascading more chips. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort:

[0039] Figure 1 shows a traditional four-wire drive scheme;

[0040] Figure 2 shows a traditional three-wire drive scheme;

[0041] Figure 3 shows a schematic diagram of a line scan synchronous display system based on dual-line cascading provided by an embodiment of the present invention, wherein each chip is in a state where no address configuration instruction has been sent;

[0042] Figure 4 shows a schematic diagram of a line scan synchronous display system based on dual-line cascading provided by an embodiment of the present invention, wherein each chip is in the state of sending address configuration instructions;

[0043] Figure 5 is a flowchart illustrating the line scan synchronous display method based on dual-line cascading provided by the present invention.

[0044] Figure 6 shows a timing diagram of address configuration instructions provided in an embodiment of the present invention;

[0045] Figure 7 shows a timing diagram for cascaded address frame synchronization provided in an embodiment of the present invention;

[0046] Figure 8 shows a row synchronization timing diagram of a cascaded chip provided in an embodiment of the present invention;

[0047] Figure 9 shows the schematic diagram of the constant current chip in the horizontal scanning synchronous display system based on dual-line cascade shown in Figure 3. Detailed Implementation

[0048] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Typical embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0050] Figure 3 shows a schematic diagram of a horizontal scanning synchronous display system based on dual-line cascading provided by an embodiment of the present invention. As shown in Figure 3, the horizontal scanning synchronous display system based on dual-line cascading provided by the present invention includes a controller and M cascaded constant current IC chips. The clock input and data input terminals of the first constant current chip are connected to the clock output and data output terminals of the controller, and the clock input and data input terminals of the kth constant current chip are connected to the clock output and data output terminals of the (k-1)th constant current chip. Here, M is a positive integer ≥ 1, and 2 ≤ k ≤ M. In this invention, each stage of the M cascaded constant current chips includes a clock input terminal, a data input terminal, and a data output terminal. The clock input terminal and data input terminal of the first stage constant current chip receive the initial clock signal and the initial serial data signal. The clock input terminal and data input terminal of the k-th stage constant current chip receive the clock signal and serial data signal output by the (k-1)-th stage constant current chip. This achieves serial output of the clock signal DCLK through the constant current chip, solving the problem of parallel clock attenuation. Furthermore, since the entire scheme has only two serial signal lines and no parallel lines, the wiring is simple, reducing the difficulty of PCB design.

[0051] Figure 5 is a flowchart illustrating the line scan synchronization display method based on dual-line cascading provided by the present invention. As shown in Figure 5, the line scan synchronization display method based on dual-line cascading provided by the present invention includes the following steps:

[0052] Step S1: Send a clock signal and an address configuration instruction to the first constant current chip through the controller. The address configuration instruction includes instruction identification information, address configuration information, and instruction synchronization period.

[0053] Specifically, in one embodiment of the present invention, the user first determines the total number of cascaded constant current chips, and then sends a clock signal and an address configuration instruction to the first constant current chip via a controller. The address configuration instruction includes at least three parts: an instruction identification code, address configuration information, and a synchronization period. The instruction identification information is a preamble to the address configuration instruction, used to distinguish it from other configuration instructions and interference information. Address configuration information is located within a specific time period following the address preamble. This specific time period can be fixed or configured by other asynchronous instructions. The address configuration information consists of a specified number of pulse signals or continuous level signals. Cascaded constant current chips generate unique address parameters by counting the pulses or levels within this specific time period. That is, the high pulse count in this time period represents the IC address to be generated. Therefore, the maximum number of pulses or the widest level supported by the address configuration information determines the maximum number of cascaded chips. For example, if the total width of this specific time period is 64 DCLKs, theoretically, up to 64 (inclusive) constant current chips can be cascaded by controlling the high pulse count; if the total width of this time period is 128 DCLKs, theoretically, up to 128 (inclusive) constant current chips can be cascaded by controlling the high pulse count. Synchronization time period information uses the IC address to delay the received instructions, while simultaneously preventing other instructions from interfering with the instruction synchronization process.

[0054] Step S2: After receiving the clock signal and address configuration instruction, the i-th constant current chip generates an IC address for the i-th constant current chip according to the address configuration information, and forwards the clock signal and address configuration instruction to the (i+1)-th constant current chip, where 1≤i≤M;

[0055] Specifically, in one embodiment of the present invention, the i-th constant current chip generates an IC address for the i-th constant current chip based on the number of pulse signals or the number of levels in the address configuration information. A relative address is generated based on all the pulse counts or levels (number of high levels or number of low levels) received in this state. Simultaneously, the total clock count of the address configuration information state determines the maximum number of pulses or the widest level it can support, and the maximum number of pulses or the widest level determines its cascading length. If the total width of the address configuration information state is 64 DCLKs, it theoretically supports 64 ICs cascading.

[0056] Specifically, in one embodiment of the present invention, the i-th constant current chip masks the first pulse or level of the received address configuration information and forwards it to the (i+1)-th constant current chip. In this invention, to ensure that the address parameters are not identical, the chip needs to mask the first pulse or level received within a specific time period and forward it to the secondary chip again. Taking cascading 32 ICs as an example, the controller needs to send 32 high pulses within the address configuration information state (if the total clock count for this state is 48 DCLKs, the total number of high pulses is exactly 32, and the total number of low-level pulses is 16); after passing through the first-stage IC, the total clock count for this state is still 48 DCLKs, but the number of high pulses is exactly 31, and the total number of low-level pulses is 17; ...; if cascading 48 ICs, the total clock count for this state is still 48 DCLKs, but it no longer includes high pulses. Figure 3 shows the state where no address configuration instruction has been sent, at which time the relative address of each cascaded constant current chip, i.e., the IC address identifier, is 0. After the controller sends the address configuration command, the cascaded chips complete the identification of the relative address. The address identification result is shown in Figure 4, where the IC address decreases sequentially according to the data flow direction.

[0057] In this embodiment, after receiving the clock signal and the address configuration instruction, the cascaded constant current chip, upon detecting the instruction identification code in the address configuration instruction, counts all received pulses or levels within a specific time period to generate the relative address of the constant current chip in the cascaded state as the IC address of the constant current chip. At the same time, after masking the first received pulse or level, the address configuration instruction is forwarded to the next cascaded constant current chip to ensure that the next stage chip does not generate a duplicate address.

[0058] Specifically, in one embodiment of the present invention, the i-th constant current chip inverts the clock signal and forwards it to the (i+1)-th constant current chip. Due to the characteristics of the circuit devices, BUF forwarding inevitably involves high-level or low-level attenuation. If all forwarding is in the forward direction, this attenuation will accumulate, resulting in greater attenuation with each cascade, until the high-level or low-level width attenuates to 0. However, with clock inversion output, if the first stage attenuates with a high level, the second stage attenuates with a low level, and the attenuation amounts are complementary. For example, if CLK0 has a 50% duty cycle, and the circuit devices have high-level attenuation, with each stage attenuating by 2%, in the forward forward direction, after cascading 25 chips, the high-level duty cycle will attenuate to 0, limiting the number of cascaded chips. However, with clock inversion output, the high-level duty cycle of the first stage becomes 48%, and after inversion, it becomes 52%. Then, after the high level of the second-stage constant current chip attenuates by another 2%, it becomes 50%, achieving duty cycle balance.

[0059] In this embodiment, in order to avoid the problem of continuous decay of the high / low level duty cycle in the serial clock output, a clock inversion output strategy is adopted, so that the decay of the high / low level duty cycle of the odd and even chips is complementary, thereby increasing the range of cascaded systems.

[0060] Step S3: The i-th constant current chip generates a frame synchronization signal based on the IC address during the instruction synchronization period;

[0061] Specifically, in one embodiment of the present invention, the i-th constant current chip generates a delay clock number based on the IC address, where the delay clock number = (IC address + 2) / 2. After entering the instruction synchronization period, a delay is performed based on the delay clock number to generate a frame synchronization signal. Thus, the chip synchronizes the instruction in the address synchronization segment using a relative address, that is, the decoded instruction is delayed based on the configured IC address. This allows the constant current chip to synchronize the instruction in the instruction synchronization period using a relative address, ensuring that the first and last chips in the cascaded state can simultaneously generate frame change flags.

[0062] Specifically, as shown in Figure 6, after receiving the address configuration instruction identification code in the idle state, the constant current chip enters the address information configuration state. The constant current chip counts the pulses received in this state, and the final result serves as the IC address; simultaneously, it masks the first high pulse in this state and continues to forward the address information. After exiting the address information configuration state, the constant current chip immediately starts counting DCLK from 0, and generates a frame synchronization signal immediately after counting to (IC address + 2) / 2 generated in the previous state. Once the address configuration instruction identification code is received again in the idle state, the steps shown in Figure 6 are repeated.

[0063] Furthermore, due to the "reverse output" cascading strategy of the clock, the frame synchronization flag will differ by half a DCLK due to the parity of the IC address. As shown in Figure 7, taking a cascade of four constant current chips as an example, the cascaded constant current chips will only shield the first high pulse sampled in the address configuration information state (the timing in Figure 7 is sampling at the rising edge of the clock). At other times, data is forwarded normally at the rising edge of the sampling clock (taking the IC with cascaded address 4 as an example, the inputs are DCLK0 and SDI0; the outputs are DCLK1 and SDI1). Therefore, the number of high pulses received by the cascaded constant current chips in the address configuration information state will decrease, and the data received in other states will only have a delay (the output is delayed by half a DCLK relative to the input). After the logic state enters the instruction synchronization period, the constant current chip will delay according to the number of high pulses received in the address configuration information state (actual delay clock count: (IC address + 2) / 2), and then generate the instruction enable flag. The remaining instructions can be cascaded synchronously by delaying the constant current chip address, and the synchronization process does not need to go through the address configuration information state.

[0064] Step S4: The i-th constant current chip uses the IC address to correct the frame synchronization signal and generate a line synchronization signal.

[0065] Specifically, in one embodiment of the present invention, a first delay signal is generated using the frame synchronization signal and the configured line spacing parameters. A second delay signal is generated by delaying the first delay signal by half a clock cycle. The start of the first delay signal corresponds to the rising edge of the clock, and the start of the second delay signal corresponds to the falling edge of the clock. It is determined whether the IC address of the i-th constant current chip is odd or even. If the IC address is odd, the second delay signal is selected as the line synchronization signal of the i-th constant current chip. If the IC address is even, the first delay signal is selected as the line synchronization signal of the i-th constant current chip.

[0066] In this embodiment, the first line feed flag is generated after a specified number of clock cycles (which can be 0) of delay on the frame synchronization signal. Then, using the first line feed flag as the starting point and the configured line interval parameter, the line feed flags for subsequent line scans are generated sequentially, which constitutes the first delay signal. The second delay signal is generated by delaying all first delay signals by half a clock cycle. The cascaded constant current chip generates line feed flags based on the frame feed flag and using the pre-configured interval parameter in the register to achieve the line synchronization requirement. The line feed flags are generated regularly using the line interval parameter starting from the frame feed flag. However, due to the "reverse output" of the clock, the actual generation interval of the frame feed flag is half a DCLK. Therefore, it is necessary to further adjust the final generated line feed flag using address parity to achieve complete synchronization of the line feed flags. The line synchronization timing is shown in Figure 8. The frame synchronization flag of the cascaded constant current chip is affected by address parity and is generated at an interval of half a cycle, but the final line synchronization flag has no phase difference after algorithm correction.

[0067] Figure 9 shows the schematic diagram of the constant current chip in the dual-line cascaded horizontal scanning synchronous display system shown in Figure 3. The system in Figure 3 includes a controller and M constant current chips. The clock and data input terminals of the first constant current chip are connected to the clock and data output terminals of the controller. The clock and data input terminals of the kth constant current chip are connected to the clock and data output terminals of the (k-1)th constant current chip. Here, M is a positive integer ≥ 1, and 2 ≤ k ≤ M. The controller is configured to send a clock signal and an address configuration instruction to the first constant current chip. The address configuration instruction includes instruction identification information, address configuration information, and an instruction synchronization period. As shown in Figure 9, each constant current chip includes a decoding module 100, a forwarding module 200, a frame synchronization signal generation module 300, and a horizontal synchronization signal generation module 400.

[0068] Specifically, in this embodiment, the decoding module 100 is used to generate an IC address based on address configuration information after receiving a clock signal and an address configuration instruction. The address configuration information consists of continuous pulses or level signals, and the decoding module generates the IC address based on the number of pulses or level signals in the address configuration information. After receiving the clock signal and the address configuration instruction, the cascaded constant current chip, upon detecting the instruction identification code in the address configuration instruction, counts all received pulses or level signals within a specific time period to generate the relative address of the constant current chip in the cascaded state as the IC address of the constant current chip.

[0069] Specifically, in this embodiment, the forwarding module processes the clock signal and address configuration instruction and forwards them to the next cascaded constant current chip. It includes: a clock signal processing unit, used to invert the clock signal and forward it to the next cascaded constant current chip; and an address configuration instruction processing module, used to mask the first pulse or level of the received address configuration information and forward the address configuration instruction to the next cascaded constant current chip. To avoid the problem of continuously decaying high / low level duty cycles in serial clock output, a clock inversion strategy is adopted, making the high / low level duty cycle decay of odd and even chips complementary, increasing the range of cascaded chips. Simultaneously, masking the first received pulse or level before forwarding the address configuration instruction to the next cascaded constant current chip ensures that the next stage chip does not generate duplicate addresses.

[0070] Specifically, in this embodiment, the frame synchronization signal generation module is used to generate a frame synchronization signal based on the IC address during the instruction synchronization period. The frame synchronization signal generation module includes: a calculation unit, used to generate a delay clock number based on the IC address; and a frame synchronization signal generation unit, used to generate a frame synchronization signal by delaying based on the delay clock number after entering the instruction synchronization period. Although the first and last chips in the serial cascaded state receive signals at different times, they can adaptively delay synchronization based on their relative addresses, achieving synchronized frame switching between cascaded chips.

[0071] Specifically, in this embodiment, the line synchronization signal generation module is used to correct the frame synchronization signal using the IC address to generate a line synchronization signal. The line synchronization signal generation module includes: a delay unit, used to generate a first delay signal using the frame synchronization signal and configured line interval parameters, and to generate a second delay signal by delaying the first delay signal by half a clock cycle, wherein the start of the first delay signal corresponds to the rising edge of the clock, and the start of the second delay signal corresponds to the falling edge of the clock; and a selection module, used to select the second delay signal as the line synchronization signal for constant current chips with odd IC addresses, and to select the first delay signal as the line synchronization signal for constant current chips with even IC addresses. The cascaded constant current chips generate line feed flags based on frame change flags and using pre-configured interval parameters in registers to achieve line synchronization. Simultaneously, the parity of the address is used to further adjust the finally generated line feed flags to achieve complete synchronization of the line feed flags.

[0072] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0073] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0074] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0075] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0076] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A method for synchronous row scanning display based on dual-line cascading, used in a display system comprising a controller and M cascaded constant current chips, characterized in that, The clock and data input terminals of the first constant current chip are connected to the clock and data output terminals of the controller, and the clock and data input terminals of the k-th constant current chip are connected to the clock and data output terminals of the (k-1)-th constant current chip, where M is a positive integer ≥ 1, 2 ≤ k ≤ M. The method includes the following steps: the controller sends a clock signal and an address configuration instruction to the first constant current chip, the address configuration instruction including instruction identification information, address configuration information, and an instruction synchronization period; after receiving the clock signal and address configuration instruction, the i-th constant current chip generates an IC address for the i-th constant current chip according to the address configuration information, and processes the clock signal and address configuration instruction before forwarding it to the (i+1)-th constant current chip, where 1 ≤ i ≤ M; the i-th constant current chip, according to the instruction synchronization period, generates an IC address for the i-th constant current chip according to the address configuration information, and processes the clock signal and address configuration instruction before forwarding it to the (i+1)-th constant current chip. The steps of generating a frame synchronization signal using the IC address; the i-th constant current chip using the IC address to correct the frame synchronization signal and generate a line synchronization signal; and the i-th constant current chip using the IC address to correct the frame synchronization signal and generate a line synchronization signal include: generating a first delay signal using the frame synchronization signal and configured line interval parameters; delaying the first delay signal by half a clock cycle to generate a second delay signal, wherein the start of the first delay signal corresponds to the rising edge of the clock, and the start of the second delay signal corresponds to the falling edge of the clock; determining whether the IC address of the i-th constant current chip is odd or even; if the IC address is odd, selecting the second delay signal as the line synchronization signal of the i-th constant current chip; and if the IC address is even, selecting the first delay signal as the line synchronization signal of the i-th constant current chip.

2. The method for synchronous row scanning display based on dual-line cascading according to claim 1, characterized in that, The i-th constant current chip generates an IC address for itself based on the number of pulse signals or the number of levels in the address configuration information.

3. The method for synchronous row scanning display based on dual-line cascading as described in claim 1, characterized in that, The i-th constant current chip inverts the clock signal and forwards it to the (i+1)-th constant current chip; the i-th constant current chip shields the first pulse or level of the received address configuration information and forwards it to the (i+1)-th constant current chip.

4. The method for synchronous row scanning display based on dual-line cascading as described in claim 1, characterized in that, The step of the i-th constant current chip generating a frame synchronization signal based on the IC address during the instruction synchronization period includes: the i-th constant current chip generating a delay clock number based on the IC address; after entering the instruction synchronization period, delaying according to the delay clock number to generate a frame synchronization signal.

5. A line scan synchronous display system based on dual-line cascade, comprising a controller and M constant current chips, characterized in that, The clock and data input terminals of the first constant current chip are connected to the clock and data output terminals of the controller, and the clock and data input terminals of the kth constant current chip are connected to the clock and data output terminals of the (k-1)th constant current chip, where M is a positive integer ≥ 1, 2 ≤ k ≤ M. The controller is configured to send a clock signal and an address configuration instruction to the first constant current chip. The address configuration instruction includes instruction identification information, address configuration information, and an instruction synchronization period. Each constant current chip includes: a decoding module, used to generate an IC address based on the address configuration information after receiving the clock signal and address configuration instruction; a forwarding module, used to forward the processed clock signal and address configuration instruction to the next cascaded constant current chip; and a frame synchronization signal generation module. The system is used to generate a frame synchronization signal based on the IC address during the instruction synchronization period; a line synchronization signal generation module is used to correct the frame synchronization signal using the IC address to generate a line synchronization signal; the line synchronization signal generation module includes: a delay unit, used to generate a first delay signal using the frame synchronization signal and configured line interval parameters, and to generate a second delay signal by delaying the first delay signal by half a clock cycle, wherein the start of the first delay signal corresponds to the rising edge of the clock, and the start of the second delay signal corresponds to the falling edge of the clock; a selection module, used to select the second delay signal as the line synchronization signal for constant current chips with odd IC addresses, and to select the first delay signal as the line synchronization signal for constant current chips with even IC addresses.

6. The line scan synchronous display system based on dual-line cascading according to claim 5, characterized in that, The address configuration information consists of continuous pulse or level signals, and the decoding module generates the IC address based on the number of pulse signals or level signals in the address configuration information.

7. The line scan synchronous display system based on dual-line cascading as described in claim 5, characterized in that, The forwarding module includes: a clock signal processing unit, used to invert the clock signal and forward it to the next cascaded constant current chip; and an address configuration instruction processing module, used to shield the first pulse or level of the received address configuration information and forward the address configuration instruction to the next cascaded constant current chip.

8. The line scan synchronous display system based on dual-line cascading as described in claim 5, characterized in that, The frame synchronization signal generation module includes: a calculation unit, used to generate a delay clock number based on the IC address; and a frame synchronization signal generation unit, used to generate a frame synchronization signal by delaying according to the delay clock number after entering the instruction synchronization period.

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