An ultra-wideband high harmonic rejection power amplifier

Abstract

The application discloses a kind of ultra-wideband high harmonic suppression power amplifier, including low-frequency power amplification branch, high-frequency power amplification branch, harmonic suppression matching network, the harmonic suppression matching network includes low-frequency harmonic suppression matching network, high-frequency harmonic suppression matching network and common output end;The low-frequency power amplification branch, high-frequency power amplification branch respectively to the frequency different low-frequency band signal, high-frequency band signal in work wideband is carried out power amplification, the low-frequency harmonic suppression matching network, high-frequency harmonic suppression matching network respectively to the impedance matching of fundamental wave in low-frequency band signal, high-frequency band signal after power amplification, while inhibiting second and third harmonic signals.The application solves the problem of low power efficiency and poor high-order harmonic suppression in the prior art.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and in particular to an ultra-wideband high harmonic suppression power amplifier. Background Technology

[0002] As the component responsible for power transmission in the transmit link, the power amplifier must operate stably in ultra-wideband mode in fields such as radar detection. However, due to the nonlinearity of the device, wideband power amplifiers, in addition to amplifying the fundamental signal, also generate higher harmonics (such as second and third harmonics), resulting in low power efficiency and poor suppression of higher harmonics. This problem leads to insufficient overall transmit link power, and because the second and third harmonics have high power, they cause severe signal interference to the transmitter, increase the difficulty of signal processing in the receiver, and easily lead to electromagnetic compatibility issues. Therefore, it is necessary to suppress the generated higher harmonics. Summary of the Invention

[0003] Purpose of the invention: The purpose of this invention is to provide an ultra-wideband high harmonic suppression power amplifier, which solves the problems of low power efficiency and poor high-order harmonic suppression in existing power amplifiers.

[0004] Technical Solution: To achieve the above objectives, the present invention provides an ultra-wideband high harmonic suppression power amplifier, comprising a low-frequency power amplification branch, a high-frequency power amplification branch, and a harmonic suppression matching network. The harmonic suppression matching network includes a low-frequency harmonic suppression matching network, a high-frequency harmonic suppression matching network, and a common output terminal. The low-frequency power amplification branch and the high-frequency power amplification branch respectively amplify low-frequency band signals and high-frequency band signals with different frequencies within the operating wide bandwidth. The low-frequency harmonic suppression matching network and the high-frequency harmonic suppression matching network respectively perform impedance matching on the fundamental frequencies of the amplified low-frequency band signals and high-frequency band signals, while suppressing the second and third harmonic signals.

[0005] Preferably, it also includes a single-pole double-throw switch, wherein the common terminal of the single-pole double-throw switch is the radio frequency signal input terminal, and the output terminal of the single-pole double-throw switch is respectively connected to the low-frequency power amplifier branch and the high-frequency power amplifier branch to realize the switching of different frequency bands.

[0006] Preferably, the low-frequency power amplifier branch includes a low-frequency input matching network, m-stage low-frequency dies, and m-1 low-frequency inter-stage matching networks. Each stage of the low-frequency dies has a transistors connected in parallel, and the sources of all transistors are connected to ground vias. The gate of the first-stage low-frequency dies is connected to the output terminal of the low-frequency input matching network, and the drain of the m-th stage low-frequency dies serves as the output terminal of the low-frequency power amplifier branch.

[0007] Preferably, the high-frequency power amplification branch includes a high-frequency input matching network, n high-frequency chips, and n-1 high-frequency inter-stage matching networks. Each high-frequency chip has b transistors connected in parallel, and the sources of all transistors are connected to ground vias. The gate of the first-stage high-frequency chip is connected to the output of the high-frequency matching network, and the drain of the nth-stage high-frequency chip serves as the output of the high-frequency power amplification branch.

[0008] Preferably, the transistor is a junction field-effect transistor, a metal-oxide-semiconductor field-effect transistor, a heterojunction field-effect crystal, a bipolar junction transistor, or a heterojunction bipolar transistor.

[0009] Preferably, the common output terminal is the output terminal of the entire operating frequency band, including a nineteenth microstrip line L19 and an eleventh capacitor C11 connected in series. The nineteenth microstrip line L19 is connected to the output terminals of the low-frequency harmonic suppression matching network and the high-frequency harmonic suppression matching network.

[0010] Preferably, the low-frequency harmonic suppression matching network includes a parallel resonant network composed of a capacitor and a microstrip line, and a series resonant network composed of the turn-off capacitor of the switching transistor and the microstrip line. Through the synergistic effect of the parallel resonant network and the series resonant network, the suppression of the second and third harmonics of the low-frequency signal is achieved.

[0011] Preferably, the low-frequency harmonic suppression matching network includes first to ninth microstrip lines L1~L9, first to fifth capacitors C1~C5, and first to fourth switching transistors S1~S4; wherein, one end of the second microstrip line L2 and the third microstrip line L3 are respectively connected to the first microstrip line L1 and the fourth microstrip line L4, and the other end is respectively connected to the upper plates of the first capacitor C1 and the second capacitor C2, and the lower plates of the first capacitor C1 and the second capacitor C2 are connected to a ground via; the upper plate of the third capacitor C3 is connected to the output terminal of the fourth microstrip line L4, and the lower plate is connected to a ground via; the upper plate of the fourth capacitor C4 and the input terminal of the fifth microstrip line L5 are connected... The upper plate of the third capacitor C3 is connected, the lower plate of the fourth capacitor C4 and the output terminal of the fifth microstrip line L5 are connected to the upper plate of the fifth capacitor C5; the lower plate of the fifth capacitor C5, the seventh microstrip line L7 and the ninth microstrip line L9 are connected in sequence; the drain terminal of the first switch S1 is connected to the input terminal of the seventh microstrip line L7, and the source terminal is connected to the drain terminal of the second switch S2, and the source terminal of the second switch S2 is connected to the ground via the sixth microstrip line L6; the drain terminal of the third switch S3 is connected to the input terminal of the ninth microstrip line L9, and the source terminal is connected to the drain terminal of the fourth switch S4, and the source terminal of the fourth switch S4 is connected to the ground via the eighth microstrip line L8;

[0012] The fourth capacitor C4 and the fifth microstrip line L5 form a first parallel resonant network. The turn-off capacitors of the first switch S1 and the second switch S2 and the sixth microstrip line L6 form a first series resonant network. The turn-off capacitors of the third switch S3 and the fourth switch S4 and the eighth microstrip line L8 form a second series resonant network.

[0013] Preferably, the high-frequency harmonic suppression matching network includes a parallel resonant network composed of a capacitor and a microstrip line, and a series resonant network composed of the turn-off capacitor of the switching transistor and the microstrip line. Through the synergistic effect of the parallel resonant network and the series resonant network, the suppression of the second and third harmonics of the high-frequency signal is achieved.

[0014] Preferably, the high-frequency harmonic suppression matching network includes tenth to eighteenth microstrip lines L10~L18, sixth to tenth capacitors C6~C10, and fifth to eighth switches S5~S8; wherein, one end of the twelfth microstrip line L12 and the eleventh microstrip line L11 are respectively connected to the tenth microstrip line L10 and the thirteenth microstrip line L13, and the other end is respectively connected to the upper plate of the sixth capacitor C6 and the seventh capacitor C7, and the lower plate of the sixth capacitor C6 and the seventh capacitor C7 is connected to a ground hole; the upper plate of the eighth capacitor C8 is connected to the output terminal of the thirteenth microstrip line L13, and the lower plate is connected to a ground hole; the upper plate of the ninth capacitor C9 is connected to the input terminal of the fourteenth microstrip line L14. The upper plate of the eighth capacitor C8, the lower plate of the ninth capacitor C9, and the output terminal of the fourteenth microstrip line L14 are connected to the upper plate of the tenth capacitor C10. The lower plate of the tenth capacitor C10 is connected to the input terminal of the sixteenth microstrip line L16. The drain terminal of the fifth switch S5 is connected to the input terminal of the sixteenth microstrip line L16, and the source terminal is connected to the drain terminal of the sixth switch S6. The source terminal of the sixth switch S6 is connected to a ground via the fifteenth microstrip line L15. The drain terminal of the seventh switch S7 is connected to the sixteenth microstrip line L16 and the eighteenth microstrip line L18, and the source terminal is connected to the drain terminal of the eighth switch S8. The source terminal of the eighth switch S8 is connected to a ground via the seventeenth microstrip line L17.

[0015] The ninth capacitor C9 and the fourteenth microstrip line L14 form a second parallel resonant network. The turn-off capacitors of the fifth switch S5 and the sixth switch S6, together with the fifteenth microstrip line L15, form a third series resonant network. The turn-off capacitors of the seventh switch S7 and the eighth switch S8, together with the seventeenth microstrip line L17, form a fourth series resonant network.

[0016] Beneficial effects: This invention has the following advantages: It divides the wide operating bandwidth into narrow bandwidths with different power levels. By utilizing low-frequency and high-frequency harmonic suppression matching networks, it performs fundamental impedance matching for the divided low-frequency and high-frequency signals respectively, while suppressing second and third harmonic signals. This solves the problem of difficult filtering of harmonic aliasing with the fundamental frequency in broadband mode, thus achieving high-performance output with both high gain and high harmonic suppression in the ultra-wideband range. In addition, by changing the wide bandwidth matching to multiple narrow bandwidth matching, matching loss is reduced, thereby improving the power and efficiency of the amplifier. Attached Figure Description

[0017] Figure 1 This is a structural diagram of an ultra-wideband high harmonic suppression power amplifier;

[0018] Figure 2 This is a schematic diagram of a harmonic suppression matching network circuit that integrates switching.

[0019] Figure 3 This is a graph showing the test results of the second harmonic suppression degree of the ultra-wideband high harmonic suppression power amplifier in Example 5;

[0020] Figure 4 This is a graph showing the test results of the third harmonic suppression degree of the ultra-wideband high harmonic suppression power amplifier in Example 5. Detailed Implementation

[0021] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0022] Example 1

[0023] like Figure 1 As shown, an ultra-wideband high harmonic suppression power amplifier has an overall structure including a single-pole double-throw switch, a low-frequency power amplification branch, a high-frequency power amplification branch, and a harmonic suppression matching network integrating the switch.

[0024] The common terminal of the single-pole double-throw (SPDT) switch is the signal input terminal for the radio frequency (RF) signal, and the output terminals are connected to the low-frequency power amplifier branch and the high-frequency power amplifier branch, respectively. The SPDT switch has a symmetrical structure. By dividing the wide operating bandwidth into narrow bands of different frequencies (wide bandwidth includes second or third harmonic frequencies, while narrow bands only include the fundamental frequency, dividing a wider bandwidth into narrow bands is beneficial for harmonic suppression), for example, dividing the wide operating bandwidth f1-f4 into low-frequency signals f1-f2 and high-frequency signals f3-f4 (the relative bandwidth of f1-f4 is 100%, and the relative relationship is f1 < f3 ≤ f2 < f4), the SPDT switch can switch between the low-frequency signals f1-f2 and the high-frequency signals f3-f4.

[0025] Both the low-frequency power amplifier branch and the high-frequency power amplifier branch are multi-stage amplification structures that amplify the power of the input radio frequency signal within the frequency band. At the same time, the multi-stage amplification is to further improve the gain.

[0026] The integrated harmonic suppression and matching network includes: a low-frequency harmonic suppression and matching network, a high-frequency harmonic suppression and matching network, and a common output terminal. The input terminals of the low-frequency and high-frequency harmonic suppression and matching networks are connected to the output terminals of the low-frequency power amplifier branch and the high-frequency power amplifier branch, respectively. Specifically, the low-frequency harmonic suppression and matching network performs impedance matching on the fundamental signal of the input low-frequency signal while suppressing the second and third harmonic signals in the low-frequency signal; the high-frequency harmonic suppression and matching network performs impedance matching on the fundamental signal of the input high-frequency signal while suppressing the second and third harmonic signals in the high-frequency signal.

[0027] The power amplifier described in this embodiment amplifies both the low-frequency and high-frequency signals before inputting them into an integrated harmonic suppression and matching network. This integrated network performs fundamental impedance matching and second and third harmonic suppression on both the amplified low-frequency and high-frequency signals, resulting in a cleaner output signal and significantly reducing the output power of the second and third harmonics. Taking the amplified low-frequency signals f1-f2 and high-frequency signals f3-f4 as examples, the low-frequency harmonic suppression and matching network performs impedance matching on the fundamental frequency of the f1-f2 signal while suppressing the second and third harmonics; similarly, the high-frequency harmonic suppression and matching network performs impedance matching on the fundamental frequency of the f3-f4 signal while suppressing the second and third harmonics.

[0028] Example 2

[0029] like Figure 1 , 2 As shown, the low-frequency power amplifier branch includes a low-frequency input matching network, m stages of low-frequency transistors, and m-1 low-frequency inter-stage matching networks. Each stage of the low-frequency transistor has a transistors connected in parallel, and the sources of all transistors are connected to ground vias. The parallel transistor structure is a microstrip line power combining structure, where m and a are both integers greater than or equal to 1. In this embodiment, the low-frequency power amplifier branch improves the power gain of the power amplifier through a multi-stage amplification structure. The last stage of the low-frequency transistors is a multi-cell power combining structure, the purpose of which is to increase the output power.

[0030] Furthermore, the physical structure type of a transistor can be a junction field-effect transistor, a metal-oxide-semiconductor field-effect transistor, a heterojunction field-effect crystal, a bipolar junction transistor, or a heterojunction bipolar transistor.

[0031] The gate of the first-stage low-frequency segment die is connected to the output of the low-frequency input matching network, and the drain of the m-th stage low-frequency segment die serves as the output of the low-frequency power amplifier branch.

[0032] When m is greater than or equal to 2, a low-frequency interstage matching network is connected in series between two adjacent low-frequency chips.

[0033] The low-frequency input matching network connects the single-pole double-throw switch to the first-stage low-frequency transistor die, transforming the impedance at the switch output to the optimal input impedance of the transistor to achieve maximum power transfer while isolating DC bias. This network typically employs an L-type, π-type, or T-type lumped-parameter structure composed of inductors and capacitors.

[0034] When the low-frequency power amplifier branch is a multi-stage structure, the low-frequency interstage matching network is connected in series between two adjacent stage chips. It is responsible for transforming the high impedance of the output of the previous stage into the input impedance required by the next stage. This network usually adopts an L-type, π-type or T-type lumped parameter structure.

[0035] Example 3

[0036] like Figure 1 , 2 As shown, the high-frequency power amplifier branch includes a high-frequency input matching network, n high-frequency transistor dies, and n-1 high-frequency inter-stage matching networks. Each high-frequency transistor die has b transistors connected in parallel. The sources of all transistors are connected to ground vias. The parallel transistor structure is a microstrip line power combining structure, where n and b are both integers greater than or equal to 1. The high-frequency power amplifier branch improves the power gain of the power amplifier through a multi-stage amplification structure. The last high-frequency transistor die is a multi-cell power combining structure, the purpose of which is to increase the output power.

[0037] Furthermore, the physical structure type of a transistor can be a junction field-effect transistor, a metal-oxide-semiconductor field-effect transistor, a heterojunction field-effect crystal, a bipolar junction transistor, or a heterojunction bipolar transistor.

[0038] The gate of the first-stage high-frequency segment die is connected to the output of the high-frequency matching network, and the drain of the nth-stage high-frequency segment die serves as the output of the high-frequency power amplification branch.

[0039] When n is greater than or equal to 2, a high-frequency inter-stage matching network is connected in series between two adjacent high-frequency chips.

[0040] A high-frequency input matching network is used to connect a single-pole double-throw switch to the first-stage high-frequency transistor die, transforming the impedance at the switch output to the optimal input impedance of the transistor to achieve maximum power transfer while isolating DC bias. This network typically employs an L-type, π-type, or T-type lumped-parameter structure composed of inductors and capacitors.

[0041] When the high-frequency power amplifier branch is a multi-stage structure, the high-frequency interstage matching network is connected in series between two adjacent stage chips. It is responsible for transforming the high impedance of the output of the previous stage into the input impedance required by the next stage. This network usually adopts an L-type, π-type or T-type lumped parameter structure.

[0042] Example 4

[0043] like Figure 2 As shown, the common output terminal of the integrated harmonic suppression matching network is the output terminal for the entire operating frequency band, including the nineteenth microstrip line L19 and the eleventh capacitor C11.

[0044] The input of the low-frequency harmonic suppression matching network is connected to the drain of the last stage low-frequency segment die of the low-frequency power amplifier branch, and the output is connected to the nineteenth microstrip line L19 of the common terminal. It is used to perform impedance matching on the fundamental signal of the low-frequency signal and suppress the second and third harmonic signals at the same time.

[0045] The low-frequency harmonic suppression matching network includes the first to the ninth microstrip lines (L1, L2, L3, L5, L6, L7, L8, L9), the first to the fifth capacitors (C1, C2, C3, C4, C5), and the first to the fourth switching transistors (S1, S2, S3, S4).

[0046] The input terminal of the first microstrip line serves as the input terminal of the low-frequency harmonic suppression matching network, and the output terminal of the ninth microstrip line L9 serves as the output terminal of the low-frequency harmonic suppression matching network. P1 is the DC feed port. The second microstrip line L2 and the third microstrip line L3 serve as feed microstrip lines, with one end connected to the first microstrip line L1 and the fourth microstrip line L4, respectively, and the other end connected to the upper plates of the first capacitor C1 and the second capacitor C2, respectively. The lower plates of the first capacitor C1 and the second capacitor C2 are connected to the ground via. The upper plate of the third capacitor C3 is connected to the output terminal of the fourth microstrip line L4, and the lower plate is connected to the ground via. The upper plate of the fourth capacitor C4 and the input terminal of the fifth microstrip line L5 are connected to the upper plate of the third capacitor C3, and the lower plate of the fourth capacitor C4 and the output terminal of the fifth microstrip line L5 are connected to the upper plate of the fifth capacitor C5. The lower plate of the fifth capacitor C5, the seventh microstrip line L7, and the ninth microstrip line L9 are connected sequentially. The drain terminal of the first switch S1 is connected to the input terminal of the seventh microstrip line L7, and the source terminal is connected to the drain terminal of the second switch S2. The source terminal of the second switch S2 is connected to a ground via the sixth microstrip line L6. The drain terminal of the third switch S3 is connected to the input terminal of the ninth microstrip line L9, and the source terminal is connected to the drain terminal of the fourth switch S4. The source terminal of the fourth switch S4 is connected to a ground via the eighth microstrip line L8.

[0047] The fourth capacitor C4 and the fifth microstrip line L5 form the first parallel resonant network, which is used to suppress part of the second harmonic of the low-frequency signal (frequency approximately f2-2f1). When the low-frequency harmonic suppression matching network is working, the control voltage is changed to turn off the switches S1, S2, S3, and S4 connected to port P3. At this time, these four switches can be equivalent to turn-off capacitors: the turn-off capacitors of the first switch S1 and the second switch S2, together with the sixth microstrip line L6, form the first series resonant network; the turn-off capacitors of the third switch S3 and the fourth switch S4, together with the eighth microstrip line L8, form the second series resonant network. These two series resonant networks are mainly responsible for suppressing part of the second harmonic and all of the third harmonic of the low-frequency signal. The low-frequency harmonic suppression matching network achieves the suppression of the second and third harmonics of the low-frequency signal through the above-mentioned series and parallel resonant networks.

[0048] Example 5

[0049] like Figure 2 As shown, the input of the high-frequency harmonic suppression matching network is connected to the drain of the last high-frequency segment die of the high-frequency power amplifier branch, and the output is connected to the nineteenth microstrip line L19 of the common terminal. It is used to match the fundamental signal in the f3-f4 frequency band and suppress the second and third harmonic signals at the same time.

[0050] The high-frequency harmonic suppression matching network includes the tenth to eighteenth microstrip lines (L10, L11, L12, L13, L14, L15, L16, L17, L18), the sixth to tenth capacitors (C6, C7, C8, C9, C10), and the fifth to eighth switches (S5, S6, S7, S8).

[0051] The input terminal of the tenth microstrip line L10 is the input terminal of the high-frequency harmonic suppression matching network, and the output terminal of the eighteenth microstrip line L18 is the output terminal of the high-frequency harmonic suppression matching network. P2 is a DC feed port. The twelfth microstrip line L12 and the eleventh microstrip line L11 serve as feed microstrip lines, with one end connected to the tenth microstrip line L10 and the thirteenth microstrip line L13, respectively, and the other end connected to the upper plates of the sixth capacitor C6 and the seventh capacitor C7, respectively. The lower plates of the sixth capacitor C6 and the seventh capacitor C7 are connected to the ground via. The upper plate of the eighth capacitor C8 is connected to the output terminal of the thirteenth microstrip line L13, and the lower plate is connected to the ground via. The upper plate of the ninth capacitor C9 and the input terminal of the fourteenth microstrip line L14 are connected to the upper plate of the eighth capacitor C8. The lower plate of the ninth capacitor C9 and the output terminal of the fourteenth microstrip line L14 are connected to the upper plate of the tenth capacitor C10. The lower plate of the tenth capacitor C10 is connected to the input terminal of the sixteenth microstrip line L16. The drain terminal of the fifth switch S5 is connected to the input terminal of the sixteenth microstrip line L16, and its source terminal is connected to the drain terminal of the sixth switch S6. The source terminal of the sixth switch S6 is connected to a ground via the fifteenth microstrip line L15. The drain terminal of the seventh switch S7 is connected to both the sixteenth and eighteenth microstrip lines L16 and L18, and its source terminal is connected to the drain terminal of the eighth switch S8. The source terminal of the eighth switch S8 is connected to a ground via the seventeenth microstrip line L17.

[0052] The ninth capacitor C9 and the fourteenth microstrip line L14 form a second parallel resonant network, which is used to suppress part of the second harmonic of the high-frequency signal (frequency approximately f4-2f3). When the high-frequency harmonic suppression matching network is working, the control voltage is changed to turn off the switches S5, S6, S7, and S8 connected to port P4. At this time, these four switches can be equivalent to turn-off capacitors: the turn-off capacitors of the fifth switch S5 and the sixth switch S6, together with the fifteenth microstrip line L15, form a third series resonant network; the turn-off capacitors of the seventh switch S7 and the eighth switch S8, together with the seventeenth microstrip line L17, form a fourth series resonant network. The third and fourth series resonant networks are used to suppress part of the second harmonic and all of the third harmonic of the high-frequency signal. The high-frequency harmonic suppression matching network achieves the suppression of the second and third harmonics of the high-frequency signal through the above series and parallel resonant networks.

[0053] Furthermore, the power amplifier circuits constructed by Examples 2 to 4 are implemented as monolithic integrated circuits or hybrid integrated circuits.

[0054] Example 5

[0055] Based on Examples 1-4, this example uses an ultra-wideband power amplifier designed and manufactured using a 0.20 μm GaN process. The operating frequencies are low-frequency signals f1-f2 and high-frequency signals f3-f4, operating in a time-division multiplexing manner. The transistor's on-state gate voltage is -2V, the off-state gate voltage is -5V, and the operating drain voltage is 28V; the switching transistor's on-state voltage is 0V, and the off-state voltage is -28V.

[0056] When the power amplifier operates in the f1-f2 frequency band, the gate voltage of all transistors in the low-frequency power amplification branch is -2V, and the gate voltage of all transistors in the high-frequency power amplification branch is -5V. The drain voltage is 28V for all transistors. Switches S1, S2, S3, and S4 are in the off state, while switches S5, S6, S7, and S8 are in the on state. The low-frequency signal f1-f2 passes sequentially through a single-pole double-throw switch, the low-frequency power amplification branch, the low-frequency harmonic suppression matching network, and the common terminal. The low-frequency power amplification branch amplifies the RF signal of the low-frequency signal f1-f2, while the parallel and series resonant networks of the low-frequency harmonic suppression matching network suppress the second and third harmonics. This significantly reduces the power of the second and third harmonic signals of the low-frequency signal f1-f2 in the RF signal output from the common terminal.

[0057] When the power amplifier operates in the f3-f4 frequency band, the gate voltage of all transistors in the high-frequency power amplification branch is -2V, and the gate voltage of all transistors in the low-frequency power amplification branch is -5V. The drain voltage of all transistors is 28V. Switches S1, S2, S3, and S4 are in the on state, while switches S5, S6, S7, and S8 are in the off state. The high-frequency signal f3-f4 passes sequentially through a single-pole double-throw switch, the low-frequency power amplification branch, the high-frequency harmonic suppression matching network, and the common terminal. The high-frequency power amplification branch amplifies the radio frequency signal f3-f4, and the parallel and series resonant networks of the high-frequency harmonic suppression matching network suppress the second and third harmonics. As a result, the power of the second and third harmonic signals of the high-frequency signal f3-f4 in the radio frequency signal output from the common terminal is significantly reduced.

[0058] like Figure 3 and Figure 4 The figures shown are the effect diagrams of the power amplifier's second and third harmonic suppression levels obtained by detecting the output signal at the common terminal in this embodiment. The harmonic suppression level is calculated as the difference between the harmonic power detected at the output terminal and the fundamental power. Figure 3 The measured results for the second harmonic suppression of this power amplifier are -15 dBc to -55 dBc within the operating frequency band. Figure 4 The measured results for the power amplifier's third harmonic suppression are -35 dBc to -60 dBc within the operating frequency band.

[0059] This invention positions the parallel resonant network of the low-frequency harmonic suppression matching network near the second harmonic of frequency f1, and the parallel resonant network of the high-frequency harmonic suppression matching network near the second harmonic of frequency f3. This effectively reduces the second harmonic output power of the lower sidebands of both frequency bands. Furthermore, by integrating the parallel and series resonant networks with the matching network, the impedance position is optimized, improving the power amplifier performance. This ultra-wideband high harmonic suppression power amplifier is suitable for applications involving ultra-wideband high-power high harmonic suppression in radio frequency, microwave, and millimeter-wave frequencies.

Claims

1. An ultra-wideband high harmonic suppression power amplifier, characterized in that, It includes a low-frequency power amplification branch, a high-frequency power amplification branch, and a harmonic suppression matching network. The harmonic suppression matching network includes a low-frequency harmonic suppression matching network, a high-frequency harmonic suppression matching network, and a common output terminal. The low-frequency power amplification branch and the high-frequency power amplification branch amplify the power of low-frequency and high-frequency signals with different frequencies within the operating wide bandwidth, respectively. The low-frequency harmonic suppression matching network and the high-frequency harmonic suppression matching network perform impedance matching on the fundamental frequencies of the amplified low-frequency and high-frequency signals, respectively, while suppressing the second and third harmonic signals. The low-frequency harmonic suppression matching network includes a parallel resonant network composed of capacitors and microstrip lines, and a series resonant network composed of the turn-off capacitor of the switching transistor and microstrip lines. Through the synergistic effect of the parallel resonant network and the series resonant network, the suppression of the second and third harmonics of the low-frequency signal is achieved. The high-frequency harmonic suppression matching network includes a parallel resonant network composed of capacitors and microstrip lines, and a series resonant network composed of the turn-off capacitor of the switching transistor and microstrip lines. Through the synergistic effect of the parallel resonant network and the series resonant network, the suppression of the second and third harmonics of the high-frequency signal is achieved.

2. The ultra-wideband high harmonic suppression power amplifier according to claim 1, characterized in that, It also includes a single-pole double-throw switch, the common terminal of which is the radio frequency signal input terminal, and the output terminals of which are respectively connected to the low-frequency power amplifier branch and the high-frequency power amplifier branch to realize the switching of different frequency bands.

3. The ultra-wideband high harmonic suppression power amplifier according to claim 1, characterized in that, The low-frequency power amplifier branch includes a low-frequency input matching network, m-stage low-frequency dies, and m-1 low-frequency inter-stage matching networks. Each stage of the low-frequency dies has a transistors connected in parallel, and the sources of all transistors are connected to ground vias. The gate of the first-stage low-frequency die is connected to the output of the low-frequency input matching network, and the drain of the m-th stage low-frequency die serves as the output of the low-frequency power amplifier branch.

4. The ultra-wideband high harmonic suppression power amplifier according to claim 1, characterized in that, The high-frequency power amplifier branch includes a high-frequency input matching network, n high-frequency dies, and n-1 high-frequency inter-stage matching networks. Each high-frequency die has b transistors connected in parallel, and the sources of all transistors are connected to ground vias. The gate of the first high-frequency die is connected to the output of the high-frequency input matching network, and the drain of the nth high-frequency die serves as the output of the high-frequency power amplifier branch.

5. The ultra-wideband high harmonic suppression power amplifier according to claim 3 or 4, characterized in that, The transistor is a junction field-effect transistor, a metal-oxide-semiconductor field-effect transistor, a heterojunction field-effect crystal, a bipolar junction transistor, or a heterojunction bipolar transistor.

6. The ultra-wideband high harmonic suppression power amplifier according to claim 1, characterized in that, The common output terminal is the output terminal of the entire operating frequency band, including the nineteenth microstrip line L19 and the eleventh capacitor C11 connected in series. The nineteenth microstrip line L19 is connected to the output terminals of the low-frequency harmonic suppression matching network and the high-frequency harmonic suppression matching network.

7. The ultra-wideband high harmonic suppression power amplifier according to claim 1, characterized in that, The low-frequency harmonic suppression matching network includes first to ninth microstrip lines L1~L9, first to fifth capacitors C1~C5, and first to fourth switching transistors S1~S4. One end of the second microstrip line L2 and the third microstrip line L3 are connected to the first microstrip line L1 and the fourth microstrip line L4, respectively, and the other end is connected to the upper plates of the first capacitor C1 and the second capacitor C2, respectively. The lower plates of the first capacitor C1 and the second capacitor C2 are connected to a ground via. The upper plate of the third capacitor C3 is connected to the output terminal of the fourth microstrip line L4, and the lower plate is connected to a ground via. The upper plate of the fourth capacitor C4 and the input terminal of the fifth microstrip line L5 are connected to the first microstrip line L1~L9. The upper plate of capacitor C3, the lower plate of capacitor C4, and the output terminal of microstrip line L5 are connected to the upper plate of capacitor C5. The lower plate of capacitor C5, microstrip line L7, and microstrip line L9 are connected in sequence. The drain terminal of the first switch S1 is connected to the input terminal of microstrip line L7, and the source terminal is connected to the drain terminal of the second switch S2. The source terminal of the second switch S2 is connected to a ground via microstrip line L6. The drain terminal of the third switch S3 is connected to the input terminal of microstrip line L9, and the source terminal is connected to the drain terminal of the fourth switch S4. The source terminal of the fourth switch S4 is connected to a ground via microstrip line L8. The fourth capacitor C4 and the fifth microstrip line L5 form a first parallel resonant network. The turn-off capacitors of the first switch S1 and the second switch S2 and the sixth microstrip line L6 form a first series resonant network. The turn-off capacitors of the third switch S3 and the fourth switch S4 and the eighth microstrip line L8 form a second series resonant network.

8. The ultra-wideband high harmonic suppression power amplifier according to claim 1, characterized in that, The high-frequency harmonic suppression matching network includes microstrip lines L10 to L18 (10th to 18th microstrip lines), capacitors C6 to C10 (6th to 10th capacitors), and switches S5 to S8 (5th to 8th switches). Specifically, microstrip lines L12 and L11 are connected at one end to microstrip lines L10 and L13 (13th microstrip line), respectively, and at the other end to the upper plates of capacitors C6 and C7 (6th and 7th capacitors), respectively. The lower plates of capacitors C6 and C7 are connected to ground vias. The upper plate of capacitor C8 is connected to the output terminal of microstrip line L13, and its lower plate is connected to a ground via. The upper plate of capacitor C9 and the input terminal of microstrip line L14 are connected to the eighth microstrip line. The upper plate of capacitor C8, the lower plate of the ninth capacitor C9, and the output terminal of the fourteenth microstrip line L14 are connected to the upper plate of the tenth capacitor C10. The lower plate of the tenth capacitor C10 is connected to the input terminal of the sixteenth microstrip line L16. The drain terminal of the fifth switch S5 is connected to the input terminal of the sixteenth microstrip line L16, and the source terminal is connected to the drain terminal of the sixth switch S6. The source terminal of the sixth switch S6 is connected to a ground via the fifteenth microstrip line L15. The drain terminal of the seventh switch S7 is connected to the sixteenth microstrip line L16 and the eighteenth microstrip line L18, and the source terminal is connected to the drain terminal of the eighth switch S8. The source terminal of the eighth switch S8 is connected to a ground via the seventeenth microstrip line L17. The ninth capacitor C9 and the fourteenth microstrip line L14 form a second parallel resonant network. The turn-off capacitors of the fifth switch S5 and the sixth switch S6, together with the fifteenth microstrip line L15, form a third series resonant network. The turn-off capacitors of the seventh switch S7 and the eighth switch S8, together with the seventeenth microstrip line L17, form a fourth series resonant network.

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